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authorAjay Kumar <ajaykumar.rs@samsung.com>2013-01-08 20:42:23 +0000
committerMinkyu Kang <mk7.kang@samsung.com>2013-01-10 10:19:47 +0900
commit1673f199d917e0649098e0cb7ef5b375b96bd6cb (patch)
tree827f9a574affebaab94e75ee1f909585f4c2357b /lib/gzip.c
parent9b572852c0547365b186651d27b3df5dcbe82be2 (diff)
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EXYNOS5: Change parent clock of FIMD to MPLL
With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to MPLL resolves this issue. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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