Merge with /home/wd/git/u-boot/custodian/u-boot-mpc83xx

7 files changed, 885 insertions, 24 deletions

diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h
index ff9512f..d1bb159 100644
--- a/include/asm-ppc/e300.h
+++ b/include/asm-ppc/e300.h
@@ -6,19 +6,9 @@
 #ifndef	__E300_H__
 #define __E300_H__
 
-/*
- * e300 Processor Version & Revision Numbers
- */
-#define PVR_83xx 0x80830000
-#define PVR_8349_REV10 (PVR_83xx | 0x0010)
-#define PVR_8349_REV11 (PVR_83xx | 0x0011)
-#define PVR_8360_REV10 (PVR_83xx | 0x0020)
-#define PVR_8360_REV11 (PVR_83xx | 0x0020)
-
-#if defined(CONFIG_MPC832X)
-#undef PVR_83xx
-#define PVR_83xx 0x80840000
-#endif
+#define PVR_E300C1	0x80830000
+#define PVR_E300C2	0x80840000
+#define PVR_E300C3	0x80850000
 
 /*
  * Hardware Implementation-Dependent Register 0 (HID0)
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 26bc875..cd24636 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -55,11 +55,13 @@ typedef	struct	global_data {
 #if defined(CONFIG_MPC83XX)
 	/* There are other clocks in the MPC83XX */
 	u32 csb_clk;
-#if defined (CONFIG_MPC834X)
+#if defined (CONFIG_MPC834X) || defined(CONFIG_MPC831X)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
-	u32 usbmph_clk;
 	u32 usbdr_clk;
+#endif
+#if defined (CONFIG_MPC834X)
+	u32 usbmph_clk;
 #endif /* CONFIG_MPC834X */
 	u32 core_clk;
 	u32 i2c1_clk;
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 5e088d6..0de9338 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -206,7 +206,9 @@ typedef struct pmc83xx {
 	u32 pmccr;		/* PMC Configuration Register */
 	u32 pmcer;		/* PMC Event Register */
 	u32 pmcmr;		/* PMC Mask Register */
-	u8 res0[0xF4];
+	u32 pmccr1;		/* PMC Configuration Register 1 */
+	u32 pmccr2;		/* PMC Configuration Register 2 */
+	u8 res0[0xEC];
 } pmc83xx_t;
 
 /*
@@ -355,7 +357,8 @@ typedef struct lbus83xx {
 	u8 res2[0x8];
 	u32 mrtpr;		/* Memory Refresh Timer Prescaler Register */
 	u32 mdr;		/* UPM Data Register */
-	u8 res3[0x8];
+	u8 res3[0x4];
+	u32 lsor;		/* Special Operation Initiation Register */
 	u32 lsdmr;		/* SDRAM Mode Register */
 	u8 res4[0x8];
 	u32 lurt;		/* UPM Refresh Timer */
@@ -369,8 +372,14 @@ typedef struct lbus83xx {
 	u8 res6[0xC];
 	u32 lbcr;		/* Configuration Register */
 	u32 lcrr;		/* Clock Ratio Register */
-	u8 res7[0x28];
-	u8 res8[0xF00];
+	u8 res7[0x8];
+	u32 fmr;		/* Flash Mode Register */
+	u32 fir;		/* Flash Instruction Register */
+	u32 fcr;		/* Flash Command Register */
+	u32 fbar;		/* Flash Block Addr Register */
+	u32 fpar;		/* Flash Page Addr Register */
+	u32 fbcr;		/* Flash Byte Count Register */
+	u8 res8[0xF08];
 } lbus83xx_t;
 
 /*
@@ -527,7 +536,7 @@ typedef struct pcictrl83xx {
  * USB
  */
 typedef struct usb83xx {
-	u8 fixme[0x2000];
+	u8 fixme[0x1000];
 } usb83xx_t;
 
 /*
@@ -574,7 +583,42 @@ typedef struct immap {
 	ios83xx_t		ios;		/* Sequencer */
 	pcictrl83xx_t		pci_ctrl[2];	/* PCI Controller Control and Status Registers */
 	u8			res5[0x19900];
-	usb83xx_t		usb;
+	usb83xx_t		usb[2];
+	tsec83xx_t		tsec[2];
+	u8			res6[0xA000];
+	security83xx_t		security;
+	u8			res7[0xC0000];
+} immap_t;
+
+#elif defined(CONFIG_MPC831X)
+typedef struct immap {
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	gtm83xx_t		gtm[2];		/* Global Timers Module */
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	gpio83xx_t		gpio[1];	/* General purpose I/O module */
+	u8			res0[0x1300];
+	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+	fsl_i2c_t		i2c[2];		/* I2C Controllers */
+	u8			res1[0x1300];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res2[0x900];
+	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	u8			res3[0x1000];
+	spi83xx_t		spi;		/* Serial Peripheral Interface */
+	dma83xx_t		dma;		/* DMA */
+	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
+	u8			res4[0x80];
+	ios83xx_t		ios;		/* Sequencer */
+	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
+	u8			res5[0x1aa00];
+	usb83xx_t		usb[1];
 	tsec83xx_t		tsec[2];
 	u8			res6[0xA000];
 	security83xx_t		security;
diff --git a/include/common.h b/include/common.h
index 40fbba5..3c4b37b 100644
--- a/include/common.h
+++ b/include/common.h
@@ -444,8 +444,6 @@ int	sdram_adjust_866 (void);
 int	adjust_sdram_tbs_8xx (void);
 #if defined(CONFIG_8260)
 int	prt_8260_clks (void);
-#elif defined(CONFIG_MPC83XX)
-int print_clock_conf(void);
 #elif defined(CONFIG_MPC5xxx)
 int	prt_mpc5xxx_clks (void);
 #endif
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
new file mode 100644
index 0000000..11858bf
--- /dev/null
+++ b/include/configs/MPC8313ERDB.h
@@ -0,0 +1,569 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * History
+ * 20061201: Wilson Lo (Wilson.Lo@freescale.com)
+ *           Initialized
+ * 20061210: Tanya Jiang (tanya.jiang@freescale.com)
+ *           Code Cleanup
+ * 20070410: Scott Wood <scottwood@freescale.com>
+ *           More cleanup
+ */
+/*
+ * mpc8313epb board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1
+#define CONFIG_MPC83XX		1
+#define CONFIG_MPC831X		1
+#define CONFIG_MPC8313		1
+#define CONFIG_MPC8313ERDB	1
+
+#define CONFIG_PCI
+#define CONFIG_83XX_GENERIC_PCI
+
+#ifdef CFG_66MHZ
+#define CONFIG_83XX_CLKIN	66666667	/* in Hz */
+#elif defined(CFG_33MHZ)
+#define CONFIG_83XX_CLKIN	33333333	/* in Hz */
+#else
+#error Unknown oscillator frequency.
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+
+#define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
+
+#define CFG_IMMR		0xE0000000
+
+#define CFG_MEMTEST_START	0x00001000
+#define CFG_MEMTEST_END		0x07f00000
+
+/* Early revs of this board will lock up hard when attempting
+ * to access the PMC registers, unless a JTAG debugger is
+ * connected, or some resistor modifications are made.
+ */
+#define CFG_8313ERDB_BROKEN_PMC 1
+
+#define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+
+/*
+ * Manually set up DDR parameters, as this board does not
+ * seem to have the SPD connected to I2C.
+ */
+#define CFG_DDR_SIZE		128		/* MB */
+#define CFG_DDR_CONFIG		( CSCONFIG_EN | CSCONFIG_AP \
+				| 0x00040000 /* TODO */ \
+				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
+				/* 0x80840102 */
+
+#define CFG_DDR_TIMING_3	0x00000000
+#define CFG_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
+				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+				/* 0x00220802 */
+#define CFG_DDR_TIMING_1	( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
+				| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
+				| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
+				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
+				| (13 << TIMING_CFG1_REFREC_SHIFT ) \
+				| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
+				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
+				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+				/* 0x3935d322 */
+#define CFG_DDR_TIMING_2	( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+				| (31 << TIMING_CFG2_CPO_SHIFT ) \
+				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
+				| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
+				| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
+				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
+				| (10 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+				/* 0x0f9048ca */ /* P9-45,may need tuning */
+#define CFG_DDR_INTERVAL	( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+				| ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+				/* 0x03200064 */
+#if defined(CONFIG_DDR_2T_TIMING)
+#define CFG_SDRAM_CFG		( SDRAM_CFG_SREN \
+				| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
+				| SDRAM_CFG_2T_EN \
+				| SDRAM_CFG_DBW_32 )
+#else
+#define CFG_SDRAM_CFG		( SDRAM_CFG_SREN \
+				| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
+				| SDRAM_CFG_32_BE )
+				/* 0x43080000 */
+#endif
+#define CFG_SDRAM_CFG2		0x00401000;
+/* set burst length to 8 for 32-bit data path */
+#define CFG_DDR_MODE		( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
+				| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
+				/* 0x44400232 */
+#define CFG_DDR_MODE_2		0x8000C000;
+
+#define CFG_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+				/*0x02000000*/
+#define CFG_DDRCDR_VALUE	( DDRCDR_EN \
+				| DDRCDR_PZ_NOMZ \
+				| DDRCDR_NZ_NOMZ \
+				| DDRCDR_M_ODR )
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI				/* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
+#define CFG_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CFG_FLASH_SIZE		8		/* flash size in MB */
+#define CFG_FLASH_EMPTY_INFO			/* display empty sectors */
+#define CFG_FLASH_USE_BUFFER_WRITE		/* buffer up multiple bytes */
+
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE |    /* flash Base address */ \
+				(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+				BR_V)		     /* valid */
+#define CFG_OR0_PRELIM		( 0xFF000000         /* 16 MByte */ \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_9 \
+				| OR_GPCM_EHTR \
+				| OR_GPCM_EAD )
+				/* 0xFF006FF7	TODO SLOW 16 MB flash size */
+#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* window base at flash base */
+#define CFG_LBLAWAR0_PRELIM	0x80000017	/* 16 MB window size */
+
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
+#define CFG_MAX_FLASH_SECT	135		/* sectors per device */
+
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#endif
+
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
+#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ */
+#define CFG_LCRR	LCRR_EADC_1 | LCRR_CLKDIV_2	/* 0x00010002 */
+#define CFG_LBC_LBCR	( 0x00040000 /* TODO */ \
+			| (0xFF << LBCR_BMT_SHIFT) \
+			| 0xF )	/* 0x0004ff0f */
+
+#define CFG_LBC_MRTPR	0x20000000  /*TODO */  /* LB refresh timer prescal, 266MHz/32 */
+
+/* drivers/nand/nand.c */
+#define CFG_NAND_BASE		0xE2800000 /* 0xF0000000 */
+#define CFG_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS		1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+
+#define CFG_BR1_PRELIM		( CFG_NAND_BASE \
+				| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+				| BR_PS_8            /* Port Size = 8 bit */ \
+				| BR_MS_FCM          /* MSEL = FCM */ \
+				| BR_V )             /* valid */
+#define CFG_OR1_PRELIM		( 0xFFFF8000	/* length 32K */ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR )
+				/* 0xFFFF8396 */
+#define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
+#define CFG_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
+
+#define CFG_VSC7385_BASE	0xF0000000
+
+#define CONFIG_VSC7385_ENET			/* VSC7385 ethernet support */
+#define CFG_BR2_PRELIM		0xf0000801	/* VSC7385 Base address */
+#define CFG_OR2_PRELIM		0xfffe09ff	/* VSC7385, 128K bytes*/
+#define CFG_LBLAWBAR2_PRELIM	CFG_VSC7385_BASE/* Access window base at VSC7385 base */
+#define CFG_LBLAWAR2_PRELIM	0x80000010	/* Access window size 128K */
+
+/* local bus read write buffer mapping */
+#define CFG_BR3_PRELIM		0xFA000801	/* map at 0xFA000000 */
+#define CFG_OR3_PRELIM		0xFFFF8FF7	/* 32kB */
+#define CFG_LBLAWBAR3_PRELIM	0xFA000000
+#define CFG_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8313@0"
+#define OF_SOC			"soc8313@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc8313@e0000000/serial@4500"
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support*/
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
+#define CFG_I2C2_OFFSET		0x3100
+
+/* TSEC */
+#define CFG_TSEC1_OFFSET	0x24000
+#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET	0x25000
+#define CFG_TSEC2		(CFG_IMMR+CFG_TSEC2_OFFSET)
+#define CONFIG_NET_MULTI
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI1_MMIO_BASE	0x90000000
+#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
+#define CFG_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xE2000000
+#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
+
+/*
+ * TSEC configuration
+ */
+#define CONFIG_TSEC_ENET		/* TSEC ethernet support */
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI		1
+#endif
+
+#define CONFIG_GMII			1	/* MII PHY management */
+#define CONFIG_MPC83XX_TSEC1		1
+
+#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
+#define CONFIG_MPC83XX_TSEC2		1
+#define CONFIG_MPC83XX_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR			0x1c
+#define TSEC2_PHY_ADDR			4
+#define TSEC1_PHYIDX			0
+#define TSEC2_PHYIDX			0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME			"TSEC1"
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1337
+#define CFG_I2C_RTC_ADDR		0x68
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+	#define CFG_ENV_IS_IN_FLASH	1
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CFG_ENV_SECT_SIZE	0x10000	/* 64K(one sector) for env */
+	#define CFG_ENV_SIZE		0x2000
+
+/* Address and size of Redundant Environment Sector */
+#else
+	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#define CFG_BASE_COMMANDS	( CONFIG_CMD_DFL	\
+				| CFG_CMD_PING		\
+				| CFG_CMD_DHCP		\
+				| CFG_CMD_I2C		\
+				| CFG_CMD_MII		\
+				| CFG_CMD_DATE		\
+				| CFG_CMD_PCI)
+
+#define CONFIG_CMDLINE_EDITING 1
+
+#define CFG_RAMBOOT_COMMANDS	(CFG_BASE_COMMANDS & \
+				 ~(CFG_CMD_ENV | CFG_CMD_LOADS))
+
+#if defined(CFG_RAMBOOT)
+#define CONFIG_COMMANDS CFG_RAMBOOT_COMMANDS
+#else
+#define CONFIG_COMMANDS CFG_BASE_COMMANDS
+#endif
+
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory */
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		16384
+#define CFG_CACHELINE_SIZE	32
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+
+#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+
+#ifdef CFG_66MHZ
+
+/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
+/* 0x62040000 */
+#define CFG_HRCW_LOW (\
+	0x20000000 /* reserved, must be set */ |\
+	HRCWL_DDRCM |\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_CSB_TO_CLKIN_2X1 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#elif defined(CFG_33MHZ)
+
+/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
+/* 0x65040000 */
+#define CFG_HRCW_LOW (\
+	0x20000000 /* reserved, must be set */ |\
+	HRCWL_DDRCM |\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_CSB_TO_CLKIN_5X1 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#endif
+
+/* 0xa0606c00 */
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_RL_EXT_LEGACY |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LALE_NORMAL)
+
+/* System IO Config */
+#define CFG_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
+#define CFG_SICRL	SICRL_USBDR /* Enable Internal USB Phy  */
+
+#define CFG_HID0_INIT	0x000000000
+#define CFG_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+                         HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+
+#define CFG_HID2 HID2_HBE
+
+/* DDR @ 0x00000000 */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI @ 0x80000000 */
+#define CFG_IBAT1L	(CFG_PCI1_MEM_BASE | BATL_PP_10)
+#define CFG_IBAT1U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L	(CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U	(CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI2 not supported on 8313 */
+#define CFG_IBAT3L	(0)
+#define CFG_IBAT3U	(0)
+#define CFG_IBAT4L	(0)
+#define CFG_IBAT4U	(0)
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
+#define CFG_IBAT5L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U	(CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CFG_IBAT6L	(0xF0000000 | BATL_PP_10)
+#define CFG_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT7L	(0)
+#define CFG_IBAT7U	(0)
+
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+#define CFG_DBAT4L	CFG_IBAT4L
+#define CFG_DBAT4U	CFG_IBAT4U
+#define CFG_DBAT5L	CFG_IBAT5L
+#define CFG_DBAT5U	CFG_IBAT5U
+#define CFG_DBAT6L	CFG_IBAT6L
+#define CFG_DBAT6U	CFG_IBAT6U
+#define CFG_DBAT7L	CFG_IBAT7L
+#define CFG_DBAT7U	CFG_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02	/* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ETHADDR		00:E0:0C:00:95:01
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		00:E0:0C:00:95:02
+
+#define CONFIG_IPADDR		10.0.0.2
+#define CONFIG_SERVERIP		10.0.0.1
+#define CONFIG_GATEWAYIP	10.0.0.1
+#define CONFIG_NETMASK		255.0.0.0
+#define CONFIG_NETDEV		eth1
+
+#define CONFIG_HOSTNAME		mpc8313erdb
+#define CONFIG_ROOTPATH		/nfs/root/path
+#define CONFIG_BOOTFILE		uImage
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
+#define CONFIG_FDTFILE		mpc8313erdb.dtb
+
+#define CONFIG_LOADADDR		200000	/* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
+#define CONFIG_BAUDRATE		115200
+
+#define XMK_STR(x)	#x
+#define MK_STR(x)	XMK_STR(x)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" MK_STR(CONFIG_NETDEV) "\0" 				\
+	"ethprime=TSEC1\0"						\
+	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" 				\
+	"tftpflash=tftpboot $loadaddr $uboot; " 			\
+		"protect off " MK_STR(TEXT_BASE) " +$filesize; " 	\
+		"erase " MK_STR(TEXT_BASE) " +$filesize; " 		\
+		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " 	\
+		"protect on " MK_STR(TEXT_BASE) " +$filesize; " 	\
+		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" 	\
+	"fdtaddr=400000\0"						\
+	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"				\
+	"console=ttyS0\0"						\
+	"setbootargs=setenv bootargs "					\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv rootdev /dev/nfs;"					\
+	"run setbootargs;"							\
+	"run setipargs;"							\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv rootdev /dev/ram;"					\
+	"run setbootargs;"						\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#undef MK_STR
+#undef XMK_STR
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 37bbfb3..906339e 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -154,6 +154,9 @@
 #define CFG_MEMTEST_START	0x1000		/* memtest region */
 #define CFG_MEMTEST_END		0x2000
 
+#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
 #ifdef CONFIG_HARD_I2C
 #define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
 #endif
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index c2a4ff5..60fc214 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -95,6 +95,11 @@
 #define SPR_8321E_REV11			0x80660011
 #define SPR_8321_REV11			0x80670011
 
+#define SPR_8311_REV10			0x80B30010
+#define SPR_8311E_REV10			0x80B20010
+#define SPR_8313_REV10			0x80B10010
+#define SPR_8313E_REV10			0x80B00010
+
 /* SPCR - System Priority Configuration Register
  */
 #define SPCR_PCIHPE			0x10000000	/* PCI Highest Priority Enable */
@@ -121,6 +126,15 @@
 #define SPCR_TSEC2BDP_SHIFT		(31-29)
 #define SPCR_TSEC2EP			0x00000003	/* TSEC2 emergency priority */
 #define SPCR_TSEC2EP_SHIFT		(31-31)
+
+#elif defined(CONFIG_MPC831X)
+/* SPCR bits - MPC831x specific */
+#define SPCR_TSECDP			0x00003000	/* TSEC data priority */
+#define SPCR_TSECDP_SHIFT		(31-19)
+#define SPCR_TSECEP			0x00000C00	/* TSEC emergency priority */
+#define SPCR_TSECEP_SHIFT		(31-21)
+#define SPCR_TSECBDP			0x00000300	/* TSEC buffer descriptor priority */
+#define SPCR_TSECBDP_SHIFT		(31-23)
 #endif
 
 /* SICRL/H - System I/O Configuration Register Low/High
@@ -195,6 +209,36 @@
 #define SICRL_PCI_MSRC			0x10000000
 #define SICRL_URT_CTPR			0x06000000
 #define SICRL_IRQ_CTPR			0x00C00000
+
+#elif defined(CONFIG_MPC831X)
+/* SICRL bits - MPC831x specific */
+#define SICRL_LBC			0x30000000
+#define SICRL_UART			0x0C000000
+#define SICRL_SPI_A			0x03000000
+#define SICRL_SPI_B			0x00C00000
+#define SICRL_SPI_C			0x00300000
+#define SICRL_SPI_D			0x000C0000
+#define SICRL_USBDR			0x00000C00
+#define SICRL_ETSEC1_A			0x0000000C
+#define SICRL_ETSEC2_A			0x00000003
+
+/* SICRH bits - MPC831x specific */
+#define SICRH_INTR_A			0x02000000
+#define SICRH_INTR_B			0x00C00000
+#define SICRH_IIC			0x00300000
+#define SICRH_ETSEC2_B			0x000C0000
+#define SICRH_ETSEC2_C			0x00030000
+#define SICRH_ETSEC2_D			0x0000C000
+#define SICRH_ETSEC2_E			0x00003000
+#define SICRH_ETSEC2_F			0x00000C00
+#define SICRH_ETSEC2_G			0x00000300
+#define SICRH_ETSEC1_B			0x00000080
+#define SICRH_ETSEC1_C			0x00000060
+#define SICRH_GTX1_DLY			0x00000008
+#define SICRH_GTX2_DLY			0x00000004
+#define SICRH_TSOBI1			0x00000002
+#define SICRH_TSOBI2			0x00000001
+
 #endif
 
 /* SWCRR - System Watchdog Control Register
@@ -393,6 +437,28 @@
 #define HRCWH_ROM_LOC_LOCAL_16BIT	0x00600000
 #define HRCWH_ROM_LOC_LOCAL_32BIT	0x00700000
 
+#if defined(CONFIG_MPC831X)
+#define HRCWH_ROM_LOC_NAND_SP_8BIT 	0x00100000
+#define HRCWH_ROM_LOC_NAND_SP_16BIT	0x00200000
+#define HRCWH_ROM_LOC_NAND_LP_8BIT 	0x00500000
+#define HRCWH_ROM_LOC_NAND_LP_16BIT	0x00600000
+
+#define HRCWH_RL_EXT_LEGACY		0x00000000
+#define HRCWH_RL_EXT_NAND		0x00040000
+
+#define HRCWH_TSEC1M_IN_MII		0x00000000
+#define HRCWH_TSEC1M_IN_RMII		0x00002000
+#define HRCWH_TSEC1M_IN_RGMII		0x00006000
+#define HRCWH_TSEC1M_IN_RTBI		0x0000A000
+#define HRCWH_TSEC1M_IN_SGMII		0x0000C000
+
+#define HRCWH_TSEC2M_IN_MII		0x00000000
+#define HRCWH_TSEC2M_IN_RMII		0x00000400
+#define HRCWH_TSEC2M_IN_RGMII		0x00000C00
+#define HRCWH_TSEC2M_IN_RTBI		0x00001400
+#define HRCWH_TSEC2M_IN_SGMII		0x00001800
+#endif
+
 #if defined(CONFIG_MPC834X)
 #define HRCWH_TSEC1M_IN_RGMII		0x00000000
 #define HRCWH_TSEC1M_IN_RTBI		0x00004000
@@ -523,6 +589,18 @@
 #define SCCR_TSEC2CM_1			0x10000000
 #define SCCR_TSEC2CM_2			0x20000000
 #define SCCR_TSEC2CM_3			0x30000000
+
+#elif defined(CONFIG_MPC831X)
+/* TSEC1 bits are for TSEC2 as well */
+#define SCCR_TSEC1CM			0xc0000000
+#define SCCR_TSEC1CM_SHIFT		30
+#define SCCR_TSEC1CM_1			0x40000000
+#define SCCR_TSEC1CM_2			0x80000000
+#define SCCR_TSEC1CM_3			0xC0000000
+
+#define SCCR_TSEC1ON			0x20000000
+#define SCCR_TSEC2ON			0x10000000
+
 #endif
 
 #define SCCR_USBMPHCM			0x00c00000
@@ -556,6 +634,25 @@
 #define CSCONFIG_COL_BIT_10		0x00000002
 #define CSCONFIG_COL_BIT_11		0x00000003
 
+/* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
+ */
+#define TIMING_CFG0_RWT			0xC0000000
+#define TIMING_CFG0_RWT_SHIFT		30
+#define TIMING_CFG0_WRT			0x30000000
+#define TIMING_CFG0_WRT_SHIFT		28
+#define TIMING_CFG0_RRT			0x0C000000
+#define TIMING_CFG0_RRT_SHIFT		26
+#define TIMING_CFG0_WWT			0x03000000
+#define TIMING_CFG0_WWT_SHIFT		24
+#define TIMING_CFG0_ACT_PD_EXIT		0x00700000
+#define TIMING_CFG0_ACT_PD_EXIT_SHIFT	20
+#define TIMING_CFG0_PRE_PD_EXIT		0x00070000
+#define TIMING_CFG0_PRE_PD_EXIT_SHIFT	16
+#define TIMING_CFG0_ODT_PD_EXIT		0x00000F00
+#define TIMING_CFG0_ODT_PD_EXIT_SHIFT	8
+#define TIMING_CFG0_MRS_CYC		0x00000F00
+#define TIMING_CFG0_MRS_CYC_SHIFT	0
+
 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
  */
 #define TIMING_CFG1_PRETOACT		0x70000000
@@ -586,6 +683,17 @@
 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT	10
 #define TIMING_CFG2_CPO_DEF		0x00000000	/* default (= CASLAT + 1) */
 
+#define TIMING_CFG2_ADD_LAT		0x70000000
+#define TIMING_CFG2_ADD_LAT_SHIFT	28
+#define TIMING_CFG2_WR_LAT_DELAY	0x00380000
+#define TIMING_CFG2_WR_LAT_DELAY_SHIFT	19
+#define TIMING_CFG2_RD_TO_PRE		0x0000E000
+#define TIMING_CFG2_RD_TO_PRE_SHIFT	13
+#define TIMING_CFG2_CKE_PLS		0x000001C0
+#define TIMING_CFG2_CKE_PLS_SHIFT	6
+#define TIMING_CFG2_FOUR_ACT		0x0000003F
+#define TIMING_CFG2_FOUR_ACT_SHIFT	0
+
 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
  */
 #define SDRAM_CFG_MEM_EN		0x80000000
@@ -593,13 +701,14 @@
 #define SDRAM_CFG_ECC_EN		0x20000000
 #define SDRAM_CFG_RD_EN			0x10000000
 #define SDRAM_CFG_SDRAM_TYPE		0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR	0x02000000
 #define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
 #define SDRAM_CFG_DYN_PWR		0x00200000
 #define SDRAM_CFG_32_BE			0x00080000
 #define SDRAM_CFG_8_BE			0x00040000
 #define SDRAM_CFG_NCAP			0x00020000
 #define SDRAM_CFG_2T_EN			0x00008000
-#define SDRAM_CFG_SDRAM_TYPE_DDR	0x02000000
+#define SDRAM_CFG_BI			0x00000001
 
 /* DDR_SDRAM_MODE - DDR SDRAM Mode Register
  */
@@ -732,11 +841,15 @@
 #define BR_PS_32			0x00001800	/* Port Size 32 bit */
 #define BR_DECC				0x00000600
 #define BR_DECC_SHIFT			9
+#define BR_DECC_OFF			0x00000000
+#define BR_DECC_CHK			0x00000200
+#define BR_DECC_CHK_GEN			0x00000400
 #define BR_WP				0x00000100
 #define BR_WP_SHIFT			8
 #define BR_MSEL				0x000000E0
 #define BR_MSEL_SHIFT			5
 #define BR_MS_GPCM			0x00000000	/* GPCM */
+#define BR_MS_FCM			0x00000020	/* FCM */
 #define BR_MS_SDRAM			0x00000060	/* SDRAM */
 #define BR_MS_UPMA			0x00000080	/* UPMA */
 #define BR_MS_UPMB			0x000000A0	/* UPMB */
@@ -803,6 +916,34 @@
 #define OR_GPCM_EAD			0x00000001
 #define OR_GPCM_EAD_SHIFT		0
 
+#define OR_FCM_AM			0xFFFF8000
+#define OR_FCM_AM_SHIFT				15
+#define OR_FCM_BCTLD			0x00001000
+#define OR_FCM_BCTLD_SHIFT			12
+#define OR_FCM_PGS			0x00000400
+#define OR_FCM_PGS_SHIFT			10
+#define OR_FCM_CSCT			0x00000200
+#define OR_FCM_CSCT_SHIFT			 9
+#define OR_FCM_CST			0x00000100
+#define OR_FCM_CST_SHIFT			 8
+#define OR_FCM_CHT			0x00000080
+#define OR_FCM_CHT_SHIFT			 7
+#define OR_FCM_SCY			0x00000070
+#define OR_FCM_SCY_SHIFT			 4
+#define OR_FCM_SCY_1			0x00000010
+#define OR_FCM_SCY_2			0x00000020
+#define OR_FCM_SCY_3			0x00000030
+#define OR_FCM_SCY_4			0x00000040
+#define OR_FCM_SCY_5			0x00000050
+#define OR_FCM_SCY_6			0x00000060
+#define OR_FCM_SCY_7			0x00000070
+#define OR_FCM_RST			0x00000008
+#define OR_FCM_RST_SHIFT			 3
+#define OR_FCM_TRLX			0x00000004
+#define OR_FCM_TRLX_SHIFT			 2
+#define OR_FCM_EHTR			0x00000002
+#define OR_FCM_EHTR_SHIFT			 1
+
 #define OR_UPM_AM			0xFFFF8000
 #define OR_UPM_AM_SHIFT			15
 #define OR_UPM_XAM			0x00006000
@@ -1019,4 +1160,118 @@
 #define PIWAR_IWS_1G			0x0000001D
 #define PIWAR_IWS_2G			0x0000001E
 
+/* PMCCR1 - PCI Configuration Register 1
+ */
+#define PMCCR1_POWER_OFF		0x00000020
+
+/* FMR - Flash Mode Register
+ */
+#define FMR_CWTO		0x0000F000
+#define FMR_CWTO_SHIFT		12
+#define FMR_BOOT		0x00000800
+#define FMR_ECCM		0x00000100
+#define FMR_AL			0x00000030
+#define FMR_AL_SHIFT		4
+#define FMR_OP			0x00000003
+#define FMR_OP_SHIFT		0
+
+/* FIR - Flash Instruction Register
+ */
+#define FIR_OP0			0xF0000000
+#define FIR_OP0_SHIFT		28
+#define FIR_OP1			0x0F000000
+#define FIR_OP1_SHIFT		24
+#define FIR_OP2			0x00F00000
+#define FIR_OP2_SHIFT		20
+#define FIR_OP3			0x000F0000
+#define FIR_OP3_SHIFT		16
+#define FIR_OP4			0x0000F000
+#define FIR_OP4_SHIFT		12
+#define FIR_OP5			0x00000F00
+#define FIR_OP5_SHIFT		8
+#define FIR_OP6			0x000000F0
+#define FIR_OP6_SHIFT		4
+#define FIR_OP7			0x0000000F
+#define FIR_OP7_SHIFT		0
+#define FIR_OP_NOP		0x0 /* No operation and end of sequence */
+#define FIR_OP_CA		0x1 /* Issue current column address */
+#define FIR_OP_PA		0x2 /* Issue current block+page address */
+#define FIR_OP_UA		0x3 /* Issue user defined address */
+#define FIR_OP_CM0		0x4 /* Issue command from FCR[CMD0] */
+#define FIR_OP_CM1		0x5 /* Issue command from FCR[CMD1] */
+#define FIR_OP_CM2		0x6 /* Issue command from FCR[CMD2] */
+#define FIR_OP_CM3		0x7 /* Issue command from FCR[CMD3] */
+#define FIR_OP_WB		0x8 /* Write FBCR bytes from FCM buffer */
+#define FIR_OP_WS		0x9 /* Write 1 or 2 bytes from MDR[AS] */
+#define FIR_OP_RB		0xA /* Read FBCR bytes to FCM buffer */
+#define FIR_OP_RS		0xB /* Read 1 or 2 bytes to MDR[AS] */
+#define FIR_OP_CW0		0xC /* Wait then issue FCR[CMD0] */
+#define FIR_OP_CW1		0xD /* Wait then issue FCR[CMD1] */
+#define FIR_OP_RBW		0xE /* Wait then read FBCR bytes */
+#define FIR_OP_RSW		0xF /* Wait then read 1 or 2 bytes */
+
+/* FCR - Flash Command Register
+ */
+#define FCR_CMD0		0xFF000000
+#define FCR_CMD0_SHIFT		24
+#define FCR_CMD1		0x00FF0000
+#define FCR_CMD1_SHIFT		16
+#define FCR_CMD2		0x0000FF00
+#define FCR_CMD2_SHIFT   	8
+#define FCR_CMD3		0x000000FF
+#define FCR_CMD3_SHIFT		0
+
+/* FBAR - Flash Block Address Register
+ */
+#define FBAR_BLK		0x00FFFFFF
+
+/* FPAR - Flash Page Address Register
+ */
+#define FPAR_SP_PI		0x00007C00
+#define FPAR_SP_PI_SHIFT	10
+#define FPAR_SP_MS		0x00000200
+#define FPAR_SP_CI		0x000001FF
+#define FPAR_SP_CI_SHIFT	0
+#define FPAR_LP_PI		0x0003F000
+#define FPAR_LP_PI_SHIFT	12
+#define FPAR_LP_MS		0x00000800
+#define FPAR_LP_CI		0x000007FF
+#define FPAR_LP_CI_SHIFT	0
+
+/* LTESR - Transfer Error Status Register
+ */
+#define LTESR_BM		0x80000000
+#define LTESR_FCT 		0x40000000
+#define LTESR_PAR 		0x20000000
+#define LTESR_WP		0x04000000
+#define LTESR_ATMW		0x00800000
+#define LTESR_ATMR		0x00400000
+#define LTESR_CS		0x00080000
+#define LTESR_CC		0x00000001
+
+/* DDR Control Driver Register
+ */
+#define DDRCDR_EN		0x40000000
+#define DDRCDR_PZ		0x3C000000
+#define DDRCDR_PZ_MAXZ		0x00000000
+#define DDRCDR_PZ_HIZ		0x20000000
+#define DDRCDR_PZ_NOMZ		0x30000000
+#define DDRCDR_PZ_LOZ		0x38000000
+#define DDRCDR_PZ_MINZ		0x3C000000
+#define DDRCDR_NZ		0x3C000000
+#define DDRCDR_NZ_MAXZ		0x00000000
+#define DDRCDR_NZ_HIZ		0x02000000
+#define DDRCDR_NZ_NOMZ		0x03000000
+#define DDRCDR_NZ_LOZ		0x03800000
+#define DDRCDR_NZ_MINZ		0x03C00000
+#define DDRCDR_ODT		0x00080000
+#define DDRCDR_DDR_CFG		0x00040000
+#define DDRCDR_M_ODR		0x00000002
+#define DDRCDR_Q_DRN		0x00000001
+
+#ifndef __ASSEMBLY__
+struct pci_region;
+void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot);
+#endif
+
 #endif	/* __MPC83XX_H__ */