Merge branch 'master-sync' of git://git.denx.de/u-boot-arm

21 files changed, 1841 insertions, 10 deletions

diff --git a/include/asm-arm/arch-kirkwood/gpio.h b/include/asm-arm/arch-kirkwood/gpio.h
index b5bacde..cd1bc00 100644
--- a/include/asm-arm/arch-kirkwood/gpio.h
+++ b/include/asm-arm/arch-kirkwood/gpio.h
@@ -1,9 +1,23 @@
 /*
  * arch/asm-arm/mach-kirkwood/include/mach/gpio.h
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
  */
 
 /*
diff --git a/include/asm-arm/arch-kirkwood/mpp.h b/include/asm-arm/arch-kirkwood/mpp.h
index bc74278..b3c090e 100644
--- a/include/asm-arm/arch-kirkwood/mpp.h
+++ b/include/asm-arm/arch-kirkwood/mpp.h
@@ -3,9 +3,23 @@
  *
  * Copyright 2009: Marvell Technology Group Ltd.
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
  */
 
 #ifndef __KIRKWOOD_MPP_H
diff --git a/include/asm-arm/arch-s3c64xx/s3c6400.h b/include/asm-arm/arch-s3c64xx/s3c6400.h
index e527c08..10b3324 100644
--- a/include/asm-arm/arch-s3c64xx/s3c6400.h
+++ b/include/asm-arm/arch-s3c64xx/s3c6400.h
@@ -817,9 +817,9 @@
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
-#define DMC1_MEM_CFG	0x80010012	/* Chip1, Burst4, Row/Column bit */
+#define DMC1_MEM_CFG	0x00010012	/* burst 4, 13-bit row, 10-bit col */
 #define DMC1_MEM_CFG2	0xB45
-#define DMC1_CHIP0_CFG	0x150F8		/* 0x4000_0000 ~ 0x43ff_ffff (64MB) */
+#define DMC1_CHIP0_CFG	0x150F8		/* 0x5000_0000~0x57ff_ffff (128 MiB) */
 #define DMC_DDR_32_CFG	0x0 		/* 32bit, DDR */
 
 /* Memory Parameters */
diff --git a/include/asm-arm/arch-s5pc1xx/sys_proto.h b/include/asm-arm/arch-s5pc1xx/sys_proto.h
new file mode 100644
index 0000000..3078aaf
--- /dev/null
+++ b/include/asm-arm/arch-s5pc1xx/sys_proto.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2009 Samsung Electrnoics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+u32 get_device_type(void);
+void invalidate_dcache(u32);
+void l2_cache_disable(void);
+void l2_cache_enable(void);
+
+#endif
diff --git a/include/asm-arm/arch-spear/hardware.h b/include/asm-arm/arch-spear/hardware.h
new file mode 100644
index 0000000..818f36c
--- /dev/null
+++ b/include/asm-arm/arch-spear/hardware.h
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#define CONFIG_SYS_USBD_BASE			(0xE1100000)
+#define CONFIG_SYS_PLUG_BASE			(0xE1200000)
+#define CONFIG_SYS_FIFO_BASE			(0xE1000800)
+#define CONFIG_SYS_SMI_BASE			(0xFC000000)
+#define CONFIG_SPEAR_SYSCNTLBASE		(0xFCA00000)
+#define CONFIG_SPEAR_TIMERBASE			(0xFC800000)
+#define CONFIG_SPEAR_MISCBASE			(0xFCA80000)
+
+#define CONFIG_SYS_NAND_CLE			(1 << 16)
+#define CONFIG_SYS_NAND_ALE			(1 << 17)
+
+#if defined(CONFIG_SPEAR600)
+#define CONFIG_SYS_I2C_BASE			(0xD0200000)
+#define CONFIG_SPEAR_FSMCBASE			(0xD1800000)
+
+#elif defined(CONFIG_SPEAR300)
+#define CONFIG_SYS_I2C_BASE			(0xD0180000)
+#define CONFIG_SPEAR_FSMCBASE			(0x94000000)
+
+#elif defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_I2C_BASE			(0xD0180000)
+#define CONFIG_SPEAR_FSMCBASE			(0x44000000)
+
+#undef CONFIG_SYS_NAND_CLE
+#undef CONFIG_SYS_NAND_ALE
+#define CONFIG_SYS_NAND_CLE			(1 << 17)
+#define CONFIG_SYS_NAND_ALE			(1 << 16)
+
+#define CONFIG_SPEAR_EMIBASE			(0x4F000000)
+#define CONFIG_SPEAR_RASBASE			(0xB4000000)
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_I2C_BASE			(0xD0180000)
+#define CONFIG_SPEAR_FSMCBASE			(0x4C000000)
+
+#define CONFIG_SPEAR_EMIBASE			(0x40000000)
+#define CONFIG_SPEAR_RASBASE			(0xB3000000)
+
+#endif
+#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-spear/spr_defs.h b/include/asm-arm/arch-spear/spr_defs.h
new file mode 100644
index 0000000..fa8412c
--- /dev/null
+++ b/include/asm-arm/arch-spear/spr_defs.h
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SPR_DEFS_H__
+#define __SPR_DEFS_H__
+
+extern int spear_board_init(ulong);
+extern void setfreq(unsigned int, unsigned int);
+extern unsigned int setfreq_sz;
+
+struct chip_data {
+	int cpufreq;
+	int dramfreq;
+	int dramtype;
+	uchar version[32];
+};
+
+/* HW mac id in i2c memory definitions */
+#define MAGIC_OFF	0x0
+#define MAGIC_LEN	0x2
+#define MAGIC_BYTE0	0x55
+#define MAGIC_BYTE1	0xAA
+#define MAC_OFF		0x2
+#define MAC_LEN		0x6
+
+#endif
diff --git a/include/asm-arm/arch-spear/spr_emi.h b/include/asm-arm/arch-spear/spr_emi.h
new file mode 100644
index 0000000..c1f1c2a
--- /dev/null
+++ b/include/asm-arm/arch-spear/spr_emi.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2009
+ * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SPEAR_EMI_H__
+#define __SPEAR_EMI_H__
+
+#ifdef CONFIG_SPEAR_EMI
+
+struct emi_bank_regs {
+	u32 tap;
+	u32 tsdp;
+	u32 tdpw;
+	u32 tdpr;
+	u32 tdcs;
+	u32 control;
+};
+
+struct emi_regs {
+	struct emi_bank_regs bank_regs[CONFIG_SYS_MAX_FLASH_BANKS];
+	u32 tout;
+	u32 ack;
+	u32 irq;
+};
+
+#define EMI_ACKMSK		0x40
+
+/* control register definitions */
+#define EMI_CNTL_ENBBYTEW	(1 << 2)
+#define EMI_CNTL_ENBBYTER	(1 << 3)
+#define EMI_CNTL_ENBBYTERW	(EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW)
+
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-spear/spr_gpt.h b/include/asm-arm/arch-spear/spr_gpt.h
new file mode 100755
index 0000000..965b5ab
--- /dev/null
+++ b/include/asm-arm/arch-spear/spr_gpt.h
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SPR_GPT_H
+#define _SPR_GPT_H
+
+struct gpt_regs {
+	u8 reserved[0x80];
+	u32 control;
+	u32 status;
+	u32 compare;
+	u32 count;
+	u32 capture_re;
+	u32 capture_fe;
+};
+
+/*
+ * TIMER_CONTROL register settings
+ */
+
+#define GPT_PRESCALER_MASK		0x000F
+#define GPT_PRESCALER_1			0x0000
+#define GPT_PRESCALER_2 		0x0001
+#define GPT_PRESCALER_4 		0x0002
+#define GPT_PRESCALER_8 		0x0003
+#define GPT_PRESCALER_16		0x0004
+#define GPT_PRESCALER_32		0x0005
+#define GPT_PRESCALER_64		0x0006
+#define GPT_PRESCALER_128		0x0007
+#define GPT_PRESCALER_256		0x0008
+
+#define GPT_MODE_SINGLE_SHOT		0x0010
+#define GPT_MODE_AUTO_RELOAD		0x0000
+
+#define GPT_ENABLE			0x0020
+
+#define GPT_CAPT_MODE_MASK		0x00C0
+#define GPT_CAPT_MODE_NONE		0x0000
+#define GPT_CAPT_MODE_RE		0x0040
+#define GPT_CAPT_MODE_FE		0x0080
+#define GPT_CAPT_MODE_BOTH		0x00C0
+
+#define GPT_INT_MATCH			0x0100
+#define GPT_INT_FE			0x0200
+#define GPT_INT_RE			0x0400
+
+/*
+ * TIMER_STATUS register settings
+ */
+
+#define GPT_STS_MATCH			0x0001
+#define GPT_STS_FE			0x0002
+#define GPT_STS_RE			0x0004
+
+/*
+ * TIMER_COMPARE register settings
+ */
+
+#define GPT_FREE_RUNNING		0xFFFF
+
+/* Timer, HZ specific defines */
+#define CONFIG_SPEAR_HZ			(1000)
+#define CONFIG_SPEAR_HZ_CLOCK		(8300000)
+
+#endif
diff --git a/include/asm-arm/arch-spear/spr_i2c.h b/include/asm-arm/arch-spear/spr_i2c.h
new file mode 100755
index 0000000..7521ebc
--- /dev/null
+++ b/include/asm-arm/arch-spear/spr_i2c.h
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SPR_I2C_H_
+#define __SPR_I2C_H_
+
+struct i2c_regs {
+	u32 ic_con;
+	u32 ic_tar;
+	u32 ic_sar;
+	u32 ic_hs_maddr;
+	u32 ic_cmd_data;
+	u32 ic_ss_scl_hcnt;
+	u32 ic_ss_scl_lcnt;
+	u32 ic_fs_scl_hcnt;
+	u32 ic_fs_scl_lcnt;
+	u32 ic_hs_scl_hcnt;
+	u32 ic_hs_scl_lcnt;
+	u32 ic_intr_stat;
+	u32 ic_intr_mask;
+	u32 ic_raw_intr_stat;
+	u32 ic_rx_tl;
+	u32 ic_tx_tl;
+	u32 ic_clr_intr;
+	u32 ic_clr_rx_under;
+	u32 ic_clr_rx_over;
+	u32 ic_clr_tx_over;
+	u32 ic_clr_rd_req;
+	u32 ic_clr_tx_abrt;
+	u32 ic_clr_rx_done;
+	u32 ic_clr_activity;
+	u32 ic_clr_stop_det;
+	u32 ic_clr_start_det;
+	u32 ic_clr_gen_call;
+	u32 ic_enable;
+	u32 ic_status;
+	u32 ic_txflr;
+	u32 ix_rxflr;
+	u32 reserved_1;
+	u32 ic_tx_abrt_source;
+};
+
+#define IC_CLK			166
+#define NANO_TO_MICRO		1000
+
+/* High and low times in different speed modes (in ns) */
+#define MIN_SS_SCL_HIGHTIME	4000
+#define MIN_SS_SCL_LOWTIME	5000
+#define MIN_FS_SCL_HIGHTIME	800
+#define MIN_FS_SCL_LOWTIME	1700
+#define MIN_HS_SCL_HIGHTIME	60
+#define MIN_HS_SCL_LOWTIME	160
+
+/* Worst case timeout for 1 byte is kept as 2ms */
+#define I2C_BYTE_TO		(CONFIG_SYS_HZ/500)
+#define I2C_STOPDET_TO		(CONFIG_SYS_HZ/500)
+#define I2C_BYTE_TO_BB		(I2C_BYTE_TO * 16)
+
+/* i2c control register definitions */
+#define IC_CON_SD		0x0040
+#define IC_CON_RE		0x0020
+#define IC_CON_10BITADDRMASTER	0x0010
+#define IC_CON_10BITADDR_SLAVE	0x0008
+#define IC_CON_SPD_MSK		0x0006
+#define IC_CON_SPD_SS		0x0002
+#define IC_CON_SPD_FS		0x0004
+#define IC_CON_SPD_HS		0x0006
+#define IC_CON_MM		0x0001
+
+/* i2c target address register definitions */
+#define TAR_ADDR		0x0050
+
+/* i2c slave address register definitions */
+#define IC_SLAVE_ADDR		0x0002
+
+/* i2c data buffer and command register definitions */
+#define IC_CMD			0x0100
+
+/* i2c interrupt status register definitions */
+#define IC_GEN_CALL		0x0800
+#define IC_START_DET		0x0400
+#define IC_STOP_DET		0x0200
+#define IC_ACTIVITY		0x0100
+#define IC_RX_DONE		0x0080
+#define IC_TX_ABRT		0x0040
+#define IC_RD_REQ		0x0020
+#define IC_TX_EMPTY		0x0010
+#define IC_TX_OVER		0x0008
+#define IC_RX_FULL		0x0004
+#define IC_RX_OVER 		0x0002
+#define IC_RX_UNDER		0x0001
+
+/* fifo threshold register definitions */
+#define IC_TL0			0x00
+#define IC_TL1			0x01
+#define IC_TL2			0x02
+#define IC_TL3			0x03
+#define IC_TL4			0x04
+#define IC_TL5			0x05
+#define IC_TL6			0x06
+#define IC_TL7			0x07
+#define IC_RX_TL		IC_TL0
+#define IC_TX_TL		IC_TL0
+
+/* i2c enable register definitions */
+#define IC_ENABLE_0B		0x0001
+
+/* i2c status register  definitions */
+#define IC_STATUS_SA		0x0040
+#define IC_STATUS_MA		0x0020
+#define IC_STATUS_RFF		0x0010
+#define IC_STATUS_RFNE		0x0008
+#define IC_STATUS_TFE		0x0004
+#define IC_STATUS_TFNF		0x0002
+#define IC_STATUS_ACT		0x0001
+
+/* Speed Selection */
+#define IC_SPEED_MODE_STANDARD	1
+#define IC_SPEED_MODE_FAST	2
+#define IC_SPEED_MODE_MAX	3
+
+#define I2C_MAX_SPEED		3400000
+#define I2C_FAST_SPEED		400000
+#define I2C_STANDARD_SPEED	100000
+
+#endif /* __SPR_I2C_H_ */
diff --git a/include/asm-arm/arch-spear/spr_misc.h b/include/asm-arm/arch-spear/spr_misc.h
new file mode 100644
index 0000000..8b96d9b
--- /dev/null
+++ b/include/asm-arm/arch-spear/spr_misc.h
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SPR_MISC_H
+#define _SPR_MISC_H
+
+struct misc_regs {
+	u32 auto_cfg_reg;	/* 0x0 */
+	u32 armdbg_ctr_reg;	/* 0x4 */
+	u32 pll1_cntl;		/* 0x8 */
+	u32 pll1_frq;		/* 0xc */
+	u32 pll1_mod;		/* 0x10 */
+	u32 pll2_cntl;		/* 0x14 */
+	u32 pll2_frq;		/* 0x18 */
+	u32 pll2_mod;		/* 0x1C */
+	u32 pll_ctr_reg;	/* 0x20 */
+	u32 amba_clk_cfg;	/* 0x24 */
+	u32 periph_clk_cfg;	/* 0x28 */
+	u32 periph1_clken;	/* 0x2C */
+	u32 periph2_clken;	/* 0x30 */
+	u32 ras_clken;		/* 0x34 */
+	u32 periph1_rst;	/* 0x38 */
+	u32 periph2_rst;	/* 0x3C */
+	u32 ras_rst;		/* 0x40 */
+	u32 prsc1_clk_cfg;	/* 0x44 */
+	u32 prsc2_clk_cfg;	/* 0x48 */
+	u32 prsc3_clk_cfg;	/* 0x4C */
+	u32 amem_cfg_ctrl;	/* 0x50 */
+	u32 port_cfg_ctrl;	/* 0x54 */
+	u32 reserved_1;		/* 0x58 */
+	u32 clcd_synth_clk;	/* 0x5C */
+	u32 irda_synth_clk;	/* 0x60 */
+	u32 uart_synth_clk;	/* 0x64 */
+	u32 gmac_synth_clk;	/* 0x68 */
+	u32 ras_synth1_clk;	/* 0x6C */
+	u32 ras_synth2_clk;	/* 0x70 */
+	u32 ras_synth3_clk;	/* 0x74 */
+	u32 ras_synth4_clk;	/* 0x78 */
+	u32 arb_icm_ml1;	/* 0x7C */
+	u32 arb_icm_ml2;	/* 0x80 */
+	u32 arb_icm_ml3;	/* 0x84 */
+	u32 arb_icm_ml4;	/* 0x88 */
+	u32 arb_icm_ml5;	/* 0x8C */
+	u32 arb_icm_ml6;	/* 0x90 */
+	u32 arb_icm_ml7;	/* 0x94 */
+	u32 arb_icm_ml8;	/* 0x98 */
+	u32 arb_icm_ml9;	/* 0x9C */
+	u32 dma_src_sel;	/* 0xA0 */
+	u32 uphy_ctr_reg;	/* 0xA4 */
+	u32 gmac_ctr_reg;	/* 0xA8 */
+	u32 port_bridge_ctrl;	/* 0xAC */
+	u32 reserved_2[4];	/* 0xB0--0xBC */
+	u32 prc1_ilck_ctrl_reg;	/* 0xC0 */
+	u32 prc2_ilck_ctrl_reg;	/* 0xC4 */
+	u32 prc3_ilck_ctrl_reg;	/* 0xC8 */
+	u32 prc4_ilck_ctrl_reg;	/* 0xCC */
+	u32 prc1_intr_ctrl_reg;	/* 0xD0 */
+	u32 prc2_intr_ctrl_reg;	/* 0xD4 */
+	u32 prc3_intr_ctrl_reg;	/* 0xD8 */
+	u32 prc4_intr_ctrl_reg;	/* 0xDC */
+	u32 powerdown_cfg_reg;	/* 0xE0 */
+	u32 ddr_1v8_compensation;	/* 0xE4  */
+	u32 ddr_2v5_compensation;	/* 0xE8 */
+	u32 core_3v3_compensation;	/* 0xEC */
+	u32 ddr_pad;		/* 0xF0 */
+	u32 bist1_ctr_reg;	/* 0xF4 */
+	u32 bist2_ctr_reg;	/* 0xF8 */
+	u32 bist3_ctr_reg;	/* 0xFC */
+	u32 bist4_ctr_reg;	/* 0x100 */
+	u32 bist5_ctr_reg;	/* 0x104 */
+	u32 bist1_rslt_reg;	/* 0x108 */
+	u32 bist2_rslt_reg;	/* 0x10C */
+	u32 bist3_rslt_reg;	/* 0x110 */
+	u32 bist4_rslt_reg;	/* 0x114 */
+	u32 bist5_rslt_reg;	/* 0x118 */
+	u32 syst_error_reg;	/* 0x11C */
+	u32 reserved_3[0x1FB8];	/* 0x120--0x7FFC */
+	u32 ras_gpp1_in;	/* 0x8000 */
+	u32 ras_gpp2_in;	/* 0x8004 */
+	u32 ras_gpp1_out;	/* 0x8008 */
+	u32 ras_gpp2_out;	/* 0x800C */
+};
+
+/* AUTO_CFG_REG value */
+#define MISC_SOCCFGMSK                  0x0000003F
+#define MISC_SOCCFG30                   0x0000000C
+#define MISC_SOCCFG31                   0x0000000D
+#define MISC_NANDDIS			0x00020000
+
+/* PERIPH_CLK_CFG value */
+#define MISC_GPT3SYNTH			0x00000400
+#define MISC_GPT4SYNTH			0x00000800
+
+/* PRSC_CLK_CFG value */
+/*
+ * Fout = Fin / (2^(N+1) * (M + 1))
+ */
+#define MISC_PRSC_N_1			0x00001000
+#define MISC_PRSC_M_9			0x00000009
+#define MISC_PRSC_N_4			0x00004000
+#define MISC_PRSC_M_399			0x0000018F
+#define MISC_PRSC_N_6			0x00006000
+#define MISC_PRSC_M_2593		0x00000A21
+#define MISC_PRSC_M_124			0x0000007C
+#define MISC_PRSC_CFG			(MISC_PRSC_N_1 | MISC_PRSC_M_9)
+
+/* PERIPH1_CLKEN, PERIPH1_RST value */
+#define MISC_USBDENB			0x01000000
+
+#endif
diff --git a/include/asm-arm/arch-spear/spr_nand.h b/include/asm-arm/arch-spear/spr_nand.h
new file mode 100644
index 0000000..2b63dc7
--- /dev/null
+++ b/include/asm-arm/arch-spear/spr_nand.h
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SPR_NAND_H__
+#define __SPR_NAND_H__
+
+struct fsmc_regs {
+	u32 reserved_1[0x10];
+	u32 genmemctrl_pc;
+	u32 reserved_2;
+	u32 genmemctrl_comm;
+	u32 genmemctrl_attrib;
+	u32 reserved_3;
+	u32 genmemctrl_ecc;
+};
+
+/* genmemctrl_pc register definitions */
+#define FSMC_RESET		(1 << 0)
+#define FSMC_WAITON		(1 << 1)
+#define FSMC_ENABLE		(1 << 2)
+#define FSMC_DEVTYPE_NAND	(1 << 3)
+#define FSMC_DEVWID_8		(0 << 4)
+#define FSMC_DEVWID_16		(1 << 4)
+#define FSMC_ECCEN		(1 << 6)
+#define FSMC_ECCPLEN_512	(0 << 7)
+#define FSMC_ECCPLEN_256	(1 << 7)
+#define FSMC_TCLR_1		(1 << 9)
+#define FSMC_TAR_1		(1 << 13)
+
+/* genmemctrl_comm register definitions */
+#define FSMC_TSET_0		(0 << 0)
+#define FSMC_TWAIT_6		(6 << 8)
+#define FSMC_THOLD_4		(4 << 16)
+#define FSMC_THIZ_1		(1 << 24)
+
+extern int spear_nand_init(struct nand_chip *nand);
+#endif
diff --git a/include/asm-arm/arch-spear/spr_smi.h b/include/asm-arm/arch-spear/spr_smi.h
new file mode 100755
index 0000000..06df745
--- /dev/null
+++ b/include/asm-arm/arch-spear/spr_smi.h
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef SPR_SMI_H
+#define SPR_SMI_H
+
+/* 0xF800.0000 . 0xFBFF.FFFF	64MB	SMI (Serial Flash Mem) */
+/* 0xFC00.0000 . 0xFC1F.FFFF	2MB	SMI (Serial Flash Reg.) */
+
+#define FLASH_START_ADDRESS	CONFIG_SYS_FLASH_BASE
+#define FLASH_BANK_SIZE		CONFIG_SYS_FLASH_BANK_SIZE
+
+#define SMIBANK0_BASE		(FLASH_START_ADDRESS)
+#define SMIBANK1_BASE		(SMIBANK0_BASE + FLASH_BANK_SIZE)
+#define SMIBANK2_BASE		(SMIBANK1_BASE + FLASH_BANK_SIZE)
+#define SMIBANK3_BASE		(SMIBANK2_BASE + FLASH_BANK_SIZE)
+
+#define BANK0			0
+#define BANK1			1
+#define BANK2			2
+#define BANK3			3
+
+struct smi_regs {
+	u32 smi_cr1;
+	u32 smi_cr2;
+	u32 smi_sr;
+	u32 smi_tr;
+	u32 smi_rr;
+};
+
+/* CONTROL REG 1 */
+#define BANK_EN			0x0000000F	/* enables all banks */
+#define DSEL_TIME		0x00000060	/* Deselect time */
+#define PRESCAL5		0x00000500	/* AHB_CK prescaling value */
+#define PRESCALA		0x00000A00	/* AHB_CK prescaling value */
+#define PRESCAL3		0x00000300	/* AHB_CK prescaling value */
+#define PRESCAL4		0x00000400	/* AHB_CK prescaling value */
+#define SW_MODE			0x10000000	/* enables SW Mode */
+#define WB_MODE			0x20000000	/* Write Burst Mode */
+#define FAST_MODE		0x00008000	/* Fast Mode */
+#define HOLD1			0x00010000
+
+/* CONTROL REG 2 */
+#define RD_STATUS_REG		0x00000400	/* reads status reg */
+#define WE			0x00000800	/* Write Enable */
+#define BANK0_SEL		0x00000000	/* Select Banck0 */
+#define BANK1_SEL		0x00001000	/* Select Banck1 */
+#define BANK2_SEL		0x00002000	/* Select Banck2 */
+#define BANK3_SEL		0x00003000	/* Select Banck3 */
+#define BANKSEL_SHIFT		12
+#define SEND			0x00000080	/* Send data */
+#define TX_LEN_1		0x00000001	/* data length = 1 byte */
+#define TX_LEN_2		0x00000002	/* data length = 2 byte */
+#define TX_LEN_3		0x00000003	/* data length = 3 byte */
+#define TX_LEN_4		0x00000004	/* data length = 4 byte */
+#define RX_LEN_1		0x00000010	/* data length = 1 byte */
+#define RX_LEN_2		0x00000020	/* data length = 2 byte */
+#define RX_LEN_3		0x00000030	/* data length = 3 byte */
+#define RX_LEN_4		0x00000040	/* data length = 4 byte */
+#define TFIE			0x00000100	/* Tx Flag Interrupt Enable */
+#define WCIE			0x00000200	/* WCF Interrupt Enable */
+
+/* STATUS_REG */
+#define INT_WCF_CLR		0xFFFFFDFF	/* clear: WCF clear */
+#define INT_TFF_CLR		0xFFFFFEFF	/* clear: TFF clear */
+#define WIP_BIT			0x00000001	/* WIP Bit of SPI SR */
+#define WEL_BIT			0x00000002	/* WEL Bit of SPI SR */
+#define RSR			0x00000005	/* Read Status regiser */
+#define TFF			0x00000100	/* Transfer Finished FLag */
+#define WCF			0x00000200	/* Transfer Finished FLag */
+#define ERF1			0x00000400	/* Error Flag 1 */
+#define ERF2			0x00000800	/* Error Flag 2 */
+#define WM0			0x00001000	/* WM Bank 0 */
+#define WM1			0x00002000	/* WM Bank 1 */
+#define WM2			0x00004000	/* WM Bank 2 */
+#define WM3			0x00008000	/* WM Bank 3 */
+#define WM_SHIFT		12
+
+/* TR REG */
+#define READ_ID			0x0000009F	/* Read Identification */
+#define BULK_ERASE		0x000000C7	/* BULK erase */
+#define SECTOR_ERASE		0x000000D8	/* SECTOR erase */
+#define WRITE_ENABLE		0x00000006	/* Wenable command to FLASH */
+
+struct flash_dev {
+	u32 density;
+	ulong size;
+	ushort sector_count;
+};
+
+#define SFLASH_PAGE_SIZE	0x100	/* flash page size */
+#define XFER_FINISH_TOUT	2	/* xfer finish timeout */
+#define WMODE_TOUT		2	/* write enable timeout */
+
+#endif
diff --git a/include/asm-arm/arch-spear/spr_syscntl.h b/include/asm-arm/arch-spear/spr_syscntl.h
new file mode 100644
index 0000000..3c92f09
--- /dev/null
+++ b/include/asm-arm/arch-spear/spr_syscntl.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2009
+ * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+struct syscntl_regs {
+	u32 scctrl;
+	u32 scsysstat;
+	u32 scimctrl;
+	u32 scimsysstat;
+	u32 scxtalctrl;
+	u32 scpllctrl;
+	u32 scpllfctrl;
+	u32 scperctrl0;
+	u32 scperctrl1;
+	u32 scperen;
+	u32 scperdis;
+	const u32 scperclken;
+	const u32 scperstat;
+};
diff --git a/include/asm-arm/arch-spear/spr_xloader_table.h b/include/asm-arm/arch-spear/spr_xloader_table.h
new file mode 100755
index 0000000..7e3da18
--- /dev/null
+++ b/include/asm-arm/arch-spear/spr_xloader_table.h
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SPR_XLOADER_TABLE_H
+#define _SPR_XLOADER_TABLE_H
+
+#define XLOADER_TABLE_VERSION_1_1	2
+#define XLOADER_TABLE_VERSION_1_2	3
+
+#define XLOADER_TABLE_ADDRESS		0xD2801FF0
+
+#define DDRMOBILE	1
+#define DDR2		2
+
+#define REV_BA		1
+#define REV_AA		2
+#define REV_AB		3
+
+struct xloader_table_1_1 {
+	unsigned short ddrfreq;
+	unsigned char ddrsize;
+	unsigned char ddrtype;
+
+	unsigned char soc_rev;
+} __attribute__ ((packed));
+
+struct xloader_table_1_2 {
+	unsigned const char *version;
+
+	unsigned short ddrfreq;
+	unsigned char ddrsize;
+	unsigned char ddrtype;
+
+	unsigned char soc_rev;
+} __attribute__ ((packed));
+
+union table_contents {
+	struct xloader_table_1_1 table_1_1;
+	struct xloader_table_1_2 table_1_2;
+};
+
+struct xloader_table {
+	unsigned char table_version;
+	union table_contents table;
+} __attribute__ ((packed));
+
+#endif
diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
index 2898618..3b46327 100644
--- a/include/asm-arm/mach-types.h
+++ b/include/asm-arm/mach-types.h
@@ -2594,6 +2594,33 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_ELTD100              2611
 #define MACH_TYPE_CAPC7117             2612
 #define MACH_TYPE_SWAN                 2613
+#define MACH_TYPE_VEU                  2614
+#define MACH_TYPE_RM2                  2615
+#define MACH_TYPE_TT2100               2616
+#define MACH_TYPE_VENICE               2617
+#define MACH_TYPE_PC7323               2618
+#define MACH_TYPE_MASP                 2619
+#define MACH_TYPE_FUJITSU_TVSTBSOC     2620
+#define MACH_TYPE_FUJITSU_TVSTBSOC1    2621
+#define MACH_TYPE_LEXIKON              2622
+#define MACH_TYPE_MINI2440V2           2623
+#define MACH_TYPE_ICONTROL             2624
+#define MACH_TYPE_SHEEVAD              2625
+#define MACH_TYPE_QSD8X50A_ST1_1       2626
+#define MACH_TYPE_QSD8X50A_ST1_5       2627
+#define MACH_TYPE_BEE                  2628
+#define MACH_TYPE_MX23EVK              2629
+#define MACH_TYPE_AP4EVB               2630
+#define MACH_TYPE_STOCKHOLM            2631
+#define MACH_TYPE_LPC_H3131            2632
+#define MACH_TYPE_STINGRAY             2633
+#define MACH_TYPE_KRAKEN               2634
+#define MACH_TYPE_GW2388               2635
+#define MACH_TYPE_JADECPU              2636
+#define MACH_TYPE_CARLISLE             2637
+#define MACH_TYPE_LUX_SFT9             2638
+#define MACH_TYPE_NEMID_TB             2639
+#define MACH_TYPE_TERRIER              2640
 
 #ifdef CONFIG_ARCH_EBSA110
 # ifdef machine_arch_type
@@ -33579,6 +33606,330 @@ extern unsigned int __machine_arch_type;
 # define machine_is_swan()	(0)
 #endif
 
+#ifdef CONFIG_MACH_VEU
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VEU
+# endif
+# define machine_is_veu()	(machine_arch_type == MACH_TYPE_VEU)
+#else
+# define machine_is_veu()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RM2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RM2
+# endif
+# define machine_is_rm2()	(machine_arch_type == MACH_TYPE_RM2)
+#else
+# define machine_is_rm2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TT2100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TT2100
+# endif
+# define machine_is_tt2100()	(machine_arch_type == MACH_TYPE_TT2100)
+#else
+# define machine_is_tt2100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VENICE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VENICE
+# endif
+# define machine_is_venice()	(machine_arch_type == MACH_TYPE_VENICE)
+#else
+# define machine_is_venice()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PC7323
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PC7323
+# endif
+# define machine_is_pc7323()	(machine_arch_type == MACH_TYPE_PC7323)
+#else
+# define machine_is_pc7323()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MASP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MASP
+# endif
+# define machine_is_masp()	(machine_arch_type == MACH_TYPE_MASP)
+#else
+# define machine_is_masp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FUJITSU_TVSTBSOC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FUJITSU_TVSTBSOC
+# endif
+# define machine_is_fujitsu_tvstbsoc0()	(machine_arch_type == MACH_TYPE_FUJITSU_TVSTBSOC)
+#else
+# define machine_is_fujitsu_tvstbsoc0()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FUJITSU_TVSTBSOC1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FUJITSU_TVSTBSOC1
+# endif
+# define machine_is_fujitsu_tvstbsoc1()	(machine_arch_type == MACH_TYPE_FUJITSU_TVSTBSOC1)
+#else
+# define machine_is_fujitsu_tvstbsoc1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LEXIKON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LEXIKON
+# endif
+# define machine_is_lexikon()	(machine_arch_type == MACH_TYPE_LEXIKON)
+#else
+# define machine_is_lexikon()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MINI2440V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MINI2440V2
+# endif
+# define machine_is_mini2440v2()	(machine_arch_type == MACH_TYPE_MINI2440V2)
+#else
+# define machine_is_mini2440v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ICONTROL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ICONTROL
+# endif
+# define machine_is_icontrol()	(machine_arch_type == MACH_TYPE_ICONTROL)
+#else
+# define machine_is_icontrol()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SHEEVAD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SHEEVAD
+# endif
+# define machine_is_sheevad()	(machine_arch_type == MACH_TYPE_SHEEVAD)
+#else
+# define machine_is_sheevad()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QSD8X50A_ST1_1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QSD8X50A_ST1_1
+# endif
+# define machine_is_qsd8x50a_st1_1()	(machine_arch_type == MACH_TYPE_QSD8X50A_ST1_1)
+#else
+# define machine_is_qsd8x50a_st1_1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QSD8X50A_ST1_5
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QSD8X50A_ST1_5
+# endif
+# define machine_is_qsd8x50a_st1_5()	(machine_arch_type == MACH_TYPE_QSD8X50A_ST1_5)
+#else
+# define machine_is_qsd8x50a_st1_5()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BEE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BEE
+# endif
+# define machine_is_bee()	(machine_arch_type == MACH_TYPE_BEE)
+#else
+# define machine_is_bee()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX23EVK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX23EVK
+# endif
+# define machine_is_mx23evk()	(machine_arch_type == MACH_TYPE_MX23EVK)
+#else
+# define machine_is_mx23evk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AP4EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AP4EVB
+# endif
+# define machine_is_ap4evb()	(machine_arch_type == MACH_TYPE_AP4EVB)
+#else
+# define machine_is_ap4evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_STOCKHOLM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STOCKHOLM
+# endif
+# define machine_is_stockholm()	(machine_arch_type == MACH_TYPE_STOCKHOLM)
+#else
+# define machine_is_stockholm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LPC_H3131
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LPC_H3131
+# endif
+# define machine_is_lpc_h3131()	(machine_arch_type == MACH_TYPE_LPC_H3131)
+#else
+# define machine_is_lpc_h3131()	(0)
+#endif
+
+#ifdef CONFIG_MACH_STINGRAY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STINGRAY
+# endif
+# define machine_is_stingray()	(machine_arch_type == MACH_TYPE_STINGRAY)
+#else
+# define machine_is_stingray()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KRAKEN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KRAKEN
+# endif
+# define machine_is_kraken()	(machine_arch_type == MACH_TYPE_KRAKEN)
+#else
+# define machine_is_kraken()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GW2388
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GW2388
+# endif
+# define machine_is_gw2388()	(machine_arch_type == MACH_TYPE_GW2388)
+#else
+# define machine_is_gw2388()	(0)
+#endif
+
+#ifdef CONFIG_MACH_JADECPU
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_JADECPU
+# endif
+# define machine_is_jadecpu()	(machine_arch_type == MACH_TYPE_JADECPU)
+#else
+# define machine_is_jadecpu()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CARLISLE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CARLISLE
+# endif
+# define machine_is_carlisle()	(machine_arch_type == MACH_TYPE_CARLISLE)
+#else
+# define machine_is_carlisle()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LUX_SFT9
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LUX_SFT9
+# endif
+# define machine_is_lux_sft9()	(machine_arch_type == MACH_TYPE_LUX_SFT9)
+#else
+# define machine_is_lux_sft9()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NEMID_TB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NEMID_TB
+# endif
+# define machine_is_nemid_tb()	(machine_arch_type == MACH_TYPE_NEMID_TB)
+#else
+# define machine_is_nemid_tb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TERRIER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TERRIER
+# endif
+# define machine_is_terrier()	(machine_arch_type == MACH_TYPE_TERRIER)
+#else
+# define machine_is_terrier()	(0)
+#endif
+
 /*
  * These have not yet been registered
  */
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index ab5cbca..c3255fa 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -48,6 +48,7 @@
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_MISC_INIT_R			/* Call misc_init_r */
 
 #define CONFIG_ARCH_CPU_INIT
 
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index bf0ee67..a8ba052 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -47,8 +47,6 @@
 
 #undef CONFIG_SKIP_RELOCATE_UBOOT
 
-#define CONFIG_L2_OFF
-
 /* input clock of PLL: SMDKC100 has 12MHz input clock */
 #define CONFIG_SYS_CLK_FREQ		12000000
 
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
new file mode 100644
index 0000000..cc52e39
--- /dev/null
+++ b/include/configs/spear-common.h
@@ -0,0 +1,213 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SPEAR_COMMON_H
+#define _SPEAR_COMMON_H
+/*
+ * Common configurations used for both spear3xx as well as spear6xx
+ */
+
+/* USBD driver configuration */
+#define CONFIG_SPEARUDC
+#define CONFIG_USB_DEVICE
+#define CONFIG_USB_TTY
+
+#define CONFIG_USBD_PRODUCT_NAME		"SPEAr SoC"
+#define CONFIG_USBD_MANUFACTURER		"ST Microelectronics"
+
+#define CONFIG_EXTRA_ENV_USBTTY			"usbtty=cdc_acm\0"
+
+/* I2C driver configuration */
+#define CONFIG_HARD_I2C
+#define CONFIG_SPEAR_I2C
+#define CONFIG_SYS_I2C_SPEED			400000
+#define CONFIG_SYS_I2C_SLAVE			0x02
+
+#define CONFIG_I2C_CHIPADDRESS			0x50
+
+/* Timer, HZ specific defines */
+#define CONFIG_SYS_HZ				(1000)
+#define CONFIG_SYS_HZ_CLOCK			(8300000)
+
+/* Flash configuration */
+#if defined(CONFIG_FLASH_PNOR)
+#define CONFIG_SPEAR_EMI			1
+#else
+#define CONFIG_SPEARSMI				1
+#endif
+
+#if defined(CONFIG_SPEARSMI)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS		2
+#define CONFIG_SYS_FLASH_BASE			(0xF8000000)
+#define CONFIG_SYS_CS1_FLASH_BASE		(0xF9000000)
+#define CONFIG_SYS_FLASH_BANK_SIZE		(0x01000000)
+#define CONFIG_SYS_FLASH_ADDR_BASE		{CONFIG_SYS_FLASH_BASE, \
+						CONFIG_SYS_CS1_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_SECT		128
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		1
+#define CONFIG_SYS_FLASH_ERASE_TOUT		(3 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT		(3 * CONFIG_SYS_HZ)
+
+#endif
+
+/*
+ * Serial Configuration (PL011)
+ * CONFIG_PL01x_PORTS is defined in specific files
+ */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK			(48 * 1000 * 1000)
+#define CONFIG_CONS_INDEX			0
+#define CONFIG_BAUDRATE				115200
+#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, \
+						57600, 115200 }
+
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/* NAND FLASH Configuration */
+#define CONFIG_NAND_SPEAR			1
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_MTD_NAND_VERIFY_WRITE		1
+
+/*
+ * Command support defines
+ */
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVES
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+/*
+ * Default Environment Varible definitions
+ */
+#if defined(CONFIG_SPEAR_USBTTY)
+#define CONFIG_BOOTDELAY			-1
+#else
+#define CONFIG_BOOTDELAY			1
+#endif
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * U-Boot Environment placing definitions.
+ */
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+#ifdef CONFIG_SPEARSMI
+/*
+ * Environment is in serial NOR flash
+ */
+#define CONFIG_SYS_MONITOR_LEN			0x00040000
+#define CONFIG_ENV_SECT_SIZE			0x00010000
+#define CONFIG_FSMTDBLK				"/dev/mtdblock8 "
+
+#define CONFIG_BOOTCOMMAND			"bootm 0xf8050000"
+
+#elif defined(CONFIG_SPEAR_EMI)
+/*
+ * Environment is in parallel NOR flash
+ */
+#define CONFIG_SYS_MONITOR_LEN			0x00060000
+#define CONFIG_ENV_SECT_SIZE			0x00020000
+#define CONFIG_FSMTDBLK				"/dev/mtdblock3 "
+
+#define CONFIG_BOOTCOMMAND			"cp.b 0x50080000 0x1600000 " \
+						"0x4C0000; bootm 0x1600000"
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_FLASH_BASE
+#define CONFIG_ENV_ADDR				(CONFIG_SYS_MONITOR_BASE + \
+						CONFIG_SYS_MONITOR_LEN)
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+/*
+ * Environment is in NAND
+ */
+
+#define CONFIG_ENV_OFFSET			0x60000
+#define CONFIG_ENV_RANGE			0x10000
+#define CONFIG_FSMTDBLK				"/dev/mtdblock12 "
+
+#define CONFIG_BOOTCOMMAND			"nand read.jffs2 0x1600000 " \
+						"0x80000 0x4C0000; " \
+						"bootm 0x1600000"
+#endif
+
+#define CONFIG_BOOTARGS_NFS			"root=/dev/nfs ip=dhcp " \
+						"console=ttyS0 init=/bin/sh"
+#define CONFIG_BOOTARGS				"console=ttyS0 mem=128M "  \
+						"root="CONFIG_FSMTDBLK \
+						"rootfstype=jffs2"
+
+#define CONFIG_ENV_SIZE				0x02000
+
+/* Miscellaneous configurable options */
+#define CONFIG_BOOT_PARAMS_ADDR			0x00000100
+#define CONFIG_CMDLINE_TAG			1
+#define CONFIG_SETUP_MEMORY_TAGS		1
+#define CONFIG_MISC_INIT_R			1
+#define CONFIG_ZERO_BOOTDELAY_CHECK		1
+#define CONFIG_AUTOBOOT_KEYED			1
+#define CONFIG_AUTOBOOT_STOP_STR		" "
+#define CONFIG_AUTOBOOT_PROMPT			\
+		"Hit SPACE in %d seconds to stop autoboot.\n", bootdelay
+
+#define CONFIG_SYS_MEMTEST_START		0x00800000
+#define CONFIG_SYS_MEMTEST_END			0x04000000
+#define CONFIG_SYS_MALLOC_LEN			(1024*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE		128
+#define CONFIG_IDENT_STRING			"-SPEAr"
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT			"u-boot> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + \
+						sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LOAD_ADDR			0x00800000
+#define CONFIG_SYS_CONSOLE_INFO_QUIET		1
+#define CONFIG_SYS_64BIT_VSPRINTF		1
+
+#define CONFIG_EXTRA_ENV_SETTINGS		CONFIG_EXTRA_ENV_USBTTY
+
+/* Stack sizes */
+#define CONFIG_STACKSIZE			(128*1024)
+
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ			(4*1024)
+#define CONFIG_STACKSIZE_FIQ			(4*1024)
+#endif
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS			1
+#define PHYS_SDRAM_1				0x00000000
+#define PHYS_SDRAM_1_MAXSIZE			0x40000000
+
+#endif
diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h
new file mode 100755
index 0000000..0248aba
--- /dev/null
+++ b/include/configs/spear3xx.h
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#if defined(CONFIG_MK_spear300)
+#define CONFIG_SPEAR3XX				1
+#define CONFIG_SPEAR300				1
+#elif defined(CONFIG_MK_spear310)
+#define CONFIG_SPEAR3XX				1
+#define CONFIG_SPEAR310				1
+#elif defined(CONFIG_MK_spear320)
+#define CONFIG_SPEAR3XX				1
+#define CONFIG_SPEAR320				1
+#endif
+
+#include <configs/spear-common.h>
+
+/* Serial Configuration (PL011) */
+#define CONFIG_SYS_SERIAL0			0xD0000000
+
+#if defined(CONFIG_SPEAR300)
+#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0}
+
+#elif defined(CONFIG_SPEAR310)
+
+#if (CONFIG_CONS_INDEX)
+#undef  CONFIG_PL011_CLOCK
+#define CONFIG_PL011_CLOCK			(83 * 1000 * 1000)
+#endif
+
+#define CONFIG_SYS_SERIAL1			0xB2000000
+#define CONFIG_SYS_SERIAL2			0xB2080000
+#define CONFIG_SYS_SERIAL3			0xB2100000
+#define CONFIG_SYS_SERIAL4			0xB2180000
+#define CONFIG_SYS_SERIAL5			0xB2200000
+#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0, \
+						(void *)CONFIG_SYS_SERIAL1, \
+						(void *)CONFIG_SYS_SERIAL2, \
+						(void *)CONFIG_SYS_SERIAL3, \
+						(void *)CONFIG_SYS_SERIAL4, \
+						(void *)CONFIG_SYS_SERIAL5 }
+#elif defined(CONFIG_SPEAR320)
+
+#if (CONFIG_CONS_INDEX)
+#undef  CONFIG_PL011_CLOCK
+#define CONFIG_PL011_CLOCK			(83 * 1000 * 1000)
+#endif
+
+#define CONFIG_SYS_SERIAL1			0xA3000000
+#define CONFIG_SYS_SERIAL2			0xA4000000
+#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0, \
+						(void *)CONFIG_SYS_SERIAL1, \
+						(void *)CONFIG_SYS_SERIAL2 }
+#endif
+
+#if defined(CONFIG_SPEAR_EMI)
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#if defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_FLASH_BASE			0x50000000
+#define CONFIG_SYS_CS1_FLASH_BASE		0x60000000
+#define CONFIG_SYS_CS2_FLASH_BASE		0x70000000
+#define CONFIG_SYS_CS3_FLASH_BASE		0x80000000
+#define CONFIG_SYS_CS4_FLASH_BASE		0x90000000
+#define CONFIG_SYS_CS5_FLASH_BASE		0xA0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST		{ CONFIG_SYS_FLASH_BASE,   \
+						CONFIG_SYS_CS1_FLASH_BASE, \
+						CONFIG_SYS_CS2_FLASH_BASE, \
+						CONFIG_SYS_CS3_FLASH_BASE, \
+						CONFIG_SYS_CS4_FLASH_BASE, \
+						CONFIG_SYS_CS5_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS		6
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_FLASH_BASE			0x44000000
+#define CONFIG_SYS_CS1_FLASH_BASE		0x45000000
+#define CONFIG_SYS_CS2_FLASH_BASE		0x46000000
+#define CONFIG_SYS_CS3_FLASH_BASE		0x47000000
+#define CONFIG_SYS_FLASH_BANKS_LIST		{ CONFIG_SYS_FLASH_BASE,   \
+						CONFIG_SYS_CS1_FLASH_BASE, \
+						CONFIG_SYS_CS2_FLASH_BASE, \
+						CONFIG_SYS_CS3_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS		4
+
+#endif
+
+#define CONFIG_SYS_MAX_FLASH_SECT		(127 + 8)
+#define CONFIG_SYS_FLASH_QUIET_TEST		1
+
+#endif
+
+#if defined(CONFIG_SPEAR300)
+#define CONFIG_SYS_NAND_BASE			(0x80000000)
+
+#elif defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_NAND_BASE			(0x40000000)
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_NAND_BASE			(0x50000000)
+
+#endif
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/spear6xx.h b/include/configs/spear6xx.h
new file mode 100755
index 0000000..2ad5beb
--- /dev/null
+++ b/include/configs/spear6xx.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SPEAR600				1
+
+#include <configs/spear-common.h>
+
+/* Serial Configuration (PL011) */
+#define CONFIG_SYS_SERIAL0			0xD0000000
+#define CONFIG_SYS_SERIAL1			0xD0080000
+#define CONFIG_PL01x_PORTS			{ (void *)CONFIG_SYS_SERIAL0, \
+						(void *)CONFIG_SYS_SERIAL1 }
+
+#define CONFIG_SYS_NAND_BASE			(0xD2000000)
+
+#endif  /* __CONFIG_H */
diff --git a/include/usb/spr_udc.h b/include/usb/spr_udc.h
new file mode 100755
index 0000000..2c332d5
--- /dev/null
+++ b/include/usb/spr_udc.h
@@ -0,0 +1,230 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SPR_UDC_H
+#define __SPR_UDC_H
+
+/*
+ * Defines for  USBD
+ *
+ * The udc_ahb controller has three AHB slaves:
+ *
+ * 1.  THe UDC registers
+ * 2.  The plug detect
+ * 3.  The RX/TX FIFO
+ */
+
+#define MAX_ENDPOINTS		16
+
+struct udc_endp_regs {
+	u32 endp_cntl;
+	u32 endp_status;
+	u32 endp_bsorfn;
+	u32 endp_maxpacksize;
+	u32 reserved_1;
+	u32 endp_desc_point;
+	u32 reserved_2;
+	u32 write_done;
+};
+
+/* Endpoint Control Register definitions */
+
+#define  ENDP_CNTL_STALL		0x00000001
+#define  ENDP_CNTL_FLUSH		0x00000002
+#define  ENDP_CNTL_SNOOP		0x00000004
+#define  ENDP_CNTL_POLL			0x00000008
+#define  ENDP_CNTL_CONTROL		0x00000000
+#define  ENDP_CNTL_ISO			0x00000010
+#define  ENDP_CNTL_BULK			0x00000020
+#define  ENDP_CNTL_INT			0x00000030
+#define  ENDP_CNTL_NAK			0x00000040
+#define  ENDP_CNTL_SNAK			0x00000080
+#define  ENDP_CNTL_CNAK			0x00000100
+#define  ENDP_CNTL_RRDY			0x00000200
+
+/* Endpoint Satus Register definitions */
+
+#define  ENDP_STATUS_PIDMSK		0x0000000f
+#define  ENDP_STATUS_OUTMSK		0x00000030
+#define  ENDP_STATUS_OUT_NONE		0x00000000
+#define  ENDP_STATUS_OUT_DATA		0x00000010
+#define  ENDP_STATUS_OUT_SETUP		0x00000020
+#define  ENDP_STATUS_IN			0x00000040
+#define  ENDP_STATUS_BUFFNAV		0x00000080
+#define  ENDP_STATUS_FATERR		0x00000100
+#define  ENDP_STATUS_HOSTBUSERR		0x00000200
+#define  ENDP_STATUS_TDC		0x00000400
+#define  ENDP_STATUS_RXPKTMSK		0x003ff800
+
+struct udc_regs {
+	struct udc_endp_regs in_regs[MAX_ENDPOINTS];
+	struct udc_endp_regs out_regs[MAX_ENDPOINTS];
+	u32 dev_conf;
+	u32 dev_cntl;
+	u32 dev_stat;
+	u32 dev_int;
+	u32 dev_int_mask;
+	u32 endp_int;
+	u32 endp_int_mask;
+	u32 reserved_3[0x39];
+	u32 reserved_4;		/* offset 0x500 */
+	u32 udc_endp_reg[MAX_ENDPOINTS];
+};
+
+/* Device Configuration Register definitions */
+
+#define  DEV_CONF_HS_SPEED		0x00000000
+#define  DEV_CONF_LS_SPEED		0x00000002
+#define  DEV_CONF_FS_SPEED		0x00000003
+#define  DEV_CONF_REMWAKEUP		0x00000004
+#define  DEV_CONF_SELFPOW		0x00000008
+#define  DEV_CONF_SYNCFRAME		0x00000010
+#define  DEV_CONF_PHYINT_8		0x00000020
+#define  DEV_CONF_PHYINT_16		0x00000000
+#define  DEV_CONF_UTMI_BIDIR		0x00000040
+#define  DEV_CONF_STATUS_STALL		0x00000080
+
+/* Device Control Register definitions */
+
+#define  DEV_CNTL_RESUME		0x00000001
+#define  DEV_CNTL_TFFLUSH		0x00000002
+#define  DEV_CNTL_RXDMAEN		0x00000004
+#define  DEV_CNTL_TXDMAEN		0x00000008
+#define  DEV_CNTL_DESCRUPD		0x00000010
+#define  DEV_CNTL_BIGEND		0x00000020
+#define  DEV_CNTL_BUFFILL		0x00000040
+#define  DEV_CNTL_TSHLDEN		0x00000080
+#define  DEV_CNTL_BURSTEN		0x00000100
+#define  DEV_CNTL_DMAMODE		0x00000200
+#define  DEV_CNTL_SOFTDISCONNECT	0x00000400
+#define  DEV_CNTL_SCALEDOWN		0x00000800
+#define  DEV_CNTL_BURSTLENU		0x00010000
+#define  DEV_CNTL_BURSTLENMSK		0x00ff0000
+#define  DEV_CNTL_TSHLDLENU		0x01000000
+#define  DEV_CNTL_TSHLDLENMSK		0xff000000
+
+/* Device Status Register definitions */
+
+#define  DEV_STAT_CFG			0x0000000f
+#define  DEV_STAT_INTF			0x000000f0
+#define  DEV_STAT_ALT			0x00000f00
+#define  DEV_STAT_SUSP			0x00001000
+#define  DEV_STAT_ENUM			0x00006000
+#define  DEV_STAT_ENUM_SPEED_HS		0x00000000
+#define  DEV_STAT_ENUM_SPEED_FS		0x00002000
+#define  DEV_STAT_ENUM_SPEED_LS		0x00004000
+#define  DEV_STAT_RXFIFO_EMPTY		0x00008000
+#define  DEV_STAT_PHY_ERR		0x00010000
+#define  DEV_STAT_TS			0xf0000000
+
+/* Device Interrupt Register definitions */
+
+#define  DEV_INT_MSK			0x0000007f
+#define  DEV_INT_SETCFG			0x00000001
+#define  DEV_INT_SETINTF		0x00000002
+#define  DEV_INT_INACTIVE		0x00000004
+#define  DEV_INT_USBRESET		0x00000008
+#define  DEV_INT_SUSPUSB		0x00000010
+#define  DEV_INT_SOF			0x00000020
+#define  DEV_INT_ENUM			0x00000040
+
+/* Endpoint Interrupt Register definitions */
+
+#define  ENDP0_INT_CTRLIN		0x00000001
+#define  ENDP1_INT_BULKIN		0x00000002
+#define  ENDP_INT_NONISOIN_MSK		0x0000AAAA
+#define  ENDP2_INT_BULKIN		0x00000004
+#define  ENDP0_INT_CTRLOUT		0x00010000
+#define  ENDP1_INT_BULKOUT		0x00020000
+#define  ENDP2_INT_BULKOUT		0x00040000
+#define  ENDP_INT_NONISOOUT_MSK		0x55540000
+
+/* Endpoint Register definitions */
+#define  ENDP_EPDIR_OUT			0x00000000
+#define  ENDP_EPDIR_IN			0x00000010
+#define  ENDP_EPTYPE_CNTL		0x0
+#define  ENDP_EPTYPE_ISO		0x1
+#define  ENDP_EPTYPE_BULK		0x2
+#define  ENDP_EPTYPE_INT		0x3
+
+/*
+ * Defines for Plug Detect
+ */
+
+struct plug_regs {
+	u32 plug_state;
+	u32 plug_pending;
+};
+
+/* Plug State Register definitions */
+#define  PLUG_STATUS_EN			0x1
+#define  PLUG_STATUS_ATTACHED		0x2
+#define  PLUG_STATUS_PHY_RESET		0x4
+#define  PLUG_STATUS_PHY_MODE		0x8
+
+/*
+ * Defines for UDC FIFO (Slave Mode)
+ */
+struct udcfifo_regs {
+	u32 *fifo_p;
+};
+
+/*
+ * USBTTY definitions
+ */
+#define  EP0_MAX_PACKET_SIZE		64
+#define  UDC_INT_ENDPOINT		1
+#define  UDC_INT_PACKET_SIZE		64
+#define  UDC_OUT_ENDPOINT		2
+#define  UDC_BULK_PACKET_SIZE		64
+#define  UDC_IN_ENDPOINT		3
+#define  UDC_OUT_PACKET_SIZE		64
+#define  UDC_IN_PACKET_SIZE		64
+
+/*
+ * UDC endpoint definitions
+ */
+#define  UDC_EP0			0
+#define  UDC_EP1			1
+#define  UDC_EP2			2
+#define  UDC_EP3			3
+
+/*
+ * Function declarations
+ */
+
+void udc_irq(void);
+
+void udc_set_nak(int epid);
+void udc_unset_nak(int epid);
+int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
+int udc_init(void);
+void udc_enable(struct usb_device_instance *device);
+void udc_disable(void);
+void udc_connect(void);
+void udc_disconnect(void);
+void udc_startup_events(struct usb_device_instance *device);
+void udc_setup_ep(struct usb_device_instance *device, unsigned int ep,
+		  struct usb_endpoint_instance *endpoint);
+
+#endif /* __SPR_UDC_H */