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| author | Kumar Gala <galak@kernel.crashing.org> | 2006-01-12 15:45:58 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2006-01-12 15:45:58 -0600 |
| commit | bc680b12d0021a1d6f9a7fc1163902007ec971e0 (patch) | |
| tree | 482c7e28ad3a08fcb22fc2281c5b771f3dac3a02 /include | |
| parent | c7428d49ace4f2f16174ca028fe7072c02a473c8 (diff) | |
| download | u-boot-imx-bc680b12d0021a1d6f9a7fc1163902007ec971e0.zip u-boot-imx-bc680b12d0021a1d6f9a7fc1163902007ec971e0.tar.gz u-boot-imx-bc680b12d0021a1d6f9a7fc1163902007ec971e0.tar.bz2 | |
Added PCI support for MPC8349ADS board
Patch by Kumar Gala 11 Jan 2006
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/mpc8349_pci.h | 1 | ||||
| -rw-r--r-- | include/configs/MPC8349ADS.h | 18 |
2 files changed, 13 insertions, 6 deletions
diff --git a/include/asm-ppc/mpc8349_pci.h b/include/asm-ppc/mpc8349_pci.h index 48255a3..7a1adba 100644 --- a/include/asm-ppc/mpc8349_pci.h +++ b/include/asm-ppc/mpc8349_pci.h @@ -77,6 +77,7 @@ #define POCMR_ENABLE 0x80000000 #define POCMR_PCI_IO 0x40000000 #define POCMR_PREFETCH_EN 0x20000000 +#define POCMR_PCI2 0x10000000 /* Soft PCI reset */ diff --git a/include/configs/MPC8349ADS.h b/include/configs/MPC8349ADS.h index d6d2fab..1849957 100644 --- a/include/configs/MPC8349ADS.h +++ b/include/configs/MPC8349ADS.h @@ -41,9 +41,8 @@ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_MPC8349ADS 1 /* MPC8349ADS board specific */ -/* FIXME: Real PCI support will come in a follow-up update. */ -#undef CONFIG_PCI - +#define CONFIG_PCI +#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -324,16 +323,23 @@ * General PCI * Addresses are mapped 1-1. */ + #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_MMIO_BASE 0x90000000 +#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE +#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ #define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe2000000 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ -#define CFG_PCI2_MEM_BASE 0xA0000000 +#define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_MMIO_BASE 0xb0000000 +#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE +#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ #define CFG_PCI2_IO_BASE 0x00000000 #define CFG_PCI2_IO_PHYS 0xe3000000 #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ |