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authorStefan Roese <sr@denx.de>2010-09-12 06:21:37 +0200
committerStefan Roese <sr@denx.de>2010-09-23 09:02:05 +0200
commitafabb498b749b48ca3ee7e833fe1501e2d6993cb (patch)
treea5e131d0d7f62e41bd9bc1c767452b43b75bf82e /include
parent5e7abce99163a00b8d267cc8045f06b498728288 (diff)
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ppc4xx: Big header cleanup part 2, mostly PPC405 related
This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. As a part from this cleanup, the GPIO definitions for PPC405EP are corrected. The high and low parts of the registers (for example CONFIG_SYS_GPIO0_OSRL vs. CONFIG_SYS_GPIO0_OSRH) have been defined in the wrong order. This patch now fixes this issue by switching these xxxH and xxxL values. This brings the GPIO 405EP port in sync with all other PPC4xx ports. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include')
-rw-r--r--include/configs/ASH405.h10
-rw-r--r--include/configs/CATcenter.h12
-rw-r--r--include/configs/CMS700.h12
-rw-r--r--include/configs/DP405.h12
-rw-r--r--include/configs/G2000.h10
-rw-r--r--include/configs/HH405.h10
-rw-r--r--include/configs/HUB405.h10
-rw-r--r--include/configs/PLU405.h10
-rw-r--r--include/configs/PPChameleonEVB.h12
-rw-r--r--include/configs/VOH405.h10
-rw-r--r--include/configs/VOM405.h12
-rw-r--r--include/configs/WUH405.h10
-rw-r--r--include/configs/bubinga.h10
-rw-r--r--include/configs/quad100hd.h10
-rw-r--r--include/configs/zeus.h10
15 files changed, 80 insertions, 80 deletions
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index 4cb8052..98bd6f3 100644
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -335,12 +335,12 @@
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
-#define CONFIG_SYS_GPIO0_OSRH 0x40000550
-#define CONFIG_SYS_GPIO0_OSRL 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1L 0x15555445
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
+#define CONFIG_SYS_GPIO0_OSRL 0x40000550
+#define CONFIG_SYS_GPIO0_OSRH 0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
+#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
index 229a513..da85442 100644
--- a/include/configs/CATcenter.h
+++ b/include/configs/CATcenter.h
@@ -535,13 +535,13 @@
* GPIO0[30] - EMAC0 input
* GPIO0[31] - EMAC1 reject packet as output
*/
-#define CONFIG_SYS_GPIO0_OSRH 0x40000550
-#define CONFIG_SYS_GPIO0_OSRL 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
-/*#define CONFIG_SYS_GPIO0_ISR1L 0x15555445*/
-#define CONFIG_SYS_GPIO0_ISR1L 0x15555444
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
+#define CONFIG_SYS_GPIO0_OSRL 0x40000550
+#define CONFIG_SYS_GPIO0_OSRH 0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
+/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/
+#define CONFIG_SYS_GPIO0_ISR1H 0x15555444
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
+#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
/*
diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
index 2b6786b..ede9970 100644
--- a/include/configs/CMS700.h
+++ b/include/configs/CMS700.h
@@ -301,12 +301,12 @@
/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
-#define CONFIG_SYS_GPIO0_OSRH 0x40000500 /* 0 ... 15 */
-#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */
-#define CONFIG_SYS_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 0 ... 15 */
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */
+#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
+#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
+#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */
diff --git a/include/configs/DP405.h b/include/configs/DP405.h
index 4423f2a..0ee456b 100644
--- a/include/configs/DP405.h
+++ b/include/configs/DP405.h
@@ -243,12 +243,12 @@
/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
-#define CONFIG_SYS_GPIO0_OSRH 0x40000540 /* 0 ... 15 */
-#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */
-#define CONFIG_SYS_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 0 ... 15 */
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_OSRL 0x40000540 /* 0 ... 15 */
+#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
+#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
+#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_TCR 0xB7FE0014 /* 0 ... 31 */
/*
diff --git a/include/configs/G2000.h b/include/configs/G2000.h
index d2883eb..4d29f21 100644
--- a/include/configs/G2000.h
+++ b/include/configs/G2000.h
@@ -367,12 +367,12 @@
*
* following GPIO setting changed for G20000, 080304
*/
-#define CONFIG_SYS_GPIO0_OSRH 0x40005555
-#define CONFIG_SYS_GPIO0_OSRL 0x40000110
-#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1L 0x15555445
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
+#define CONFIG_SYS_GPIO0_OSRL 0x40005555
+#define CONFIG_SYS_GPIO0_OSRH 0x40000110
+#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
+#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
/*
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index 01e0bc6..d940a88 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -461,12 +461,12 @@
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
-#define CONFIG_SYS_GPIO0_OSRH 0x40000550
-#define CONFIG_SYS_GPIO0_OSRL 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1L 0x15555440
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
+#define CONFIG_SYS_GPIO0_OSRL 0x40000550
+#define CONFIG_SYS_GPIO0_OSRH 0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H 0x15555440
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
+#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FE0017
#define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7)
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
index 8c6d5ed..72e907b 100644
--- a/include/configs/HUB405.h
+++ b/include/configs/HUB405.h
@@ -334,12 +334,12 @@
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
-#define CONFIG_SYS_GPIO0_OSRH 0x40000550
-#define CONFIG_SYS_GPIO0_OSRL 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1L 0x15555445
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
+#define CONFIG_SYS_GPIO0_OSRL 0x40000550
+#define CONFIG_SYS_GPIO0_OSRH 0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
+#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index f917eb5..a308782 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -379,12 +379,12 @@
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
-#define CONFIG_SYS_GPIO0_OSRH 0x00000550
-#define CONFIG_SYS_GPIO0_OSRL 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1L 0x15555445
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
+#define CONFIG_SYS_GPIO0_OSRL 0x00000550
+#define CONFIG_SYS_GPIO0_OSRH 0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
+#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0x77FE0014
#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index 09f3544..e9cae85 100644
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -542,13 +542,13 @@
* GPIO0[30] - EMAC0 input
* GPIO0[31] - EMAC1 reject packet as output
*/
-#define CONFIG_SYS_GPIO0_OSRH 0x40000550
-#define CONFIG_SYS_GPIO0_OSRL 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
-/*#define CONFIG_SYS_GPIO0_ISR1L 0x15555445*/
-#define CONFIG_SYS_GPIO0_ISR1L 0x15555444
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
+#define CONFIG_SYS_GPIO0_OSRL 0x40000550
+#define CONFIG_SYS_GPIO0_OSRH 0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
+/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/
+#define CONFIG_SYS_GPIO0_ISR1H 0x15555444
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
+#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
/*
diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
index 9c91fcc..21bb5b6 100644
--- a/include/configs/VOH405.h
+++ b/include/configs/VOH405.h
@@ -388,12 +388,12 @@
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
*/
-#define CONFIG_SYS_GPIO0_OSRH 0x00000550
-#define CONFIG_SYS_GPIO0_OSRL 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1L 0x15555440
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
+#define CONFIG_SYS_GPIO0_OSRL 0x00000550
+#define CONFIG_SYS_GPIO0_OSRH 0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H 0x15555440
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
+#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0x777E0017
#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index 871e4c3..747d6a0 100644
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -273,12 +273,12 @@
/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
-#define CONFIG_SYS_GPIO0_OSRH 0x40000500 /* 0 ... 15 */
-#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */
-#define CONFIG_SYS_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 0 ... 15 */
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */
+#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
+#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
+#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
/*
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
index be9ac62..7756d3a 100644
--- a/include/configs/WUH405.h
+++ b/include/configs/WUH405.h
@@ -332,12 +332,12 @@
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
-#define CONFIG_SYS_GPIO0_OSRH 0x40000550
-#define CONFIG_SYS_GPIO0_OSRL 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1L 0x15555445
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
+#define CONFIG_SYS_GPIO0_OSRL 0x40000550
+#define CONFIG_SYS_GPIO0_OSRH 0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
+#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
index 159a265..05c4766 100644
--- a/include/configs/bubinga.h
+++ b/include/configs/bubinga.h
@@ -284,12 +284,12 @@
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
-#define CONFIG_SYS_GPIO0_OSRH 0x55555555
-#define CONFIG_SYS_GPIO0_OSRL 0x40000110
-#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1L 0x15555445
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
+#define CONFIG_SYS_GPIO0_OSRL 0x55555555
+#define CONFIG_SYS_GPIO0_OSRH 0x40000110
+#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
+#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xFFFF8014
/*-----------------------------------------------------------------------
diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h
index 5538b18..b778187 100644
--- a/include/configs/quad100hd.h
+++ b/include/configs/quad100hd.h
@@ -270,12 +270,12 @@
* Taken in part from PPCBoot board/icecube/icecube.h
*/
/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
-#define CONFIG_SYS_GPIO0_OSRH 0x55555550
-#define CONFIG_SYS_GPIO0_OSRL 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1L 0x15555445
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
+#define CONFIG_SYS_GPIO0_OSRL 0x55555550
+#define CONFIG_SYS_GPIO0_OSRH 0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
+#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xFFFF8097
#define CONFIG_SYS_GPIO0_ODR 0x00000000
diff --git a/include/configs/zeus.h b/include/configs/zeus.h
index 3b2aede..1ae990f 100644
--- a/include/configs/zeus.h
+++ b/include/configs/zeus.h
@@ -279,12 +279,12 @@
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
-#define CONFIG_SYS_GPIO0_OSRH 0x15555550 /* Chip selects */
-#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* UART_DTR-pin 27 alt out */
-#define CONFIG_SYS_GPIO0_ISR1H 0x10000041 /* Pin 2, 12 is input */
-#define CONFIG_SYS_GPIO0_ISR1L 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
+#define CONFIG_SYS_GPIO0_OSRL 0x15555550 /* Chip selects */
+#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* UART_DTR-pin 27 alt out */
+#define CONFIG_SYS_GPIO0_ISR1L 0x10000041 /* Pin 2, 12 is input */
+#define CONFIG_SYS_GPIO0_ISR1H 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
+#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
#define CONFIG_SYS_GPIO0_ODR 0x00000000
generated by cgit v1.1 at 2024-11-28 04:50:26 +0000