diff options
| author | Asen Dimov <dimov@ronetix.at> | 2011-06-08 22:01:16 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-09-03 22:40:44 +0200 |
| commit | 684a567ace2bc5673d52b2cb4f517909f5481153 (patch) | |
| tree | a607ac4e950ba83665b7f08e8c3d3abb2312a387 /include | |
| parent | 58fb6020c15580365e441ab3a7b8cc6aa787269d (diff) | |
| download | u-boot-imx-684a567ace2bc5673d52b2cb4f517909f5481153.zip u-boot-imx-684a567ace2bc5673d52b2cb4f517909f5481153.tar.gz u-boot-imx-684a567ace2bc5673d52b2cb4f517909f5481153.tar.bz2 | |
make pm9263 buildable for v2011.06 release
Signed-off-by: Asen Chavdarov Dimov <dimov@ronetix.at>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/pm9263.h | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 96e12f2..1e282d2 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -28,6 +28,12 @@ #ifndef __CONFIG_H #define __CONFIG_H +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include <asm/hardware.h> + /* ARM asynchronous clock */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -36,16 +42,15 @@ #define MASTER_PLL_MUL 65 #define MAIN_PLL_DIV 2 /* 2 or 4 */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_HZ 1000 -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ +#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" #define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */ #define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_SYS_TEXT_BASE 0 -#define CONFIG_AT91FAMILY /* clocks */ #define CONFIG_SYS_MOR_VAL \ @@ -170,10 +175,8 @@ */ #define CONFIG_AT91_GPIO 1 #define CONFIG_ATMEL_USART 1 -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS /* LCD */ #define CONFIG_LCD 1 |