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| author | Wolfgang Denk <wd@pollux.(none)> | 2006-02-21 16:41:43 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@pollux.(none)> | 2006-02-21 16:41:43 +0100 |
| commit | 654c2d2836ff49c94a0bceb700701976e2682375 (patch) | |
| tree | b48b6863cd3a672d4e6da6dfb4953decd68e8d66 /include | |
| parent | 84e106c09d324e345f335d2edef246d0b4c9131a (diff) | |
| parent | 79830d591afb758be8556396949d433fee1527c2 (diff) | |
| download | u-boot-imx-654c2d2836ff49c94a0bceb700701976e2682375.zip u-boot-imx-654c2d2836ff49c94a0bceb700701976e2682375.tar.gz u-boot-imx-654c2d2836ff49c94a0bceb700701976e2682375.tar.bz2 | |
Merge with /home/sr/git/u-boot
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/CPCI750.h | 12 | ||||
| -rw-r--r-- | include/configs/HH405.h | 15 |
2 files changed, 22 insertions, 5 deletions
diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 150e526..1632f37 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -285,13 +285,19 @@ * FLASH related *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CFG_FLASH_INCREMENT 0x01000000 /* there is only one bank */ #define CFG_FLASH_PROTECTION 1 /* use hardware protection */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ #define CFG_FLASH_BASE 0xfc000000 /* start of flash banks */ +#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ +#define CFG_FLASH_INCREMENT 0x01000000 /* size of flash bank */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \ + CFG_FLASH_BASE + 1*CFG_FLASH_INCREMENT, \ + CFG_FLASH_BASE + 2*CFG_FLASH_INCREMENT, \ + CFG_FLASH_BASE + 3*CFG_FLASH_INCREMENT } +#define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */ /* areas to map different things with the GT in physical space */ #define CFG_DRAM_BANKS 4 diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 131c215..4f62b8a 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -5,6 +5,9 @@ * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * + * (C) Copyright 2006 + * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com + * * See file CREDITS for list of people who contributed to this * project. * @@ -61,9 +64,13 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 + #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ @@ -79,6 +86,7 @@ #else #define CONFIG_VIDEO_SM501_16BPP #endif +#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000 #define CONFIG_CFB_CONSOLE #define CONFIG_VIDEO_LOGO #define CONFIG_VGA_AS_SINGLE_DEVICE @@ -434,9 +442,12 @@ #define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008 #define CFG_FPGA_CTRL_CF_RESET 0x0040 #define CFG_FPGA_CTRL_PS2_PWR 0x0080 -#define CFG_FPGA_CTRL_CF_PWR 0x0100 /* low active */ +#define CFG_FPGA_CTRL_CF_PWRN 0x0100 /* low active */ #define CFG_FPGA_CTRL_CF_BUS_EN 0x0200 #define CFG_FPGA_CTRL_LCD_CLK 0x7000 /* Mask for lcd clock */ +#define CFG_FPGA_CTRL_OW_ENABLE 0x8000 + +#define CFG_FPGA_STATUS_CF_DETECT 0x8000 #define LCD_CLK_OFF 0x0000 /* Off */ #define LCD_CLK_02083 0x1000 /* 2.083 MHz */ |