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| author | Felix Radensky <felix@embedded-sol.com> | 2009-09-27 23:56:12 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-10-02 13:53:28 +0200 |
| commit | d24bd2517a2b847f773453eab0ee5b1c8ebc74ba (patch) | |
| tree | f5e7c0f371867fc03adafc3da8fe2916b245e468 /include | |
| parent | 1d96cfe8f5eebfc6ea39d1a387f35ca4499e6b67 (diff) | |
| download | u-boot-imx-d24bd2517a2b847f773453eab0ee5b1c8ebc74ba.zip u-boot-imx-d24bd2517a2b847f773453eab0ee5b1c8ebc74ba.tar.gz u-boot-imx-d24bd2517a2b847f773453eab0ee5b1c8ebc74ba.tar.bz2 | |
ppc4xx: Reorganize DDR2 ECC handling
Reorganize DDR2 ECC handling to use common code for
SPD DIMMs and soldered SDRAM. Also, use common code
to display SDRAM info (ECC, CAS latency) for SPD and
soldered SDRAM variants.
Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/ppc405.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/ppc405.h b/include/ppc405.h index 5e56897..8a4ba3f 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -768,6 +768,10 @@ #define SDR0_SDCS_SDD (0x80000000 >> 31) +/* SDR0_SDSTP0 Serial Device Strap Register0 */ +#define SDR0_SDSTP0 0x0020 +#define SDR0_SDSTP0_PLB2xDV0_DECODE(n) ((((unsigned long)(n)) & 0x07)) + /* CUST0 Customer Configuration Register0 */ #define SDR0_CUST0 0x4000 #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ |