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authorStefan Roese <sr@denx.de>2008-09-23 10:15:59 +0200
committerStefan Roese <sr@denx.de>2008-09-23 10:15:59 +0200
commit50a874b3b0272f32e3627732fab90b27fbd35066 (patch)
tree0adead0a65471cce00f6475208e513e7a8469eb3 /include
parent5289feadb7857e2eaf81848aa632afa4a07bc0cc (diff)
parent8fd4166c467a46773f80208bda1ec3b4757747bc (diff)
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Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'include')
-rw-r--r--include/configs/socrates.h6
-rw-r--r--include/spartan3.h15
2 files changed, 6 insertions, 15 deletions
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 0135ac8..bbb9d18 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -87,8 +87,8 @@
#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
#undef CFG_DRAM_TEST /* memory test, takes time */
-#define CFG_MEMTEST_START 0x00000000
-#define CFG_MEMTEST_END 0x10000000
+#define CFG_MEMTEST_START 0x00400000
+#define CFG_MEMTEST_END 0x00C00000
/*
* Base addresses -- Note these are effective addresses where the
@@ -117,7 +117,7 @@
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
+#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
diff --git a/include/spartan3.h b/include/spartan3.h
index 9a3a5d4..b0fa1cd 100644
--- a/include/spartan3.h
+++ b/include/spartan3.h
@@ -81,9 +81,6 @@ typedef struct {
#define XILINX_XC3S1200E_SIZE 3841184/8
#define XILINX_XC3S1600E_SIZE 5969696/8
-/* Spartan-IIIE (1.2V) */
-#define XILINX_XC3S1200E_SIZE 3841184/8
-
/* Descriptor Macros
*********************************************************************/
/* Spartan-III devices */
@@ -103,14 +100,13 @@ typedef struct {
{ Xilinx_Spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie }
#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S2000E_SIZE, fn_table, cookie }
+{ Xilinx_Spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie }
#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S4000E_SIZE, fn_table, cookie }
+{ Xilinx_Spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie }
#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S5000E_SIZE, fn_table, cookie }
-
+{ Xilinx_Spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie }
/* Spartan-3E devices */
#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
@@ -128,9 +124,4 @@ typedef struct {
#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie }
-
-/* Spartan-IIIE devices */
-#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
-{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie }
-
#endif /* _SPARTAN3_H_ */