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| author | Wolfgang Denk <wd@pollux.denx.de> | 2006-04-05 23:55:15 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@pollux.denx.de> | 2006-04-05 23:55:15 +0200 |
| commit | 197b049b8b8a488384f351b988dd15f78830ba4e (patch) | |
| tree | d059e889505774b875e71335ec06a92078c63cb0 /include | |
| parent | db28ddb4da7387f4658ae5d032263258e53a1f37 (diff) | |
| parent | 35118539435d1a6f40eab348a4ac2040f3bd882c (diff) | |
| download | u-boot-imx-197b049b8b8a488384f351b988dd15f78830ba4e.zip u-boot-imx-197b049b8b8a488384f351b988dd15f78830ba4e.tar.gz u-boot-imx-197b049b8b8a488384f351b988dd15f78830ba4e.tar.bz2 | |
Merge with /home/sr/git/u-boot/4xx-sdram
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/PPChameleonEVB.h | 10 | ||||
| -rw-r--r-- | include/configs/p3p440.h | 12 |
2 files changed, 18 insertions, 4 deletions
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index e1155e2..16e2cc6 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -139,8 +139,18 @@ #define CFG_I2C_RTC_ADDR 0x68 #define CFG_M41T11_BASE_YEAR 1900 +/* + * SDRAM configuration (please see cpu/ppc/sdram.[ch]) + */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ +/* SDRAM timings used in datasheet */ +#define CFG_SDRAM_CL 2 +#define CFG_SDRAM_tRP 20 +#define CFG_SDRAM_tRC 65 +#define CFG_SDRAM_tRCD 20 +#undef CFG_SDRAM_tRFC + /* * Miscellaneous configurable options */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index 831d018..0662544 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005 + * (C) Copyright 2005-2006 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> @@ -71,9 +71,10 @@ * DDR SDRAM *----------------------------------------------------------------------*/ #define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/ -#define CFG_SDRAM_TABLE { \ - {(256 << 20), 0x000C4001}, /* 256MB mode 3, 13x10(4) */ \ - {(64 << 20), 0x00082001}} /* 64MB mode 2, 12x9(4) */ +#define CONFIG_SDRAM_ECC /* enable ECC support */ +#define CFG_SDRAM_TABLE { \ + {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \ + {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */ /*----------------------------------------------------------------------- * Serial Port @@ -275,6 +276,9 @@ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ + #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ |