sh: Add support PCI of SuperH and SH7780

This patch add support PCI of SuperH base code and SH7780 specific code.

Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

2 files changed, 103 insertions, 57 deletions

diff --git a/include/asm-sh/cpu_sh7780.h b/include/asm-sh/cpu_sh7780.h
index b0569c2..d4f824e 100644
--- a/include/asm-sh/cpu_sh7780.h
+++ b/include/asm-sh/cpu_sh7780.h
@@ -118,63 +118,63 @@
 #define	DBK_2		0xFE800404
 
 /* PCI	Controller */
-#define	PCIECR		0xFE000008
-#define	PCIVID		0xFE040000
-#define	PCIDID		0xFE040002
-#define	PCICMD		0xFE040004
-#define	PCISTATUS	0xFE040006
-#define	PCIRID		0xFE040008
-#define	PCIPIF		0xFE040009
-#define	PCISUB		0xFE04000A
-#define	PCIBCC		0xFE04000B
-#define	PCICLS		0xFE04000C
-#define	PCILTM		0xFE04000D
-#define	PCIHDR		0xFE04000E
-#define	PCIBIST		0xFE04000F
-#define	PCIIBAR		0xFE040010
-#define	PCIMBAR0	0xFE040014
-#define	PCIMBAR1	0xFE040018
-#define	PCISVID		0xFE04002C
-#define	PCISID		0xFE04002E
-#define	PCICP		0xFE040034
-#define	PCIINTLINE	0xFE04003C
-#define	PCIINTPIN	0xFE04003D
-#define	PCIMINGNT	0xFE04003E
-#define	PCIMAXLAT	0xFE04003F
-#define	PCICID		0xFE040040
-#define	PCINIP		0xFE040041
-#define	PCIPMC		0xFE040042
-#define	PCIPMCSR	0xFE040044
-#define	PCIPMCSRBSE	0xFE040046
-#define	PCI_CDD		0xFE040047
-#define	PCICR		0xFE040100
-#define	PCILSR0		0xFE040104
-#define	PCILSR1		0xFE040108
-#define	PCILAR0		0xFE04010C
-#define	PCILAR1		0xFE040110
-#define	PCIIR		0xFE040114
-#define	PCIIMR		0xFE040118
-#define	PCIAIR		0xFE04011C
-#define	PCICIR		0xFE040120
-#define	PCIAINT		0xFE040130
-#define	PCIAINTM	0xFE040134
-#define	PCIBMIR		0xFE040138
-#define	PCIPAR		0xFE0401C0
-#define	PCIPINT		0xFE0401CC
-#define	PCIPINTM	0xFE0401D0
-#define	PCIMBR0		0xFE0401E0
-#define	PCIMBMR0	0xFE0401E4
-#define	PCIMBR1		0xFE0401E8
-#define	PCIMBMR1	0xFE0401EC
-#define	PCIMBR2		0xFE0401F0
-#define	PCIMBMR2	0xFE0401F4
-#define	PCIIOBR		0xFE0401F8
-#define	PCIIOBMR	0xFE0401FC
-#define	PCICSCR0	0xFE040210
-#define	PCICSCR1	0xFE040214
-#define	PCICSAR0	0xFE040218
-#define	PCICSAR1	0xFE04021C
-#define	PCIPDR		0xFE040220
+#define	SH7780_PCIECR		0xFE000008
+#define	SH7780_PCIVID		0xFE040000
+#define	SH7780_PCIDID		0xFE040002
+#define	SH7780_PCICMD		0xFE040004
+#define	SH7780_PCISTATUS	0xFE040006
+#define	SH7780_PCIRID		0xFE040008
+#define	SH7780_PCIPIF		0xFE040009
+#define	SH7780_PCISUB		0xFE04000A
+#define	SH7780_PCIBCC		0xFE04000B
+#define	SH7780_PCICLS		0xFE04000C
+#define	SH7780_PCILTM		0xFE04000D
+#define	SH7780_PCIHDR		0xFE04000E
+#define	SH7780_PCIBIST		0xFE04000F
+#define	SH7780_PCIIBAR		0xFE040010
+#define	SH7780_PCIMBAR0		0xFE040014
+#define	SH7780_PCIMBAR1		0xFE040018
+#define	SH7780_PCISVID		0xFE04002C
+#define	SH7780_PCISID		0xFE04002E
+#define	SH7780_PCICP		0xFE040034
+#define	SH7780_PCIINTLINE	0xFE04003C
+#define	SH7780_PCIINTPIN	0xFE04003D
+#define	SH7780_PCIMINGNT	0xFE04003E
+#define	SH7780_PCIMAXLAT	0xFE04003F
+#define	SH7780_PCICID		0xFE040040
+#define	SH7780_PCINIP		0xFE040041
+#define	SH7780_PCIPMC		0xFE040042
+#define	SH7780_PCIPMCSR		0xFE040044
+#define	SH7780_PCIPMCSRBSE	0xFE040046
+#define	SH7780_PCI_CDD		0xFE040047
+#define	SH7780_PCICR		0xFE040100
+#define	SH7780_PCILSR0		0xFE040104
+#define	SH7780_PCILSR1		0xFE040108
+#define	SH7780_PCILAR0		0xFE04010C
+#define	SH7780_PCILAR1		0xFE040110
+#define	SH7780_PCIIR		0xFE040114
+#define	SH7780_PCIIMR		0xFE040118
+#define	SH7780_PCIAIR		0xFE04011C
+#define	SH7780_PCICIR		0xFE040120
+#define	SH7780_PCIAINT		0xFE040130
+#define	SH7780_PCIAINTM		0xFE040134
+#define	SH7780_PCIBMIR		0xFE040138
+#define	SH7780_PCIPAR		0xFE0401C0
+#define	SH7780_PCIPINT		0xFE0401CC
+#define	SH7780_PCIPINTM		0xFE0401D0
+#define	SH7780_PCIMBR0		0xFE0401E0
+#define	SH7780_PCIMBMR0		0xFE0401E4
+#define	SH7780_PCIMBR1		0xFE0401E8
+#define	SH7780_PCIMBMR1		0xFE0401EC
+#define	SH7780_PCIMBR2		0xFE0401F0
+#define	SH7780_PCIMBMR2		0xFE0401F4
+#define	SH7780_PCIIOBR		0xFE0401F8
+#define	SH7780_PCIIOBMR		0xFE0401FC
+#define	SH7780_PCICSCR0		0xFE040210
+#define	SH7780_PCICSCR1		0xFE040214
+#define	SH7780_PCICSAR0		0xFE040218
+#define	SH7780_PCICSAR1		0xFE04021C
+#define	SH7780_PCIPDR		0xFE040220
 
 /* DMAC */
 #define	DMAC_SAR0	0xFC808020
diff --git a/include/asm-sh/pci.h b/include/asm-sh/pci.h
new file mode 100644
index 0000000..821961f
--- /dev/null
+++ b/include/asm-sh/pci.h
@@ -0,0 +1,46 @@
+/*
+ * SH4 PCI Controller (PCIC) for U-Boot.
+ * (C) Dustin McIntire (dustin@sensoria.com)
+ * (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * u-boot/include/asm-sh/pci.h
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _ASM_PCI_H_
+#define _ASM_PCI_H_
+
+#include <pci.h>
+
+#if defined(CONFIG_CPU_SH7780)
+int pci_sh7780_init(struct pci_controller *hose);
+#else
+#error "Not support PCI."
+#endif
+
+/* PCI dword read for sh4 */
+int pci_sh4_read_config_dword(struct pci_controller *hose,
+		pci_dev_t dev, int offset, u32 *value);
+
+/* PCI dword write for sh4 */
+int pci_sh4_write_config_dword(struct pci_controller *hose,
+		pci_dev_t dev, int offset, u32 value);
+
+#endif	/* _ASM_PCI_H_ */