Merge branch 'master' of git://git.denx.de/u-boot-nand-flash

3 files changed, 56 insertions, 72 deletions

diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index c4389cc..fff888ab 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -155,8 +155,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
  *
  * Localbus non-cacheable
- * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
+ * 0xe000_0000	0xe7ff_ffff	Promjet/free		128M non-cacheable
  * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
+ * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
  * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
@@ -243,6 +244,57 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
 
+#define CONFIG_SYS_NAND_BASE           0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS      CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
+				CONFIG_SYS_NAND_BASE + 0x40000, \
+				CONFIG_SYS_NAND_BASE + 0x80000, \
+				CONFIG_SYS_NAND_BASE + 0xC0000}
+#define CONFIG_SYS_MAX_NAND_DEVICE	4
+#define NAND_MAX_CHIPS		1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND		1
+#define CONFIG_NAND_FSL_ELBC	1
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE_PHYS \
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8              /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CONFIG_NAND_OR_PRELIM	(0xFFFC0000            /* length 256K */ \
+				| OR_FCM_PGS            /* Large Page*/ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
+
+#define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8              /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CONFIG_SYS_OR4_PRELIM	CONFIG_NAND_OR_PRELIM     /* NAND Options */
+#define CONFIG_SYS_BR5_PRELIM  ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8              /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CONFIG_SYS_OR5_PRELIM	CONFIG_NAND_OR_PRELIM     /* NAND Options */
+
+#define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8              /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CONFIG_SYS_OR6_PRELIM	CONFIG_NAND_OR_PRELIM     /* NAND Options */
+
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
@@ -440,7 +492,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 #define CONFIG_ENV_ADDR		0xfff80000
 #else
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x60000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #endif
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index f98e7fb..244ecc2 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -509,7 +509,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 #define CONFIG_ENV_ADDR		0xfff80000
 #else
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #endif
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 39f8aec..24ad2bd 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -29,6 +29,7 @@
 
 #include "linux/mtd/compat.h"
 #include "linux/mtd/mtd.h"
+#include "linux/mtd/bbm.h"
 
 
 struct mtd_info;
@@ -480,75 +481,6 @@ extern struct nand_manufacturers nand_manuf_ids[];
 #define NAND_MAX_CHIPS 8
 #endif
 
-/**
- * struct nand_bbt_descr - bad block table descriptor
- * @options:	options for this descriptor
- * @pages:	the page(s) where we find the bbt, used with option BBT_ABSPAGE
- *		when bbt is searched, then we store the found bbts pages here.
- *		Its an array and supports up to 8 chips now
- * @offs:	offset of the pattern in the oob area of the page
- * @veroffs:	offset of the bbt version counter in the oob are of the page
- * @version:	version read from the bbt page during scan
- * @len:	length of the pattern, if 0 no pattern check is performed
- * @maxblocks:	maximum number of blocks to search for a bbt. This number of
- *		blocks is reserved at the end of the device where the tables are
- *		written.
- * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
- *              bad) block in the stored bbt
- * @pattern:	pattern to identify bad block table or factory marked good /
- *		bad blocks, can be NULL, if len = 0
- *
- * Descriptor for the bad block table marker and the descriptor for the
- * pattern which identifies good and bad blocks. The assumption is made
- * that the pattern and the version count are always located in the oob area
- * of the first block.
- */
-struct nand_bbt_descr {
-	int	options;
-	int	pages[NAND_MAX_CHIPS];
-	int	offs;
-	int	veroffs;
-	uint8_t	version[NAND_MAX_CHIPS];
-	int	len;
-	int	maxblocks;
-	int	reserved_block_code;
-	uint8_t	*pattern;
-};
-
-/* Options for the bad block table descriptors */
-
-/* The number of bits used per block in the bbt on the device */
-#define NAND_BBT_NRBITS_MSK	0x0000000F
-#define NAND_BBT_1BIT		0x00000001
-#define NAND_BBT_2BIT		0x00000002
-#define NAND_BBT_4BIT		0x00000004
-#define NAND_BBT_8BIT		0x00000008
-/* The bad block table is in the last good block of the device */
-#define	NAND_BBT_LASTBLOCK	0x00000010
-/* The bbt is at the given page, else we must scan for the bbt */
-#define NAND_BBT_ABSPAGE	0x00000020
-/* The bbt is at the given page, else we must scan for the bbt */
-#define NAND_BBT_SEARCH		0x00000040
-/* bbt is stored per chip on multichip devices */
-#define NAND_BBT_PERCHIP	0x00000080
-/* bbt has a version counter at offset veroffs */
-#define NAND_BBT_VERSION	0x00000100
-/* Create a bbt if none axists */
-#define NAND_BBT_CREATE		0x00000200
-/* Search good / bad pattern through all pages of a block */
-#define NAND_BBT_SCANALLPAGES	0x00000400
-/* Scan block empty during good / bad block scan */
-#define NAND_BBT_SCANEMPTY	0x00000800
-/* Write bbt if neccecary */
-#define NAND_BBT_WRITE		0x00001000
-/* Read and write back block contents when writing bbt */
-#define NAND_BBT_SAVECONTENT	0x00002000
-/* Search good / bad pattern on the first and the second page */
-#define NAND_BBT_SCAN2NDPAGE	0x00004000
-
-/* The maximum number of blocks to scan for a bbt */
-#define NAND_BBT_SCAN_MAXBLOCKS	4
-
 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
 extern int nand_default_bbt(struct mtd_info *mtd);