sh: Update core code of SuperH.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

7 files changed, 704 insertions, 211 deletions

diff --git a/include/asm-sh/bitops.h b/include/asm-sh/bitops.h
index 44dca9f..529d0f2 100644
--- a/include/asm-sh/bitops.h
+++ b/include/asm-sh/bitops.h
@@ -1,13 +1,166 @@
-#ifndef __ASM_SH_BITOPS_H_
-#define __ASM_SH_BITOPS_H_
-
-extern void set_bit(int nr, volatile void * a);
-extern void clear_bit(int nr, volatile void * a);
-extern int test_and_clear_bit(int nr, volatile void * a);
-extern void change_bit(unsigned long nr, volatile void *addr);
-extern int test_and_set_bit(int nr, volatile void * a);
-extern int test_and_change_bit(int nr, volatile void * addr);
-extern int test_bit(int nr, volatile void * a);
-extern int ffs(int i);
+#ifndef __ASM_SH_BITOPS_H
+#define __ASM_SH_BITOPS_H
 
+#ifdef __KERNEL__
+//#include <asm/system.h>
+#include <asm/irqflags.h>
+/* For __swab32 */
+#include <asm/byteorder.h>
+
+static inline void set_bit(int nr, volatile void * addr)
+{
+	int	mask;
+	volatile unsigned int *a = addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a |= mask;
+	local_irq_restore(flags);
+}
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit()	barrier()
+#define smp_mb__after_clear_bit()	barrier()
+static inline void clear_bit(int nr, volatile void * addr)
+{
+	int	mask;
+	volatile unsigned int *a = addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a &= ~mask;
+	local_irq_restore(flags);
+}
+
+static inline void change_bit(int nr, volatile void * addr)
+{
+	int	mask;
+	volatile unsigned int *a = addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a ^= mask;
+	local_irq_restore(flags);
+}
+
+static inline int test_and_set_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	local_irq_restore(flags);
+
+	return retval;
+}
+
+static inline int test_and_clear_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	local_irq_restore(flags);
+
+	return retval;
+}
+
+static inline int test_and_change_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	local_irq_restore(flags);
+
+	return retval;
+}
+
+//#include <asm-generic/bitops/non-atomic.h>
+
+static inline unsigned long ffz(unsigned long word)
+{
+	unsigned long result;
+
+	__asm__("1:\n\t"
+		"shlr	%1\n\t"
+		"bt/s	1b\n\t"
+		" add	#1, %0"
+		: "=r" (result), "=r" (word)
+		: "0" (~0L), "1" (word)
+		: "t");
+	return result;
+}
+
+/**
+ * ffs - find first bit in word.
+ * @word: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static inline int ffs(int x)
+{
+  int r = 1;
+
+  if (!x)
+    return 0;
+  if (!(x & 0xffff)) {
+    x >>= 16;
+    r += 16;
+  }
+  if (!(x & 0xff)) {
+    x >>= 8;
+    r += 8;
+  }
+  if (!(x & 0xf)) {
+    x >>= 4;
+    r += 4;
+  }
+  if (!(x & 3)) {
+    x >>= 2;
+    r += 2;
+  }
+  if (!(x & 1)) {
+    x >>= 1;
+    r += 1;
+  }
+  return r;
+}
+
+#if 0
+#include <asm-generic/bitops/find.h>
+#include <asm-generic/bitops/ffs.h>
+#include <asm-generic/bitops/hweight.h>
+#include <asm-generic/bitops/sched.h>
+#include <asm-generic/bitops/ext2-non-atomic.h>
+#include <asm-generic/bitops/ext2-atomic.h>
+#include <asm-generic/bitops/minix.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/fls64.h>
 #endif
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_BITOPS_H */
diff --git a/include/asm-sh/cpu_sh4.h b/include/asm-sh/cpu_sh4.h
index e0275f3..dca61ca 100644
--- a/include/asm-sh/cpu_sh4.h
+++ b/include/asm-sh/cpu_sh4.h
@@ -1,10 +1,48 @@
+/*
+ * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
 #ifndef _ASM_CPU_SH4_H_
 #define _ASM_CPU_SH4_H_
+
+/* cache control */
+#define CCR_CACHE_STOP   0x00000808
+#define CCR_CACHE_ENABLE 0x00000101
+#define CCR_CACHE_ICI    0x00000800
+
+#define CACHE_OC_ADDRESS_ARRAY	0xf4000000
+#define CACHE_OC_WAY_SHIFT	14
+#define CACHE_OC_NUM_ENTRIES	512
+#define CACHE_OC_ENTRY_SHIFT	5
+//#define CACHE_OC_NUM_WAYS	1
+
 #if defined (CONFIG_CPU_SH7750)
 #include <asm/cpu_sh7750.h>
-#elif defined (CONFIG_CPU_SH7780)
-#include <asm/cpu_sh7780.h>
+//#ifdef CONFIG_CPU_TYPE_R
+//#define CCR_CACHE_INIT   0x8000090d     /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
+//#else
+//#define CCR_CACHE_INIT   0x0000090b
+//#endif
+#elif defined (CONFIG_CPU_SH7722)
+#include <asm/cpu_sh7722.h>
+//#define CCR_CACHE_INIT   0x0000090d
 #else
 #error "Unknown SH4 variant"
 #endif
-#endif
+
+#endif	/* _ASM_CPU_SH4_H_ */
diff --git a/include/asm-sh/cpu_sh7750.h b/include/asm-sh/cpu_sh7750.h
index eb4f1af..9993e63 100644
--- a/include/asm-sh/cpu_sh7750.h
+++ b/include/asm-sh/cpu_sh7750.h
@@ -1,13 +1,44 @@
+/*
+ * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SH7750/SH7750S/SH7750R/SH7751/SH7751R 
+ *  Internal I/O register
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
 #ifndef _ASM_CPU_SH7750_H_
 #define _ASM_CPU_SH7750_H_
 
-#define PTEH 	0xFF000000 
-#define PTEL 	0xFF000004 
-#define TTB 	0xFF000008 
-#define TEA 	0xFF00000C 
-#define MMUCR 	0xFF000010 
-#define BASRA 	0xFF000014 
-#define BASRB	0xFF000018 
+#ifdef CONFIG_CPU_TYPE_R
+#define CACHE_OC_NUM_WAYS     2
+#define CCR_CACHE_INIT   0x8000090d     /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
+#else
+#define CACHE_OC_NUM_WAYS     1
+#define CCR_CACHE_INIT   0x0000090b
+#endif
+
+/*      OCN     */
+#define PTEH 	0xFF000000
+#define PTEL 	0xFF000004
+#define TTB 	0xFF000008
+#define TEA 	0xFF00000C
+#define MMUCR 	0xFF000010
+#define BASRA 	0xFF000014
+#define BASRB	0xFF000018
 #define CCR	0xFF00001C
 #define TRA 	0xFF000020
 #define EXPEVT 	0xFF000024
@@ -15,6 +46,8 @@
 #define PTEA 	0xFF000034
 #define QACR0 	0xFF000038
 #define QACR1 	0xFF00003C
+
+/*      UBC     */
 #define BARA 	0xFF200000
 #define BAMRA 	0xFF200004
 #define BBRA 	0xFF200008
@@ -25,121 +58,139 @@
 #define BDMRB 	0xFF20001C
 #define BRCR 	0xFF200020
 
+/*      BSC     */
 #define BCR1	0xFF800000
-#define BCR2	0xFF800004 
-#define BCR3 	0xFF800050 
-#define BCR4	0xFE0A00F0 
-#define WCR1 	0xFF800008 
-#define WCR2 	0xFF80000C 
-#define WCR3 	0xFF800010 
-#define MCR 	0xFF800014 
-#define PCR 	0xFF800018 
-#define RTCSR 	0xFF80001C 
-#define RTCNT 	0xFF800020 
-#define RTCOR 	0xFF800024 
-#define RFCR 	0xFF800028 
-#define PCTRA 	0xFF80002C 
-#define PDTRA 	0xFF800030 
-#define PCTRB 	0xFF800040 
-#define PDTRB 	0xFF800044 
-#define GPIOIC 	0xFF800048 
-#define SAR0 	0xFFA00000 
-#define DAR0 	0xFFA00004 
-#define DMATCR0 0xFFA00008 
-#define CHCR0	0xFFA0000C 
-#define SAR1 	0xFFA00010 
-#define DAR1 	0xFFA00014 
-#define DMATCR1 0xFFA00018 
-#define CHCR1 	0xFFA0001C 
-#define SAR2 	0xFFA00020 
-#define DAR2 	0xFFA00024 
-#define DMATCR2 0xFFA00028 
-#define CHCR2 	0xFFA0002C 
-#define SAR3 	0xFFA00030 
-#define DAR3 	0xFFA00034 
-#define DMATCR3 0xFFA00038 
-#define CHCR3 	0xFFA0003C 
-#define DMAOR 	0xFFA00040 
-#define SAR4	0xFFA00050 
-#define DAR4 	0xFFA00054 
-#define DMATCR4 0xFFA00058 
+#define BCR2	0xFF800004
+#define BCR3 	0xFF800050
+#define BCR4	0xFE0A00F0
+#define WCR1 	0xFF800008
+#define WCR2 	0xFF80000C
+#define WCR3 	0xFF800010
+#define MCR 	0xFF800014
+#define PCR 	0xFF800018
+#define RTCSR 	0xFF80001C
+#define RTCNT 	0xFF800020
+#define RTCOR 	0xFF800024
+#define RFCR 	0xFF800028
+#define PCTRA 	0xFF80002C
+#define PDTRA 	0xFF800030
+#define PCTRB 	0xFF800040
+#define PDTRB 	0xFF800044
+#define GPIOIC 	0xFF800048
+
+/*      DMAC    */
+#define SAR0 	0xFFA00000
+#define DAR0 	0xFFA00004
+#define DMATCR0 0xFFA00008
+#define CHCR0	0xFFA0000C
+#define SAR1 	0xFFA00010
+#define DAR1 	0xFFA00014
+#define DMATCR1 0xFFA00018
+#define CHCR1 	0xFFA0001C
+#define SAR2 	0xFFA00020
+#define DAR2 	0xFFA00024
+#define DMATCR2 0xFFA00028
+#define CHCR2 	0xFFA0002C
+#define SAR3 	0xFFA00030
+#define DAR3 	0xFFA00034
+#define DMATCR3 0xFFA00038
+#define CHCR3 	0xFFA0003C
+#define DMAOR 	0xFFA00040
+#define SAR4	0xFFA00050
+#define DAR4 	0xFFA00054
+#define DMATCR4 0xFFA00058
+
+/*      CPG     */
+#define FRQCR 	0xFFC00000
+#define STBCR 	0xFFC00004
+#define WTCNT 	0xFFC00008
+#define WTCSR 	0xFFC0000C
+#define STBCR2 	0xFFC00010
+
+/*      RTC     */
+#define R64CNT	0xFFC80000
+#define RSECCNT 0xFFC80004
+#define RMINCNT 0xFFC80008
+#define RHRCNT 	0xFFC8000C
+#define RWKCNT 	0xFFC80010
+#define RDAYCNT 0xFFC80014
+#define RMONCNT 0xFFC80018
+#define RYRCNT 	0xFFC8001C
+#define RSECAR 	0xFFC80020
+#define RMINAR 	0xFFC80024
+#define RHRAR 	0xFFC80028
+#define RWKAR 	0xFFC8002C
+#define RDAYAR 	0xFFC80030
+#define RMONAR 	0xFFC80034
+#define RCR1 	0xFFC80038
+#define RCR2 	0xFFC8003C
+#define RCR3 	0xFFC80050
+#define RYRAR 	0xFFC80054
 
-#define FRQCR 	0xFFC00000 
-#define STBCR 	0xFFC00004 
-#define WTCNT 	0xFFC00008 
-#define WTCSR 	0xFFC0000C 
-#define STBCR2 	0xFFC00010 
-#define R64CNT	0xFFC80000 
-#define RSECCNT 0xFFC80004 
-#define RMINCNT 0xFFC80008 
-#define RHRCNT 	0xFFC8000C 
-#define RWKCNT 	0xFFC80010 
-#define RDAYCNT 0xFFC80014 
-#define RMONCNT 0xFFC80018 
-#define RYRCNT 	0xFFC8001C 
-#define RSECAR 	0xFFC80020 
-#define RMINAR 	0xFFC80024 
-#define RHRAR 	0xFFC80028 
-#define RWKAR 	0xFFC8002C 
-#define RDAYAR 	0xFFC80030 
-#define RMONAR 	0xFFC80034 
-#define RCR1 	0xFFC80038 
-#define RCR2 	0xFFC8003C 
-#define RCR3 	0xFFC80050 
-#define RYRAR 	0xFFC80054 
-#define ICR 	0xFFD00000 
-#define IPRA 	0xFFD00004 
-#define IPRB 	0xFFD00008 
-#define IPRC	0xFFD0000C 
-#define IPRD 	0xFFD00010 
-#define INTPRI 	0xFE080000 
-#define INTREQ	0xFE080020 
-#define INTMSK	0xFE080040 
-#define INTMSKCL	0xFE080060 
+/*      ICR     */
+#define ICR 	0xFFD00000
+#define IPRA 	0xFFD00004
+#define IPRB 	0xFFD00008
+#define IPRC	0xFFD0000C
+#define IPRD 	0xFFD00010
+#define INTPRI 	0xFE080000
+#define INTREQ	0xFE080020
+#define INTMSK	0xFE080040
+#define INTMSKCL	0xFE080060
+
+/*      CPG     */
 #define CLKSTP		0xFE0A0000
 #define CLKSTPCLR	0xFE0A0008
-#define TSTR2 	0xFE100004 
-#define TCOR3 	0xFE100008 
-#define TCNT3 	0xFE10000C 
-#define TCR3 	0xFE100010 
-#define TCOR4 	0xFE100014 
-#define TCNT4 	0xFE100018 
-#define TCR4 	0xFE10001C 
-#define TOCR 	0xFFD80000 
-#define TSTR0 	0xFFD80004 
-#define TCOR0	0xFFD80008 
-#define TCNT0 	0xFFD8000C 
-#define TCR0 	0xFFD80010 
-#define TCOR1 	0xFFD80014 
-#define TCNT1 	0xFFD80018 
-#define TCR1 	0xFFD8001C 
-#define TCOR2 	0xFFD80020 
-#define TCNT2 	0xFFD80024 
-#define TCR2 	0xFFD80028 
+
+/*      TMU     */
+#define TSTR2 	0xFE100004
+#define TCOR3 	0xFE100008
+#define TCNT3 	0xFE10000C
+#define TCR3 	0xFE100010
+#define TCOR4 	0xFE100014
+#define TCNT4 	0xFE100018
+#define TCR4 	0xFE10001C
+#define TOCR 	0xFFD80000
+#define TSTR0 	0xFFD80004
+#define TCOR0	0xFFD80008
+#define TCNT0 	0xFFD8000C
+#define TCR0 	0xFFD80010
+#define TCOR1 	0xFFD80014
+#define TCNT1 	0xFFD80018
+#define TCR1 	0xFFD8001C
+#define TCOR2 	0xFFD80020
+#define TCNT2 	0xFFD80024
+#define TCR2 	0xFFD80028
 #define TCPR2 	0xFFD8002C
-#define SCSMR1 	0xFFE00000 
-#define SCBRR1 	0xFFE00004 
-#define SCSCR1 	0xFFE00008 
-#define SCTDR1 	0xFFE0000C 
-#define SCSSR1 	0xFFE00010 
-#define SCRDR1 	0xFFE00014 
-#define SCSCMR1 0xFFE00018 
-#define SCSPTR1 0xFFE0001C 
+#define TSTR	TSTR0
+
+/*      SCI     */
+#define SCSMR1 	0xFFE00000
+#define SCBRR1 	0xFFE00004
+#define SCSCR1 	0xFFE00008
+#define SCTDR1 	0xFFE0000C
+#define SCSSR1 	0xFFE00010
+#define SCRDR1 	0xFFE00014
+#define SCSCMR1 0xFFE00018
+#define SCSPTR1 0xFFE0001C
 #define SCF0_BASE	SCSMR1
+
+/*      SCIF    */
 #define SCSMR2 	0xFFE80000
-#define SCBRR2 	0xFFE80004 
-#define SCSCR2 	0xFFE80008 
-#define SCFTDR2 0xFFE8000C 
-#define SCFSR2 	0xFFE80010 
-#define SCFRDR2	0xFFE80014 
-#define SCFCR2 	0xFFE80018 
-#define SCFDR2 	0xFFE8001C 
-#define SCSPTR2	0xFFE80020 
-#define SCLSR2 	0xFFE80024 
+#define SCBRR2 	0xFFE80004
+#define SCSCR2 	0xFFE80008
+#define SCFTDR2 0xFFE8000C
+#define SCFSR2 	0xFFE80010
+#define SCFRDR2	0xFFE80014
+#define SCFCR2 	0xFFE80018
+#define SCFDR2 	0xFFE8001C
+#define SCSPTR2	0xFFE80020
+#define SCLSR2 	0xFFE80024
 #define SCIF1_BASE	SCSMR2
-#define SDIR 	0xFFF00000 
-#define SDDR 	0xFFF00008 
-#define SDINT 	0xFFF00014 
 
-#endif	/* _ASM_CPU_SH7750_H_ */
+/*      H-UDI   */
+#define SDIR 	0xFFF00000
+#define SDDR 	0xFFF00008
+#define SDINT 	0xFFF00014
 
+#endif	/* _ASM_CPU_SH7750_H_ */
diff --git a/include/asm-sh/errno.h b/include/asm-sh/errno.h
new file mode 100644
index 0000000..0d2c618
--- /dev/null
+++ b/include/asm-sh/errno.h
@@ -0,0 +1,156 @@
+/*
+ * U-boot - errno.h Error number defines
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _BLACKFIN_ERRNO_H
+#define _BLACKFIN_ERRNO_H
+
+#define	EPERM		1	/* Operation not permitted */
+#define	ENOENT		2	/* No such file or directory */
+#define	ESRCH		3	/* No such process */
+#define	EINTR		4	/* Interrupted system call */
+#define	EIO		5	/* I/O error */
+#define	ENXIO		6	/* No such device or address */
+#define	E2BIG		7	/* Arg list too long */
+#define	ENOEXEC		8	/* Exec format error */
+#define	EBADF		9	/* Bad file number */
+#define	ECHILD		10	/* No child processes */
+#define	EAGAIN		11	/* Try again */
+#define	ENOMEM		12	/* Out of memory */
+#define	EACCES		13	/* Permission denied */
+#define	EFAULT		14	/* Bad address */
+#define	ENOTBLK		15	/* Block device required */
+#define	EBUSY		16	/* Device or resource busy */
+#define	EEXIST		17	/* File exists */
+#define	EXDEV		18	/* Cross-device link */
+#define	ENODEV		19	/* No such device */
+#define	ENOTDIR		20	/* Not a directory */
+#define	EISDIR		21	/* Is a directory */
+#define	EINVAL		22	/* Invalid argument */
+#define	ENFILE		23	/* File table overflow */
+#define	EMFILE		24	/* Too many open files */
+#define	ENOTTY		25	/* Not a typewriter */
+#define	ETXTBSY		26	/* Text file busy */
+#define	EFBIG		27	/* File too large */
+#define	ENOSPC		28	/* No space left on device */
+#define	ESPIPE		29	/* Illegal seek */
+#define	EROFS		30	/* Read-only file system */
+#define	EMLINK		31	/* Too many links */
+#define	EPIPE		32	/* Broken pipe */
+#define	EDOM		33	/* Math argument out of domain of func */
+#define	ERANGE		34	/* Math result not representable */
+#define	EDEADLK		35	/* Resource deadlock would occur */
+#define	ENAMETOOLONG	36	/* File name too long */
+#define	ENOLCK		37	/* No record locks available */
+#define	ENOSYS		38	/* Function not implemented */
+#define	ENOTEMPTY	39	/* Directory not empty */
+#define	ELOOP		40	/* Too many symbolic links encountered */
+#define	EWOULDBLOCK	EAGAIN	/* Operation would block */
+#define	ENOMSG		42	/* No message of desired type */
+#define	EIDRM		43	/* Identifier removed */
+#define	ECHRNG		44	/* Channel number out of range */
+#define	EL2NSYNC	45	/* Level 2 not synchronized */
+#define	EL3HLT		46	/* Level 3 halted */
+#define	EL3RST		47	/* Level 3 reset */
+#define	ELNRNG		48	/* Link number out of range */
+#define	EUNATCH		49	/* Protocol driver not attached */
+#define	ENOCSI		50	/* No CSI structure available */
+#define	EL2HLT		51	/* Level 2 halted */
+#define	EBADE		52	/* Invalid exchange */
+#define	EBADR		53	/* Invalid request descriptor */
+#define	EXFULL		54	/* Exchange full */
+#define	ENOANO		55	/* No anode */
+#define	EBADRQC		56	/* Invalid request code */
+#define	EBADSLT		57	/* Invalid slot */
+
+#define	EDEADLOCK	EDEADLK
+
+#define	EBFONT		59	/* Bad font file format */
+#define	ENOSTR		60	/* Device not a stream */
+#define	ENODATA		61	/* No data available */
+#define	ETIME		62	/* Timer expired */
+#define	ENOSR		63	/* Out of streams resources */
+#define	ENONET		64	/* Machine is not on the network */
+#define	ENOPKG		65	/* Package not installed */
+#define	EREMOTE		66	/* Object is remote */
+#define	ENOLINK		67	/* Link has been severed */
+#define	EADV		68	/* Advertise error */
+#define	ESRMNT		69	/* Srmount error */
+#define	ECOMM		70	/* Communication error on send */
+#define	EPROTO		71	/* Protocol error */
+#define	EMULTIHOP	72	/* Multihop attempted */
+#define	EDOTDOT		73	/* RFS specific error */
+#define	EBADMSG		74	/* Not a data message */
+#define	EOVERFLOW	75	/* Value too large for defined data type */
+#define	ENOTUNIQ	76	/* Name not unique on network */
+#define	EBADFD		77	/* File descriptor in bad state */
+#define	EREMCHG		78	/* Remote address changed */
+#define	ELIBACC		79	/* Can not access a needed shared library */
+#define	ELIBBAD		80	/* Accessing a corrupted shared library */
+#define	ELIBSCN		81	/* .lib section in a.out corrupted */
+#define	ELIBMAX		82	/* Attempting to link in too many shared libraries */
+#define	ELIBEXEC	83	/* Cannot exec a shared library directly */
+#define	EILSEQ		84	/* Illegal byte sequence */
+#define	ERESTART	85	/* Interrupted system call should be restarted */
+#define	ESTRPIPE	86	/* Streams pipe error */
+#define	EUSERS		87	/* Too many users */
+#define	ENOTSOCK	88	/* Socket operation on non-socket */
+#define	EDESTADDRREQ	89	/* Destination address required */
+#define	EMSGSIZE	90	/* Message too long */
+#define	EPROTOTYPE	91	/* Protocol wrong type for socket */
+#define	ENOPROTOOPT	92	/* Protocol not available */
+#define	EPROTONOSUPPORT	93	/* Protocol not supported */
+#define	ESOCKTNOSUPPORT	94	/* Socket type not supported */
+#define	EOPNOTSUPP	95	/* Operation not supported on transport endpoint */
+#define	EPFNOSUPPORT	96	/* Protocol family not supported */
+#define	EAFNOSUPPORT	97	/* Address family not supported by protocol */
+#define	EADDRINUSE	98	/* Address already in use */
+#define	EADDRNOTAVAIL	99	/* Cannot assign requested address */
+#define	ENETDOWN	100	/* Network is down */
+#define	ENETUNREACH	101	/* Network is unreachable */
+#define	ENETRESET	102	/* Network dropped connection because of reset */
+#define	ECONNABORTED	103	/* Software caused connection abort */
+#define	ECONNRESET	104	/* Connection reset by peer */
+#define	ENOBUFS		105	/* No buffer space available */
+#define	EISCONN		106	/* Transport endpoint is already connected */
+#define	ENOTCONN	107	/* Transport endpoint is not connected */
+#define	ESHUTDOWN	108	/* Cannot send after transport endpoint shutdown */
+#define	ETOOMANYREFS	109	/* Too many references: cannot splice */
+#define	ETIMEDOUT	110	/* Connection timed out */
+#define	ECONNREFUSED	111	/* Connection refused */
+#define	EHOSTDOWN	112	/* Host is down */
+#define	EHOSTUNREACH	113	/* No route to host */
+#define	EALREADY	114	/* Operation already in progress */
+#define	EINPROGRESS	115	/* Operation now in progress */
+#define	ESTALE		116	/* Stale NFS file handle */
+#define	EUCLEAN		117	/* Structure needs cleaning */
+#define	ENOTNAM		118	/* Not a XENIX named type file */
+#define	ENAVAIL		119	/* No XENIX semaphores available */
+#define	EISNAM		120	/* Is a named type file */
+#define	EREMOTEIO	121	/* Remote I/O error */
+#define	EDQUOT		122	/* Quota exceeded */
+
+#define	ENOMEDIUM	123	/* No medium found */
+#define	EMEDIUMTYPE	124	/* Wrong medium type */
+
+#endif
diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h
index 70e60b1..03427ad 100644
--- a/include/asm-sh/io.h
+++ b/include/asm-sh/io.h
@@ -91,23 +91,21 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen);
  *
  * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
  */
-#ifdef __io
-#define outb(v,p)			__raw_writeb(v,__io(p))
-#define outw(v,p)			__raw_writew(cpu_to_le16(v),__io(p))
-#define outl(v,p)			__raw_writel(cpu_to_le32(v),__io(p))
-
-#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
-#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
-#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
-
-#define outsb(p,d,l)			__raw_writesb(__io(p),d,l)
-#define outsw(p,d,l)			__raw_writesw(__io(p),d,l)
-#define outsl(p,d,l)			__raw_writesl(__io(p),d,l)
-
-#define insb(p,d,l)			__raw_readsb(__io(p),d,l)
-#define insw(p,d,l)			__raw_readsw(__io(p),d,l)
-#define insl(p,d,l)			__raw_readsl(__io(p),d,l)
-#endif
+#define outb(v,p)               __raw_writeb(v, p)
+#define outw(v,p)               __raw_writew(cpu_to_le16(v),p)
+#define outl(v,p)               __raw_writel(cpu_to_le32(v),p)
+
+#define inb(p)  ({ unsigned int __v = __raw_readb(p); __v; })
+#define inw(p)  ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; })
+#define inl(p)  ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; })
+
+#define outsb(p,d,l)			__raw_writesb(p,d,l)
+#define outsw(p,d,l)			__raw_writesw(p,d,l)
+#define outsl(p,d,l)			__raw_writesl(p,d,l)
+
+#define insb(p,d,l)			__raw_readsb(p,d,l)
+#define insw(p,d,l)			__raw_readsw(p,d,l)
+#define insl(p,d,l)			__raw_readsl(p,d,l)
 
 #define outb_p(val,port)		outb((val),(port))
 #define outw_p(val,port)		outw((val),(port))
@@ -174,8 +172,6 @@ extern void _memcpy_fromio(void *, unsigned long, size_t);
 extern void _memcpy_toio(unsigned long, const void *, size_t);
 extern void _memset_io(unsigned long, int, size_t);
 
-extern void __readwrite_bug(const char *fn);
-
 /*
  * If this architecture has PCI memory IO, then define the read/write
  * macros.  These should only be used with the cookie passed from
@@ -217,76 +213,19 @@ out:
 
 #elif !defined(readb)
 
-#define readb(addr)			(__readwrite_bug("readb"),0)
-#define readw(addr)			(__readwrite_bug("readw"),0)
-#define readl(addr)			(__readwrite_bug("readl"),0)
-#define writeb(v,addr)			__readwrite_bug("writeb")
-#define writew(v,addr)			__readwrite_bug("writew")
-#define writel(v,addr)			__readwrite_bug("writel")
-
-#define eth_io_copy_and_sum(a,b,c,d)	__readwrite_bug("eth_io_copy_and_sum")
+#define readb(addr)	__raw_readb(addr)
+#define readw(addr)	__raw_readw(addr)
+#define readl(addr)	__raw_readl(addr)
+#define writeb(v,addr)	__raw_writeb(v, addr)
+#define writew(v,addr)	__raw_writew(v, addr)
+#define writel(v,addr)	__raw_writel(v, addr)
 
 #define check_signature(io,sig,len)	(0)
 
 #endif	/* __mem_pci */
 
-/*
- * If this architecture has ISA IO, then define the isa_read/isa_write
- * macros.
- */
-#ifdef __mem_isa
-
-#define isa_readb(addr)			__raw_readb(__mem_isa(addr))
-#define isa_readw(addr)			__raw_readw(__mem_isa(addr))
-#define isa_readl(addr)			__raw_readl(__mem_isa(addr))
-#define isa_writeb(val,addr)		__raw_writeb(val,__mem_isa(addr))
-#define isa_writew(val,addr)		__raw_writew(val,__mem_isa(addr))
-#define isa_writel(val,addr)		__raw_writel(val,__mem_isa(addr))
-#define isa_memset_io(a,b,c)		_memset_io(__mem_isa(a),(b),(c))
-#define isa_memcpy_fromio(a,b,c)	_memcpy_fromio((a),__mem_isa(b),(c))
-#define isa_memcpy_toio(a,b,c)		_memcpy_toio(__mem_isa((a)),(b),(c))
-
-#define isa_eth_io_copy_and_sum(a,b,c,d) \
-				eth_copy_and_sum((a),__mem_isa(b),(c),(d))
-
-static inline int
-isa_check_signature(unsigned long io_addr, const unsigned char *signature,
-		    int length)
-{
-	int retval = 0;
-	do {
-		if (isa_readb(io_addr) != *signature)
-			goto out;
-		io_addr++;
-		signature++;
-		length--;
-	} while (length);
-	retval = 1;
-out:
-	return retval;
-}
-
-#else	/* __mem_isa */
-
-#define isa_readb(addr)			(__readwrite_bug("isa_readb"),0)
-#define isa_readw(addr)			(__readwrite_bug("isa_readw"),0)
-#define isa_readl(addr)			(__readwrite_bug("isa_readl"),0)
-#define isa_writeb(val,addr)		__readwrite_bug("isa_writeb")
-#define isa_writew(val,addr)		__readwrite_bug("isa_writew")
-#define isa_writel(val,addr)		__readwrite_bug("isa_writel")
-#define isa_memset_io(a,b,c)		__readwrite_bug("isa_memset_io")
-#define isa_memcpy_fromio(a,b,c)	__readwrite_bug("isa_memcpy_fromio")
-#define isa_memcpy_toio(a,b,c)		__readwrite_bug("isa_memcpy_toio")
-
-#define isa_eth_io_copy_and_sum(a,b,c,d) \
-				__readwrite_bug("isa_eth_io_copy_and_sum")
-
-#define isa_check_signature(io,sig,len)	(0)
-
 static inline void sync(void)
 {
 }
-
-#endif	/* __mem_isa */
 #endif	/* __KERNEL__ */
 #endif	/* __ASM_SH_IO_H */
diff --git a/include/asm-sh/irqflags.h b/include/asm-sh/irqflags.h
new file mode 100644
index 0000000..830e548
--- /dev/null
+++ b/include/asm-sh/irqflags.h
@@ -0,0 +1,126 @@
+#ifndef __ASM_SH_IRQFLAGS_H
+#define __ASM_SH_IRQFLAGS_H
+
+static inline void raw_local_irq_enable(void)
+{
+	unsigned long __dummy0, __dummy1;
+
+	__asm__ __volatile__ (
+		"stc	sr, %0\n\t"
+		"and	%1, %0\n\t"
+#ifdef CONFIG_CPU_HAS_SR_RB
+		"stc	r6_bank, %1\n\t"
+		"or	%1, %0\n\t"
+#endif
+		"ldc	%0, sr\n\t"
+		: "=&r" (__dummy0), "=r" (__dummy1)
+		: "1" (~0x000000f0)
+		: "memory"
+	);
+}
+
+static inline void raw_local_irq_disable(void)
+{
+	unsigned long flags;
+
+	__asm__ __volatile__ (
+		"stc	sr, %0\n\t"
+		"or	#0xf0, %0\n\t"
+		"ldc	%0, sr\n\t"
+		: "=&z" (flags)
+		: /* no inputs */
+		: "memory"
+	);
+}
+
+static inline void set_bl_bit(void)
+{
+	unsigned long __dummy0, __dummy1;
+
+	__asm__ __volatile__ (
+		"stc	sr, %0\n\t"
+		"or	%2, %0\n\t"
+		"and	%3, %0\n\t"
+		"ldc	%0, sr\n\t"
+		: "=&r" (__dummy0), "=r" (__dummy1)
+		: "r" (0x10000000), "r" (0xffffff0f)
+		: "memory"
+	);
+}
+
+static inline void clear_bl_bit(void)
+{
+	unsigned long __dummy0, __dummy1;
+
+	__asm__ __volatile__ (
+		"stc	sr, %0\n\t"
+		"and	%2, %0\n\t"
+		"ldc	%0, sr\n\t"
+		: "=&r" (__dummy0), "=r" (__dummy1)
+		: "1" (~0x10000000)
+		: "memory"
+	);
+}
+
+static inline unsigned long __raw_local_save_flags(void)
+{
+	unsigned long flags;
+
+	__asm__ __volatile__ (
+		"stc	sr, %0\n\t"
+		"and	#0xf0, %0\n\t"
+		: "=&z" (flags)
+		: /* no inputs */
+		: "memory"
+	);
+
+	return flags;
+}
+
+#define raw_local_save_flags(flags) \
+		do { (flags) = __raw_local_save_flags(); } while (0)
+
+static inline int raw_irqs_disabled_flags(unsigned long flags)
+{
+	return (flags != 0);
+}
+
+static inline int raw_irqs_disabled(void)
+{
+	unsigned long flags = __raw_local_save_flags();
+
+	return raw_irqs_disabled_flags(flags);
+}
+
+static inline unsigned long __raw_local_irq_save(void)
+{
+	unsigned long flags, __dummy;
+
+	__asm__ __volatile__ (
+		"stc	sr, %1\n\t"
+		"mov	%1, %0\n\t"
+		"or	#0xf0, %0\n\t"
+		"ldc	%0, sr\n\t"
+		"mov	%1, %0\n\t"
+		"and	#0xf0, %0\n\t"
+		: "=&z" (flags), "=&r" (__dummy)
+		: /* no inputs */
+		: "memory"
+	);
+
+	return flags;
+}
+
+#define raw_local_irq_save(flags) \
+		do { (flags) = __raw_local_irq_save(); } while (0)
+
+#define local_irq_save raw_local_irq_save
+
+static inline void raw_local_irq_restore(unsigned long flags)
+{
+	if ((flags & 0xf0) != 0xf0)
+		raw_local_irq_enable();
+}
+#define local_irq_restore raw_local_irq_restore
+
+#endif /* __ASM_SH_IRQFLAGS_H */
diff --git a/include/asm-sh/string.h b/include/asm-sh/string.h
index a78ef81..27d981b 100644
--- a/include/asm-sh/string.h
+++ b/include/asm-sh/string.h
@@ -8,6 +8,8 @@
  * from linux kernel code.
  */
 
+#ifdef __KERNEL__               /* only set these up for kernel code */
+
 #define __HAVE_ARCH_STRCPY
 static inline char *strcpy(char *__dest, const char *__src)
 {
@@ -129,4 +131,32 @@ extern size_t strlen(const char *);
 /* arch/sh/lib/strcasecmp.c */
 extern int strcasecmp(const char *, const char *);
 
+#else                           /* KERNEL */
+
+/*
+ * let user libraries deal with these,
+ * IMHO the kernel has no place defining these functions for user apps
+ */
+
+#define __HAVE_ARCH_STRCPY      1
+#define __HAVE_ARCH_STRNCPY     1
+#define __HAVE_ARCH_STRCAT      1
+#define __HAVE_ARCH_STRNCAT     1
+#define __HAVE_ARCH_STRCMP      1
+#define __HAVE_ARCH_STRNCMP     1
+#define __HAVE_ARCH_STRNICMP    1
+#define __HAVE_ARCH_STRCHR      1
+#define __HAVE_ARCH_STRRCHR     1
+#define __HAVE_ARCH_STRSTR      1
+#define __HAVE_ARCH_STRLEN      1
+#define __HAVE_ARCH_STRNLEN     1
+#define __HAVE_ARCH_MEMSET      1
+#define __HAVE_ARCH_MEMCPY      1
+#define __HAVE_ARCH_MEMMOVE     1
+#define __HAVE_ARCH_MEMSCAN     1
+#define __HAVE_ARCH_MEMCMP      1
+#define __HAVE_ARCH_MEMCHR      1
+#define __HAVE_ARCH_STRTOK      1
+
+#endif /* KERNEL */
 #endif /* __ASM_SH_STRING_H */