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| author | Kumar Gala <galak@kernel.crashing.org> | 2009-09-01 22:01:54 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-09-08 09:10:04 -0500 |
| commit | 2abbd31da6d900473ed678ca50789ee58bc9bb00 (patch) | |
| tree | 04faa2d9df989a87f184b745848e657dd03ff634 /include | |
| parent | 13d46ab2572c0283d34f93bebc9a41295ef84ca5 (diff) | |
| download | u-boot-imx-2abbd31da6d900473ed678ca50789ee58bc9bb00.zip u-boot-imx-2abbd31da6d900473ed678ca50789ee58bc9bb00.tar.gz u-boot-imx-2abbd31da6d900473ed678ca50789ee58bc9bb00.tar.bz2 | |
ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist
The ddr_pd_cntl isn't defined in any reference manual and thus we wil
remove especially since we set it to 0, which would most likely be its
POR value.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/fsl_ddr_sdram.h | 1 | ||||
| -rw-r--r-- | include/asm-ppc/immap_85xx.h | 2 |
2 files changed, 1 insertions, 2 deletions
diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index c2e5aee..69b857b 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -110,7 +110,6 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int timing_cfg_5; unsigned int ddr_zq_cntl; unsigned int ddr_wrlvl_cntl; - unsigned int ddr_pd_cntl; unsigned int ddr_sr_cntr; unsigned int ddr_sdram_rcw_1; unsigned int ddr_sdram_rcw_2; diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 375d804..e7d412d 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -132,7 +132,7 @@ typedef struct ccsr_ddr { char reg8_1a[8]; uint ddr_zq_cntl; /* 0x2170 - DDR ZQ calibration control*/ uint ddr_wrlvl_cntl; /* 0x2174 - DDR write leveling control*/ - uint ddr_pd_cntl; /* 0x2178 - DDR pre-drive conditioning control*/ + char reg8_1aa[4]; uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */ uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */ uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */ |