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| author | Liu Yu <yu.liu@freescale.com> | 2008-10-10 11:40:59 +0800 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:54:07 +0200 |
| commit | 7e183cad0c5ab6415dca95d6ac290ea918b28c55 (patch) | |
| tree | 43e8f0df0bff836c69834c0241bfc695b85940d0 /include | |
| parent | bff188baf9427c35745356439435acf3864d4c65 (diff) | |
| download | u-boot-imx-7e183cad0c5ab6415dca95d6ac290ea918b28c55.zip u-boot-imx-7e183cad0c5ab6415dca95d6ac290ea918b28c55.tar.gz u-boot-imx-7e183cad0c5ab6415dca95d6ac290ea918b28c55.tar.bz2 | |
Enabled the Freescale SGMII riser card on 8572DS
This patch based on Andy's work.
Including command 'pixis_set_sgmii' support.
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/MPC8572DS.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index c2606fa..5688589 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -239,6 +239,22 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 +#define PIXIS_VSPEED2_TSEC1SER 0x8 +#define PIXIS_VSPEED2_TSEC2SER 0x4 +#define PIXIS_VSPEED2_TSEC3SER 0x2 +#define PIXIS_VSPEED2_TSEC4SER 0x1 +#define PIXIS_VCFGEN1_TSEC1SER 0x20 +#define PIXIS_VCFGEN1_TSEC2SER 0x20 +#define PIXIS_VCFGEN1_TSEC3SER 0x20 +#define PIXIS_VCFGEN1_TSEC4SER 0x20 +#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ + | PIXIS_VSPEED2_TSEC2SER \ + | PIXIS_VSPEED2_TSEC3SER \ + | PIXIS_VSPEED2_TSEC4SER) +#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ + | PIXIS_VCFGEN1_TSEC2SER \ + | PIXIS_VCFGEN1_TSEC3SER \ + | PIXIS_VCFGEN1_TSEC4SER) /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM @@ -418,6 +434,14 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_TSEC4 1 #define CONFIG_TSEC4_NAME "eTSEC4" +#define CONFIG_PIXIS_SGMII_CMD +#define CONFIG_FSL_SGMII_RISER 1 +#define SGMII_RISER_PHY_OFFSET 0x1c + +#ifdef CONFIG_FSL_SGMII_RISER +#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ +#endif + #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC3_PHY_ADDR 2 |