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| author | Stefan Roese <sr@denx.de> | 2007-11-16 14:16:54 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-11-16 14:16:54 +0100 |
| commit | f31d38b9eea9b32f6a1ac848a298cc71ca4c9a03 (patch) | |
| tree | 8af96c3ac5e48e17b0f4595f5cd53f8eabef3204 /include | |
| parent | ecdcbd4f8c1f8cefd785752f4e7536aae2a4ecf9 (diff) | |
| download | u-boot-imx-f31d38b9eea9b32f6a1ac848a298cc71ca4c9a03.zip u-boot-imx-f31d38b9eea9b32f6a1ac848a298cc71ca4c9a03.tar.gz u-boot-imx-f31d38b9eea9b32f6a1ac848a298cc71ca4c9a03.tar.bz2 | |
ppc4xx: Enable 405EX PCIe UTL register configuration
Till now the UTL registers on 405EX were not initialized but left with
their default values. This patch new initializes some of the UTL
registers on 405EX.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/4xx_pcie.h | 2 | ||||
| -rw-r--r-- | include/common.h | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index ffe0770..4c03b05 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -203,6 +203,7 @@ /* * UTL register offsets */ +#define PEUTL_PBCTL 0x00 #define PEUTL_PBBSZ 0x20 #define PEUTL_OPDBSZ 0x68 #define PEUTL_IPHBSZ 0x70 @@ -210,6 +211,7 @@ #define PEUTL_OUTTR 0x90 #define PEUTL_INTR 0x98 #define PEUTL_PCTL 0xa0 +#define PEUTL_RCSTA 0xb0 #define PEUTL_RCIRQEN 0xb8 /* diff --git a/include/common.h b/include/common.h index 46ed6bd..77aed1a 100644 --- a/include/common.h +++ b/include/common.h @@ -516,10 +516,10 @@ void get_sys_info ( sys_info_t * ); # if defined(CONFIG_440SPE) unsigned long determine_sysper(void); unsigned long determine_pci_clock_per(void); - int ppc440spe_revB(void); # endif # endif typedef PPC4xx_SYS_INFO sys_info_t; +int ppc440spe_revB(void); void get_sys_info ( sys_info_t * ); #endif |