diff options
| author | Kumar Gala <galak@kernel.crashing.org> | 2008-04-29 10:28:34 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-04-29 11:42:05 -0500 |
| commit | ef7d30b14394e4c4a153118f5845760cadada02a (patch) | |
| tree | bcd8f2e813728bbf069b71aab97d3cf771680abe /include | |
| parent | cf6cc014270549684873a5972d2595052c468cb6 (diff) | |
| download | u-boot-imx-ef7d30b14394e4c4a153118f5845760cadada02a.zip u-boot-imx-ef7d30b14394e4c4a153118f5845760cadada02a.tar.gz u-boot-imx-ef7d30b14394e4c4a153118f5845760cadada02a.tar.bz2 | |
85xx/86xx: Rename DDR init address and init extended address register
Rename init_addr and init_ext_addr to match the docs between
85xx and 86xx. Both now use 'init_addr' and 'init_ext_addr'.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/immap_85xx.h | 4 | ||||
| -rw-r--r-- | include/asm-ppc/immap_86xx.h | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index dc6e278..da97cd4 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -106,8 +106,8 @@ typedef struct ccsr_ddr { char res6[4]; uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ char res7[20]; - uint init_address; /* 0x2148 - DDR training initialization address */ - uint init_ext_address; /* 0x214C - DDR training initialization extended address */ + uint init_addr; /* 0x2148 - DDR training initialization address */ + uint init_ext_addr; /* 0x214C - DDR training initialization extended address */ char res8_1[16]; uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */ uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */ diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 7526061..4287cf4 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -126,7 +126,7 @@ typedef struct ccsr_ddr { uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */ uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */ uint init_addr; /* 0x2148 - DDR training initialzation address */ - uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */ + uint init_ext_addr; /* 0x214C - DDR training initialzation extended address */ char res10[2728]; uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ |