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| author | Stefan Roese <sr@denx.de> | 2015-03-25 12:51:18 +0100 |
|---|---|---|
| committer | Luka Perkov <luka.perkov@sartura.hr> | 2015-07-23 10:38:30 +0200 |
| commit | ff9112df8b643ad989e8673452c75e073f3c9ff3 (patch) | |
| tree | 8986434c16c6ee7316b64add8d7c0b9653eddaab /include | |
| parent | edb470253346f4a882ba9e891c8b102ce388b9cc (diff) | |
| download | u-boot-imx-ff9112df8b643ad989e8673452c75e073f3c9ff3.zip u-boot-imx-ff9112df8b643ad989e8673452c75e073f3c9ff3.tar.gz u-boot-imx-ff9112df8b643ad989e8673452c75e073f3c9ff3.tar.bz2 | |
arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new directory
With the upcoming addition of the Armada 38x DDR support, which is not
compatible to the Armada XP DDR init code, we need to introduce a new
directory infrastructure. To support multiple Marvell DDR controller.
This will be the new structure:
drivers/ddr/marvell/axp
Supporting Armada XP (AXP) devices (and perhaps Armada 370)
drivers/ddr/marvell/a38x
Supporting Armada 38x devices (and perhaps Armada 39x)
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/db-mv784mp-gp.h | 2 | ||||
| -rw-r--r-- | include/configs/maxbcm.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index aeddbf9..41e6fdc 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -138,7 +138,7 @@ #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SYS_MVEBU_DDR +#define CONFIG_SYS_MVEBU_DDR_AXP #define CONFIG_SPD_EEPROM 0x4e #endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index 4826044..0fb117f 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -108,7 +108,7 @@ #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SYS_MVEBU_DDR +#define CONFIG_SYS_MVEBU_DDR_AXP #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ #endif /* _CONFIG_DB_MV7846MP_GP_H */ |