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authorPrabhakar Kushwaha <prabhakar@freescale.com>2015-03-20 19:28:26 -0700
committerYork Sun <yorksun@freescale.com>2015-04-23 16:46:50 -0700
commite60476a01ebe7d8c46aac5673dcf55b661187c19 (patch)
treed73031d7cf49371660c3fa4c9796c73c62c53e2a /include
parente2b65ea975c2ddc67a958bf428e34ee3c543061a (diff)
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board/ls2085qds: Add support ethernet
Add support of ethernet: - eth.c: mapping lane to slot for (0x2A, 0x07) - ls2085a.c: To enable/disable dpmac and get link type Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/ls2085aqds.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
index b1d2d48..74c71d9 100644
--- a/include/configs/ls2085aqds.h
+++ b/include/configs/ls2085aqds.h
@@ -280,4 +280,23 @@ unsigned long get_board_ddr_clk(void);
"kernel_load=0xa0000000\0" \
"kernel_size=0x1000000\0"
+#ifdef CONFIG_FSL_MC_ENET
+#define CONFIG_FSL_MEMAC
+#define CONFIG_PHYLIB
+#define CONFIG_PHYLIB_10G
+#define CONFIG_CMD_MII
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "DPNI1"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+
+#endif
+
#endif /* __LS2_QDS_H */