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| author | Tom Rini <trini@konsulko.com> | 2015-05-22 17:23:15 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-05-22 17:23:15 -0400 |
| commit | a84988c76d1dbca2dbe870d6b4f0ad398f287f85 (patch) | |
| tree | ac63bcd85d6cdcc73718ab1d9d6067917ed3e35d /include | |
| parent | 133ebeabc22d9cff260c29af9783b714146121a7 (diff) | |
| parent | a88cc3bd90b05420a84ee360efa1133652dcac5c (diff) | |
| download | u-boot-imx-a84988c76d1dbca2dbe870d6b4f0ad398f287f85.zip u-boot-imx-a84988c76d1dbca2dbe870d6b4f0ad398f287f85.tar.gz u-boot-imx-a84988c76d1dbca2dbe870d6b4f0ad398f287f85.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/ls1021aqds.h | 2 | ||||
| -rw-r--r-- | include/configs/ls1021atwr.h | 25 | ||||
| -rw-r--r-- | include/fsl_immap.h | 4 |
3 files changed, 26 insertions, 5 deletions
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 9a8fd50..1a41a2f 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -124,7 +124,7 @@ unsigned long get_board_ddr_clk(void); #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x67f80000 +#define CONFIG_SYS_TEXT_BASE 0x60100000 #endif #define CONFIG_NR_DRAM_BANKS 1 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 729205f..8ea428e 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -35,6 +35,29 @@ #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000 +#define DDR_SDRAM_CFG 0x470c0008 +#define DDR_CS0_BNDS 0x008000bf +#define DDR_CS0_CONFIG 0x80014302 +#define DDR_TIMING_CFG_0 0x50550004 +#define DDR_TIMING_CFG_1 0xbcb38c56 +#define DDR_TIMING_CFG_2 0x0040d120 +#define DDR_TIMING_CFG_3 0x010e1000 +#define DDR_TIMING_CFG_4 0x00000001 +#define DDR_TIMING_CFG_5 0x03401400 +#define DDR_SDRAM_CFG_2 0x00401010 +#define DDR_SDRAM_MODE 0x00061c60 +#define DDR_SDRAM_MODE_2 0x00180000 +#define DDR_SDRAM_INTERVAL 0x18600618 +#define DDR_DDR_WRLVL_CNTL 0x8655f605 +#define DDR_DDR_WRLVL_CNTL_2 0x05060607 +#define DDR_DDR_WRLVL_CNTL_3 0x05050505 +#define DDR_DDR_CDR1 0x80040000 +#define DDR_DDR_CDR2 0x00000001 +#define DDR_SDRAM_CLK_CNTL 0x02000000 +#define DDR_DDR_ZQ_CNTL 0x89080600 +#define DDR_CS0_CONFIG_2 0 +#define DDR_SDRAM_CFG_MEM_EN 0x80000000 + #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg #endif @@ -73,7 +96,7 @@ #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x67f80000 +#define CONFIG_SYS_TEXT_BASE 0x60100000 #endif #define CONFIG_NR_DRAM_BANKS 1 diff --git a/include/fsl_immap.h b/include/fsl_immap.h index d63cc19..e4addad 100644 --- a/include/fsl_immap.h +++ b/include/fsl_immap.h @@ -87,9 +87,7 @@ struct ccsr_ddr { u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */ u8 res_258[0x260-0x258]; u32 sdram_cfg_3; - u8 res_264[0x2a0-0x264]; - u32 deskew_cntl; - u8 res_2a4[0x400-0x2a4]; + u8 res_264[0x400-0x264]; u32 dq_map_0; u32 dq_map_1; u32 dq_map_2; |