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authorShengzhou Liu <Shengzhou.Liu@freescale.com>2015-11-20 15:52:03 +0800
committerYork Sun <yorksun@freescale.com>2015-12-13 18:27:28 -0800
commita07bdad749ea080e009a82ba40e791dc7361ab54 (patch)
treee194d47ecfe1f787122b261a2cac161fb8b4210b /include
parent0c028a03284aabceb89a85736e23661d6fe7915e (diff)
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fsl/errata: move fsl_errata.h to common directory
move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h to make it public for both ARM and POWER SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix soc.h path in fsl_errata.h] Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/fsl_errata.h61
1 files changed, 61 insertions, 0 deletions
diff --git a/include/fsl_errata.h b/include/fsl_errata.h
new file mode 100644
index 0000000..aebe3d2
--- /dev/null
+++ b/include/fsl_errata.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2013 - 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FSL_ERRATA_H
+#define _FSL_ERRATA_H
+
+#include <common.h>
+#if defined(CONFIG_PPC)
+#include <asm/processor.h>
+#elif defined(CONFIG_LS102XA)
+#include <asm/arch-ls102xa/immap_ls102xa.h>
+#elif defined(CONFIG_FSL_LAYERSCAPE)
+#include <asm/arch/soc.h>
+#endif
+
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
+static inline bool has_erratum_a006379(void)
+{
+ u32 svr = get_svr();
+ if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) ||
+ ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) ||
+ ((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) ||
+ ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) ||
+ ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) ||
+ ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) ||
+ ((SVR_SOC_VER(svr) == SVR_T2081) && SVR_MAJ(svr) <= 1))
+ return true;
+
+ return false;
+}
+#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+static inline bool has_erratum_a007186(void)
+{
+ u32 svr = get_svr();
+ u32 soc = SVR_SOC_VER(svr);
+
+ switch (soc) {
+ case SVR_T4240:
+ return IS_SVR_REV(svr, 2, 0);
+ case SVR_T4160:
+ return IS_SVR_REV(svr, 2, 0);
+ case SVR_B4860:
+ return IS_SVR_REV(svr, 2, 0);
+ case SVR_B4420:
+ return IS_SVR_REV(svr, 2, 0);
+ case SVR_T2081:
+ case SVR_T2080:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+ }
+
+ return false;
+}
+#endif
+
+#endif /* _FSL_ERRATA_H */