powerpc: 74xx_7xx: remove 74xx_7xx cpu support

All the 74xx_7xx boards are still non-generic boards:
P3G4, ZUMA, ppmc7xx, ELPPC, mpc7448hpc2

Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Nye Liu <nyet@zumanetworks.com>
Cc: Roy Zang <tie-fei.zang@freescale.com>

11 files changed, 0 insertions, 3646 deletions

diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h
deleted file mode 100644
index 3deeeea..0000000
--- a/include/74xx_7xx.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber, Mission Critical Linux, Inc. <huber@mclx.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * 74xx_7xx.h
- *
- * 74xx/7xx specific definitions
- */
-
-#ifndef __MPC74XX_H__
-#define __MPC74XX_H__
-
-/*----------------------------------------------------------------
- * Exception offsets (PowerPC standard)
- */
-#define EXC_OFF_SYS_RESET        0x0100      /* default system reset offset */
-#define _START_OFFSET		EXC_OFF_SYS_RESET
-
-/*----------------------------------------------------------------
- * l2cr values
- */
-#define l2cr		 1017
-
-#define L2CR_L2E         0x80000000 /* bit 0 - enable */
-#define L2CR_L2PE        0x40000000 /* bit 1 - data parity */
-#define L2CR_L2SIZ_2M    0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */
-#define L2CR_L2SIZ_1M    0x30000000 /* ... 1MB */
-#define L2CR_L2SIZ_HM    0x20000000 /* ... 512K */
-#define L2CR_L2SIZ_QM    0x10000000 /* ... 256k */
-#define L2CR_L2CLK_1     0x02000000 /* bits 4-6 clock ratio div 1 */
-#define L2CR_L2CLK_1_5   0x04000000 /* bits 4-6 clock ratio div 1.5 */
-#define L2CR_L2CLK_2     0x08000000 /* bits 4-6 clock ratio div 2 */
-#define L2CR_L2CLK_2_5   0x0a000000 /* bits 4-6 clock ratio div 2.5 */
-#define L2CR_L2CLK_3     0x0c000000 /* bits 4-6 clock ratio div 3 */
-#define L2CR_L2CLK_3_5   0x06000000 /* bits 4-6 clock ratio div 3.5 */
-#define L2CR_L2CLK_4     0x0e000000 /* bits 4-6 clock ratio div 4 */
-#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */
-#define L2CR_DO          0x00400000 /* bit 9 - enable caching of instr. in L2 */
-#define L2CR_L2I         0x00200000 /* bit 10 - global invalidate bit */
-#define L2CR_L2CTL       0x00100000 /* bit 11 - l2 ram control */
-#define L2CR_L2WT        0x00080000 /* bit 12 - l2 write-through */
-#define L2CR_TS          0x00040000 /* bit 13 - test support on */
-#define L2CR_TS_OFF      -L2CR_TS   /* bit 13 - test support off */
-#define L2CR_L2OH_5      0x00000000 /* bits 14-15 - output hold time = short */
-#define L2CR_L2OH_1      0x00010000 /* bits 14-15 - output hold time = medium */
-#define L2CR_L2OH_INV    0x00020000 /* bits 14-15 - output hold time = long */
-#define L2CR_L2IP        0x00000001 /* global invalidate in progress */
-
-#ifndef __ASSEMBLY__
-/* cpu ids we detect */
-typedef enum __cpu_t {
-	CPU_740, CPU_750,
-	CPU_740P, CPU_750P,
-	CPU_745, CPU_755,
-	CPU_750CX, CPU_750FX, CPU_750GX,
-	CPU_7400,
-	CPU_7410,
-	CPU_7447A, CPU_7448,
-	CPU_7450, CPU_7455, CPU_7457,
-	CPU_UNKNOWN} cpu_t;
-
-extern cpu_t get_cpu_type(void);
-
-#define l1icache_enable	icache_enable
-
-void l2cache_enable(void);
-void l1dcache_enable(void);
-
-static __inline__ unsigned long get_msr (void)
-{
-	unsigned long msr;
-	asm volatile("mfmsr %0" : "=r" (msr) :);
-	return msr;
-}
-
-static __inline__ void set_msr (unsigned long msr)
-{
-	asm volatile("mtmsr %0" : : "r" (msr));
-}
-
-static __inline__ unsigned long get_hid0 (void)
-{
-	unsigned long hid0;
-	asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
-	return hid0;
-}
-
-static __inline__ unsigned long get_hid1 (void)
-{
-	unsigned long hid1;
-	asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
-	return hid1;
-}
-
-static __inline__ void set_hid0 (unsigned long hid0)
-{
-	asm volatile("mtspr 1008, %0" : : "r" (hid0));
-}
-
-static __inline__ void set_hid1 (unsigned long hid1)
-{
-	asm volatile("mtspr 1009, %0" : : "r" (hid1));
-}
-
-#endif	/* __ASSEMBLY__ */
-#endif  /* __MPC74XX_H__ */
diff --git a/include/common.h b/include/common.h
index 29350e4..4b3e0d3 100644
--- a/include/common.h
+++ b/include/common.h
@@ -435,13 +435,6 @@ extern ssize_t spi_read	 (uchar *, int, uchar *, int);
 extern ssize_t spi_write (uchar *, int, uchar *, int);
 #endif
 
-#ifdef CONFIG_EVB64260
-void  evb64260_init(void);
-void  debug_led(int, int);
-void  display_mem_map(void);
-void  perform_soft_reset(void);
-#endif
-
 /* $(BOARD)/$(BOARD).c */
 int board_early_init_f (void);
 int board_late_init (void);
@@ -486,10 +479,6 @@ ulong	get_endaddr   (void);
 void	trap_init     (ulong);
 #if defined (CONFIG_4xx)	|| \
     defined (CONFIG_MPC5xxx)	|| \
-    defined (CONFIG_74xx_7xx)	|| \
-    defined (CONFIG_74x)	|| \
-    defined (CONFIG_75x)	|| \
-    defined (CONFIG_74xx)	|| \
     defined (CONFIG_MPC85xx)	|| \
     defined (CONFIG_MPC86xx)	|| \
     defined (CONFIG_MPC83xx)
diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h
deleted file mode 100644
index debfc36..0000000
--- a/include/configs/ELPPC.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/*
- * (C) Copyright 2002 ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define GTREGREAD(x) 0xffffffff         /* needed for debug */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-/* these hardware addresses are pretty bogus, please change them to
-   suit your needs */
-
-/* first ethernet */
-#define CONFIG_ETHADDR          00:00:5b:ee:de:ad
-
-#define CONFIG_IPADDR           192.168.0.105
-#define CONFIG_SERVERIP         192.168.0.100
-
-#define CONFIG_ELPPC            1       /* this is an BAB740/BAB750 board */
-
-#define CONFIG_BAUDRATE         9600    /* console baudrate */
-
-#undef  CONFIG_WATCHDOG
-
-#define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#undef  CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND                                  \
-    "bootp 1000000; "                                       \
-    "setenv bootargs root=ramfs console=ttyS00,9600 "       \
-    "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:"    \
-    "${netmask}:${hostname}:eth0:none; "                    \
-    "bootm"
-
-#define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE           /* allow baudrate changes */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_JFFS2
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP                    /* undef to save memory */
-
-/*
- * choose between COM1 and COM2 as serial console
- */
-#define CONFIG_CONS_INDEX       1
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE              1024        /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE              256         /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS             16          /* max number of command args    */
-#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START       0x00000000  /* memtest works on    */
-#define CONFIG_SYS_MEMTEST_END         0x04000000  /* 0 ... 64 MB in DRAM    */
-
-#define CONFIG_SYS_LOAD_ADDR           0x1000000   /* default load address    */
-
-#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-#define CONFIG_SYS_BOARD_ASM_INIT
-#define CONFIG_MISC_INIT_R
-
-/*
- * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP)
- */
-#undef  CONFIG_SYS_ADDRESS_MAP_A
-
-#define CONFIG_SYS_PCI_MEMORY_BUS      0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS     0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE     0x40000000
-
-#define CONFIG_SYS_PCI_MEM_BUS         0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS        0x80000000
-#define CONFIG_SYS_PCI_MEM_SIZE        0x7d000000
-
-#define CONFIG_SYS_ISA_MEM_BUS         0x00000000
-#define CONFIG_SYS_ISA_MEM_PHYS        0xfd000000
-#define CONFIG_SYS_ISA_MEM_SIZE        0x01000000
-
-#define CONFIG_SYS_PCI_IO_BUS          0x00800000
-#define CONFIG_SYS_PCI_IO_PHYS         0xfe800000
-#define CONFIG_SYS_PCI_IO_SIZE         0x00400000
-
-#define CONFIG_SYS_ISA_IO_BUS          0x00000000
-#define CONFIG_SYS_ISA_IO_PHYS         0xfe000000
-#define CONFIG_SYS_ISA_IO_SIZE         0x00800000
-
-/* driver defines FDC,IDE,... */
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
-#define CONFIG_SYS_ISA_IO              CONFIG_SYS_ISA_IO_PHYS
-#define CONFIG_SYS_60X_PCI_IO_OFFSET   CONFIG_SYS_ISA_IO_PHYS
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE          0x00000000
-
-#define CONFIG_SYS_USR_LED_BASE        0x78000000
-#define CONFIG_SYS_NVRAM_BASE          0xff000000
-#define CONFIG_SYS_UART_BASE           0xff400000
-#define CONFIG_SYS_FLASH_BASE          0xfff00000
-
-#define MPC107_EUMB_ADDR        0xfce00000
-#define MPC107_EUMB_PI          0xfce41090
-#define MPC107_EUMB_GCR         0xfce41020
-#define MPC107_EUMB_IACKR       0xfce600a0
-#define MPC107_I2C_ADDR         0xfce03000
-
-/*
- * Definitions for initial stack pointer and data area
- */
-#define CONFIG_SYS_INIT_RAM_ADDR       0x00fd0000  /* above the memtest region */
-#define CONFIG_SYS_INIT_RAM_SIZE        0x4000
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Flash mapping/organization on the MPC10x.
- */
-#define FLASH_BASE0_PRELIM      0xff800000
-#define FLASH_BASE1_PRELIM      0xffc00000
-
-#define CONFIG_SYS_MAX_FLASH_BANKS     2           /* max number of memory banks    */
-#define CONFIG_SYS_MAX_FLASH_SECT      67          /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT    120000      /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500         /* Timeout for Flash Write (in ms) */
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		"nor0=elppc-0,nor1=elppc-1"
-#define MTDPARTS_DEFAULT	"mtdparts=elppc-0:-(jffs2),elppc-1:-(user)"
-*/
-
-#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN         0x40000     /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN          0x20000     /* Reserve 128 kB for malloc() */
-#undef  CONFIG_SYS_MEMTEST
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_IS_IN_NVRAM     1           /* use NVRAM for environment vars */
-#define CONFIG_SYS_NVRAM_SIZE          0x800       /* NVRAM size (2kB) */
-#define CONFIG_ENV_SIZE            0x400       /* Size of Environment vars (1kB) */
-#define CONFIG_ENV_ADDR            0x0
-#define CONFIG_ENV_MAP_ADRS        0xff000000
-#define CONFIG_SYS_NV_SROM_COPY_ADDR   (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
-#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE            /* only byte accsess alowed */
-#define CONFIG_SYS_SROM_SIZE           0x100       /* shadow of revision info is in nvram */
-
-/*
- * Serial devices
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE    1
-#define CONFIG_SYS_NS16550_CLK         24000000
-#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_UART_BASE + 0)
-#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_UART_BASE + 8)
-
-/*
- * PCI stuff
- */
-#define CONFIG_PCI                                /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_PNP                            /* pci plug-and-play */
-#define CONFIG_PCI_HOST         PCI_HOST_AUTO
-#undef  CONFIG_PCI_SCAN_SHOW
-
-/*
- * Optional Video console (graphic: SMI LynxEM)
- */
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define VIDEO_KBD_INIT_FCT    (simple_strtol (getenv("console"), NULL, 10))
-#define VIDEO_TSTC_FCT		serial_stub_tstc
-#define VIDEO_GETC_FCT		serial_stub_getc
-
-#define CONFIG_VIDEO_SMI_LYNXEM
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_CONSOLE_EXTRA_INFO
-
-/*
- * Initial BATs
- */
-#if 1
-
-#define CONFIG_SYS_IBAT0L 0
-#define CONFIG_SYS_IBAT0U 0
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
-
-#define CONFIG_SYS_IBAT1L 0
-#define CONFIG_SYS_IBAT1U 0
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-#define CONFIG_SYS_IBAT2L 0
-#define CONFIG_SYS_IBAT2U 0
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-#define CONFIG_SYS_IBAT3L 0
-#define CONFIG_SYS_IBAT3U 0
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-#else
-
-/* SDRAM */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_RW)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
-
-/* address range for flashes */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* ISA IO space */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* ISA memory space */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-#endif
-
-/*
- * Speed settings are board specific
- */
-#define CONFIG_SYS_BUS_CLK	100000000
-#define CONFIG_SYS_CPU_CLK	400000000
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ           (8 << 20)           /* Initial Memory map for Linux */
-
-/*
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE        32    /* For all MPC74xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT        5    /* log base 2 of the above value */
-#endif
-
-/*
- * L2CR setup -- make sure this is right for your board!
- * look in include/74xx_7xx.h for the defines used here
- */
-
-#define CONFIG_SYS_L2
-
-#if 1
-#define L2_INIT     0       /* cpu 750 CXe*/
-#else
-#define L2_INIT     (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-		     L2CR_L2OH_5   | L2CR_L2CTL | L2CR_L2WT)
-#endif
-#define L2_ENABLE   (L2_INIT | L2CR_L2E)
-
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
-#define CONFIG_EEPRO100_SROM_WRITE
-
-#endif    /* __CONFIG_H */
diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h
deleted file mode 100644
index ac75d3e..0000000
--- a/include/configs/P3G4.h
+++ /dev/null
@@ -1,407 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifndef __ASSEMBLY__
-#include <galileo/core.h>
-#endif
-
-#include "../board/evb64260/local.h"
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_P3G4		1	/* this is a P3G4  board	*/
-#define CONFIG_SYS_GT_6426x        GT_64260 /* with a 64260 system controller */
-
-#define	CONFIG_SYS_TEXT_BASE	0xfff00000
-
-#define CONFIG_BAUDRATE		115200	/* console baudrate = 115200	*/
-
-#undef	CONFIG_ECC			/* enable ECC support */
-/* #define CONFIG_EVB64260_750CX  1 */      /* Support the EVB-64260-750CX Board */
-
-/* which initialization functions to call for this board */
-#define CONFIG_MISC_INIT_R	1
-#define CONFIG_BOARD_EARLY_INIT_F 1
-
-#define CONFIG_SYS_BOARD_NAME		"P3G4"
-
-#undef CONFIG_SYS_HUSH_PARSER
-
-/*
- * The following defines let you select what serial you want to use
- * for your console driver.
- *
- * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
- * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
- */
-#define	CONFIG_MPSC
-#define CONFIG_MPSC_PORT	0
-
-
-/* define this if you want to enable GT MAC filtering */
-#define CONFIG_GT_USE_MAC_HASH_TABLE
-
-#undef CONFIG_ETHER_PORT_MII	/* use RMII */
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=p3g4\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-		"bootm\0"						\
-	"rootpath=/opt/eldk/ppc_74xx\0"					\
-	"bootfile=/tftpboot/p3g4/uImage\0"				\
-	"kernel_addr=ff000000\0"					\
-	"ramdisk_addr=ff010000\0"					\
-	"load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0"			\
-	"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;"	\
-		"cp.b 100000 fff00000 ${filesize};"			\
-		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
-#define	CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#undef	CONFIG_ALTIVEC                  /* undef to disable             */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_UNIVERSE
-#define CONFIG_CMD_BSP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CONFIG_SYS_LOAD_ADDR		0x00300000	/* default load address	*/
-#define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz		*/
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define	CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_RAM_LOCK
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define	CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xff000000
-#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
-#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define	CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
-
-/* areas to map different things with the GT in physical space */
-#define CONFIG_SYS_DRAM_BANKS		1
-#define CONFIG_SYS_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */
-
-/* What to put in the bats. */
-#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
-
-/* Peripheral Device section */
-#define CONFIG_SYS_GT_REGS		0xf8000000
-#define CONFIG_SYS_DEV_BASE		0xff000000
-
-#define CONFIG_SYS_DEV0_SPACE		CONFIG_SYS_DEV_BASE
-#define CONFIG_SYS_DEV1_SPACE		(CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
-#define CONFIG_SYS_DEV2_SPACE		(CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
-#define CONFIG_SYS_DEV3_SPACE		(CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
-
-#define CONFIG_SYS_DEV0_SIZE		 _8M /* Flash bank */
-#define CONFIG_SYS_DEV1_SIZE		 0   /* unused */
-#define CONFIG_SYS_DEV2_SIZE		 0   /* unused */
-#define CONFIG_SYS_DEV3_SIZE		 0   /* unused */
-
-#define CONFIG_SYS_16BIT_BOOT_PAR	0xc01b5e7c
-#define CONFIG_SYS_DEV0_PAR		CONFIG_SYS_16BIT_BOOT_PAR
-
-#if 0 /* Wrong?? NTL */
-#define CONFIG_SYS_MPP_CONTROL_0	0x53541717	/* InitAct EOT[4] DBurst TCEn[1] */
-						/* DMAAck[1:0] GNT0[1:0] */
-#else
-#define CONFIG_SYS_MPP_CONTROL_0	0x53547777	/* InitAct EOT[4] DBurst TCEn[1] */
-						/* REQ0[1:0] GNT0[1:0] */
-#endif
-#define CONFIG_SYS_MPP_CONTROL_1	0x44009911	/* TCEn[4] TCTcnt[4] GPP[13:12] */
-						/* DMAReq[4] DMAAck[4] WDNMI WDE */
-#if 0 /* Wrong?? NTL */
-#define CONFIG_SYS_MPP_CONTROL_2	0x40091818	/* TCTcnt[0] GPP[22:21] BClkIn */
-						/* DMAAck[1:0] GNT1[1:0] */
-#else
-#define CONFIG_SYS_MPP_CONTROL_2	0x40098888	/* TCTcnt[0] */
-						/* GPP[22] (RS232IntB or PCI1Int) */
-						/* GPP[21] (RS323IntA) */
-						/* BClkIn */
-						/* REQ1[1:0] GNT1[1:0] */
-#endif
-
-#if 0 /* Wrong?? NTL */
-# define CONFIG_SYS_MPP_CONTROL_3	0x00090066	/* GPP[31:29] BClkOut0 */
-						/* GPP[27:26] Int[1:0] */
-#else
-# define CONFIG_SYS_MPP_CONTROL_3	0x22090066      /* MREQ MGNT */
-						/* GPP[29]    (PCI1Int) */
-						/* BClkOut0 */
-						/* GPP[27]    (PCI0Int) */
-						/* GPP[26]    (RtcInt or PCI1Int) */
-						/* CPUInt[25:24] */
-#endif
-
-#define CONFIG_SYS_SERIAL_PORT_MUX	0x00001102	/* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
-
-#if 0 /* Wrong?? - NTL */
-# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x000002c6
-#else
-# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x2c600000	/* 0010 1100 0110 0000 */
-						/* gpp[29] */
-						/* gpp[27:26] */
-						/* gpp[22:21] */
-
-# define CONFIG_SYS_SDRAM_CONFIG	0xd8e18200	/* 0x448 */
-				/* idmas use buffer 1,1
-				   comm use buffer 0
-				   pci use buffer 1,1
-				   cpu use buffer 0
-				   normal load (see also ifdef HVL)
-				   standard SDRAM (see also ifdef REG)
-				   non staggered refresh */
-				/* 31:26  25 23  20 19 18 16 */
-				/* 110110 00 111 0  0  00 1 */
-				/* refresh_count=0x200
-				   phisical interleaving disable
-				   virtual interleaving enable */
-				/* 15 14 13:0 */
-				/* 1  0  0x200 */
-#endif
-
-#if 0
-#define CONFIG_SYS_DUART_IO		CONFIG_SYS_DEV2_SPACE
-#define CONFIG_SYS_DUART_CHAN		1		/* channel to use for console */
-#endif
-#undef CONFIG_SYS_INIT_CHAN1
-#undef CONFIG_SYS_INIT_CHAN2
-#if 0
-#define SRAM_BASE		CONFIG_SYS_DEV0_SPACE
-#define SRAM_SIZE		0x00100000		/* 1 MB of sram */
-#endif
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-
-#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI                      /* include pci support          */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
-#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
-
-/* PCI MEMORY MAP section */
-#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
-#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
-
-#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
-#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
-#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
-
-/* PCI I/O MAP section */
-#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
-#define CONFIG_SYS_PCI0_IO_SIZE	_16M
-#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
-#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000
-
-#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
-#define CONFIG_SYS_PCI1_IO_SIZE	_16M
-#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
-#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000
-
-/*----------------------------------------------------------------------
- * Initial BAT mappings
- */
-
-/* NOTES:
- * 1) GUARDED and WRITE_THRU not allowed in IBATS
- * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
- */
-
-/* SDRAM */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* init ram */
-#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
-
-/* PCI0, PCI1 in one BAT */
-#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* GT regs, bootrom, all the devices, PCI I/O */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* I2C speed and slave address (for compatability) defaults */
-#define CONFIG_SYS_I2C_SPEED	400000
-#define CONFIG_SYS_I2C_SLAVE	0x7F
-
-/* I2C addresses for the two DIMM SPD chips */
-#ifndef CONFIG_EVB64260_750CX
-#define DIMM0_I2C_ADDR	0x56
-#define DIMM1_I2C_ADDR	0x54
-#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
-#define DIMM0_I2C_ADDR  0x54
-#define DIMM1_I2C_ADDR	0x54
-#endif
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CONFIG_SYS_BOOTMAPSZ		(8<<20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
-
-#define CONFIG_SYS_EXTRA_FLASH_DEVICE	BOOT_DEVICE
-#define CONFIG_SYS_EXTRA_FLASH_WIDTH	2	/* 16 bit */
-#define CONFIG_SYS_BOOT_FLASH_WIDTH	2	/* 16 bit */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_CFI		1
-
-#define	CONFIG_ENV_IS_IN_FLASH	1
-#define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR		0xFFFE0000
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * L2CR setup -- make sure this is right for your board!
- * look in include/74xx_7xx.h for the defines used here
- */
-
-#define CONFIG_SYS_L2
-
-#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-			 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-
-#define L2_ENABLE	(L2_INIT | L2CR_L2E)
-
-#define CONFIG_SYS_BOARD_ASM_INIT      1
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h
deleted file mode 100644
index cac6a67..0000000
--- a/include/configs/ZUMA.h
+++ /dev/null
@@ -1,370 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_GT_6426x        GT_64260 /* with a 64260 system controller */
-#define CONFIG_ETHER_PORT_MII	/* use two MII ports */
-#define CONFIG_INTEL_LXT97X	/* Intel LXT97X phy */
-
-#ifndef __ASSEMBLY__
-#include <galileo/core.h>
-#endif
-
-#include "../board/evb64260/local.h"
-
-#define CONFIG_EVB64260		1	/* this is an EVB64260 board	*/
-#define CONFIG_ZUMA_V2		1	/* always define this for ZUMA v2 */
-
-#define	CONFIG_SYS_TEXT_BASE	0xfff00000
-
-/* #define CONFIG_ZUMA_V2_OLD	1 */	/* backwards compat for old V2 board */
-
-#define CONFIG_BAUDRATE		38400	/* console baudrate = 38400	*/
-
-#define CONFIG_ECC			/* enable ECC support */
-
-#define CONFIG_750CX			/* we have a 750CX/CXe (override local.h) */
-
-/* which initialization functions to call for this board */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_SYS_BOARD_ASM_INIT
-
-#define CONFIG_SYS_BOARD_NAME		"Zuma APv2"
-
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * The following defines let you select what serial you want to use
- * for your console driver.
- *
- * what to do:
- * to use the DUART, undef CONFIG_MPSC.	 If you have hacked a serial
- * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
- * to 0 below.
- *
- * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
- * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
- */
-#define CONFIG_MPSC
-
-#define CONFIG_MPSC_PORT	0
-
-
-/* define this if you want to enable GT MAC filtering */
-#define CONFIG_GT_USE_MAC_HASH_TABLE
-
-#if 1
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_BOOTCOMMAND							\
-	"tftpboot && "								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
-	"ip=$ipaddr:$serverip:$gatewayip:"				\
-	"$netmask:$hostname:eth0:none panic=5 && bootm"
-
-#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#undef	CONFIG_ALTIVEC			/* undef to disable		*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_MII		/* enable MII commands */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_DATE
-
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		"nor1=zuma-1,nor2=zuma-2"
-#define MTDPARTS_DEFAULT	"mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
-*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x00300000	/* default load address */
-
-#define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz		*/
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_RAM_LOCK
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xfff00000
-#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
-
-/* areas to map different things with the GT in physical space */
-#define CONFIG_SYS_DRAM_BANKS		4
-#define CONFIG_SYS_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */
-
-/* What to put in the bats. */
-#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
-
-/* Peripheral Device section */
-#define CONFIG_SYS_GT_REGS		0xf8000000	/* later mapped GT_REGS */
-#define CONFIG_SYS_DEV_BASE		0xf0000000
-#define CONFIG_SYS_DEV0_SIZE		_64M /* zuma flash @ 0xf000.0000*/
-#define CONFIG_SYS_DEV1_SIZE		 _8M /* zuma IDE   @ 0xf400.0000 */
-#define CONFIG_SYS_DEV2_SIZE		 _8M /* unused */
-#define CONFIG_SYS_DEV3_SIZE		 _8M /* unused */
-
-#define CONFIG_SYS_DEV0_PAR		0xc498243c
-	/*     c    4     9     8     2	    4     3     c */
-	/* 33 22|2222|22 22|111 1|11 11|1 1  |	   |      */
-	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
-	/* 11|00|0100|10 01|100|0 00|10 0|100 0|011 1|100 */
-	/*  3| 0|.... ..| 1| 4 |  0 |  4 |   8 |   7 | 4  */
-
-#define CONFIG_SYS_DEV1_PAR		0xc01b6ac5
-	/*     c    0     1     b     6	    a     c     5 */
-	/* 33 22|2222|22 22|111 1|11 11|1 1  |	   |      */
-	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
-	/* 11|00|0000|00 01|101|1 01|10 1|010 1|100 0|101 */
-	/*  3| 0|.... ..| 1| 5 |  5 |  5 |   5 |   8 | 5  */
-
-
-#define CONFIG_SYS_8BIT_BOOT_PAR	0xc00b5e7c
-
-#define CONFIG_SYS_MPP_CONTROL_0	0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */
-#define CONFIG_SYS_MPP_CONTROL_1	0x00000000 /* GPP[15:12] : GPP[11:8] */
-#define CONFIG_SYS_MPP_CONTROL_2	0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */
-#define CONFIG_SYS_MPP_CONTROL_3	0x00000000 /* GPP[31:28] (int[3:0]) */
-					   /* GPP[27:24] (27 is int4, rest are GPP) */
-
-#define CONFIG_SYS_SERIAL_PORT_MUX	0x00001101 /* 11=MPSC1/MPSC0 01=ETH,  0=only MII */
-#define CONFIG_SYS_GPP_LEVEL_CONTROL	0xf8000000 /* interrupt inputs: GPP[31:27] */
-
-#define CONFIG_SYS_SDRAM_CONFIG	0xe4e18200	/* 0x448 */
-				/* idmas use buffer 1,1
-				   comm use buffer 1
-				   pci use buffer 0,0 (pci1->0 pci0->0)
-				   cpu use buffer 1 (R*18)
-				   normal load (see also ifdef HVL)
-				   standard SDRAM (see also ifdef REG)
-				   non staggered refresh */
-				/* 31:26  25 23	 20 19 18 16 */
-				/* 111001 00 111 0  0  00 1 */
-
-				/* refresh count=0x200
-				   phy interleave disable (by default,
-				   set later by dram config..)
-				   virt interleave enable */
-				/* 15 14 13:0 */
-				/* 1  0	 0x200 */
-
-#define CONFIG_SYS_DEV0_SPACE		CONFIG_SYS_DEV_BASE
-#define CONFIG_SYS_DEV1_SPACE		(CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
-#define CONFIG_SYS_DEV2_SPACE		(CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
-#define CONFIG_SYS_DEV3_SPACE		(CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- */
-
-#define PCI_HOST_ADAPTER	0	/* configure ar pci adapter	*/
-#define PCI_HOST_FORCE		1	/* configure as pci host	*/
-#define PCI_HOST_AUTO		2	/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-
-/* PCI MEMORY MAP section */
-#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
-#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
-#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
-
-#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
-#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
-
-/* PCI I/O MAP section */
-#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
-#define CONFIG_SYS_PCI0_IO_SIZE	_16M
-#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
-#define CONFIG_SYS_PCI1_IO_SIZE	_16M
-
-#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
-#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000
-#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
-#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000
-
-
-/*----------------------------------------------------------------------
- * Initial BAT mappings
- */
-
-/* NOTES:
- * 1) GUARDED and WRITE_THRU not allowed in IBATS
- * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
- */
-
-/* SDRAM */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* init ram */
-#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
-
-/* PCI0, PCI1 memory space (starting at PCI0 base, mapped in one BAT) */
-#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* GT regs, bootrom, all the devices, PCI I/O */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
-
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* max number of memory banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	130	/* max number of sectors on one chip */
-
-#define CONFIG_SYS_EXTRA_FLASH_DEVICE	DEVICE0 /* extra flash at device 0 */
-#define CONFIG_SYS_EXTRA_FLASH_WIDTH	2	/* 16 bit */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_CFI		1
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE	0x10000 /* see README - env sect real size */
-#define CONFIG_ENV_ADDR		(0xfff80000 - CONFIG_ENV_SECT_SIZE)
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * L2CR setup -- make sure this is right for your board!
- * look in include/74xx_7xx.h for the defines used here
- */
-
-#define CONFIG_SYS_L2
-
-#ifdef CONFIG_750CX
-#define L2_INIT		0
-#else
-#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-#endif
-
-#define L2_ENABLE	(L2_INIT | L2CR_L2E)
-
-/*------------------------------------------------------------------------
- * Real time clock
- */
-#define CONFIG_RTC_DS1302
-
-
-/*------------------------------------------------------------------------
- * Galileo I2C driver
- */
-#define CONFIG_GT_I2C
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h
deleted file mode 100644
index 0308c52..0000000
--- a/include/configs/mpc7448hpc2.h
+++ /dev/null
@@ -1,386 +0,0 @@
-/*
- * Copyright (c) 2005 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2006
- * Alex Bounine , Tundra Semiconductor Corp.
- * Roy Zang	, <tie-fei.zang@freescale.com> Freescale Corp.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board specific configuration options for Freescale
- * MPC7448HPC2 (High-Performance Computing II) (Taiga) board
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Board Configuration Definitions */
-/* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */
-
-#define CONFIG_MPC7448HPC2
-
-#define CONFIG_74xx
-#define CONFIG_HIGH_BATS	/* High BATs supported */
-#define CONFIG_ALTIVEC		/* undef to disable */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFF000000
-
-#define CONFIG_SYS_BOARD_NAME		"MPC7448 HPC II"
-#define CONFIG_IDENT_STRING	" Freescale MPC7448 HPC II"
-
-#define CONFIG_SYS_OCN_CLK		133000000	/* 133 MHz */
-#define CONFIG_SYS_BUS_CLK		133000000
-
-#define CONFIG_SYS_CLK_SPREAD		/* Enable Spread-Spectrum Clock generation */
-
-#undef  CONFIG_ECC		/* disable ECC support */
-
-#ifndef __ASSEMBLY__
-#include <galileo/core.h>
-#endif
-
-/* Board-specific Initialization Functions to be called */
-#define CONFIG_SYS_BOARD_ASM_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_BAUDRATE		115200	/* console baudrate = 115000 */
-
-/*#define CONFIG_SYS_HUSH_PARSER */
-#undef CONFIG_SYS_HUSH_PARSER
-
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
-#define OF_TSI			"tsi108@c0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH		"/tsi108@c0000000/serial@7808"
-
-/*
- * The following defines let you select what serial you want to use
- * for your console driver.
- *
- * what to do:
- * If you have hacked a serial cable onto the second DUART channel,
- * change the CONFIG_SYS_DUART port from 1 to 0 below.
- *
- */
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_OCN_CLK * 8
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_TSI108_CSR_RST_BASE+0x7808)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_TSI108_CSR_RST_BASE+0x7C08)
-
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#undef CONFIG_BOOTARGS
-/* #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
-
-#if (CONFIG_BOOTDELAY >= 0)
-#define CONFIG_BOOTCOMMAND	"tftpboot 0x400000 zImage.initrd.elf;\
- setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
- ip=$(ipaddr):$(serverip)$(bootargs_end);  bootm 0x400000; "
-
-#define CONFIG_BOOTARGS "console=ttyS0,115200"
-#endif
-
-#undef CONFIG_EXTRA_ENV_SETTINGS
-
-#define CONFIG_SERIAL	"No. 1"
-
-/* Networking Configuration */
-
-#define CONFIG_TSI108_ETH
-#define CONFIG_TSI108_ETH_NUM_PORTS	2
-
-
-#define CONFIG_BOOTFILE		"zImage.initrd.elf"
-#define CONFIG_LOADADDR		0x400000
-
-/*-------------------------------------------------------------------------- */
-
-#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate changes */
-
-#undef CONFIG_WATCHDOG		/* watchdog disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DATE
-
-
-/*set date in u-boot*/
-#define CONFIG_RTC_M48T35A
-#define CONFIG_SYS_NVRAM_BASE_ADDR	0xfc000000
-#define CONFIG_SYS_NVRAM_SIZE		0x8000
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_VERSION_VARIABLE		1
-#define CONFIG_TSI108_I2C
-#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* I2C EEPROM page 1 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1	/* Bytes of address */
-
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
-#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-#endif
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR	0x00400000	/* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-/*
- * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
- * To an unused memory region. The stack will remain in cache until RAM
- * is initialized
- */
-#undef  CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0x07d00000	/* unused memory region */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000/* larger space - we have SDRAM initialized */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-
-#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* first 256 MB of SDRAM */
-#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* next 256MB of SDRAM */
-
-#define CONFIG_SYS_SDRAM2_BASE	0x40000000	/* beginning of non-cacheable alias for SDRAM - first 256MB */
-#define CONFIG_SYS_SDRAM3_BASE	0x50000000	/* next Non-Cacheable 256MB of SDRAM */
-
-#define CONFIG_SYS_PCI_PFM_BASE	0x80000000	/* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */
-
-#define CONFIG_SYS_PCI_MEM32_BASE	0xE0000000	/* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */
-
-#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000	/* Base Address for (PCI/X + Flash) region */
-
-#define CONFIG_SYS_FLASH_BASE	0xff000000	/* Base Address of Flash device */
-#define CONFIG_SYS_FLASH_BASE2	0xfe000000	/* Alternate Flash Base Address */
-
-#define CONFIG_VERY_BIG_RAM	/* we will use up to 256M memory for cause we are short of BATS */
-
-#define PCI0_IO_BASE_BOOTM	0xfd000000
-
-#define CONFIG_SYS_RESET_ADDRESS	0x3fffff00
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* u-boot code base */
-#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
-
-/* Peripheral Device section */
-
-/*
- * Resources on the Tsi108
- */
-
-#define CONFIG_SYS_TSI108_CSR_RST_BASE	0xC0000000	/* Tsi108 CSR base after reset */
-#define CONFIG_SYS_TSI108_CSR_BASE	CONFIG_SYS_TSI108_CSR_RST_BASE	/* Runtime Tsi108 CSR base */
-
-#define ENABLE_PCI_CSR_BAR	/* enables access to Tsi108 CSRs from the PCI/X bus */
-
-#undef  DISABLE_PBM
-
-/*
- * PCI stuff
- *
- */
-
-#define CONFIG_PCI		/* include pci support */
-#define CONFIG_TSI108_PCI	/* include tsi108 pci support */
-
-#define PCI_HOST_ADAPTER	0	/* configure as pci adapter */
-#define PCI_HOST_FORCE		1	/* configure as pci host */
-#define PCI_HOST_AUTO		2	/* detected via arbiter enable */
-
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function */
-#define CONFIG_PCI_PNP		/* do pci plug-and-play */
-
-/* PCI MEMORY MAP section */
-
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
-
-/* PCI Memory Space */
-#define CONFIG_SYS_PCI_MEM_BUS		(CONFIG_SYS_PCI_MEM_PHYS)
-#define CONFIG_SYS_PCI_MEM_PHYS	(CONFIG_SYS_PCI_MEM32_BASE)	/* 0xE0000000 */
-#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000	/* 256 MB space for PCI/X Mem + SDRAM OCN */
-
-/* PCI I/O Space */
-#define CONFIG_SYS_PCI_IO_BUS		0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS		0xfa000000	/* Changed from fd000000 */
-
-#define CONFIG_SYS_PCI_IO_SIZE		0x01000000	/* 16MB */
-
-/* PCI Config Space mapping */
-#define CONFIG_SYS_PCI_CFG_BASE	0xfb000000	/* Changed from FE000000 */
-#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000	/* 16MB */
-
-#define CONFIG_SYS_IBAT0U	0xFE0003FF
-#define CONFIG_SYS_IBAT0L	0xFE000002
-
-#define CONFIG_SYS_IBAT1U	0x00007FFF
-#define CONFIG_SYS_IBAT1L	0x00000012
-
-#define CONFIG_SYS_IBAT2U	0x80007FFF
-#define CONFIG_SYS_IBAT2L	0x80000022
-
-#define CONFIG_SYS_IBAT3U	0x00000000
-#define CONFIG_SYS_IBAT3L	0x00000000
-
-#define CONFIG_SYS_IBAT4U	0x00000000
-#define CONFIG_SYS_IBAT4L	0x00000000
-
-#define CONFIG_SYS_IBAT5U	0x00000000
-#define CONFIG_SYS_IBAT5L	0x00000000
-
-#define CONFIG_SYS_IBAT6U	0x00000000
-#define CONFIG_SYS_IBAT6L	0x00000000
-
-#define CONFIG_SYS_IBAT7U	0x00000000
-#define CONFIG_SYS_IBAT7L	0x00000000
-
-#define CONFIG_SYS_DBAT0U	0xE0003FFF
-#define CONFIG_SYS_DBAT0L	0xE000002A
-
-#define CONFIG_SYS_DBAT1U	0x00007FFF
-#define CONFIG_SYS_DBAT1L	0x00000012
-
-#define CONFIG_SYS_DBAT2U	0x00000000
-#define CONFIG_SYS_DBAT2L	0x00000000
-
-#define CONFIG_SYS_DBAT3U	0xC0000003
-#define CONFIG_SYS_DBAT3L	0xC000002A
-
-#define CONFIG_SYS_DBAT4U	0x00000000
-#define CONFIG_SYS_DBAT4L	0x00000000
-
-#define CONFIG_SYS_DBAT5U	0x00000000
-#define CONFIG_SYS_DBAT5L	0x00000000
-
-#define CONFIG_SYS_DBAT6U	0x00000000
-#define CONFIG_SYS_DBAT6L	0x00000000
-
-#define CONFIG_SYS_DBAT7U	0x00000000
-#define CONFIG_SYS_DBAT7L	0x00000000
-
-/* I2C addresses for the two DIMM SPD chips */
-#define DIMM0_I2C_ADDR	0x51
-#define DIMM1_I2C_ADDR	0x52
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(8<<20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Flash can be at one of two addresses */
-#define FLASH_BANK_SIZE		0x01000000	/* 16 MB Total */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, /* CONFIG_SYS_FLASH_BASE2 */ }
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
-
-#define PHYS_FLASH_SIZE		0x01000000
-#define CONFIG_SYS_MAX_FLASH_SECT	(128)
-
-#define CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_ADDR		0xFC000000
-
-#define CONFIG_ENV_OFFSET	0x00000000	/* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE	0x00000400	/* Total Size of Environment Space */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * L2CR setup -- make sure this is right for your board!
- * look in include/mpc74xx.h for the defines used here
- */
-#undef CONFIG_SYS_L2
-
-#define L2_INIT		0
-#define L2_ENABLE	(L2_INIT | L2CR_L2E)
-#define CONFIG_SYS_SERIAL_HANG_IN_EXCEPTION
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h
deleted file mode 100644
index 18f9a6c..0000000
--- a/include/configs/ppmc7xx.h
+++ /dev/null
@@ -1,416 +0,0 @@
-/*
- * ppmc7xx.h
- * ---------
- *
- * Wind River PPMC 7xx/74xx board configuration file.
- *
- * By Richard Danter (richard.danter@windriver.com)
- * Copyright (C) 2005 Wind River Systems
- */
-
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PPMC7XX
-
-
-/*===================================================================
- *
- * User configurable settings - Modify to your preference
- *
- *===================================================================
- */
-
-/*
- * Debug
- *
- * DEBUG		- Define this is you want extra debug info
- * GTREGREAD		- Required to build with debug
- * do_bdinfo		- Required to build with debug
- */
-
-#ifdef	DEBUG
-#define	GTREGREAD(x)	0xFFFFFFFF
-#define	do_bdinfo(a,b,c,d)
-#endif
-
-/*
- * CPU type
- *
- * CONFIG_7xx		- We have a 750 or 755 CPU
- * CONFIG_74xx		- We have a 7400 CPU
- * CONFIG_ALTIVEC	- We have altivec enabled CPU (only 7400)
- * CONFIG_BUS_CLK	- System bus clock in Hz
- */
-
-#define	CONFIG_7xx
-#undef	CONFIG_74xx
-#undef	CONFIG_ALTIVEC
-#define CONFIG_BUS_CLK	66000000
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-#ifndef __ASSEMBLY__
-#include <galileo/core.h>
-#endif
-
-/*
- * Monitor configuration
- *
- * List of command sets to include in shell
- *
- * The following command sets have been tested and known to work:
- *
- * CMD_CACHE		- Cache control commands
- * CMD_MEMORY		- Memory display, change and test commands
- * CMD_FLASH		- Erase and program flash
- * CMD_ENV		- Environment commands
- * CMD_RUN		- Run commands stored in env vars
- * CMD_ELF		- Load ELF files
- * CMD_NET		- Networking/file download commands
- * CMD_PIN		- ICMP Echo Request command
- * CMD_PCI		- PCI Bus scanning command
- */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_PCI
-
-#undef CONFIG_CMD_KGDB
-
-
-/*
- * Serial configuration
- *
- * CONFIG_CONS_INDEX		- Serial console port number (COM1)
- * CONFIG_BAUDRATE		- Serial speed
- */
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		9600
-
-
-/*
- * PCI config
- *
- * CONFIG_PCI			- Enable PCI bus
- * CONFIG_PCI_PNP		- Enable Plug & Play support
- * CONFIG_PCI_SCAN_SHOW		- Enable display of devices at startup
- */
-
-#define	CONFIG_PCI
-#define	CONFIG_PCI_INDIRECT_BRIDGE
-#define	CONFIG_PCI_PNP
-#undef	CONFIG_PCI_SCAN_SHOW
-
-
-/*
- * Network config
- *
- * CONFIG_EEPRO100		- Intel 8255x Ethernet Controller
- * CONFIG_EEPRO100_SROM_WRITE	- Enable writing to network card ROM
- */
-
-#define	CONFIG_EEPRO100
-#define	CONFIG_EEPRO100_SROM_WRITE
-
-
-/*
- * Enable extra init functions
- *
- * CONFIG_MISC_INIT_F		- Call pre-relocation init functions
- * CONFIG_MISC_INIT_R		- Call post relocation init functions
- */
-
-#undef	CONFIG_MISC_INIT_F
-#define CONFIG_MISC_INIT_R
-
-
-/*
- * Boot config
- *
- * CONFIG_BOOTCOMMAND		- Command(s) to execute to auto-boot
- * CONFIG_BOOTDELAY		- How long to wait before auto-boot (in sec)
- */
-
-#define CONFIG_BOOTCOMMAND		\
-	"bootp;" \
-	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
-	"bootm"
-#define CONFIG_BOOTDELAY		5
-
-
-/*===================================================================
- *
- * Board configuration settings - You should not need to modify these
- *
- *===================================================================
- */
-
-
-/*
- * Memory map
- *
- * This board runs in a standard CHRP (Map-B) configuration.
- *
- *	Type	    Start	End	    Size    Width   Chip Sel
- *	----------- ----------- ----------- ------- ------- --------
- *	SDRAM	    0x00000000	0x04000000  64MB    64b	    SDRAMCS0
- *	User LED's  0x78000000				    RCS3
- *	UART	    0x7C000000				    RCS2
- *	Mailbox	    0xFF000000				    RCS1
- *	Flash	    0xFFC00000	0xFFFFFFFF   4MB    64b	    RCS0
- *
- * Flash sectors are laid out as follows.
- *
- *	Sector	Start		End	Size	Comments
- *	------- ----------- ----------- ------- -----------
- *	 0	0xFFC00000  0xFFC3FFFF	256KB
- *	 1	0xFFC40000  0xFFC7FFFF	256KB
- *	 2	0xFFC80000  0xFFCBFFFF	256KB
- *	 3	0xFFCC0000  0xFFCFFFFF	256KB
- *	 4	0xFFD00000  0xFFD3FFFF	256KB
- *	 5	0xFFD40000  0xFFD7FFFF	256KB
- *	 6	0xFFD80000  0xFFDBFFFF	256KB
- *	 7	0xFFDC0000  0xFFDFFFFF	256KB
- *	 8	0xFFE00000  0xFFE3FFFF	256KB
- *	 9	0xFFE40000  0xFFE7FFFF	256KB
- *	10	0xFFE80000  0xFFEBFFFF	256KB
- *	11	0xFFEC0000  0xFFEFFFFF	256KB
- *	12	0xFFF00000  0xFFF3FFFF	256KB	U-Boot code here
- *	13	0xFFF40000  0xFFF7FFFF	256KB
- *	14	0xFFF80000  0xFFFBFFFF	256KB
- *	15	0xFFFC0000  0xFFFDFFFF	128KB
- *	16	0xFFFE0000  0xFFFE7FFF	 32KB	U-Boot env vars here
- *	17	0xFFFE8000  0xFFFEFFFF	 32KB	U-Boot backup copy of env vars here
- *	18	0xFFFF0000  0xFFFFFFFF	 64KB
- */
-
-
-/*
- * SDRAM config - see memory map details above.
- *
- * CONFIG_SYS_SDRAM_BASE		- Start address of SDRAM, this _must_ be zero!
- * CONFIG_SYS_SDRAM_SIZE		- Total size of contiguous SDRAM bank(s)
- */
-
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_SIZE		0x04000000
-
-
-/*
- * Flash config - see memory map details above.
- *
- * CONFIG_SYS_FLASH_BASE		- Start address of flash memory
- * CONFIG_SYS_FLASH_SIZE		- Total size of contiguous flash mem
- * CONFIG_SYS_FLASH_ERASE_TOUT		- Erase timeout in ms
- * CONFIG_SYS_FLASH_WRITE_TOUT		- Write timeout in ms
- * CONFIG_SYS_MAX_FLASH_BANKS		- Number of banks of flash on board
- * CONFIG_SYS_MAX_FLASH_SECT		- Number of sectors in a bank
- */
-
-#define CONFIG_SYS_FLASH_BASE		0xFFC00000
-#define CONFIG_SYS_FLASH_SIZE		0x00400000
-#define CONFIG_SYS_FLASH_ERASE_TOUT	250000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	5000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	128
-
-
-/*
- * Monitor config - see memory map details above
- *
- * CONFIG_SYS_MONITOR_BASE		- Base address of monitor code
- * CONFIG_SYS_MALLOC_LEN		- Size of malloc pool (128KB)
- */
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN		0x20000
-
-
-/*
- * Command shell settings
- *
- * CONFIG_SYS_BARGSIZE			- Boot Argument buffer size
- * CONFIG_SYS_BOOTMAPSZ		- Size of app's mapped RAM at boot (Linux=8MB)
- * CONFIG_SYS_CBSIZE			- Console Buffer (input) size
- * CONFIG_SYS_LOAD_ADDR		- Default load address
- * CONFIG_SYS_LONGHELP			- Provide more detailed help
- * CONFIG_SYS_MAXARGS			- Number of args accepted by monitor commands
- * CONFIG_SYS_MEMTEST_START		- Start address of test to run on RAM
- * CONFIG_SYS_MEMTEST_END		- End address of RAM test
- * CONFIG_SYS_PBSIZE			- Print Buffer (output) size
- * CONFIG_SYS_PROMPT			- Prompt string
- */
-
-#define CONFIG_SYS_BARGSIZE		1024
-#define CONFIG_SYS_BOOTMAPSZ		0x800000
-#define CONFIG_SYS_CBSIZE		1024
-#define CONFIG_SYS_LOAD_ADDR		0x100000
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_MAXARGS		16
-#define CONFIG_SYS_MEMTEST_START	0x00040000
-#define CONFIG_SYS_MEMTEST_END		0x00040100
-#define CONFIG_SYS_PBSIZE		1024
-
-
-/*
- * Environment config - see memory map details above
- *
- * CONFIG_ENV_IS_IN_FLASH		- The env variables are stored in flash
- * CONFIG_ENV_ADDR			- Address of the sector containing env vars
- * CONFIG_ENV_SIZE			- Ammount of RAM for env vars (used to save RAM, 4KB)
- * CONFIG_ENV_SECT_SIZE		- Size of sector containing env vars (32KB)
- */
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		0xFFFE0000
-#define CONFIG_ENV_SIZE		0x1000
-#define CONFIG_ENV_ADDR_REDUND	0xFFFE8000
-#define CONFIG_ENV_SIZE_REDUND	0x1000
-#define CONFIG_ENV_SECT_SIZE	0x8000
-
-
-/*
- * Initial RAM config
- *
- * Since the main system RAM is initialised very early, we place the INIT_RAM
- * in the main system RAM just above the exception vectors. The contents are
- * copied to top of RAM by the init code.
- *
- * CONFIG_SYS_INIT_RAM_ADDR		- Address of Init RAM, above exception vect
- * CONFIG_SYS_INIT_RAM_SIZE		- Size of Init RAM
- * GENERATED_GBL_DATA_SIZE		- Ammount of RAM to reserve for global data
- * CONFIG_SYS_GBL_DATA_OFFSET		- Start of global data, top of stack
- */
-
-#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x4000)
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-
-/*
- * Initial BAT config
- *
- * BAT0	- System SDRAM
- * BAT1 - LED's and Serial Port
- * BAT2 - PCI Memory
- * BAT3 - PCI I/O including Flash Memory
- */
-
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-
-/*
- * Cache config
- *
- * CONFIG_SYS_CACHELINE_SIZE		- Size of a cache line (CPU specific)
- * CONFIG_SYS_L2			- L2 cache enabled if defined
- * L2_INIT			- L2 cache init flags
- * L2_ENABLE			- L2 cache enable flags
- */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#undef	CONFIG_SYS_L2
-#define L2_INIT			0
-#define L2_ENABLE		0
-
-
-/*
- * Clocks config
- *
- * CONFIG_SYS_BUS_CLK			- Bus clock frequency in Hz
- * CONFIG_SYS_HZ			- Decrementer freq in Hz
- */
-
-#define CONFIG_SYS_BUS_CLK		CONFIG_BUS_CLK
-
-
-/*
- * Serial port config
- *
- * CONFIG_SYS_NS16550			- Include the NS16550 driver
- * CONFIG_SYS_NS16550_SERIAL		- Include the serial (wrapper) driver
- * CONFIG_SYS_NS16550_CLK		- Frequency of reference clock
- * CONFIG_SYS_NS16550_REG_SIZE		- 64-bit accesses to 8-bit port
- * CONFIG_SYS_NS16550_COM1		- Base address of 1st serial port
- */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_CLK		3686400
-#define CONFIG_SYS_NS16550_REG_SIZE	-8
-#define CONFIG_SYS_NS16550_COM1	0x7C000000
-
-
-/*
- * PCI Config - Address Map B (CHRP)
- */
-
-#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE	0x40000000
-#define CONFIG_SYS_PCI_MEM_BUS		0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS	0x80000000
-#define CONFIG_SYS_PCI_MEM_SIZE	0x7D000000
-#define CONFIG_SYS_ISA_MEM_BUS		0x00000000
-#define CONFIG_SYS_ISA_MEM_PHYS	0xFD000000
-#define CONFIG_SYS_ISA_MEM_SIZE	0x01000000
-#define CONFIG_SYS_PCI_IO_BUS		0x00800000
-#define CONFIG_SYS_PCI_IO_PHYS		0xFE800000
-#define CONFIG_SYS_PCI_IO_SIZE		0x00400000
-#define CONFIG_SYS_ISA_IO_BUS		0x00000000
-#define CONFIG_SYS_ISA_IO_PHYS		0xFE000000
-#define CONFIG_SYS_ISA_IO_SIZE		0x00800000
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
-#define CONFIG_SYS_ISA_IO		CONFIG_SYS_ISA_IO_PHYS
-#define CONFIG_SYS_60X_PCI_IO_OFFSET	CONFIG_SYS_ISA_IO_PHYS
-
-
-/*
- * Extra init functions
- *
- * CONFIG_SYS_BOARD_ASM_INIT		- Call assembly init code
- */
-
-#define CONFIG_SYS_BOARD_ASM_INIT
-
-#endif /* __CONFIG_H */
diff --git a/include/galileo/core.h b/include/galileo/core.h
deleted file mode 100644
index 95013fa..0000000
--- a/include/galileo/core.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/* Core.h - Basic core logic functions and definitions */
-
-/* Copyright Galileo Technology. */
-
-/*
-DESCRIPTION
-This header file contains simple read/write macros for addressing
-the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
-space). The macros take care of Big/Little endian conversions.
-*/
-
-#ifndef __INCcoreh
-#define __INCcoreh
-
-/* includes */
-#include "gt64260R.h"
-#include <stdbool.h>
-
-extern unsigned int INTERNAL_REG_BASE_ADDR;
-
-/*
- * GT-6426x variants
- */
-#define GT_64260	0  /* includes both 64260A and 64260B */
-#define GT_64261	1
-
-#if (CONFIG_SYS_GT_6426x == GT_64260)
-#ifdef CONFIG_ETHER_PORT_MII
-#define GAL_ETH_DEVS 2
-#else
-#define GAL_ETH_DEVS 3
-#endif
-#elif (CONFIG_SYS_GT_6426x == GT_64261)
-#define GAL_ETH_DEVS 2
-#else
-#define GAL_ETH_DEVS 3	/* default to a 64260 */
-#endif
-
-/****************************************/
-/*          GENERAL Definitions			*/
-/****************************************/
-
-#define NO_BIT          0x00000000
-#define BIT0            0x00000001
-#define BIT1            0x00000002
-#define BIT2            0x00000004
-#define BIT3            0x00000008
-#define BIT4            0x00000010
-#define BIT5            0x00000020
-#define BIT6            0x00000040
-#define BIT7            0x00000080
-#define BIT8            0x00000100
-#define BIT9            0x00000200
-#define BIT10           0x00000400
-#define BIT11           0x00000800
-#define BIT12           0x00001000
-#define BIT13           0x00002000
-#define BIT14           0x00004000
-#define BIT15           0x00008000
-#define BIT16           0x00010000
-#define BIT17           0x00020000
-#define BIT18           0x00040000
-#define BIT19           0x00080000
-#define BIT20           0x00100000
-#define BIT21           0x00200000
-#define BIT22           0x00400000
-#define BIT23           0x00800000
-#define BIT24           0x01000000
-#define BIT25           0x02000000
-#define BIT26           0x04000000
-#define BIT27           0x08000000
-#define BIT28           0x10000000
-#define BIT29           0x20000000
-#define BIT30           0x40000000
-#define BIT31           0x80000000
-
-#define _1K             0x00000400
-#define _2K             0x00000800
-#define _4K             0x00001000
-#define _8K             0x00002000
-#define _16K            0x00004000
-#define _32K            0x00008000
-#define _64K            0x00010000
-#define _128K           0x00020000
-#define _256K           0x00040000
-#define _512K           0x00080000
-
-#define _1M             0x00100000
-#define _2M             0x00200000
-#define _3M             0x00300000
-#define _4M             0x00400000
-#define _5M             0x00500000
-#define _6M             0x00600000
-#define _7M             0x00700000
-#define _8M             0x00800000
-#define _9M             0x00900000
-#define _10M            0x00a00000
-#define _11M            0x00b00000
-#define _12M            0x00c00000
-#define _13M            0x00d00000
-#define _14M            0x00e00000
-#define _15M            0x00f00000
-#define _16M            0x01000000
-
-#define _32M            0x02000000
-#define _64M            0x04000000
-#define _128M           0x08000000
-#define _256M           0x10000000
-#define _512M           0x20000000
-
-#define _1G             0x40000000
-#define _2G             0x80000000
-
-/* Little to Big endian conversion macros */
-
-#ifdef LE /* Little Endian */
-#define SHORT_SWAP(X) (X)
-#define WORD_SWAP(X) (X)
-#define LONG_SWAP(X) ((l64)(X))
-
-#else    /* Big Endian */
-#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8))
-
-#define WORD_SWAP(X) (((X)&0xff)<<24)+      \
-		    (((X)&0xff00)<<8)+      \
-		    (((X)&0xff0000)>>8)+    \
-		    (((X)&0xff000000)>>24)
-
-#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+               \
-			    (((X)&0xff00ULL)<<40)+              \
-			    (((X)&0xff0000ULL)<<24)+            \
-			    (((X)&0xff000000ULL)<<8)+           \
-			    (((X)&0xff00000000ULL)>>8)+         \
-			    (((X)&0xff0000000000ULL)>>24)+      \
-			    (((X)&0xff000000000000ULL)>>40)+    \
-			    (((X)&0xff00000000000000ULL)>>56))
-
-#endif
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-/* Those two definitions were defined to be compatible with MIPS */
-#define NONE_CACHEABLE		0x00000000
-#define CACHEABLE			0x00000000
-
-/* 750 cache line */
-#define CACHE_LINE_SIZE 32
-#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1)
-#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS)
-
-/* Read/Write to/from GT`s internal registers */
-#define GT_REG_READ(offset, pData)                                          \
-*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE |                     \
-		INTERNAL_REG_BASE_ADDR | (offset))) ) ;                                              \
-*pData = WORD_SWAP(*pData)
-
-#define GTREGREAD(offset)                                                   \
-	 (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE |            \
-		   INTERNAL_REG_BASE_ADDR | (offset))) ))
-
-#define GT_REG_WRITE(offset, data)                                          \
-*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) =                   \
-		    WORD_SWAP(data)
-
-/* Write 32/16/8 bit */
-#define WRITE_CHAR(address, data)                                           \
-	*((unsigned char *)(address)) = data
-#define WRITE_SHORT(address, data)                                          \
-	*((unsigned short *)(address)) = data
-#define WRITE_WORD(address, data)                                           \
-	*((unsigned int *)(address)) = data
-
-/* Read 32/16/8 bits - returns data in variable. */
-#define READ_CHAR(address, pData)                                           \
-	*pData = *((volatile unsigned char *)(address))
-
-#define READ_SHORT(address, pData)                                          \
-	*pData = *((volatile unsigned short *)(address))
-
-#define READ_WORD(address, pData)                                           \
-	*pData = *((volatile unsigned int *)(address))
-
-/* Read 32/16/8 bit - returns data direct. */
-#define READCHAR(address)                                                   \
-	*((volatile unsigned char *)((address) | NONE_CACHEABLE))
-
-#define READSHORT(address)                                                  \
-	*((volatile unsigned short *)((address) | NONE_CACHEABLE))
-
-#define READWORD(address)                                                   \
-	*((volatile unsigned int *)((address) | NONE_CACHEABLE))
-
-/* Those two Macros were defined to be compatible with MIPS */
-#define VIRTUAL_TO_PHY(x)    (((unsigned int)x) & 0xffffffff)
-#define PHY_TO_VIRTUAL(x)    (((unsigned int)x) | NONE_CACHEABLE)
-
-/*  SET_REG_BITS(regOffset,bits) -
-   gets register offset and bits: a 32bit value. It set to logic '1' in the
-   internal register the bits which given as an input example:
-   SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
-   '1' in register 0x840 while the other bits stays as is. */
-#define SET_REG_BITS(regOffset,bits) \
-	*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR |  \
-	regOffset) |= (unsigned int)WORD_SWAP(bits)
-
-/*  RESET_REG_BITS(regOffset,bits) -
-   gets register offset and bits: a 32bit value. It set to logic '0' in the
-   internal register the bits which given as an input example:
-   RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
-   '0' in register 0x840 while the other bits stays as is. */
-#define RESET_REG_BITS(regOffset,bits) \
-	*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR   \
-	| regOffset) &= ~( (unsigned int)WORD_SWAP(bits) )
-
-#endif /* __INCcoreh */
diff --git a/include/galileo/gt64260R.h b/include/galileo/gt64260R.h
deleted file mode 100644
index b55da9d..0000000
--- a/include/galileo/gt64260R.h
+++ /dev/null
@@ -1,1194 +0,0 @@
-/* gt64260R.h - GT64260 Internal registers definition file */
-
-/* Copyright - Galileo technology. */
-
-#ifndef __INCgt64260rh
-#define __INCgt64260rh
-
-#ifndef GT64260
-#define GT64260
-#endif
-
-/* CPU MASTER CONTROL REGISTER */
-#define	CPU_CONFIGURATION	0x0
-#define	CPU_MASTER_CONTROL	0x160
-
-/****************************************/
-/* Processor Address Space		*/
-/****************************************/
-
-/* Sdram's BAR'S */
-#define SCS_0_LOW_DECODE_ADDRESS			0x008
-#define SCS_0_HIGH_DECODE_ADDRESS			0x010
-#define SCS_1_LOW_DECODE_ADDRESS			0x208
-#define SCS_1_HIGH_DECODE_ADDRESS			0x210
-#define SCS_2_LOW_DECODE_ADDRESS			0x018
-#define SCS_2_HIGH_DECODE_ADDRESS			0x020
-#define SCS_3_LOW_DECODE_ADDRESS			0x218
-#define SCS_3_HIGH_DECODE_ADDRESS			0x220
-/* Devices BAR'S */
-#define CS_0_LOW_DECODE_ADDRESS				0x028
-#define CS_0_HIGH_DECODE_ADDRESS			0x030
-#define CS_1_LOW_DECODE_ADDRESS				0x228
-#define CS_1_HIGH_DECODE_ADDRESS			0x230
-#define CS_2_LOW_DECODE_ADDRESS				0x248
-#define CS_2_HIGH_DECODE_ADDRESS			0x250
-#define CS_3_LOW_DECODE_ADDRESS				0x038
-#define CS_3_HIGH_DECODE_ADDRESS			0x040
-#define BOOTCS_LOW_DECODE_ADDRESS			0x238
-#define BOOTCS_HIGH_DECODE_ADDRESS			0x240
-
-#define PCI_0I_O_LOW_DECODE_ADDRESS			0x048
-#define PCI_0I_O_HIGH_DECODE_ADDRESS			0x050
-#define PCI_0MEMORY0_LOW_DECODE_ADDRESS			0x058
-#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS		0x060
-#define PCI_0MEMORY1_LOW_DECODE_ADDRESS			0x080
-#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS		0x088
-#define PCI_0MEMORY2_LOW_DECODE_ADDRESS			0x258
-#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS		0x260
-#define PCI_0MEMORY3_LOW_DECODE_ADDRESS			0x280
-#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS		0x288
-
-#define PCI_1I_O_LOW_DECODE_ADDRESS			0x090
-#define PCI_1I_O_HIGH_DECODE_ADDRESS			0x098
-#define PCI_1MEMORY0_LOW_DECODE_ADDRESS			0x0a0
-#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS		0x0a8
-#define PCI_1MEMORY1_LOW_DECODE_ADDRESS			0x0b0
-#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS		0x0b8
-#define PCI_1MEMORY2_LOW_DECODE_ADDRESS			0x2a0
-#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS		0x2a8
-#define PCI_1MEMORY3_LOW_DECODE_ADDRESS			0x2b0
-#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS		0x2b8
-
-
-#define INTERNAL_SPACE_DECODE				0x068
-
-#define CPU_0_LOW_DECODE_ADDRESS			0x290
-#define CPU_0_HIGH_DECODE_ADDRESS			0x298
-#define CPU_1_LOW_DECODE_ADDRESS			0x2c0
-#define CPU_1_HIGH_DECODE_ADDRESS			0x2c8
-
-#define PCI_0I_O_ADDRESS_REMAP				0x0f0
-#define PCI_0MEMORY0_ADDRESS_REMAP			0x0f8
-#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP			0x320
-#define PCI_0MEMORY1_ADDRESS_REMAP			0x100
-#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP			0x328
-#define PCI_0MEMORY2_ADDRESS_REMAP			0x2f8
-#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP			0x330
-#define PCI_0MEMORY3_ADDRESS_REMAP			0x300
-#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP			0x338
-
-#define PCI_1I_O_ADDRESS_REMAP				0x108
-#define PCI_1MEMORY0_ADDRESS_REMAP			0x110
-#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP			0x340
-#define PCI_1MEMORY1_ADDRESS_REMAP			0x118
-#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP			0x348
-#define PCI_1MEMORY2_ADDRESS_REMAP			0x310
-#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP			0x350
-#define PCI_1MEMORY3_ADDRESS_REMAP			0x318
-#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP			0x358
-
-
-/****************************************/
-/* CPU Sync Barrier			*/
-/****************************************/
-
-#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER		0x0c0
-#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER		0x0c8
-
-
-/****************************************/
-/* CPU Access Protect			*/
-/****************************************/
-
-#define CPU_LOW_PROTECT_ADDRESS_0			0x180
-#define CPU_HIGH_PROTECT_ADDRESS_0			0x188
-#define CPU_LOW_PROTECT_ADDRESS_1			0x190
-#define CPU_HIGH_PROTECT_ADDRESS_1			0x198
-#define CPU_LOW_PROTECT_ADDRESS_2			0x1a0
-#define CPU_HIGH_PROTECT_ADDRESS_2			0x1a8
-#define CPU_LOW_PROTECT_ADDRESS_3			0x1b0
-#define CPU_HIGH_PROTECT_ADDRESS_3			0x1b8
-#define CPU_LOW_PROTECT_ADDRESS_4			0x1c0
-#define CPU_HIGH_PROTECT_ADDRESS_4			0x1c8
-#define CPU_LOW_PROTECT_ADDRESS_5			0x1d0
-#define CPU_HIGH_PROTECT_ADDRESS_5			0x1d8
-#define CPU_LOW_PROTECT_ADDRESS_6			0x1e0
-#define CPU_HIGH_PROTECT_ADDRESS_6			0x1e8
-#define CPU_LOW_PROTECT_ADDRESS_7			0x1f0
-#define CPU_HIGH_PROTECT_ADDRESS_7			0x1f8
-
-
-/****************************************/
-/*	    Snoop Control		*/
-/****************************************/
-
-#define SNOOP_BASE_ADDRESS_0				0x380
-#define SNOOP_TOP_ADDRESS_0				0x388
-#define SNOOP_BASE_ADDRESS_1				0x390
-#define SNOOP_TOP_ADDRESS_1				0x398
-#define SNOOP_BASE_ADDRESS_2				0x3a0
-#define SNOOP_TOP_ADDRESS_2				0x3a8
-#define SNOOP_BASE_ADDRESS_3				0x3b0
-#define SNOOP_TOP_ADDRESS_3				0x3b8
-
-/****************************************/
-/*	    CPU Error Report		*/
-/****************************************/
-
-#define CPU_ERROR_ADDRESS_LOW				0x070
-#define CPU_ERROR_ADDRESS_HIGH				0x078
-#define CPU_ERROR_DATA_LOW				0x128
-#define CPU_ERROR_DATA_HIGH				0x130
-#define CPU_ERROR_PARITY				0x138
-#define CPU_ERROR_CAUSE					0x140
-#define CPU_ERROR_MASK					0x148
-
-/****************************************/
-/*	    Pslave Debug		*/
-/****************************************/
-
-#define X_0_ADDRESS					0x360
-#define X_0_COMMAND_ID					0x368
-#define X_1_ADDRESS					0x370
-#define X_1_COMMAND_ID					0x378
-#define WRITE_DATA_LOW					0x3c0
-#define WRITE_DATA_HIGH					0x3c8
-#define WRITE_BYTE_ENABLE				0x3e0
-#define READ_DATA_LOW					0x3d0
-#define READ_DATA_HIGH					0x3d8
-#define READ_ID						0x3e8
-
-
-/****************************************/
-/* SDRAM and Device Address Space	*/
-/****************************************/
-
-
-/****************************************/
-/* SDRAM Configuration			*/
-/****************************************/
-
-
-#define SDRAM_CONFIGURATION				0x448
-#define SDRAM_OPERATION_MODE				0x474
-#define SDRAM_ADDRESS_DECODE				0x47c
-#define SDRAM_UMA_CONTROL				0x4a4
-#define SDRAM_CROSS_BAR_CONTROL_LOW			0x4a8
-#define SDRAM_CROSS_BAR_CONTROL_HIGH			0x4ac
-#define SDRAM_CROSS_BAR_TIMEOUT				0x4b0
-#define SDRAM_TIMING					0x4b4
-
-
-/****************************************/
-/* SDRAM Parameters			*/
-/****************************************/
-
-#define SDRAM_BANK0PARAMETERS				0x44C
-#define SDRAM_BANK1PARAMETERS				0x450
-#define SDRAM_BANK2PARAMETERS				0x454
-#define SDRAM_BANK3PARAMETERS				0x458
-
-
-/****************************************/
-/* SDRAM Error Report			*/
-/****************************************/
-
-#define SDRAM_ERROR_DATA_LOW				0x484
-#define SDRAM_ERROR_DATA_HIGH				0x480
-#define SDRAM_AND_DEVICE_ERROR_ADDRESS			0x490
-#define SDRAM_RECEIVED_ECC				0x488
-#define SDRAM_CALCULATED_ECC				0x48c
-#define SDRAM_ECC_CONTROL				0x494
-#define SDRAM_ECC_ERROR_COUNTER				0x498
-
-
-/****************************************/
-/* SDunit Debug (for internal use)	*/
-/****************************************/
-
-#define X0_ADDRESS					0x500
-#define X0_COMMAND_AND_ID				0x504
-#define X0_WRITE_DATA_LOW				0x508
-#define X0_WRITE_DATA_HIGH				0x50c
-#define X0_WRITE_BYTE_ENABLE				0x518
-#define X0_READ_DATA_LOW				0x510
-#define X0_READ_DATA_HIGH				0x514
-#define X0_READ_ID					0x51c
-#define X1_ADDRESS					0x520
-#define X1_COMMAND_AND_ID				0x524
-#define X1_WRITE_DATA_LOW				0x528
-#define X1_WRITE_DATA_HIGH				0x52c
-#define X1_WRITE_BYTE_ENABLE				0x538
-#define X1_READ_DATA_LOW				0x530
-#define X1_READ_DATA_HIGH				0x534
-#define X1_READ_ID					0x53c
-#define X0_SNOOP_ADDRESS				0x540
-#define X0_SNOOP_COMMAND				0x544
-#define X1_SNOOP_ADDRESS				0x548
-#define X1_SNOOP_COMMAND				0x54c
-
-
-/****************************************/
-/* Device Parameters			*/
-/****************************************/
-
-#define DEVICE_BANK0PARAMETERS				0x45c
-#define DEVICE_BANK1PARAMETERS				0x460
-#define DEVICE_BANK2PARAMETERS				0x464
-#define DEVICE_BANK3PARAMETERS				0x468
-#define DEVICE_BOOT_BANK_PARAMETERS			0x46c
-#define DEVICE_CONTROL					0x4c0
-#define DEVICE_CROSS_BAR_CONTROL_LOW			0x4c8
-#define DEVICE_CROSS_BAR_CONTROL_HIGH			0x4cc
-#define DEVICE_CROSS_BAR_TIMEOUT			0x4c4
-
-
-/****************************************/
-/* Device Interrupt			*/
-/****************************************/
-
-#define DEVICE_INTERRUPT_CAUSE				0x4d0
-#define DEVICE_INTERRUPT_MASK				0x4d4
-#define DEVICE_ERROR_ADDRESS				0x4d8
-
-/****************************************/
-/* DMA Record				*/
-/****************************************/
-
-#define CHANNEL0_DMA_BYTE_COUNT				0x800
-#define CHANNEL1_DMA_BYTE_COUNT				0x804
-#define CHANNEL2_DMA_BYTE_COUNT				0x808
-#define CHANNEL3_DMA_BYTE_COUNT				0x80C
-#define CHANNEL4_DMA_BYTE_COUNT				0x900
-#define CHANNEL5_DMA_BYTE_COUNT				0x904
-#define CHANNEL6_DMA_BYTE_COUNT				0x908
-#define CHANNEL7_DMA_BYTE_COUNT				0x90C
-#define CHANNEL0_DMA_SOURCE_ADDRESS			0x810
-#define CHANNEL1_DMA_SOURCE_ADDRESS			0x814
-#define CHANNEL2_DMA_SOURCE_ADDRESS			0x818
-#define CHANNEL3_DMA_SOURCE_ADDRESS			0x81C
-#define CHANNEL4_DMA_SOURCE_ADDRESS			0x910
-#define CHANNEL5_DMA_SOURCE_ADDRESS			0x914
-#define CHANNEL6_DMA_SOURCE_ADDRESS			0x918
-#define CHANNEL7_DMA_SOURCE_ADDRESS			0x91C
-#define CHANNEL0_DMA_DESTINATION_ADDRESS		0x820
-#define CHANNEL1_DMA_DESTINATION_ADDRESS		0x824
-#define CHANNEL2_DMA_DESTINATION_ADDRESS		0x828
-#define CHANNEL3_DMA_DESTINATION_ADDRESS		0x82C
-#define CHANNEL4_DMA_DESTINATION_ADDRESS		0x920
-#define CHANNEL5_DMA_DESTINATION_ADDRESS		0x924
-#define CHANNEL6_DMA_DESTINATION_ADDRESS		0x928
-#define CHANNEL7_DMA_DESTINATION_ADDRESS		0x92C
-#define CHANNEL0NEXT_RECORD_POINTER			0x830
-#define CHANNEL1NEXT_RECORD_POINTER			0x834
-#define CHANNEL2NEXT_RECORD_POINTER			0x838
-#define CHANNEL3NEXT_RECORD_POINTER			0x83C
-#define CHANNEL4NEXT_RECORD_POINTER			0x930
-#define CHANNEL5NEXT_RECORD_POINTER			0x934
-#define CHANNEL6NEXT_RECORD_POINTER			0x938
-#define CHANNEL7NEXT_RECORD_POINTER			0x93C
-#define CHANNEL0CURRENT_DESCRIPTOR_POINTER		0x870
-#define CHANNEL1CURRENT_DESCRIPTOR_POINTER		0x874
-#define CHANNEL2CURRENT_DESCRIPTOR_POINTER		0x878
-#define CHANNEL3CURRENT_DESCRIPTOR_POINTER		0x87C
-#define CHANNEL4CURRENT_DESCRIPTOR_POINTER		0x970
-#define CHANNEL5CURRENT_DESCRIPTOR_POINTER		0x974
-#define CHANNEL6CURRENT_DESCRIPTOR_POINTER		0x978
-#define CHANNEL7CURRENT_DESCRIPTOR_POINTER		0x97C
-#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS		0x890
-#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS		0x894
-#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS		0x898
-#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS		0x89c
-#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS		0x990
-#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS		0x994
-#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS		0x998
-#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS		0x99c
-#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x8a0
-#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x8a4
-#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x8a8
-#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x8ac
-#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x9a0
-#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x9a4
-#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x9a8
-#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x9ac
-#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x8b0
-#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x8b4
-#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x8b8
-#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x8bc
-#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x9b0
-#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x9b4
-#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x9b8
-#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x9bc
-
-/****************************************/
-/* DMA Channel Control			*/
-/****************************************/
-
-#define CHANNEL0CONTROL					0x840
-#define CHANNEL0CONTROL_HIGH				0x880
-#define CHANNEL1CONTROL					0x844
-#define CHANNEL1CONTROL_HIGH				0x884
-#define CHANNEL2CONTROL					0x848
-#define CHANNEL2CONTROL_HIGH				0x888
-#define CHANNEL3CONTROL					0x84C
-#define CHANNEL3CONTROL_HIGH				0x88C
-
-#define CHANNEL4CONTROL					0x940
-#define CHANNEL4CONTROL_HIGH				0x980
-#define CHANNEL5CONTROL					0x944
-#define CHANNEL5CONTROL_HIGH				0x984
-#define CHANNEL6CONTROL					0x948
-#define CHANNEL6CONTROL_HIGH				0x988
-#define CHANNEL7CONTROL					0x94C
-#define CHANNEL7CONTROL_HIGH				0x98C
-
-
-/****************************************/
-/* DMA Arbiter				*/
-/****************************************/
-
-#define ARBITER_CONTROL_0_3										0x860
-#define ARBITER_CONTROL_4_7										0x960
-
-
-/****************************************/
-/* DMA Interrupt			*/
-/****************************************/
-
-#define CHANELS0_3_INTERRUPT_CAUSE			0x8c0
-#define CHANELS0_3_INTERRUPT_MASK			0x8c4
-#define CHANELS0_3_ERROR_ADDRESS			0x8c8
-#define CHANELS0_3_ERROR_SELECT				0x8cc
-#define CHANELS4_7_INTERRUPT_CAUSE			0x9c0
-#define CHANELS4_7_INTERRUPT_MASK			0x9c4
-#define CHANELS4_7_ERROR_ADDRESS			0x9c8
-#define CHANELS4_7_ERROR_SELECT				0x9cc
-
-
-/****************************************/
-/* DMA Debug (for internal use)		*/
-/****************************************/
-
-#define DMA_X0_ADDRESS					0x8e0
-#define DMA_X0_COMMAND_AND_ID				0x8e4
-#define DMA_X0_WRITE_DATA_LOW				0x8e8
-#define DMA_X0_WRITE_DATA_HIGH				0x8ec
-#define DMA_X0_WRITE_BYTE_ENABLE			0x8f8
-#define DMA_X0_READ_DATA_LOW				0x8f0
-#define DMA_X0_READ_DATA_HIGH				0x8f4
-#define DMA_X0_READ_ID					0x8fc
-#define DMA_X1_ADDRESS					0x9e0
-#define DMA_X1_COMMAND_AND_ID				0x9e4
-#define DMA_X1_WRITE_DATA_LOW				0x9e8
-#define DMA_X1_WRITE_DATA_HIGH				0x9ec
-#define DMA_X1_WRITE_BYTE_ENABLE			0x9f8
-#define DMA_X1_READ_DATA_LOW				0x9f0
-#define DMA_X1_READ_DATA_HIGH				0x9f4
-#define DMA_X1_READ_ID					0x9fc
-
-/****************************************/
-/* Timer_Counter			*/
-/****************************************/
-
-#define TIMER_COUNTER0					0x850
-#define TIMER_COUNTER1					0x854
-#define TIMER_COUNTER2					0x858
-#define TIMER_COUNTER3					0x85C
-#define TIMER_COUNTER_0_3_CONTROL			0x864
-#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE		0x868
-#define TIMER_COUNTER_0_3_INTERRUPT_MASK		0x86c
-#define TIMER_COUNTER4					0x950
-#define TIMER_COUNTER5					0x954
-#define TIMER_COUNTER6					0x958
-#define TIMER_COUNTER7					0x95C
-#define TIMER_COUNTER_4_7_CONTROL			0x964
-#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE		0x968
-#define TIMER_COUNTER_4_7_INTERRUPT_MASK		0x96c
-
-/****************************************/
-/* PCI Slave Address Decoding		*/
-/****************************************/
-
-#define PCI_0SCS_0_BANK_SIZE				0xc08
-#define PCI_1SCS_0_BANK_SIZE				0xc88
-#define PCI_0SCS_1_BANK_SIZE				0xd08
-#define PCI_1SCS_1_BANK_SIZE				0xd88
-#define PCI_0SCS_2_BANK_SIZE				0xc0c
-#define PCI_1SCS_2_BANK_SIZE				0xc8c
-#define PCI_0SCS_3_BANK_SIZE				0xd0c
-#define PCI_1SCS_3_BANK_SIZE				0xd8c
-#define PCI_0CS_0_BANK_SIZE				0xc10
-#define PCI_1CS_0_BANK_SIZE				0xc90
-#define PCI_0CS_1_BANK_SIZE				0xd10
-#define PCI_1CS_1_BANK_SIZE				0xd90
-#define PCI_0CS_2_BANK_SIZE				0xd18
-#define PCI_1CS_2_BANK_SIZE				0xd98
-#define PCI_0CS_3_BANK_SIZE				0xc14
-#define PCI_1CS_3_BANK_SIZE				0xc94
-#define PCI_0CS_BOOT_BANK_SIZE				0xd14
-#define PCI_1CS_BOOT_BANK_SIZE				0xd94
-#define PCI_0P2P_MEM0_BAR_SIZE				0xd1c
-#define PCI_1P2P_MEM0_BAR_SIZE				0xd9c
-#define PCI_0P2P_MEM1_BAR_SIZE				0xd20
-#define PCI_1P2P_MEM1_BAR_SIZE				0xda0
-#define PCI_0P2P_I_O_BAR_SIZE				0xd24
-#define PCI_1P2P_I_O_BAR_SIZE				0xda4
-#define PCI_0CPU_BAR_SIZE				0xd28
-#define PCI_1CPU_BAR_SIZE				0xda8
-#define PCI_0DAC_SCS_0_BANK_SIZE			0xe00
-#define PCI_1DAC_SCS_0_BANK_SIZE			0xe80
-#define PCI_0DAC_SCS_1_BANK_SIZE			0xe04
-#define PCI_1DAC_SCS_1_BANK_SIZE			0xe84
-#define PCI_0DAC_SCS_2_BANK_SIZE			0xe08
-#define PCI_1DAC_SCS_2_BANK_SIZE			0xe88
-#define PCI_0DAC_SCS_3_BANK_SIZE			0xe0c
-#define PCI_1DAC_SCS_3_BANK_SIZE			0xe8c
-#define PCI_0DAC_CS_0_BANK_SIZE				0xe10
-#define PCI_1DAC_CS_0_BANK_SIZE				0xe90
-#define PCI_0DAC_CS_1_BANK_SIZE				0xe14
-#define PCI_1DAC_CS_1_BANK_SIZE				0xe94
-#define PCI_0DAC_CS_2_BANK_SIZE				0xe18
-#define PCI_1DAC_CS_2_BANK_SIZE				0xe98
-#define PCI_0DAC_CS_3_BANK_SIZE				0xe1c
-#define PCI_1DAC_CS_3_BANK_SIZE				0xe9c
-#define PCI_0DAC_BOOTCS_BANK_SIZE			0xe20
-#define PCI_1DAC_BOOTCS_BANK_SIZE			0xea0
-#define PCI_0DAC_P2P_MEM0_BAR_SIZE			0xe24
-#define PCI_1DAC_P2P_MEM0_BAR_SIZE			0xea4
-#define PCI_0DAC_P2P_MEM1_BAR_SIZE			0xe28
-#define PCI_1DAC_P2P_MEM1_BAR_SIZE			0xea8
-#define PCI_0DAC_CPU_BAR_SIZE				0xe2c
-#define PCI_1DAC_CPU_BAR_SIZE				0xeac
-#define PCI_0EXPANSION_ROM_BAR_SIZE			0xd2c
-#define PCI_1EXPANSION_ROM_BAR_SIZE			0xdac
-#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE		0xc3c
-#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE		0xcbc
-#define PCI_0SCS_0_BASE_ADDRESS_REMAP			0xc48
-#define PCI_1SCS_0_BASE_ADDRESS_REMAP			0xcc8
-#define PCI_0SCS_1_BASE_ADDRESS_REMAP			0xd48
-#define PCI_1SCS_1_BASE_ADDRESS_REMAP			0xdc8
-#define PCI_0SCS_2_BASE_ADDRESS_REMAP			0xc4c
-#define PCI_1SCS_2_BASE_ADDRESS_REMAP			0xccc
-#define PCI_0SCS_3_BASE_ADDRESS_REMAP			0xd4c
-#define PCI_1SCS_3_BASE_ADDRESS_REMAP			0xdcc
-#define PCI_0CS_0_BASE_ADDRESS_REMAP			0xc50
-#define PCI_1CS_0_BASE_ADDRESS_REMAP			0xcd0
-#define PCI_0CS_1_BASE_ADDRESS_REMAP			0xd50
-#define PCI_1CS_1_BASE_ADDRESS_REMAP			0xdd0
-#define PCI_0CS_2_BASE_ADDRESS_REMAP			0xd58
-#define PCI_1CS_2_BASE_ADDRESS_REMAP			0xdd8
-#define PCI_0CS_3_BASE_ADDRESS_REMAP			0xc54
-#define PCI_1CS_3_BASE_ADDRESS_REMAP			0xcd4
-#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP		0xd54
-#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP		0xdd4
-#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW		0xd5c
-#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW		0xddc
-#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH		0xd60
-#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH		0xde0
-#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW		0xd64
-#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW		0xde4
-#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH		0xd68
-#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH		0xde8
-#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP			0xd6c
-#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP			0xdec
-#define PCI_0CPU_BASE_ADDRESS_REMAP			0xd70
-#define PCI_1CPU_BASE_ADDRESS_REMAP			0xdf0
-#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP		0xf00
-#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP		0xff0
-#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP		0xf04
-#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP		0xf84
-#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP		0xf08
-#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP		0xf88
-#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP		0xf0c
-#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP		0xf8c
-#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP		0xf10
-#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP		0xf90
-#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP		0xf14
-#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP		0xf94
-#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP		0xf18
-#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP		0xf98
-#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP		0xf1c
-#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP		0xf9c
-#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP		0xf20
-#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP		0xfa0
-#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW	0xf24
-#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW	0xfa4
-#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH	0xf28
-#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH	0xfa8
-#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW	0xf2c
-#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW	0xfac
-#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH	0xf30
-#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH	0xfb0
-#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP			0xf34
-#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP			0xfb4
-#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP		0xf38
-#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP		0xfb8
-#define PCI_0ADDRESS_DECODE_CONTROL			0xd3c
-#define PCI_1ADDRESS_DECODE_CONTROL			0xdbc
-
-/****************************************/
-/* PCI Control				*/
-/****************************************/
-
-#define PCI_0COMMAND					0xc00
-#define PCI_1COMMAND					0xc80
-#define PCI_0MODE					0xd00
-#define PCI_1MODE					0xd80
-#define PCI_0TIMEOUT_RETRY				0xc04
-#define PCI_1TIMEOUT_RETRY				0xc84
-#define PCI_0READ_BUFFER_DISCARD_TIMER			0xd04
-#define PCI_1READ_BUFFER_DISCARD_TIMER			0xd84
-#define MSI_0TRIGGER_TIMER				0xc38
-#define MSI_1TRIGGER_TIMER				0xcb8
-#define PCI_0ARBITER_CONTROL				0x1d00
-#define PCI_1ARBITER_CONTROL				0x1d80
-/* changing untill here */
-#define PCI_0CROSS_BAR_CONTROL_LOW			0x1d08
-#define PCI_0CROSS_BAR_CONTROL_HIGH			0x1d0c
-#define PCI_0CROSS_BAR_TIMEOUT				0x1d04
-#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW	0x1d18
-#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH	0x1d1c
-#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER		0x1d10
-#define PCI_0P2P_CONFIGURATION				0x1d14
-#define PCI_0ACCESS_CONTROL_BASE_0_LOW			0x1e00
-#define PCI_0ACCESS_CONTROL_BASE_0_HIGH			0x1e04
-#define PCI_0ACCESS_CONTROL_TOP_0			0x1e08
-#define PCI_0ACCESS_CONTROL_BASE_1_LOW			0x1e10
-#define PCI_0ACCESS_CONTROL_BASE_1_HIGH			0x1e14
-#define PCI_0ACCESS_CONTROL_TOP_1			0x1e18
-#define PCI_0ACCESS_CONTROL_BASE_2_LOW			0x1e20
-#define PCI_0ACCESS_CONTROL_BASE_2_HIGH			0x1e24
-#define PCI_0ACCESS_CONTROL_TOP_2			0x1e28
-#define PCI_0ACCESS_CONTROL_BASE_3_LOW			0x1e30
-#define PCI_0ACCESS_CONTROL_BASE_3_HIGH			0x1e34
-#define PCI_0ACCESS_CONTROL_TOP_3			0x1e38
-#define PCI_0ACCESS_CONTROL_BASE_4_LOW			0x1e40
-#define PCI_0ACCESS_CONTROL_BASE_4_HIGH			0x1e44
-#define PCI_0ACCESS_CONTROL_TOP_4			0x1e48
-#define PCI_0ACCESS_CONTROL_BASE_5_LOW			0x1e50
-#define PCI_0ACCESS_CONTROL_BASE_5_HIGH			0x1e54
-#define PCI_0ACCESS_CONTROL_TOP_5			0x1e58
-#define PCI_0ACCESS_CONTROL_BASE_6_LOW			0x1e60
-#define PCI_0ACCESS_CONTROL_BASE_6_HIGH			0x1e64
-#define PCI_0ACCESS_CONTROL_TOP_6			0x1e68
-#define PCI_0ACCESS_CONTROL_BASE_7_LOW			0x1e70
-#define PCI_0ACCESS_CONTROL_BASE_7_HIGH			0x1e74
-#define PCI_0ACCESS_CONTROL_TOP_7			0x1e78
-#define PCI_1CROSS_BAR_CONTROL_LOW			0x1d88
-#define PCI_1CROSS_BAR_CONTROL_HIGH			0x1d8c
-#define PCI_1CROSS_BAR_TIMEOUT				0x1d84
-#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW	0x1d98
-#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH	0x1d9c
-#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER		0x1d90
-#define PCI_1P2P_CONFIGURATION				0x1d94
-#define PCI_1ACCESS_CONTROL_BASE_0_LOW			0x1e80
-#define PCI_1ACCESS_CONTROL_BASE_0_HIGH			0x1e84
-#define PCI_1ACCESS_CONTROL_TOP_0			0x1e88
-#define PCI_1ACCESS_CONTROL_BASE_1_LOW			0x1e90
-#define PCI_1ACCESS_CONTROL_BASE_1_HIGH			0x1e94
-#define PCI_1ACCESS_CONTROL_TOP_1			0x1e98
-#define PCI_1ACCESS_CONTROL_BASE_2_LOW			0x1ea0
-#define PCI_1ACCESS_CONTROL_BASE_2_HIGH			0x1ea4
-#define PCI_1ACCESS_CONTROL_TOP_2			0x1ea8
-#define PCI_1ACCESS_CONTROL_BASE_3_LOW			0x1eb0
-#define PCI_1ACCESS_CONTROL_BASE_3_HIGH			0x1eb4
-#define PCI_1ACCESS_CONTROL_TOP_3			0x1eb8
-#define PCI_1ACCESS_CONTROL_BASE_4_LOW			0x1ec0
-#define PCI_1ACCESS_CONTROL_BASE_4_HIGH			0x1ec4
-#define PCI_1ACCESS_CONTROL_TOP_4			0x1ec8
-#define PCI_1ACCESS_CONTROL_BASE_5_LOW			0x1ed0
-#define PCI_1ACCESS_CONTROL_BASE_5_HIGH			0x1ed4
-#define PCI_1ACCESS_CONTROL_TOP_5			0x1ed8
-#define PCI_1ACCESS_CONTROL_BASE_6_LOW			0x1ee0
-#define PCI_1ACCESS_CONTROL_BASE_6_HIGH			0x1ee4
-#define PCI_1ACCESS_CONTROL_TOP_6			0x1ee8
-#define PCI_1ACCESS_CONTROL_BASE_7_LOW			0x1ef0
-#define PCI_1ACCESS_CONTROL_BASE_7_HIGH			0x1ef4
-#define PCI_1ACCESS_CONTROL_TOP_7			0x1ef8
-
-/****************************************/
-/* PCI Snoop Control			*/
-/****************************************/
-
-#define PCI_0SNOOP_CONTROL_BASE_0_LOW			0x1f00
-#define PCI_0SNOOP_CONTROL_BASE_0_HIGH			0x1f04
-#define PCI_0SNOOP_CONTROL_TOP_0			0x1f08
-#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW			0x1f10
-#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH		0x1f14
-#define PCI_0SNOOP_CONTROL_TOP_1			0x1f18
-#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW			0x1f20
-#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH		0x1f24
-#define PCI_0SNOOP_CONTROL_TOP_2			0x1f28
-#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW			0x1f30
-#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH		0x1f34
-#define PCI_0SNOOP_CONTROL_TOP_3			0x1f38
-#define PCI_1SNOOP_CONTROL_BASE_0_LOW			0x1f80
-#define PCI_1SNOOP_CONTROL_BASE_0_HIGH			0x1f84
-#define PCI_1SNOOP_CONTROL_TOP_0			0x1f88
-#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW			0x1f90
-#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH		0x1f94
-#define PCI_1SNOOP_CONTROL_TOP_1			0x1f98
-#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW			0x1fa0
-#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH		0x1fa4
-#define PCI_1SNOOP_CONTROL_TOP_2			0x1fa8
-#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW			0x1fb0
-#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH		0x1fb4
-#define PCI_1SNOOP_CONTROL_TOP_3			0x1fb8
-
-/****************************************/
-/* PCI Configuration Address		*/
-/****************************************/
-
-#define PCI_0CONFIGURATION_ADDRESS			0xcf8
-#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER	0xcfc
-#define PCI_1CONFIGURATION_ADDRESS			0xc78
-#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER	0xc7c
-#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER	0xc34
-#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER	0xcb4
-
-/****************************************/
-/* PCI Error Report			*/
-/****************************************/
-
-#define PCI_0SERR_MASK										 0xc28
-#define PCI_0ERROR_ADDRESS_LOW				0x1d40
-#define PCI_0ERROR_ADDRESS_HIGH				0x1d44
-#define PCI_0ERROR_DATA_LOW				0x1d48
-#define PCI_0ERROR_DATA_HIGH				0x1d4c
-#define PCI_0ERROR_COMMAND				0x1d50
-#define PCI_0ERROR_CAUSE				0x1d58
-#define PCI_0ERROR_MASK					0x1d5c
-#define PCI_1SERR_MASK										 0xca8
-#define PCI_1ERROR_ADDRESS_LOW				0x1dc0
-#define PCI_1ERROR_ADDRESS_HIGH				0x1dc4
-#define PCI_1ERROR_DATA_LOW				0x1dc8
-#define PCI_1ERROR_DATA_HIGH				0x1dcc
-#define PCI_1ERROR_COMMAND				0x1dd0
-#define PCI_1ERROR_CAUSE				0x1dd8
-#define PCI_1ERROR_MASK					0x1ddc
-
-
-/****************************************/
-/* Lslave Debug  (for internal use)	*/
-/****************************************/
-
-#define L_SLAVE_X0_ADDRESS				0x1d20
-#define L_SLAVE_X0_COMMAND_AND_ID			0x1d24
-#define L_SLAVE_X1_ADDRESS				0x1d28
-#define L_SLAVE_X1_COMMAND_AND_ID			0x1d2c
-#define L_SLAVE_WRITE_DATA_LOW				0x1d30
-#define L_SLAVE_WRITE_DATA_HIGH				0x1d34
-#define L_SLAVE_WRITE_BYTE_ENABLE			0x1d60
-#define L_SLAVE_READ_DATA_LOW				0x1d38
-#define L_SLAVE_READ_DATA_HIGH				0x1d3c
-#define L_SLAVE_READ_ID					0x1d64
-
-/****************************************/
-/* PCI Configuration Function 0		*/
-/****************************************/
-
-#define PCI_DEVICE_AND_VENDOR_ID			0x000
-#define PCI_STATUS_AND_COMMAND				0x004
-#define PCI_CLASS_CODE_AND_REVISION_ID			0x008
-#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	0x00C
-#define PCI_SCS_0_BASE_ADDRESS				0x010
-#define PCI_SCS_1_BASE_ADDRESS				0x014
-#define PCI_SCS_2_BASE_ADDRESS				0x018
-#define PCI_SCS_3_BASE_ADDRESS				0x01C
-#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS  0x020
-#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS	0x024
-#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	0x02C
-#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER		0x030
-#define PCI_CAPABILTY_LIST_POINTER			0x034
-#define PCI_INTERRUPT_PIN_AND_LINE			0x03C
-#define PCI_POWER_MANAGEMENT_CAPABILITY			0x040
-#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		0x044
-#define PCI_VPD_ADDRESS					0x048
-#define PCI_VPD_DATA					0x04c
-#define PCI_MSI_MESSAGE_CONTROL				0x050
-#define PCI_MSI_MESSAGE_ADDRESS				0x054
-#define PCI_MSI_MESSAGE_UPPER_ADDRESS			0x058
-#define PCI_MSI_MESSAGE_DATA				0x05c
-#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY		0x058
-
-/****************************************/
-/* PCI Configuration Function 1		*/
-/****************************************/
-
-#define PCI_CS_0_BASE_ADDRESS				0x110
-#define PCI_CS_1_BASE_ADDRESS				0x114
-#define PCI_CS_2_BASE_ADDRESS				0x118
-#define PCI_CS_3_BASE_ADDRESS				0x11c
-#define PCI_BOOTCS_BASE_ADDRESS				0x120
-
-/****************************************/
-/* PCI Configuration Function 2		*/
-/****************************************/
-
-#define PCI_P2P_MEM0_BASE_ADDRESS			0x210
-#define PCI_P2P_MEM1_BASE_ADDRESS			0x214
-#define PCI_P2P_I_O_BASE_ADDRESS			0x218
-#define PCI_CPU_BASE_ADDRESS				0x21c
-
-/****************************************/
-/* PCI Configuration Function 4		*/
-/****************************************/
-
-#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW			0x410
-#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH			0x414
-#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW			0x418
-#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH			0x41c
-#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW		0x420
-#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH		0x424
-
-
-/****************************************/
-/* PCI Configuration Function 5		*/
-/****************************************/
-
-#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW			0x510
-#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH			0x514
-#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW			0x518
-#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH			0x51c
-#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW		0x520
-#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH		0x524
-
-
-/****************************************/
-/* PCI Configuration Function 6		*/
-/****************************************/
-
-#define PCI_DAC_CS_0_BASE_ADDRESS_LOW			0x610
-#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH			0x614
-#define PCI_DAC_CS_1_BASE_ADDRESS_LOW			0x618
-#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH			0x61c
-#define PCI_DAC_CS_2_BASE_ADDRESS_LOW			0x620
-#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH			0x624
-
-/****************************************/
-/* PCI Configuration Function 7		*/
-/****************************************/
-
-#define PCI_DAC_CS_3_BASE_ADDRESS_LOW			0x710
-#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH			0x714
-#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW			0x718
-#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH		0x71c
-#define PCI_DAC_CPU_BASE_ADDRESS_LOW			0x720
-#define PCI_DAC_CPU_BASE_ADDRESS_HIGH			0x724
-
-/****************************************/
-/* Interrupts				*/
-/****************************************/
-
-#define LOW_INTERRUPT_CAUSE_REGISTER			0xc18
-#define HIGH_INTERRUPT_CAUSE_REGISTER			0xc68
-#define CPU_INTERRUPT_MASK_REGISTER_LOW			0xc1c
-#define CPU_INTERRUPT_MASK_REGISTER_HIGH		0xc6c
-#define CPU_SELECT_CAUSE_REGISTER			0xc70
-#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW		0xc24
-#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH		0xc64
-#define PCI_0SELECT_CAUSE				0xc74
-#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW		0xca4
-#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH		0xce4
-#define PCI_1SELECT_CAUSE				0xcf4
-#define CPU_INT_0_MASK					0xe60
-#define CPU_INT_1_MASK					0xe64
-#define CPU_INT_2_MASK					0xe68
-#define CPU_INT_3_MASK					0xe6c
-
-/****************************************/
-/* I20 Support registers		*/
-/****************************************/
-
-#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x010
-#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x014
-#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x018
-#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x01C
-#define INBOUND_DOORBELL_REGISTER_PCI_SIDE		0x020
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x024
-#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x028
-#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE		0x02C
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x030
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x034
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x040
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x044
-#define QUEUE_CONTROL_REGISTER_PCI_SIDE			0x050
-#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE		0x054
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x060
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x064
-#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x068
-#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x06C
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x070
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x074
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x078
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x07C
-
-#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1C10
-#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1C14
-#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1C18
-#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1C1C
-#define INBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1C20
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1C24
-#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1C28
-#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1C2C
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1C30
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1C34
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	0x1C40
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	0x1C44
-#define QUEUE_CONTROL_REGISTER_CPU_SIDE			0x1C50
-#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE		0x1C54
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	0x1C60
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	0x1C64
-#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	0x1C68
-#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	0x1C6C
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	0x1C70
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	0x1C74
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	0x1C78
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	0x1C7C
-
-/****************************************/
-/* Communication Unit Registers		*/
-/****************************************/
-
-#define ETHERNET_0_ADDRESS_CONTROL_LOW			0xf200
-#define ETHERNET_0_ADDRESS_CONTROL_HIGH			0xf204
-#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	0xf208
-#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	0xf20c
-#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf210
-#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214
-#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS		0xf218
-#define ETHERNET_1_ADDRESS_CONTROL_LOW			0xf220
-#define ETHERNET_1_ADDRESS_CONTROL_HIGH			0xf224
-#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	0xf228
-#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	0xf22c
-#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf230
-#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234
-#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS		0xf238
-#define ETHERNET_2_ADDRESS_CONTROL_LOW			0xf240
-#define ETHERNET_2_ADDRESS_CONTROL_HIGH			0xf244
-#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	0xf248
-#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	0xf24c
-#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf250
-#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254
-#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS		0xf258
-#define MPSC_0_ADDRESS_CONTROL_LOW			0xf280
-#define MPSC_0_ADDRESS_CONTROL_HIGH			0xf284
-#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS		0xf288
-#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS		0xf28c
-#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf290
-#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf294
-#define MPSC_1_ADDRESS_CONTROL_LOW			0xf2c0
-#define MPSC_1_ADDRESS_CONTROL_HIGH			0xf2c4
-#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS		0xf2c8
-#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS		0xf2cc
-#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf2d0
-#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf2d4
-#define SERIAL_INIT_PCI_HIGH_ADDRESS			0xf320
-#define SERIAL_INIT_LAST_DATA				0xf324
-#define SERIAL_INIT_STATUS_AND_CONTROL			0xf328
-#define COMM_UNIT_ARBITER_CONTROL			0xf300
-#define COMM_UNIT_CROSS_BAR_TIMEOUT			0xf304
-#define COMM_UNIT_INTERRUPT_CAUSE			0xf310
-#define COMM_UNIT_INTERRUPT_MASK			0xf314
-#define COMM_UNIT_ERROR_ADDRESS				0xf314
-
-/****************************************/
-/* Cunit Debug	(for internal use)     */
-/****************************************/
-
-#define CUNIT_ADDRESS					0xf340
-#define CUNIT_COMMAND_AND_ID				0xf344
-#define CUNIT_WRITE_DATA_LOW				0xf348
-#define CUNIT_WRITE_DATA_HIGH				0xf34c
-#define CUNIT_WRITE_BYTE_ENABLE				0xf358
-#define CUNIT_READ_DATA_LOW				0xf350
-#define CUNIT_READ_DATA_HIGH				0xf354
-#define CUNIT_READ_ID					0xf35c
-
-/****************************************/
-/* Fast Ethernet Unit Registers		*/
-/****************************************/
-
-/* Ethernet */
-
-#define ETHERNET_PHY_ADDRESS_REGISTER			0x2000
-#define ETHERNET_SMI_REGISTER				0x2010
-
-/* Ethernet 0 */
-
-#define ETHERNET0_PORT_CONFIGURATION_REGISTER		0x2400
-#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER	0x2408
-#define ETHERNET0_PORT_COMMAND_REGISTER			0x2410
-#define ETHERNET0_PORT_STATUS_REGISTER			0x2418
-#define ETHERNET0_SERIAL_PARAMETRS_REGISTER		0x2420
-#define ETHERNET0_HASH_TABLE_POINTER_REGISTER		0x2428
-#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW	0x2430
-#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH	0x2438
-#define ETHERNET0_SDMA_CONFIGURATION_REGISTER		0x2440
-#define ETHERNET0_SDMA_COMMAND_REGISTER			0x2448
-#define ETHERNET0_INTERRUPT_CAUSE_REGISTER		0x2450
-#define ETHERNET0_INTERRUPT_MASK_REGISTER		0x2458
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0		0x2480
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1		0x2484
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2		0x2488
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3		0x248c
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0	0x24a0
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1	0x24a4
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2	0x24a8
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3	0x24ac
-#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0	0x24e0
-#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1	0x24e4
-#define ETHERNET0_MIB_COUNTER_BASE			0x2500
-
-/* Ethernet 1 */
-
-#define ETHERNET1_PORT_CONFIGURATION_REGISTER		0x2800
-#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER	0x2808
-#define ETHERNET1_PORT_COMMAND_REGISTER			0x2810
-#define ETHERNET1_PORT_STATUS_REGISTER			0x2818
-#define ETHERNET1_SERIAL_PARAMETRS_REGISTER		0x2820
-#define ETHERNET1_HASH_TABLE_POINTER_REGISTER		0x2828
-#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW	0x2830
-#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH	0x2838
-#define ETHERNET1_SDMA_CONFIGURATION_REGISTER		0x2840
-#define ETHERNET1_SDMA_COMMAND_REGISTER			0x2848
-#define ETHERNET1_INTERRUPT_CAUSE_REGISTER		0x2850
-#define ETHERNET1_INTERRUPT_MASK_REGISTER		0x2858
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0		0x2880
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1		0x2884
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2		0x2888
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3		0x288c
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0	0x28a0
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1	0x28a4
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2	0x28a8
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3	0x28ac
-#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0	0x28e0
-#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1	0x28e4
-#define ETHERNET1_MIB_COUNTER_BASE			0x2900
-
-/* Ethernet 2 */
-
-#define ETHERNET2_PORT_CONFIGURATION_REGISTER		0x2c00
-#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER	0x2c08
-#define ETHERNET2_PORT_COMMAND_REGISTER			0x2c10
-#define ETHERNET2_PORT_STATUS_REGISTER			0x2c18
-#define ETHERNET2_SERIAL_PARAMETRS_REGISTER		0x2c20
-#define ETHERNET2_HASH_TABLE_POINTER_REGISTER		0x2c28
-#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW	0x2c30
-#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH	0x2c38
-#define ETHERNET2_SDMA_CONFIGURATION_REGISTER		0x2c40
-#define ETHERNET2_SDMA_COMMAND_REGISTER			0x2c48
-#define ETHERNET2_INTERRUPT_CAUSE_REGISTER		0x2c50
-#define ETHERNET2_INTERRUPT_MASK_REGISTER		0x2c58
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0		0x2c80
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1		0x2c84
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2		0x2c88
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3		0x2c8c
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0	0x2ca0
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1	0x2ca4
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2	0x2ca8
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3	0x2cac
-#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0	0x2ce0
-#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1	0x2ce4
-#define ETHERNET2_MIB_COUNTER_BASE			0x2d00
-
-/****************************************/
-/* SDMA Registers			*/
-/****************************************/
-
-#define SDMA_GROUP_CONFIGURATION_REGISTER		0xb1f0
-#define CHANNEL0_CONFIGURATION_REGISTER			0x4000
-#define CHANNEL0_COMMAND_REGISTER			0x4008
-#define CHANNEL0_RX_CMD_STATUS				0x4800
-#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES		0x4804
-#define CHANNEL0_RX_BUFFER_POINTER			0x4808
-#define CHANNEL0_RX_NEXT_POINTER			0x480c
-#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER		0x4810
-#define CHANNEL0_TX_CMD_STATUS				0x4C00
-#define CHANNEL0_TX_PACKET_SIZE				0x4C04
-#define CHANNEL0_TX_BUFFER_POINTER			0x4C08
-#define CHANNEL0_TX_NEXT_POINTER			0x4C0c
-#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER		0x4c10
-#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER		0x4c14
-#define CHANNEL1_CONFIGURATION_REGISTER			0x5000
-#define CHANNEL1_COMMAND_REGISTER			0x5008
-#define CHANNEL1_RX_CMD_STATUS				0x5800
-#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES		0x5804
-#define CHANNEL1_RX_BUFFER_POINTER			0x5808
-#define CHANNEL1_RX_NEXT_POINTER			0x580c
-#define CHANNEL1_TX_CMD_STATUS				0x5C00
-#define CHANNEL1_TX_PACKET_SIZE				0x5C04
-#define CHANNEL1_TX_BUFFER_POINTER			0x5C08
-#define CHANNEL1_TX_NEXT_POINTER			0x5C0c
-#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER		0x5810
-#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER		0x5c10
-#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER		0x5c14
-#define CHANNEL2_CONFIGURATION_REGISTER			0x6000
-#define CHANNEL2_COMMAND_REGISTER			0x6008
-#define CHANNEL2_RX_CMD_STATUS				0x6800
-#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES		0x6804
-#define CHANNEL2_RX_BUFFER_POINTER			0x6808
-#define CHANNEL2_RX_NEXT_POINTER			0x680c
-#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER		0x6810
-#define CHANNEL2_TX_CMD_STATUS				0x6C00
-#define CHANNEL2_TX_PACKET_SIZE				0x6C04
-#define CHANNEL2_TX_BUFFER_POINTER			0x6C08
-#define CHANNEL2_TX_NEXT_POINTER			0x6C0c
-#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER		0x6810
-#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER		0x6c10
-#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER		0x6c14
-
-/* SDMA Interrupt */
-
-#define SDMA_CAUSE					0xb820
-#define SDMA_MASK					0xb8a0
-
-
-/****************************************/
-/* Baude Rate Generators Registers	*/
-/****************************************/
-
-/* BRG 0 */
-
-#define BRG0_CONFIGURATION_REGISTER			0xb200
-#define BRG0_BAUDE_TUNING_REGISTER			0xb204
-
-/* BRG 1 */
-
-#define BRG1_CONFIGURATION_REGISTER			0xb208
-#define BRG1_BAUDE_TUNING_REGISTER			0xb20c
-
-/* BRG 2 */
-
-#define BRG2_CONFIGURATION_REGISTER			0xb210
-#define BRG2_BAUDE_TUNING_REGISTER			0xb214
-
-/* BRG Interrupts */
-
-#define BRG_CAUSE_REGISTER				0xb834
-#define BRG_MASK_REGISTER				0xb8b4
-
-/* MISC */
-
-#define MAIN_ROUTING_REGISTER				0xb400
-#define RECEIVE_CLOCK_ROUTING_REGISTER			0xb404
-#define TRANSMIT_CLOCK_ROUTING_REGISTER			0xb408
-#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER	0xb40c
-#define WATCHDOG_CONFIGURATION_REGISTER			0xb410
-#define WATCHDOG_VALUE_REGISTER				0xb414
-
-
-/****************************************/
-/* Flex TDM Registers			*/
-/****************************************/
-
-/* FTDM Port */
-
-#define FLEXTDM_TRANSMIT_READ_POINTER			0xa800
-#define FLEXTDM_RECEIVE_READ_POINTER			0xa804
-#define FLEXTDM_CONFIGURATION_REGISTER			0xa808
-#define FLEXTDM_AUX_CHANNELA_TX_REGISTER		0xa80c
-#define FLEXTDM_AUX_CHANNELA_RX_REGISTER		0xa810
-#define FLEXTDM_AUX_CHANNELB_TX_REGISTER		0xa814
-#define FLEXTDM_AUX_CHANNELB_RX_REGISTER		0xa818
-
-/* FTDM Interrupts */
-
-#define FTDM_CAUSE_REGISTER				0xb830
-#define FTDM_MASK_REGISTER				0xb8b0
-
-
-/****************************************/
-/* GPP Interface Registers		*/
-/****************************************/
-
-#define GPP_IO_CONTROL					0xf100
-#define GPP_LEVEL_CONTROL				0xf110
-#define GPP_VALUE					0xf104
-#define GPP_INTERRUPT_CAUSE				0xf108
-#define GPP_INTERRUPT_MASK				0xf10c
-
-#define MPP_CONTROL0					0xf000
-#define MPP_CONTROL1					0xf004
-#define MPP_CONTROL2					0xf008
-#define MPP_CONTROL3					0xf00c
-#define DEBUG_PORT_MULTIPLEX				0xf014
-#define SERIAL_PORT_MULTIPLEX				0xf010
-
-/****************************************/
-/* I2C Registers			*/
-/****************************************/
-
-#define I2C_SLAVE_ADDRESS				0xc000
-#define I2C_EXTENDED_SLAVE_ADDRESS			0xc040
-#define I2C_DATA					0xc004
-#define I2C_CONTROL					0xc008
-#define I2C_STATUS_BAUDE_RATE				0xc00C
-#define I2C_SOFT_RESET					0xc01c
-
-/****************************************/
-/* MPSC Registers			*/
-/****************************************/
-
-/* MPSC0  */
-
-#define MPSC0_MAIN_CONFIGURATION_LOW			0x8000
-#define MPSC0_MAIN_CONFIGURATION_HIGH			0x8004
-#define MPSC0_PROTOCOL_CONFIGURATION			0x8008
-#define CHANNEL0_REGISTER1				0x800c
-#define CHANNEL0_REGISTER2				0x8010
-#define CHANNEL0_REGISTER3				0x8014
-#define CHANNEL0_REGISTER4				0x8018
-#define CHANNEL0_REGISTER5				0x801c
-#define CHANNEL0_REGISTER6				0x8020
-#define CHANNEL0_REGISTER7				0x8024
-#define CHANNEL0_REGISTER8				0x8028
-#define CHANNEL0_REGISTER9				0x802c
-#define CHANNEL0_REGISTER10				0x8030
-#define CHANNEL0_REGISTER11				0x8034
-
-/* MPSC1  */
-
-#define MPSC1_MAIN_CONFIGURATION_LOW			0x8840
-#define MPSC1_MAIN_CONFIGURATION_HIGH			0x8844
-#define MPSC1_PROTOCOL_CONFIGURATION			0x8848
-#define CHANNEL1_REGISTER1				0x884c
-#define CHANNEL1_REGISTER2				0x8850
-#define CHANNEL1_REGISTER3				0x8854
-#define CHANNEL1_REGISTER4				0x8858
-#define CHANNEL1_REGISTER5				0x885c
-#define CHANNEL1_REGISTER6				0x8860
-#define CHANNEL1_REGISTER7				0x8864
-#define CHANNEL1_REGISTER8				0x8868
-#define CHANNEL1_REGISTER9				0x886c
-#define CHANNEL1_REGISTER10				0x8870
-#define CHANNEL1_REGISTER11				0x8874
-
-/* MPSC2  */
-
-#define MPSC2_MAIN_CONFIGURATION_LOW			0x9040
-#define MPSC2_MAIN_CONFIGURATION_HIGH			0x9044
-#define MPSC2_PROTOCOL_CONFIGURATION			0x9048
-#define CHANNEL2_REGISTER1				0x904c
-#define CHANNEL2_REGISTER2				0x9050
-#define CHANNEL2_REGISTER3				0x9054
-#define CHANNEL2_REGISTER4				0x9058
-#define CHANNEL2_REGISTER5				0x905c
-#define CHANNEL2_REGISTER6				0x9060
-#define CHANNEL2_REGISTER7				0x9064
-#define CHANNEL2_REGISTER8				0x9068
-#define CHANNEL2_REGISTER9				0x906c
-#define CHANNEL2_REGISTER10				0x9070
-#define CHANNEL2_REGISTER11				0x9074
-
-/* MPSCs Interrupts  */
-
-#define MPSC0_CAUSE					0xb824
-#define MPSC0_MASK					0xb8a4
-#define MPSC1_CAUSE					0xb828
-#define MPSC1_MASK					0xb8a8
-#define MPSC2_CAUSE					0xb82c
-#define MPSC2_MASK					0xb8ac
-
-#endif /* __INCgt64260rh */
diff --git a/include/galileo/memory.h b/include/galileo/memory.h
deleted file mode 100644
index 0c46c24..0000000
--- a/include/galileo/memory.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Memory.h - Memory mappings and remapping functions declarations */
-
-/* Copyright - Galileo technology. */
-
-#ifndef __INCmemoryh
-#define __INCmemoryh
-
-/* includes */
-
-#include "core.h"
-
-/* defines */
-
-#define DONT_MODIFY     0xffffffff
-#define PARITY_SUPPORT  0x40000000
-
-#define _8BIT           0x00000000
-#define _16BIT          0x00100000
-#define _32BIT          0x00200000
-#define _64BIT          0x00300000
-
-/* typedefs */
-
- typedef struct deviceParam
-{                               /* boundary values  */
-    unsigned int    turnOff;    /* 0x0 - 0xf        */
-    unsigned int    acc2First;  /* 0x0 - 0x1f       */
-    unsigned int    acc2Next;   /* 0x0 - 0x1f       */
-    unsigned int    ale2Wr;     /* 0x0 - 0xf        */
-    unsigned int    wrLow;      /* 0x0 - 0xf        */
-    unsigned int    wrHigh;     /* 0x0 - 0xf        */
-    unsigned int    deviceWidth;    /* in Bytes  */
-} DEVICE_PARAM;
-
-typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK;
-typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE;
-
-typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2,       \
-				   MEM_REGION3,MEM_REGION4,MEM_REGION5,       \
-				   MEM_REGION6,MEM_REGION7}                   \
-				   MEMORY_PROTECT_REGION;
-typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN}           \
-			    MEMORY_ACCESS;
-typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN}              \
-			   MEMORY_ACCESS_WRITE;
-typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN}       \
-				  MEMORY_CACHE_PROTECT;
-typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB}        \
-			       MEMORY_SNOOP_TYPE;
-typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1,         \
-				 MEM_SNOOP_REGION2,MEM_SNOOP_REGION3}         \
-				 MEMORY_SNOOP_REGION;
-
-/* functions */
-unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank);
-unsigned int memoryGetDeviceBaseAddress(DEVICE device);
-unsigned int memoryGetBankSize(MEMORY_BANK bank);
-unsigned int memoryGetDeviceSize(DEVICE device);
-unsigned int memoryGetDeviceWidth(DEVICE device);
-
-/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/
-bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength);
-bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength);
-
-/* Change the Internal Register Base Address to a new given Address. */
-bool memoryMapInternalRegistersSpace(unsigned int internalRegBase);
-/* returns internal Register Space Base Address. */
-unsigned int memoryGetInternalRegistersSpace(void);
-/* Configurate the protection feature to a given space. */
-bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
-			    MEMORY_ACCESS memoryAccess,
-			    MEMORY_ACCESS_WRITE memoryWrite,
-			    MEMORY_CACHE_PROTECT cacheProtection,
-			    unsigned int baseAddress,
-			    unsigned int regionLength);
-/* Configurate the snoop feature to a given space. */
-bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
-			      MEMORY_SNOOP_TYPE snoopType,
-			      unsigned int baseAddress,
-			      unsigned int regionLength);
-
-bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue);
-bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
-bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
-#endif  /* __INCmemoryh */
diff --git a/include/galileo/pci.h b/include/galileo/pci.h
deleted file mode 100644
index 6ed8b95..0000000
--- a/include/galileo/pci.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* PCI.h - PCI functions header file */
-
-/* Copyright - Galileo technology. */
-
-#ifndef __INCpcih
-#define __INCpcih
-
-/* includes */
-
-#include "core.h"
-#include "memory.h"
-
-/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
-#define PCI_MAX_DEVICES 22
-
-
-/* Macros */
-#define     SELF                    32
-
-/* Defines for the access regions. */
-#define     PREFETCH_ENABLE                 BIT12
-#define     PREFETCH_DISABLE                NO_BIT
-#define     DELAYED_READ_ENABLE             BIT13
-/* #define     CACHING_ENABLE                  BIT14 */
-/* aggressive prefetch: PCI slave prefetch two burst in advance*/
-#define     AGGRESSIVE_PREFETCH              BIT16
-/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
-#define     READ_LINE_AGGRESSIVE_PREFETCH   BIT17
-/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
-#define     READ_MULTI_AGGRESSIVE_PREFETCH  BIT18
-#define     MAX_BURST_4                     NO_BIT
-#define     MAX_BURST_8                     BIT20  /* Bits[21:20] = 01 */
-#define     MAX_BURST_16                    BIT21  /* Bits[21:20] = 10 */
-#define     PCI_BYTE_SWAP                   NO_BIT /* Bits[25:24] = 00 */
-#define     PCI_NO_SWAP                     BIT24  /* Bits[25:24] = 01 */
-#define     PCI_BYTE_AND_WORD_SWAP          BIT25  /* Bits[25:24] = 10 */
-#define     PCI_WORD_SWAP                  (BIT24 | BIT25) /* Bits[25:24] = 11 */
-#define     PCI_ACCESS_PROTECT              BIT28
-#define     PCI_WRITE_PROTECT               BIT29
-
-/* typedefs */
-
-typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
-				REGION6,REGION7} PCI_ACCESS_REGIONS;
-
-typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
-typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;
-
-typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB}
-			    PCI_SNOOP_TYPE;
-typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
-			      PCI_SNOOP_REGION2,PCI_SNOOP_REGION3}
-			      PCI_SNOOP_REGION;
-
-typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST;
-typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1,
-			 PCI_REGION2,PCI_REGION3,
-			 PCI_IO}
-			 PCI_REGION;
-
-/* read/write configuration registers on local PCI bus. */
-void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,
-		       unsigned int pciDevNum, unsigned int data);
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
-			       unsigned int pciDevNum);
-
-/* read/write configuration registers on another PCI bus. */
-void pciOverBridgeWriteConfigReg(PCI_HOST host,
-				 unsigned int regOffset,
-				 unsigned int pciDevNum,
-				 unsigned int busNum,unsigned int data);
-unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
-					unsigned int regOffset,
-					unsigned int pciDevNum,
-					unsigned int busNum);
-
-/*      Master`s memory space   */
-bool pciMapSpace(PCI_HOST host, PCI_REGION region,
-		unsigned int remapBase,
-		unsigned int deviceBase,
-		unsigned int deviceLength);
-unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region);
-unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region);
-
-/*      Slave`s memory space   */
-void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank,
-		      unsigned int pci0Dram0Base, unsigned int pci0Dram0Size);
-
-/* PCI region options */
-
-bool  pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,
-	unsigned int features, unsigned int baseAddress,
-	unsigned int regionLength);
-
-void  pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region);
-
-/* PCI arbiter */
-
-bool pciArbiterEnable(PCI_HOST host);
-bool pciArbiterDisable(PCI_HOST host);
-bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
-			PCI_AGENT_PARK externalAgent0,
-			PCI_AGENT_PARK externalAgent1,
-			PCI_AGENT_PARK externalAgent2,
-			PCI_AGENT_PARK externalAgent3,
-			PCI_AGENT_PARK externalAgent4,
-			PCI_AGENT_PARK externalAgent5);
-bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,
-			    PCI_SNOOP_TYPE snoopType,
-			    unsigned int baseAddress,
-			    unsigned int regionLength);
-
-#endif /* __INCpcih */