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authorHeiko Schocher <hs@denx.de>2014-11-18 11:53:53 +0100
committerAndreas Bießmann <andreas.devel@googlemail.com>2015-01-19 12:49:29 +0100
commita5f8ccaeab6db682ad5ba47255287604d781d552 (patch)
tree8fca4cfcfa36218b20c50c5b90df60736f91a4f6 /include
parenta1655bb2e1e2bf8f30f40b46d1bb7a45810634be (diff)
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arm, at91: corvus board updates
- corvus board fix problems with toshiba nand chips on the corvus board problems with toshiba chips Manufacturer ID: 0x98 Chip ID: 0xdc encounterd. Solve this in the following way: - set other nand timings - enable CONFIG_SYS_NAND_READY_PIN - correct the MACH_TYPE setting Signed-off-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'include')
-rw-r--r--include/configs/corvus.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 5b50c1d..ace511f 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -18,6 +18,7 @@
#define MACH_TYPE_CORVUS 2066
+#define CONFIG_MACH_TYPE MACH_TYPE_CORVUS
#define CONFIG_SYS_GENERIC_BOARD
/*
* Warning: changing CONFIG_SYS_TEXT_BASE requires
@@ -106,6 +107,7 @@
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
#endif
/* Ethernet */
@@ -171,7 +173,6 @@
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
@@ -184,7 +185,6 @@
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_SIZE (256*1024*1024)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \