Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx

* 'master' of git://git.denx.de/u-boot-mpc83xx:
  km/common: check test_bank and testpin for testboot
  powerpc/83xx/km: readout dip_switch on kmcoge5ne
  powerpc/83xx: configure CONFIG_POST for kmcoge5ne
  powerpc/83xx/km: added missing enable of application buffer
  km/common: increase bootlimit to 3
  km/common: fixed error in ethaddr (1-byte-shift)
  MAINTAINERS: cleanup for keymile boards
  powerpc/83xx: add kmcoge5ne board support
  km/common: add support for second flash
  powerpc83xx/km: remove unneeded CONFIG_PCI for kmeter1
  powerpc83xx/km: lock the window size to 2GiB befor fixing sdram size
  powerpc/83xx/km: use tuxx1.h for kmsupx5 target
  powerpc/83xx: increment malloc heap size for the MPC832x MDS boards

Signed-off-by: Wolfgang Denk <wd@denx.de>

9 files changed, 352 insertions, 309 deletions

diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 4ed5a97..6f8622c 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -181,7 +181,7 @@
 
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 #define CONFIG_SYS_MONITOR_LEN	(384 * 1024)	/* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)	/* Reserved for malloc */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
 
 /*
  * Initial RAM Base Address Setup
diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index 7a01705..b650539 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -126,12 +126,29 @@
 	"netdev=eth0\0"
 #endif
 
-#ifndef CONFIG_KM_UBI_PARTITION_NAME
-#define CONFIG_KM_UBI_PARTITION_NAME	"ubi0"
-#endif
-#ifndef CONFIG_KM_UBI_LINUX_MTD_NAME
-#define CONFIG_KM_UBI_LINUX_MTD_NAME	"ubi0"
-#endif
+#ifndef CONFIG_KM_UBI_PARTITION_NAME_BOOT
+#define CONFIG_KM_UBI_PARTITION_NAME_BOOT	"ubi0"
+#endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */
+
+#ifndef CONFIG_KM_UBI_PARTITION_NAME_APP
+/* one flash chip only called boot */
+/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
+# define CONFIG_KM_UBI_LINUX_MTD					\
+	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT
+# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI				\
+	"ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0"
+#else /* CONFIG_KM_UBI_PARTITION_NAME_APP */
+/* two flash chips called boot and app */
+/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
+/* app:  CONFIG_KM_UBI_PARTITION_NAME_APP */
+# define CONFIG_KM_UBI_LINUX_MTD					\
+	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT " "		\
+	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP
+# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI				\
+	"ubiattach=if test ${boot_bank} -eq 0; then; "			\
+	"ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "; else; "	\
+	"ubi part " CONFIG_KM_UBI_PARTITION_NAME_APP "; fi\0"
+#endif /* CONFIG_KM_UBI_PARTITION_NAME_APP */
 
 #define xstr(s)	str(s)
 #define str(s)	#s
@@ -173,7 +190,7 @@
 		" console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}"	\
 		" mem=${kernelmem} init=${init}"			\
 		" phram.phram=phvar,${varaddr}," xstr(CONFIG_KM_PHRAM)	\
-		" ubi.mtd=" CONFIG_KM_UBI_LINUX_MTD_NAME " "		\
+		" " CONFIG_KM_UBI_LINUX_MTD " "				\
 		CONFIG_KM_DEF_BOOT_ARGS_CPU				\
 		"\0"							\
 	"addpanic="							\
@@ -199,10 +216,9 @@
 #define CONFIG_KM_DEF_ENV_FLASH_BOOT					\
 	"cramfsaddr=" xstr(CONFIG_KM_CRAMFS_ADDR) "\0"			\
 	"cramfsloadkernel=cramfsload ${load_addr_r} uImage\0"		\
-	"ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME "\0"		\
 	"ubicopy=ubi read "xstr(CONFIG_KM_CRAMFS_ADDR)			\
 			" bootfs${boot_bank}\0"				\
-	""
+	CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI
 
 /*
  * constants
@@ -229,12 +245,14 @@
 	CONFIG_KM_DEF_ENV_CONSTANTS					\
 	"altbootcmd=run bootcmd\0"					\
 	"bootcmd=km_checkbidhwk &&  "					\
-	"	setenv bootcmd \'setenv boot_bank ${actual_bank}; "	\
+		"setenv bootcmd \'if km_checktestboot; then; "          \
+				"setenv boot_bank ${test_bank}; else; " \
+				"setenv boot_bank ${actual_bank}; fi;"  \
 			"run ${subbootcmds}; reset\' && "		\
 		"setenv altbootcmd \'setenv boot_bank ${backup_bank}; "	\
 			"run ${subbootcmds}; reset\' && "		\
 		"saveenv && saveenv && boot\0"				\
-	"bootlimit=2\0"							\
+	"bootlimit=3\0"							\
 	"init=/sbin/init-overlay.sh\0"					\
 	"load_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0"			\
 	"load=tftpboot ${load_addr_r} ${u-boot}\0"			\
diff --git a/include/configs/km/km82xx-common.h b/include/configs/km/km82xx-common.h
index 02a82a6..2c763bb 100644
--- a/include/configs/km/km82xx-common.h
+++ b/include/configs/km/km82xx-common.h
@@ -73,7 +73,7 @@
 		"128k(env),"						\
 		"128k(envred),"						\
 		"3072k(free),"						\
-		"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
+		"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ")"
 
 /*
  * Default environment settings
diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h
index 06ecb8a..877d841 100644
--- a/include/configs/km/km83xx-common.h
+++ b/include/configs/km/km83xx-common.h
@@ -15,13 +15,18 @@
 #include "keymile-common.h"
 #include "km-powerpc.h"
 
-#define MTDIDS_DEFAULT		"nor0=boot"
-#define MTDPARTS_DEFAULT	"mtdparts="			\
+#ifndef MTDIDS_DEFAULT
+# define MTDIDS_DEFAULT	"nor0=boot"
+#endif /* MTDIDS_DEFAULT */
+
+#ifndef MTDPARTS_DEFAULT
+# define MTDPARTS_DEFAULT	"mtdparts="			\
 	"boot:"							\
 		"768k(u-boot),"					\
 		"128k(env),"					\
 		"128k(envred),"					\
-		"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
+		"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
+#endif /* MTDPARTS_DEFAULT */
 
 #define CONFIG_MISC_INIT_R
 /*
@@ -49,6 +54,8 @@
  */
 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
+
 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index c73a10c..011f838 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -229,11 +229,15 @@ int get_scl(void);
 
 #define FLASH_GPIO_PIN			0x00010000
 
-#define MTDIDS_DEFAULT		"nand0=orion_nand"
-/* test-only: partitioning needs some tuning, this is just for tests */
-#define MTDPARTS_DEFAULT	"mtdparts="				\
-	"orion_nand:"							\
-		"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
+#ifndef MTDIDS_DEFAULT
+# define MTDIDS_DEFAULT		"nand0=orion_nand"
+#endif /* MTDIDS_DEFAULT */
+
+#ifndef MTDPARTS_DEFAULT
+# define MTDPARTS_DEFAULT	"mtdparts="			\
+	"orion_nand:"						\
+		"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
+#endif /* MTDPARTS_DEFAULT */
 
 #define	CONFIG_KM_DEF_ENV_UPDATE					\
 	"update="							\
@@ -257,7 +261,6 @@ int get_scl(void);
 	""
 
 #if defined(CONFIG_SYS_NO_FLASH)
-#define CONFIG_KM_UBI_PARTITION_NAME   "ubi0"
 #undef	CONFIG_FLASH_CFI_MTD
 #undef	CONFIG_JFFS2_CMDLINE
 #endif
diff --git a/include/configs/km8360.h b/include/configs/km8360.h
new file mode 100644
index 0000000..7631ab6
--- /dev/null
+++ b/include/configs/km8360.h
@@ -0,0 +1,289 @@
+/*
+ * (C) Copyright 2012
+ * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
+ * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* KMBEC FPGA (PRIO) */
+#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE	64
+
+#if defined CONFIG_KMETER1
+#define CONFIG_HOSTNAME		kmeter1
+#define CONFIG_KM_BOARD_NAME   "kmeter1"
+#define CONFIG_KM_DEF_NETDEV	"netdev=eth2\0"
+#elif defined CONFIG_KMCOGE5NE
+#define CONFIG_HOSTNAME		kmcoge5ne
+#define CONFIG_KM_BOARD_NAME	"kmcoge5ne"
+#define CONFIG_KM_DEF_NETDEV	"netdev=eth1\0"
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_KMETER1
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS				1
+#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
+
+#define CONFIG_KM_UBI_PARTITION_NAME_BOOT	"ubi0"
+#define CONFIG_KM_UBI_PARTITION_NAME_APP	"ubi1"
+#define MTDIDS_DEFAULT			"nor0=boot,nand0=app"
+
+#define MTDPARTS_DEFAULT		"mtdparts="			\
+	"boot:"								\
+		"768k(u-boot),"						\
+		"128k(env),"						\
+		"128k(envred),"						\
+		"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"		\
+	"app:"								\
+		"-(" CONFIG_KM_UBI_PARTITION_NAME_APP ");"
+#else
+#error ("Board not supported")
+#endif
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_QE			/* Has QE */
+#define CONFIG_MPC8360			/* MPC8360 CPU specific */
+
+#define	CONFIG_SYS_TEXT_BASE	0xF0000000
+
+/* include common defines/options for all 83xx Keymile boards */
+#include "km/km83xx-common.h"
+
+/*
+ * System IO Setup
+ */
+#define CONFIG_SYS_SICRH		(SICRH_UC1EOBI | SICRH_UC2E1OBI)
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_CSB_TO_CLKIN_4X1 | \
+	HRCWL_CORE_TO_CSB_2X1 | \
+	HRCWL_CE_PLL_VCO_DIV_2 | \
+	HRCWL_CE_TO_PLL_1X6)
+
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_CORE_ENABLE | \
+	HRCWH_FROM_0X00000100 | \
+	HRCWH_BOOTSEQ_DISABLE | \
+	HRCWH_SW_WATCHDOG_DISABLE | \
+	HRCWH_ROM_LOC_LOCAL_16BIT | \
+	HRCWH_BIG_ENDIAN | \
+	HRCWH_LALE_EARLY | \
+	HRCWH_LDP_CLEAR)
+
+/**
+ * DDR RAM settings
+ */
+#define CONFIG_SYS_DDR_SDRAM_CFG (\
+	SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+	SDRAM_CFG_SREN | \
+	SDRAM_CFG_HSE)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+
+#ifdef CONFIG_KMCOGE5NE
+/**
+ * KMCOGE5NE has 512 MB RAM
+ */
+#define CONFIG_SYS_DDR_CS0_CONFIG (\
+	CSCONFIG_EN | \
+	CSCONFIG_AP | \
+	CSCONFIG_ODT_RD_ONLY_CURRENT | \
+	CSCONFIG_BANK_BIT_3 | \
+	CSCONFIG_ROW_BIT_13 | \
+	CSCONFIG_COL_BIT_10)
+#else
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
+					 CSCONFIG_ROW_BIT_13 | \
+					 CSCONFIG_COL_BIT_10 | \
+					 CSCONFIG_ODT_RD_ONLY_CURRENT)
+#endif
+
+#define CONFIG_SYS_DDR_CLK_CNTL (\
+	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
+#define CONFIG_SYS_DDR_INTERVAL (\
+	(0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+	(0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_BNDS			0x0000007f
+
+#define CONFIG_SYS_DDRCDR (\
+	DDRCDR_EN | \
+	DDRCDR_Q_DRN)
+#define CONFIG_SYS_DDR_MODE		0x47860452
+#define CONFIG_SYS_DDR_MODE2		0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0 (\
+	(2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+	(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+	(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+	(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+	(0 << TIMING_CFG0_WWT_SHIFT) | \
+	(0 << TIMING_CFG0_RRT_SHIFT) | \
+	(0 << TIMING_CFG0_WRT_SHIFT) | \
+	(0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_50) | \
+				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
+				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2 (\
+	(0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+	(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+	(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+	(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+	(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+	(5 << TIMING_CFG2_CPO_SHIFT) | \
+	(0 << TIMING_CFG2_ADD_LAT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3			0x00000000
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
+#define CONFIG_SYS_LCRR_EADC		LCRR_EADC_2
+#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_4
+
+/*
+ * PAXE on the local bus CS3
+ */
+#define CONFIG_SYS_PAXE_BASE		0xA0000000
+#define CONFIG_SYS_PAXE_SIZE		256
+
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_PAXE_BASE
+
+#define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000001C /* 512MB window size */
+
+#define CONFIG_SYS_BR3_PRELIM (\
+	CONFIG_SYS_PAXE_BASE | \
+	(1 << BR_PS_SHIFT) | \
+	BR_V)
+
+#define CONFIG_SYS_OR3_PRELIM (\
+	MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
+	OR_GPCM_CSNT | \
+	OR_GPCM_ACS_DIV2 | \
+	OR_GPCM_SCY_2 | \
+	OR_GPCM_TRLX | \
+	OR_GPCM_EAD)
+
+#ifdef CONFIG_KMCOGE5NE
+/*
+ * BFTIC3 on the local bus CS4
+ */
+#define CONFIG_SYS_BFTIC3_BASE			0xB0000000
+#define CONFIG_SYS_BFTIC3_SIZE			256
+
+#define CONFIG_SYS_BR4_PRELIM (\
+	CONFIG_SYS_BFTIC3_BASE |\
+	(1 << BR_PS_SHIFT) | \
+	BR_V)
+
+#define CONFIG_SYS_OR4_PRELIM (\
+	MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
+	OR_GPCM_CSNT | \
+	OR_GPCM_ACS_DIV2 |\
+	OR_GPCM_SCY_2 |\
+	OR_GPCM_TRLX |\
+	OR_GPCM_EAD)
+#endif
+
+/*
+ * MMU Setup
+ */
+
+/* PAXE:  icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT5L (\
+	CONFIG_SYS_PAXE_BASE | \
+	BATL_PP_10 | \
+	BATL_MEMCOHERENCE)
+
+#define CONFIG_SYS_IBAT5U (\
+	CONFIG_SYS_PAXE_BASE | \
+	BATU_BL_256M | \
+	BATU_VS | \
+	BATU_VP)
+
+#define CONFIG_SYS_DBAT5L (\
+	CONFIG_SYS_PAXE_BASE | \
+	BATL_PP_10 | \
+	BATL_CACHEINHIBIT | \
+	BATL_GUARDEDSTORAGE)
+
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+
+
+#ifdef CONFIG_KMCOGE5NE
+/* BFTIC3:  icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT6L (\
+	CONFIG_SYS_BFTIC3_BASE | \
+	BATL_PP_10 | \
+	BATL_MEMCOHERENCE)
+
+#define CONFIG_SYS_IBAT6U (\
+	CONFIG_SYS_BFTIC3_BASE | \
+	BATU_BL_256M | \
+	BATU_VS | \
+	BATU_VP)
+
+#define CONFIG_SYS_DBAT6L (\
+	CONFIG_SYS_BFTIC3_BASE | \
+	BATL_PP_10 | \
+	BATL_CACHEINHIBIT | \
+	BATL_GUARDEDSTORAGE)
+
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+
+/* DDR/LBC SDRAM next 256M: cacheable */
+#define CONFIG_SYS_IBAT7L (\
+	CONFIG_SYS_SDRAM_BASE2 |\
+	BATL_PP_10 |\
+	BATL_CACHEINHIBIT |\
+	BATL_GUARDEDSTORAGE)
+
+#define CONFIG_SYS_IBAT7U (\
+	CONFIG_SYS_SDRAM_BASE2 |\
+	BATU_BL_256M |\
+	BATU_VS |\
+	BATU_VP)
+/* enable POST tests */
+#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
+#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
+#define CPM_POST_WORD_ADDR  CONFIG_SYS_MEMTEST_END
+#define CONFIG_TESTPIN_REG  gprt3	/* for kmcoge5ne */
+#define CONFIG_TESTPIN_MASK 0x20	/* for kmcoge5ne */
+#define CONFIG_CMD_DIAG	/* so that testpin is inquired for POST test */
+
+#else
+#define CONFIG_SYS_IBAT6L	(0)
+#define CONFIG_SYS_IBAT6U	(0)
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#endif
+
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+#endif /* CONFIG */
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
deleted file mode 100644
index 6b5a6fe..0000000
--- a/include/configs/kmeter1.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- *                    Dave Liu <daveliu@freescale.com>
- *
- * Copyright (C) 2007 Logic Product Development, Inc.
- *                    Peter Barada <peterb@logicpd.com>
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- *                    Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * (C) Copyright 2008-2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_QE		/* Has QE */
-#define CONFIG_MPC8360		/* MPC8360 CPU specific */
-#define CONFIG_KMETER1		/* KMETER1 board specific */
-#define CONFIG_HOSTNAME		kmeter1
-#define CONFIG_KM_BOARD_NAME   "kmeter1"
-
-#define	CONFIG_SYS_TEXT_BASE	0xF0000000
-#define CONFIG_KM_DEF_NETDEV	\
-	"netdev=eth2\0"		\
-
-/* include common defines/options for all 83xx Keymile boards */
-#include "km/km83xx-common.h"
-
-#define CONFIG_MISC_INIT_R
-/*
- * System IO Setup
- */
-#define CONFIG_SYS_SICRH		(SICRH_UC1EOBI | SICRH_UC2E1OBI)
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_CSB_TO_CLKIN_4X1 | \
-	HRCWL_CORE_TO_CSB_2X1 | \
-	HRCWL_CE_PLL_VCO_DIV_2 | \
-	HRCWL_CE_TO_PLL_1X6)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_CORE_ENABLE | \
-	HRCWH_FROM_0X00000100 | \
-	HRCWH_BOOTSEQ_DISABLE | \
-	HRCWH_SW_WATCHDOG_DISABLE | \
-	HRCWH_ROM_LOC_LOCAL_16BIT | \
-	HRCWH_BIG_ENDIAN | \
-	HRCWH_LALE_EARLY | \
-	HRCWH_LDP_CLEAR)
-
-#define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
-#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
-					 SDRAM_CFG_SREN)
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
-#define CONFIG_SYS_DDR_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL	((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
-				 (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
-
-#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
-					 CSCONFIG_ROW_BIT_13 | \
-					 CSCONFIG_COL_BIT_10 | \
-					 CSCONFIG_ODT_WR_ONLY_CURRENT)
-
-#define	CONFIG_SYS_DDRCDR		(DDRCDR_EN | DDRCDR_Q_DRN)
-					/* 0x40000001 */
-#define CONFIG_SYS_DDR_MODE		0x47860452
-#define CONFIG_SYS_DDR_MODE2		0x8080c000
-
-#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
-				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
-				 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
-				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
-				 (0 << TIMING_CFG0_WWT_SHIFT) | \
-				 (0 << TIMING_CFG0_RRT_SHIFT) | \
-				 (0 << TIMING_CFG0_WRT_SHIFT) | \
-				 (0 << TIMING_CFG0_RWT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_50) | \
-				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
-				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
-				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
-				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
-				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
-				 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
-				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
-				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
-				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
-				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
-				 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
-				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
-				 (5 << TIMING_CFG2_CPO_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-
-/* PRIO FPGA */
-#define	CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
-#define	CONFIG_SYS_KMBEC_FPGA_SIZE	128
-/* PAXE FPGA */
-#define	CONFIG_SYS_PAXE_BASE		0xA0000000
-#define	CONFIG_SYS_PAXE_SIZE		512
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
-#define CONFIG_SYS_LCRR_EADC	LCRR_EADC_2
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
-
-/*
- * Init Local Bus Memory Controller:
- *
- * Bank Bus     Machine PortSz  Size  Device
- * ---- ---     ------- ------  -----  ------
- *  3   Local   GPCM     8 bit  512MB PAXE
- *
- */
-
-/*
- * PAXE on the local bus CS3
- */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_PAXE_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_512MB)
-
-#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_PAXE_BASE | \
-				BR_PS_8 | /* 8 bit port size */ \
-				BR_MS_GPCM | /* MSEL = GPCM */ \
-				BR_V)
-#define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
-				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-				OR_GPCM_SCY_2 | \
-				OR_GPCM_TRLX_SET | OR_GPCM_EAD)
-
-/*
- * MMU Setup
- */
-
-/* PAXE:  icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \
-				 BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \
-				 BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \
-				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CFG_IBAT6L	(CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U	(CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CFG_IBAT7L	(CFG_PCI1_MMIO_PHYS | BATL_PP_RW | \
-			 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT7U	(CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
-#else /* CONFIG_PCI */
-#define CONFIG_SYS_IBAT6L	(0)
-#define CONFIG_SYS_IBAT6U	(0)
-#define CONFIG_SYS_IBAT7L	(0)
-#define CONFIG_SYS_IBAT7U	(0)
-#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
-#endif /* CONFIG_PCI */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h
deleted file mode 100644
index b0dd88c..0000000
--- a/include/configs/kmsupx5.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- *                    Dave Liu <daveliu@freescale.com>
- *
- * Copyright (C) 2007 Logic Product Development, Inc.
- *                    Peter Barada <peterb@logicpd.com>
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- *                    Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * (C) Copyright 2008
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * (C) Copyright 2010
- * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
- *
- * (C) Copyright 2010-2011
- * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_KMSUPX5		1 /* Keymile PBEC8321 board specific */
-#define CONFIG_HOSTNAME		supx5
-#define CONFIG_KM_BOARD_NAME	"supx5"
-
-#define	CONFIG_SYS_TEXT_BASE	0xF0000000
-
-/* include common defines/options for all 8321 Keymile boards */
-#include "km/km8321-common.h"
-
-/*
- * Init Local Bus Memory Controller:
- *
- * Bank Bus     Machine PortSz  Size  Device
- * ---- ---     ------- ------  -----  ------
- *  2   Local   GPCM    8 bit  256MB	LPXF
- *  3   Local   not used
- *
- */
-
-/*
- * LPXF on the local bus CS2
- * Window base at flash base
- * Window size: 256 MB
- */
-
-#define	CONFIG_SYS_LPXF_BASE		0xA0000000    /* LPXF */
-#define	CONFIG_SYS_LPXF_SIZE		256 /* Megabytes */
-
-#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_LPXF_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
-
-#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_LPXF_BASE | \
-				 BR_PS_8 | \
-				 BR_MS_GPCM | \
-				 BR_V)
-
-#define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_LPXF_SIZE) | \
-				 OR_GPCM_CSNT | \
-				 OR_GPCM_ACS_DIV4 | \
-				 OR_GPCM_SCY_2 | \
-				 OR_GPCM_TRLX_SET | \
-				 OR_GPCM_EHTR_CLEAR | \
-				 OR_GPCM_EAD)
-
-/* LPXF:  icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \
-				 BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \
-				 BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \
-				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
-
-/* Bank 3 not used */
-#define CONFIG_SYS_IBAT6L       (0)
-#define CONFIG_SYS_IBAT6U       (0)
-#define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h
index f6d2b17..90d2e61 100644
--- a/include/configs/tuxx1.h
+++ b/include/configs/tuxx1.h
@@ -11,7 +11,7 @@
  * (C) Copyright 2008
  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  *
- * (C) Copyright 2010-2011
+ * (C) Copyright 2010-2012
  * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
  * Holger Brunck,  Keymile GmbH, holger.bruncl@keymile.com
  *
@@ -27,12 +27,16 @@
 /*
  * High Level Configuration Options
  */
+#ifdef CONFIG_KMSUPX5
+#define CONFIG_KM_BOARD_NAME	"kmsupx5"
+#define CONFIG_HOSTNAME		kmsupx5
+#elif defined CONFIG_TUGE1
+#define CONFIG_KM_BOARD_NAME	"tuge1"
+#define CONFIG_HOSTNAME		tuge1
+#else
 #define CONFIG_TUXXX		/* TUXX1 board (tuxa1/tuda1) specific */
+#define CONFIG_KM_BOARD_NAME	"tuxx1"
 #define CONFIG_HOSTNAME		tuxx1
-#ifdef CONFIG_KM_DISABLE_APP2
-#define CONFIG_KM_BOARD_NAME   "tuge1"
-#else
-#define CONFIG_KM_BOARD_NAME   "tuxx1"
 #endif
 
 #define	CONFIG_SYS_TEXT_BASE	0xF0000000
@@ -50,10 +54,10 @@
 /*
  * Init Local Bus Memory Controller:
  *
- * Bank Bus     Machine PortSz  Size  Device on TUDA1  TUXA1  TUGE1
- * ---- ---     ------- ------  -----  ----------------------------
- *  2   Local   GPCM    8 bit  256MB	         PAXG  LPXF   PAXI
- *  3   Local   GPCM    8 bit  256MB	         PINC3 PINC2  unused
+ * Bank Bus     Machine PortSz  Size  Device on TUDA1  TUXA1  TUGE1   KMSUPX4
+ * ---- ---     ------- ------  -----  ---------------------------------------
+ *  2   Local   GPCM    8 bit  256MB	         PAXG  LPXF   PAXI     LPXF
+ *  3   Local   GPCM    8 bit  256MB	         PINC3 PINC2  unused   unused
  *
  */