Merge branch 'master' of git://git.denx.de/u-boot-arm

37 files changed, 394 insertions, 248 deletions

diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h
index d4104de..9371ec3 100644
--- a/include/configs/eb_cpux9k2.h
+++ b/include/configs/eb_cpux9k2.h
@@ -44,7 +44,12 @@
 #define MACH_TYPE_EB_CPUX9K2		1977
 #define CONFIG_MACH_TYPE		MACH_TYPE_EB_CPUX9K2
 /*--------------------------------------------------------------------------*/
-#define CONFIG_SYS_TEXT_BASE 		0x00000000
+#ifndef CONFIG_RAMBOOT
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+#else
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE		0x21f00000
+#endif
 #define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
 
 #define CONFIG_SYS_BOOT_SIZE		0x00 /* 0 KBytes */
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index f0fb488..f2cfaf8 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -69,13 +69,18 @@
  * - GPIO16 is Power LED control (0 = on, 1 = off)
  * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
  * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
- * - Last GPIO is 26, further bits are supposed to be 0.
+ * - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
+ * - GPIO22 is SATA disk power status ()
+ * - GPIO23 is supply status for SATA disk ()
+ * - GPIO24 is supply control for board (write 1 to power off)
+ * Last GPIO is 25, further bits are supposed to be 0.
  * Enable mask has ones for INPUT, 0 for OUTPUT.
- * Default is LED ON.
+ * Default is LED ON, board ON :)
  */
 
-#define ORION5X_GPIO_OUT_ENABLE	0x03fcffff
-#define ORION5X_GPIO_OUT_VALUE	0x03fcffff
+#define ORION5X_GPIO_OUT_ENABLE		0xfef4f0ca
+#define ORION5X_GPIO_OUT_VALUE		0x00000000
+#define ORION5X_GPIO_IN_POLARITY	0x000000d0
 
 /*
  * NS16550 Configuration
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 027a5dc..46171b9 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -31,7 +31,6 @@
  /* High Level Configuration Options */
 #define CONFIG_ARM1136	/* This is an arm1136 CPU core */
 #define CONFIG_MX35
-#define CONFIG_MX35_HCLK_FREQ	24000000
 
 #define CONFIG_SYS_DCACHE_OFF
 #define CONFIG_SYS_CACHELINE_SIZE	32
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index d0555c1..e407ff4 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -34,15 +34,15 @@
 
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (Harmony) # "
-#define CONFIG_TEGRA20_BOARD_STRING	"NVIDIA Harmony"
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Harmony"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD
+#define CONFIG_TEGRA_ENABLE_UARTD
 
 /* UARTD: keyboard satellite board UART, default */
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
-#ifdef CONFIG_TEGRA20_ENABLE_UARTA
+#ifdef CONFIG_TEGRA_ENABLE_UARTA
 /* UARTA: debug board UART */
 #define CONFIG_SYS_NS16550_COM2		NV_PA_APB_UARTA_BASE
 #endif
@@ -62,8 +62,15 @@
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 
-/* Environment not stored */
-#define CONFIG_ENV_IS_NOWHERE
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE	NV_PA_NAND_BASE
+
+/* Environment in NAND (which is 512M), aligned to start of last sector */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	(SZ_512M - SZ_128K) /* 128K sector size */
 
 /* USB Host support */
 #define CONFIG_USB_EHCI
@@ -80,6 +87,6 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h
index 567061a..dbc59b9 100644
--- a/include/configs/ima3-mx53.h
+++ b/include/configs/ima3-mx53.h
@@ -64,7 +64,6 @@
 /* Ethernet on FEC */
 #define CONFIG_NET_MULTI
 #define CONFIG_MII
-#define CONFIG_DISCOVER_PHY
 
 #define CONFIG_FEC_MXC
 #define IMX_FEC_BASE			FEC_BASE_ADDR
@@ -72,7 +71,7 @@
 #define CONFIG_PHY_ADDR			CONFIG_FEC_MXC_PHYADDR
 #define CONFIG_RESET_PHY_R
 #define CONFIG_FEC_MXC_NO_ANEG
-#define CONFIG_PRIME	"FEC0"
+#define CONFIG_ETHPRIME			"FEC0"
 
 /* SPI */
 #define CONFIG_HARD_SPI
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 8cca478..6ae764a 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -33,7 +33,6 @@
  /* High Level Configuration Options */
 #define CONFIG_ARM1136		1    /* This is an arm1136 CPU core */
 #define CONFIG_MX31		1    /* in a mx31 */
-#define CONFIG_MX31_HCLK_FREQ	26000000
 #define CONFIG_MX31_CLK32	32000
 
 #define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index b21621c..f36ceea 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -33,7 +33,6 @@
 /* High Level Configuration Options */
 #define CONFIG_ARM1136			/* This is an arm1136 CPU core */
 #define CONFIG_MX31			/* in a mx31 */
-#define CONFIG_MX31_HCLK_FREQ	26000000
 #define CONFIG_MX31_CLK32	32000
 
 #define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h
new file mode 100644
index 0000000..564b418
--- /dev/null
+++ b/include/configs/integrator-common.h
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2012
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ * Common ARM Integrator configuration settings
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define CONFIG_INTEGRATOR
+
+#define CONFIG_SYS_TEXT_BASE		0x01000000
+#define CONFIG_SYS_MEMTEST_START	0x100000
+#define CONFIG_SYS_MEMTEST_END		0x10000000
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_TIMERBASE		0x13000100	/* Timer1 */
+#define CONFIG_SYS_LOAD_ADDR		0x7fc0	/* default load address */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size*/
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size*/
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_MISC_INIT_R		/* call misc_init_r during start up */
+
+/*
+ * There are various dependencies on the core module (CM) fitted
+ * Users should refer to their CM user guide
+ */
+#include "armcoremodule.h"
+
+/*
+ * Initialize and remap the core module, use SPD to detect memory size
+ * If CONFIG_SKIP_LOWLEVEL_INIT is not defined &
+ * the core module has a CM_INIT register
+ * then the U-Boot initialisation code will
+ * e.g. ARM Boot Monitor or pre-loader is repeated once
+ * (to re-initialise any existing CM_INIT settings to safe values).
+ *
+ * This is usually not the desired behaviour since the platform
+ * will either reboot into the ARM monitor (or pre-loader)
+ * or continuously cycle thru it without U-Boot running,
+ * depending upon the setting of Integrator/CP switch S2-4.
+ *
+ * However it may be needed if Integrator/CP switch S2-1
+ * is set OFF to boot direct into U-Boot.
+ * In that case comment out the line below.
+ */
+#define CONFIG_CM_INIT
+#define CONFIG_CM_REMAP
+#define CONFIG_CM_SPD_DETECT
+
+/*
+ * The ARM boot monitor initializes the board.
+ * However, the default U-Boot code also performs the initialization.
+ * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT
+ * - see documentation supplied with board for details of how to choose the
+ * image to run at reset/power up
+ * e.g. whether the ARM Boot Monitor runs before U-Boot
+ */
+/* #define CONFIG_SKIP_LOWLEVEL_INIT */
+
+/*
+ * The ARM boot monitor does not relocate U-Boot.
+ * However, the default U-Boot code performs the relocation check,
+ * and may relocate the code if the memory map is changed.
+ * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT
+ */
+/* #define SKIP_CONFIG_RELOCATE_UBOOT */
+
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
+				    CONFIG_SYS_INIT_RAM_SIZE - \
+				    GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
index 2770c82..c6907b5 100644
--- a/include/configs/integratorap.h
+++ b/include/configs/integratorap.h
@@ -31,32 +31,11 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_INTEGRATOR
+#include "integrator-common.h"
+
+/* Integrator/AP-specific configuration */
 #define CONFIG_ARCH_INTEGRATOR
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SYS_TEXT_BASE		0x01000000
-#define CONFIG_SYS_MEMTEST_START	0x100000
-#define CONFIG_SYS_MEMTEST_END		0x10000000
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_HZ_CLOCK		24000000	/* Timer 1 is clocked at 24Mhz */
-#define CONFIG_SYS_TIMERBASE		0x13000100	/* Timer1		       */
-
-#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r during start up */
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_CM_INIT		1
-#define CONFIG_CM_REMAP		1
-#define CONFIG_CM_SPD_DETECT
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
 
 /*
  * PL010 Configuration
@@ -90,29 +69,7 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LONGHELP	/* undef to save memory	    */
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT	"Integrator-AP # "	/* Monitor Command Prompt   */
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size  */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_LOAD_ADDR	0x7fc0	/* default load address */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1	/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
-				    CONFIG_SYS_INIT_RAM_SIZE - \
-				    GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_FLASH_BASE	0x24000000
 
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
index d5043df..ca02a6f 100644
--- a/include/configs/integratorcp.h
+++ b/include/configs/integratorcp.h
@@ -31,32 +31,11 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/* Integrator-specific configuration */
-#define CONFIG_INTEGRATOR
-#define CONFIG_ARCH_CINTEGRATOR
-#define CONFIG_CM_INIT
-#define CONFIG_CM_REMAP
-#define CONFIG_CM_SPD_DETECT
+#include "integrator-common.h"
 
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SYS_TEXT_BASE		0x01000000
-#define CONFIG_SYS_MEMTEST_START	0x100000
-#define CONFIG_SYS_MEMTEST_END		0x10000000
-#define CONFIG_SYS_HZ			1000
+/* Integrator CP-specific configuration */
+#define CONFIG_ARCH_CINTEGRATOR
 #define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer 1 is clocked at 1Mhz */
-#define CONFIG_SYS_TIMERBASE		0x13000100
-
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs  */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_MISC_INIT_R		1	/* call misc_init_r during start up */
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
 
 /*
  * Hardware drivers
@@ -66,9 +45,7 @@
 #define CONFIG_SMC91111_BASE    0xC8000000
 #undef CONFIG_SMC91111_EXT_PHY
 
-/*
- * NS16550 Configuration
- */
+/* PL011 configuration */
 #define CONFIG_PL011_SERIAL
 #define CONFIG_PL011_CLOCK	14745600
 #define CONFIG_PL01x_PORTS	{ (void *)CONFIG_SYS_SERIAL0, (void *)CONFIG_SYS_SERIAL1 }
@@ -77,16 +54,6 @@
 #define CONFIG_SYS_SERIAL0		0x16000000
 #define CONFIG_SYS_SERIAL1		0x17000000
 
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
 /*
  * Command line configuration.
  */
@@ -102,32 +69,10 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LONGHELP				/* undef to save memory */
 #define CONFIG_SYS_PROMPT	"Integrator-CP # "	/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE	256			/* Console I/O Buffer Size*/
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS	16			/* max number of command args */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE		/* Boot Argument Buffer Size*/
 
-#define CONFIG_SYS_LOAD_ADDR	0x7fc0	/* default load address */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
-				    CONFIG_SYS_INIT_RAM_SIZE - \
-				    GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
+/*
  * FLASH and environment organization
-
  * Top varies according to amount fitted
  * Reserve top 4 blocks of flash
  * - ARM Boot Monitor
@@ -136,7 +81,6 @@
  * - U-Boot environment
  *
  * Base is always 0x24000000
-
  */
 #define CONFIG_SYS_FLASH_BASE		0x24000000
 #define CONFIG_SYS_FLASH_CFI		1
@@ -178,53 +122,4 @@
 #define CONFIG_ENV_SECT_SIZE	0x40000		/* 256KB */
 #define CONFIG_ENV_SIZE		8192		/* 8KB */
 
-/*
- * The ARM boot monitor initializes the board.
- * However, the default U-Boot code also performs the initialization.
- * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT
- * - see documentation supplied with board for details of how to choose the
- * image to run at reset/power up
- * e.g. whether the ARM Boot Monitor runs before U-Boot
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
- */
-
-/*
- * The ARM boot monitor does not relocate U-Boot.
- * However, the default U-Boot code performs the relocation check,
- * and may relocate the code if the memory map is changed.
- * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT
-
-#define SKIP_CONFIG_RELOCATE_UBOOT
-
- */
-/*-----------------------------------------------------------------------
- * There are various dependencies on the core module (CM) fitted
- * Users should refer to their CM user guide
- * - when porting adjust u-boot/Makefile accordingly
- * to define the necessary CONFIG_ s for the CM involved
- * see e.g. cp_926ejs_config
- */
-
-#include "armcoremodule.h"
-
-/*
- * If CONFIG_SKIP_LOWLEVEL_INIT is not defined &
- * the core module has a CM_INIT register
- * then the U-Boot initialisation code will
- * e.g. ARM Boot Monitor or pre-loader is repeated once
- * (to re-initialise any existing CM_INIT settings to safe values).
- *
- * This is usually not the desired behaviour since the platform
- * will either reboot into the ARM monitor (or pre-loader)
- * or continuously cycle thru it without U-Boot running,
- * depending upon the setting of Integrator/CP switch S2-4.
- *
- * However it may be needed if Integrator/CP switch S2-1
- * is set OFF to boot direct into U-Boot.
- * In that case comment out the line below.
-#undef	CONFIG_CM_INIT
- */
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index 7ed9958..9983104 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -81,7 +81,6 @@
 
 #define CONFIG_LOADS_ECHO
 #define CONFIG_SYS_LOADS_BAUD_CHANGE
-#define CONFIG_SYS_BOARD_DRAM_INIT	/* Used board specific dram_init */
 
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_SYS_MAX_I2C_BUS		1
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 27b77d3..44d5373 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -57,10 +57,14 @@
 #define CONFIG_CMD_SF
 #define CONFIG_SOFT_I2C		/* I2C bit-banged	*/
 
+/* SPI NOR Flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED		8100000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+
 #if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
 #define CONFIG_ENV_SPI_BUS		0
 #define CONFIG_ENV_SPI_CS		0
-#define CONFIG_ENV_SPI_MAX_HZ		5000000
+#define CONFIG_ENV_SPI_MAX_HZ		8100000
 #define CONFIG_ENV_SPI_MODE		SPI_MODE_3
 #endif
 
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index d0f2b48..9eb2a54 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -171,9 +171,9 @@
 #define	CONFIG_LZO
 #define	CONFIG_MTD_DEVICE
 #define	CONFIG_MTD_PARTITIONS
-#define	MTDIDS_DEFAULT			"nand0=gpmi-nand.0"
+#define	MTDIDS_DEFAULT			"nand0=gpmi-nand"
 #define	MTDPARTS_DEFAULT			\
-	"mtdparts=gpmi-nand.0:"			\
+	"mtdparts=gpmi-nand:"			\
 		"3m(bootloader)ro,"		\
 		"512k(environment),"		\
 		"512k(redundant-environment),"	\
diff --git a/include/configs/medcom.h b/include/configs/medcom.h
index bce03a4..678b36b 100644
--- a/include/configs/medcom.h
+++ b/include/configs/medcom.h
@@ -35,11 +35,11 @@
 
 /* High-level configuration options */
 #define V_PROMPT			"Tegra20 (Medcom) # "
-#define CONFIG_TEGRA20_BOARD_STRING	"Avionic Design Medcom"
+#define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Medcom"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD	/* UARTD: debug UART */
+#define CONFIG_TEGRA_ENABLE_UARTD	/* UARTD: debug UART */
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 #define CONFIG_BOARD_EARLY_INIT_F
@@ -78,6 +78,6 @@
 	"ext2load mmc 0 0x17000000 /boot/uImage;"	\
 	"bootm"
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h
index 5db6d57..8d35943 100644
--- a/include/configs/mt_ventoux.h
+++ b/include/configs/mt_ventoux.h
@@ -2,6 +2,9 @@
  * Copyright (C) 2011
  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  *
+ *
+ * Configuration settings for the Teejet mt_ventoux board.
+ *
  * Copyright (C) 2009 TechNexion Ltd.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -24,6 +27,10 @@
 
 #include "tam3517-common.h"
 
+#undef CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10) + \
+					6 * 1024 * 1024)
+
 #define MACH_TYPE_AM3517_MT_VENTOUX	3832
 #define CONFIG_MACH_TYPE	MACH_TYPE_AM3517_MT_VENTOUX
 
@@ -31,6 +38,7 @@
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_AUTO_COMPLETE
 
+#define CONFIG_OMAP3_GPIO_4
 #define CONFIG_HOSTNAME mt_ventoux
 
 /*
@@ -62,6 +70,15 @@
 #define CONFIG_FPGA_DELAY() udelay(1)
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_CMD_BMP
+#define CONFIG_VIDEO_OMAP3	/* DSS Support			*/
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
 #define	CONFIG_EXTRA_ENV_SETTINGS	CONFIG_TAM3517_SETTINGS \
 	"bootcmd=run net_nfs\0"
 
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
index 359a308..96c143e 100644
--- a/include/configs/mx25pdk.h
+++ b/include/configs/mx25pdk.h
@@ -17,7 +17,6 @@
 
 /* High Level Configuration Options */
 
-#define CONFIG_MX25_CLK32		32768	/* OSC32K frequency */
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_TEXT_BASE		0x81200000
 
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index 4e1e6bc..dffb744 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -184,6 +184,9 @@
 #define	CONFIG_EHCI_MXS_PORT 1
 #define	CONFIG_EHCI_IS_TDI
 #define	CONFIG_USB_STORAGE
+#define	CONFIG_USB_HOST_ETHER
+#define	CONFIG_USB_ETHER_ASIX
+#define	CONFIG_USB_ETHER_SMSC95XX
 #endif
 
 /* I2C */
@@ -199,6 +202,7 @@
 #ifdef CONFIG_CMD_SPI
 #define CONFIG_HARD_SPI
 #define CONFIG_MXS_SPI
+#define CONFIG_MXS_SPI_DMA_ENABLE
 #define CONFIG_SPI_HALF_DUPLEX
 #define CONFIG_DEFAULT_SPI_BUS		2
 #define CONFIG_DEFAULT_SPI_MODE		SPI_MODE_0
@@ -235,7 +239,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE	"uImage"
-#define CONFIG_BOOTCOMMAND	"run bootcmd_net"
 #define CONFIG_LOADADDR	0x42000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 #define CONFIG_OF_LIBFDT
@@ -244,13 +247,80 @@
  * Extra Environments
  */
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"console_fsl=console=ttyAM0" \
-	"console_mainline=console=ttyAMA0" \
-	"netargs=setenv bootargs console=${console_mainline}" \
+	"update_nand_full_filename=u-boot.nand\0" \
+	"update_nand_firmware_filename=u-boot.sb\0"	\
+	"update_sd_firmware_filename=u-boot.sd\0" \
+	"update_nand_firmware_maxsz=0x100000\0"	\
+	"update_nand_stride=0x40\0"	/* MX28 datasheet ch. 12.12 */ \
+	"update_nand_count=0x4\0"	/* MX28 datasheet ch. 12.12 */ \
+	"update_nand_get_fcb_size="	/* Get size of FCB blocks */ \
+		"nand device 0 ; " \
+		"nand info ; " \
+		"setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \
+		"setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \
+	"update_nand_full="		    /* Update FCB, DBBT and FW */ \
+		"if tftp ${update_nand_full_filename} ; then " \
+		"run update_nand_get_fcb_size ; " \
+		"nand scrub -y 0x0 ${filesize} ; " \
+		"nand write.raw ${loadaddr} 0x0 ${update_nand_fcb} ; " \
+		"setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
+		"setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
+		"nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
+		"fi\0" \
+	"update_nand_firmware="		/* Update only firmware */ \
+		"if tftp ${update_nand_firmware_filename} ; then " \
+		"run update_nand_get_fcb_size ; " \
+		"setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \
+		"setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \
+		"setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \
+		"nand erase ${fcb_sz} ${fw_sz} ; " \
+		"nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \
+		"nand write ${loadaddr} ${fw_off} ${filesize} ; " \
+		"fi\0" \
+	"update_sd_firmware="		/* Update the SD firmware partition */ \
+		"if mmc rescan ; then "	\
+		"if tftp ${update_sd_firmware_filename} ; then " \
+		"setexpr fw_sz ${filesize} / 0x200 ; "	/* SD block size */ \
+		"setexpr fw_sz ${fw_sz} + 1 ; "	\
+		"mmc write ${loadaddr} 0x800 ${fw_sz} ; " \
+		"fi ; "	\
+		"fi\0" \
+	"script=boot.scr\0"	\
+	"uimage=uImage\0" \
+	"console_fsl=ttyAM0\0" \
+	"console_mainline=ttyAMA0\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0"	\
+	"mmcargs=setenv bootargs console=${console_mainline},${baudrate} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0"	\
+	"loadbootscript="  \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; "	\
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; "	\
+		"bootm\0" \
+	"netargs=setenv bootargs console=${console_mainline},${baudrate} " \
 		"root=/dev/nfs " \
-		"ip=dhcp nfsroot=${serverip}:${nfsroot}\0" \
-	"bootcmd_net=echo Booting from net ...; " \
-		"run netargs; " \
-		"dhcp ${uimage}; bootm\0" \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; "	\
+		"dhcp ${uimage}; bootm\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc rescan ${mmcdev}; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
 
 #endif /* __MX28EVK_CONFIG_H__ */
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index 081fbf6..9d9f4a7 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -27,8 +27,6 @@
  /* High Level Configuration Options */
 #define CONFIG_ARM1136		1		/* This is an arm1136 CPU core */
 #define CONFIG_MX31		1		/* in a mx31 */
-#define CONFIG_MX31_HCLK_FREQ	26000000	/* RedBoot says 26MHz */
-#define CONFIG_MX31_CLK32	32768
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 17d3143..b272674 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -35,8 +35,6 @@
 /* High Level Configuration Options */
 #define CONFIG_ARM1136			/* This is an arm1136 CPU core */
 #define CONFIG_MX31			/* in a mx31 */
-#define CONFIG_MX31_HCLK_FREQ	26000000
-#define CONFIG_MX31_CLK32	32768
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index 5816152..69bd654 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -31,7 +31,6 @@
  /* High Level Configuration Options */
 #define CONFIG_ARM1136	/* This is an arm1136 CPU core */
 #define CONFIG_MX35
-#define CONFIG_MX35_HCLK_FREQ	24000000
 
 #define CONFIG_DISPLAY_CPUINFO
 
@@ -111,6 +110,12 @@
 #define CONFIG_NET_RETRY_COUNT	100
 #define CONFIG_CMD_DATE
 
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
 #define CONFIG_BOOTDELAY	3
 
 #define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
@@ -237,6 +242,13 @@
 #define CONFIG_MXC_NAND_HWECC
 #define CONFIG_SYS_NAND_LARGEPAGE
 
+/* mmc driver */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
 /*
  * Default environment and default scripts
  * to update uboot and load kernel
@@ -278,8 +290,8 @@
 	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0"			\
 	"load=tftp ${loadaddr} ${u-boot}\0"				\
 	"uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0"		\
-	"update=protect off ${uboot_addr} +40000;"			\
-		"erase ${uboot_addr} +40000;"				\
+	"update=protect off ${uboot_addr} +80000;"			\
+		"erase ${uboot_addr} +80000;"				\
 		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
 	"upd=if run load;then echo Updating u-boot;if run update;"	\
 		"then echo U-Boot updated;"				\
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index 99b8753..24cda48 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -27,11 +27,11 @@
 
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (Paz00) MOD # "
-#define CONFIG_TEGRA20_BOARD_STRING	"Compal Paz00"
+#define CONFIG_TEGRA_BOARD_STRING	"Compal Paz00"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTA
+#define CONFIG_TEGRA_ENABLE_UARTA
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_PAZ00
@@ -69,6 +69,6 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/plutux.h b/include/configs/plutux.h
index 42291d4..65b42ed 100644
--- a/include/configs/plutux.h
+++ b/include/configs/plutux.h
@@ -35,11 +35,11 @@
 
 /* High-level configuration options */
 #define V_PROMPT			"Tegra20 (Plutux) # "
-#define CONFIG_TEGRA20_BOARD_STRING	"Avionic Design Plutux"
+#define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Plutux"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD	/* UARTD: debug UART */
+#define CONFIG_TEGRA_ENABLE_UARTD	/* UARTD: debug UART */
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 #define CONFIG_BOARD_EARLY_INIT_F
@@ -78,6 +78,6 @@
 	"ext2load mmc 0 0x17000000 /boot/uImage;"	\
 	"bootm"
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/qong.h b/include/configs/qong.h
index 485e1b1..c2bd097 100644
--- a/include/configs/qong.h
+++ b/include/configs/qong.h
@@ -28,8 +28,6 @@
 #define CONFIG_ARM1136			/* This is an arm1136 CPU core */
 #define CONFIG_MX31			/* in a mx31 */
 #define CONFIG_QONG
-#define CONFIG_MX31_HCLK_FREQ	26000000	/* 26MHz */
-#define CONFIG_MX31_CLK32	32768
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h
index 0ebdfb8..f5dc393 100644
--- a/include/configs/sc_sps_1.h
+++ b/include/configs/sc_sps_1.h
@@ -39,8 +39,6 @@
 #include <asm/arch/regs-base.h>
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_ARCH_MISC_INIT
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 8dc6d4b..de19e38 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -27,7 +27,7 @@
 #include <asm/sizes.h>
 
 /* LP0 suspend / resume */
-#define CONFIG_TEGRA20_LP0
+#define CONFIG_TEGRA_LP0
 #define CONFIG_AES
 #define CONFIG_TEGRA_PMU
 #define CONFIG_TPS6586X_POWER
@@ -42,11 +42,11 @@
 
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (SeaBoard) # "
-#define CONFIG_TEGRA20_BOARD_STRING	"NVIDIA Seaboard"
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Seaboard"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD
+#define CONFIG_TEGRA_ENABLE_UARTD
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 /* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */
@@ -96,14 +96,23 @@
 #define CONFIG_CMD_DHCP
 
 /* Enable keyboard */
-#define CONFIG_TEGRA20_KEYBOARD
+#define CONFIG_TEGRA_KEYBOARD
 #define CONFIG_KEYBOARD
 
-#undef TEGRA20_DEVICE_SETTINGS
-#define TEGRA20_DEVICE_SETTINGS	"stdin=serial,tegra-kbc\0" \
-					"stdout=serial\0" \
-					"stderr=serial\0"
+#undef TEGRA_DEVICE_SETTINGS
+#define TEGRA_DEVICE_SETTINGS	"stdin=serial,tegra-kbc\0" \
+				"stdout=serial\0" \
+				"stderr=serial\0"
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+
+/* Max number of NAND devices */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* Somewhat oddly, the NAND base address must be a config option */
+#define CONFIG_SYS_NAND_BASE	NV_PA_NAND_BASE
 #endif /* __CONFIG_H */
diff --git a/include/configs/stamp9g20.h b/include/configs/stamp9g20.h
index a2a0156..a881eef 100644
--- a/include/configs/stamp9g20.h
+++ b/include/configs/stamp9g20.h
@@ -59,6 +59,7 @@
 #define CONFIG_INITRD_TAG		/* pass initrd param to kernel */
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
 #define CONFIG_BOARD_EARLY_INIT_f	/* call board_early_init_f() */
+#define CONFIG_BOARD_POSTCLK_INIT	/* call board_postclk_init() */
 #define CONFIG_DISPLAY_CPUINFO		/* display CPU Info at startup */
 
 /* setting board specific options */
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index 375265d..a13fd93 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -124,6 +124,7 @@
 #define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_USB
+#define CONFIG_CMD_EEPROM
 
 #undef CONFIG_CMD_FLASH		/* only NAND on the SOM */
 #undef CONFIG_CMD_IMLS
@@ -134,6 +135,9 @@
 #define CONFIG_SYS_I2C_SLAVE		1
 #define CONFIG_SYS_I2C_BUS		0
 #define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CONFIG_DRIVER_OMAP34XX_I2C
 
 
@@ -347,4 +351,66 @@
 		"fi;"							\
 		"else echo U-Boot not downloaded..exiting;fi\0"		\
 
+
+/*
+ * this is common code for all TAM3517 boards.
+ * MAC address is stored from manufacturer in
+ * I2C EEPROM
+ */
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+
+/*
+ * The I2C EEPROM on the TAM3517 contains
+ * mac address and production data
+ */
+struct tam3517_module_info {
+	char customer[48];
+	char product[48];
+
+	/*
+	 * bit 0~47  : sequence number
+	 * bit 48~55 : week of year, from 0.
+	 * bit 56~63 : year
+	 */
+	unsigned long long sequence_number;
+
+	/*
+	 * bit 0~7   : revision fixed
+	 * bit 8~15  : revision major
+	 * bit 16~31 : TNxxx
+	 */
+	unsigned int revision;
+	unsigned char eth_addr[4][8];
+	unsigned char _rev[100];
+};
+
+#define TAM3517_READ_MAC_FROM_EEPROM	\
+do {					\
+	struct tam3517_module_info info;\
+	char buf[80], ethname[20];	\
+	int i;				\
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);	\
+	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,		\
+			(void *)&info, sizeof(info)))		\
+		break;						\
+	memset(buf, 0, sizeof(buf));				\
+	for (i = 0 ; i < ARRAY_SIZE(info.eth_addr); i++) {	\
+		sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X",	\
+			info.eth_addr[i][5],			\
+			info.eth_addr[i][4],			\
+			info.eth_addr[i][3],			\
+			info.eth_addr[i][2],			\
+			info.eth_addr[i][1],			\
+			info.eth_addr[i][0]);			\
+								\
+		if (i)						\
+			sprintf(ethname, "eth%daddr", i);	\
+		else						\
+			sprintf(ethname, "ethaddr");		\
+		printf("Setting %s from EEPROM with %s\n", ethname, buf);\
+		setenv(ethname, buf);				\
+	}							\
+} while (0)
+#endif
+
 #endif /* __TAM3517_H */
diff --git a/include/configs/tec.h b/include/configs/tec.h
index 9b3f88d..d5da3c7 100644
--- a/include/configs/tec.h
+++ b/include/configs/tec.h
@@ -35,24 +35,32 @@
 
 /* High-level configuration options */
 #define V_PROMPT			"Tegra20 (TEC) # "
-#define CONFIG_TEGRA20_BOARD_STRING	"Avionic Design Tamonten Evaluation Carrier"
+#define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Tamonten Evaluation Carrier"
 #define CONFIG_SYS_BOARD_ODMDATA	0x2b0d8011
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD	/* UARTD: debug UART */
+#define CONFIG_TEGRA_ENABLE_UARTD	/* UARTD: debug UART */
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 #define CONFIG_BOARD_EARLY_INIT_F
 
-#define CONFIG_ENV_IS_NOWHERE
-
 /* SD/MMC */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
 #define CONFIG_CMD_MMC
 
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		NV_PA_NAND_BASE
+
+/* Environment in NAND, aligned to start of last sector */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		(SZ_512M - SZ_128K) /* 128K sectors */
+
 /* USB host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
@@ -79,6 +87,6 @@
 	"ext2load mmc 0 0x17000000 /boot/uImage;"	\
 	"bootm"
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/tegra20-common-post.h b/include/configs/tegra-common-post.h
index 42f270f..168b64b 100644
--- a/include/configs/tegra20-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -21,8 +21,8 @@
  * MA 02111-1307 USA
  */
 
-#ifndef __TEGRA20_COMMON_POST_H
-#define __TEGRA20_COMMON_POST_H
+#ifndef __TEGRA_COMMON_POST_H
+#define __TEGRA_COMMON_POST_H
 
 #ifdef CONFIG_BOOTCOMMAND
 
@@ -141,7 +141,7 @@
 #endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	TEGRA20_DEVICE_SETTINGS \
+	TEGRA_DEVICE_SETTINGS \
 	"fdt_load=0x01000000\0" \
 	"fdt_high=01100000\0" \
 	BOOTCMDS_COMMON
@@ -174,8 +174,8 @@
 #ifdef CONFIG_GENERIC_MMC
 #undef CONFIG_GENERIC_MMC
 #endif
-#ifdef CONFIG_TEGRA20_MMC
-#undef CONFIG_TEGRA20_MMC
+#ifdef CONFIG_TEGRA_MMC
+#undef CONFIG_TEGRA_MMC
 #endif
 #ifdef CONFIG_CMD_MMC
 #undef CONFIG_CMD_MMC
@@ -211,4 +211,4 @@
 
 #endif /* CONFIG_SPL_BUILD */
 
-#endif /* __TEGRA20_COMMON_POST_H */
+#endif /* __TEGRA_COMMON_POST_H */
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index 4c02f20..098cdb4 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -54,7 +54,7 @@
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
 #define CONFIG_OF_LIBFDT		/* enable passing of devicetree */
 
-#ifdef CONFIG_TEGRA20_LP0
+#ifdef CONFIG_TEGRA_LP0
 #define TEGRA_LP0_ADDR			0x1C406000
 #define TEGRA_LP0_SIZE			0x2000
 #define TEGRA_LP0_VEC \
@@ -132,9 +132,9 @@
 /* Environment information, boards can override if required */
 #define CONFIG_CONSOLE_MUX
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define TEGRA20_DEVICE_SETTINGS	"stdin=serial\0" \
-					"stdout=serial\0" \
-					"stderr=serial\0"
+#define TEGRA_DEVICE_SETTINGS	"stdin=serial\0" \
+				"stdout=serial\0" \
+				"stderr=serial\0"
 
 #define CONFIG_LOADADDR		0x408000	/* def. location for kernel */
 #define CONFIG_BOOTDELAY	2		/* -1 to disable auto boot */
@@ -157,7 +157,7 @@
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
 
-#define CONFIG_SYS_MEMTEST_START	(TEGRA20_SDRC_CS0 + 0x600000)
+#define CONFIG_SYS_MEMTEST_START	(NV_PA_SDRC_CS0 + 0x600000)
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x100000)
 
 #define CONFIG_SYS_LOAD_ADDR		(0xA00800)	/* default */
@@ -169,7 +169,7 @@
  * Physical Memory Map
  */
 #define CONFIG_NR_DRAM_BANKS	1
-#define PHYS_SDRAM_1		TEGRA20_SDRC_CS0
+#define PHYS_SDRAM_1		NV_PA_SDRC_CS0
 #define PHYS_SDRAM_1_SIZE	0x20000000	/* 512M */
 
 #define CONFIG_SYS_TEXT_BASE	0x0010c000
@@ -201,4 +201,6 @@
 #define CONFIG_SPL_GPIO_SUPPORT
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/tegra20/u-boot-spl.lds"
 
+#define CONFIG_SYS_NAND_SELF_INIT
+
 #endif /* __TEGRA20_COMMON_H */
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index b3c5249..a46890c 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h
@@ -34,12 +34,12 @@
 
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (TrimSlice) # "
-#define CONFIG_TEGRA20_BOARD_STRING	"Compulab Trimslice"
+#define CONFIG_TEGRA_BOARD_STRING	"Compulab Trimslice"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTA
-#define CONFIG_TEGRA20_UARTA_GPU
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_TEGRA_UARTA_GPU
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_TRIMSLICE
@@ -94,6 +94,6 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/tt01.h b/include/configs/tt01.h
index cc68a42..f46efa5 100644
--- a/include/configs/tt01.h
+++ b/include/configs/tt01.h
@@ -31,8 +31,6 @@
 /* High Level Configuration Options */
 #define CONFIG_ARM1136
 #define CONFIG_MX31
-#define CONFIG_MX31_HCLK_FREQ	26000000
-#define CONFIG_MX31_CLK32	32768
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index f5e1bf8..7d3a54f 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -34,11 +34,11 @@
 
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (Ventana) # "
-#define CONFIG_TEGRA20_BOARD_STRING	"NVIDIA Ventana"
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Ventana"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD
+#define CONFIG_TEGRA_ENABLE_UARTD
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_VENTANA
@@ -76,6 +76,6 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index 3235718..6c565ba 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -34,12 +34,12 @@
 
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (Whistler) # "
-#define CONFIG_TEGRA20_BOARD_STRING	"NVIDIA Whistler"
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Whistler"
 
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTA
-#define CONFIG_TEGRA20_UARTA_UAA_UAB
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_TEGRA_UARTA_UAA_UAB
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_WHISTLER
@@ -90,6 +90,6 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h
index 072945a..447683a 100644
--- a/include/configs/zmx25.h
+++ b/include/configs/zmx25.h
@@ -28,7 +28,6 @@
 
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
 #define CONFIG_MX25
-#define CONFIG_MX25_CLK32		32768	/* OSC32K frequency */
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_TEXT_BASE		0xA0000000
 
diff --git a/include/fdtdec.h b/include/fdtdec.h
index a8f783f..474a4b9 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -63,6 +63,7 @@ enum fdt_compat_id {
 	COMPAT_NVIDIA_TEGRA20_EMC,	/* Tegra20 memory controller */
 	COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
 	COMPAT_NVIDIA_TEGRA20_KBC,	/* Tegra20 Keyboard */
+	COMPAT_NVIDIA_TEGRA20_NAND,	/* Tegra2 NAND controller */
 
 	COMPAT_COUNT,
 };
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index c06866b..f63e04b 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -390,9 +390,10 @@ struct nand_ecc_ctrl {
  * consecutive order.
  */
 struct nand_buffers {
-	uint8_t	ecccalc[NAND_MAX_OOBSIZE];
-	uint8_t	ecccode[NAND_MAX_OOBSIZE];
-	uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
+	uint8_t	ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+	uint8_t	ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+	uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
+			      ARCH_DMA_MINALIGN)];
 };
 
 /**