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| author | Kumar Gala <galak@kernel.crashing.org> | 2010-03-26 15:14:43 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-03-30 10:48:30 -0500 |
| commit | 33f57bd553edf29dffef5a6c7d76e169c79a6049 (patch) | |
| tree | cae931b06803cf6ff873209a52e5e7dd706beb26 /include | |
| parent | 060f28532b09dd3d2c78423bdd809ac768a27629 (diff) | |
| download | u-boot-imx-33f57bd553edf29dffef5a6c7d76e169c79a6049.zip u-boot-imx-33f57bd553edf29dffef5a6c7d76e169c79a6049.tar.gz u-boot-imx-33f57bd553edf29dffef5a6c7d76e169c79a6049.tar.bz2 | |
85xx: Fix enabling of L1 cache parity on secondary cores
Use the same code between primary and secondary cores to init the
L1 cache. We were not enabling cache parity on the secondary cores.
Also, reworked the L1 cache init code to match the e500mc L2 init code
that first invalidates the cache and locks. Than enables the cache and
makes sure its enabled before continuing.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/processor.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index c6da411..9b3d616 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -485,10 +485,12 @@ #define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */ #define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ +#define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */ #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ #define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ +#define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */ #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ #define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */ |