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authorHolger Brunck <holger.brunck@keymile.com>2011-05-31 02:12:52 +0000
committerU-Boot <uboot@lilith.(none)>2011-05-31 19:46:19 +0200
commit8612b7015400e8b897ed3aeba03baf47cfbf1e94 (patch)
tree52b02980fc960f9402216ad1251b5f8c18619405 /include
parentd3920144e132eb7f30d40d4a5ad13ae85d2e2818 (diff)
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arm/km: update mgcoge3un board support
We change default settings for egiga on mgcoge3un. The reason we need this is that we have the gig port on mgcoge3un connected using a back-to-back pair of PHYs. There are no magnetics and because of that the port has to be run with a fixd configuration and auto-negotiation must be disabled. In the default mode the egiga driver uses autoneg to determine port speed - which defaults to 1G (we need 100M full duplex). Add wait for the GPIO line connected to mgcoge3ne before starting mgcoge3un. A board specific ethernet present function was added, because on this board ethernet is always present. The BOCO FPGA access was enhanced and changed to use register definitions. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Acked-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Detlev Zundel <dzu@denx.de> cc: Prafulla Wadaskar <prafulla@marvell.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/mgcoge3un.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/include/configs/mgcoge3un.h b/include/configs/mgcoge3un.h
index 22d1961..6d56d7d 100644
--- a/include/configs/mgcoge3un.h
+++ b/include/configs/mgcoge3un.h
@@ -50,4 +50,29 @@
/* we use a new RAM type on mgcoge3un board */
#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
+/*
+ * mgcoge3un has a fixed link to the marvell switch
+ * with 100MB full duplex and autoneg off, for this
+ * reason we have to change the default settings
+ */
+#define PORT_SERIAL_CONTROL_VALUE ( \
+ MVGBE_FORCE_LINK_PASS | \
+ MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
+ MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
+ MVGBE_ADV_NO_FLOW_CTRL | \
+ MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
+ MVGBE_FORCE_BP_MODE_NO_JAM | \
+ (1 << 9) /* Reserved bit has to be 1 */ | \
+ MVGBE_DO_NOT_FORCE_LINK_FAIL | \
+ MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
+ MVGBE_DTE_ADV_0 | \
+ MVGBE_MIIPHY_MAC_MODE | \
+ MVGBE_AUTO_NEG_NO_CHANGE | \
+ MVGBE_MAX_RX_PACKET_1552BYTE | \
+ MVGBE_CLR_EXT_LOOPBACK | \
+ MVGBE_SET_FULL_DUPLEX_MODE | \
+ MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
+ MVGBE_SET_GMII_SPEED_TO_10_100 |\
+ MVGBE_SET_MII_SPEED_TO_100)
+
#endif /* _CONFIG_MGCOGE3UN_H */