Merge branch 'next' of ../next

62 files changed, 1280 insertions, 134 deletions

diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h
index 646fc77..c91e30c 100644
--- a/include/asm-arm/arch-davinci/emif_defs.h
+++ b/include/asm-arm/arch-davinci/emif_defs.h
@@ -55,6 +55,16 @@ typedef struct {
 	dv_reg		NANDF2ECC;
 	dv_reg		NANDF3ECC;
 	dv_reg		NANDF4ECC;
+	u_int8_t	RSVD2[60];
+	dv_reg		NAND4BITECCLOAD;
+	dv_reg		NAND4BITECC1;
+	dv_reg		NAND4BITECC2;
+	dv_reg		NAND4BITECC3;
+	dv_reg		NAND4BITECC4;
+	dv_reg		NANDERRADD1;
+	dv_reg		NANDERRADD2;
+	dv_reg		NANDERRVAL1;
+	dv_reg		NANDERRVAL2;
 } emif_registers;
 
 typedef emif_registers	*emifregs;
diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h
index 50ea087..531f420 100644
--- a/include/asm-m68k/io.h
+++ b/include/asm-m68k/io.h
@@ -28,6 +28,10 @@
 
 #include <asm/byteorder.h>
 
+#ifndef _IO_BASE
+#define _IO_BASE 0
+#endif
+
 #define __raw_readb(addr) (*(volatile u8 *)(addr))
 #define __raw_readw(addr) (*(volatile u16 *)(addr))
 #define __raw_readl(addr) (*(volatile u32 *)(addr))
diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h
index c9ba805..5670d06 100644
--- a/include/asm-ppc/config.h
+++ b/include/asm-ppc/config.h
@@ -38,4 +38,11 @@
 #endif
 #endif
 
+#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \
+	defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
+#define CONFIG_MAX_CPUS        2
+#else
+#define CONFIG_MAX_CPUS        1
+#endif
+
 #endif /* _ASM_CONFIG_H_ */
diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h
index 624ca56..f625d19 100644
--- a/include/asm-ppc/fsl_pci.h
+++ b/include/asm-ppc/fsl_pci.h
@@ -20,8 +20,7 @@
 #ifndef __FSL_PCI_H_
 #define __FSL_PCI_H_
 
-int fsl_pci_setup_inbound_windows(struct pci_region *r);
-void fsl_pci_init(struct pci_controller *hose);
+void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data);
 void fsl_pci_config_unlock(struct pci_controller *hose);
 void ft_fsl_pci_setup(void *blob, const char *pci_alias,
 			struct pci_controller *hose);
@@ -155,4 +154,30 @@ typedef struct ccsr_pci {
 	char	res24[252];
 } ccsr_fsl_pci_t;
 
+struct fsl_pci_info {
+	unsigned long	regs;
+	pci_addr_t	mem_bus;
+	phys_size_t	mem_phys;
+	pci_size_t	mem_size;
+	pci_addr_t	io_bus;
+	phys_size_t	io_phys;
+	pci_size_t	io_size;
+	int		pci_num;
+};
+
+int fsl_pci_init_port(struct fsl_pci_info *pci_info,
+				struct pci_controller *hose, int busno);
+
+#define SET_STD_PCIE_INFO(x, num) \
+{			\
+	x.regs = CONFIG_SYS_PCIE##num##_ADDR;	\
+	x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
+	x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
+	x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
+	x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
+	x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
+	x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
+	x.pci_num = num; \
+}
+
 #endif
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 244c161..db4b1ea 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -86,11 +86,12 @@ typedef	struct	global_data {
 	u32  mem_sec_clk;
 #endif /* CONFIG_MPC8360 */
 #endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8536)
+#if defined(CONFIG_FSL_ESDHC)
 	u32 sdhc_clk;
 #endif
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
 	u32 lbc_clk;
+	void *cpu;
 #endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
 #if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
 	u32 i2c1_clk;
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 0efef05..375d804 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -411,6 +411,11 @@ typedef struct ccsr_l2cache {
 	char	res15[420];
 } ccsr_l2cache_t;
 
+#define MPC85xx_L2CTL_L2E			0x80000000
+#define MPC85xx_L2CTL_L2SRAM_ENTIRE		0x00010000
+#define MPC85xx_L2ERRDIS_MBECC			0x00000008
+#define MPC85xx_L2ERRDIS_SBECC			0x00000004
+
 /*
  * DMA Registers(0x2_1000-0x2_2000)
  */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 2841104..dcaf8c0 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -1009,6 +1009,12 @@
 #define SVR_8569_E	0x808800
 #define SVR_8572	0x80E000
 #define SVR_8572_E	0x80E800
+#define SVR_P1011	0x80E500
+#define SVR_P1011_E	0x80ED00
+#define SVR_P1020	0x80E400
+#define SVR_P1020_E	0x80EC00
+#define SVR_P2010	0x80E300
+#define SVR_P2010_E	0x80EB00
 #define SVR_P2020	0x80E200
 #define SVR_P2020_E	0x80EA00
 
@@ -1065,13 +1071,14 @@ n:
 struct cpu_type {
 	char name[15];
 	u32 soc_ver;
+	u32 num_cores;
 };
 
 struct cpu_type *identify_cpu(u32 ver);
 
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
-#define CPU_TYPE_ENTRY(n, v) \
-	{ .name = #n, .soc_ver = SVR_##v, }
+#define CPU_TYPE_ENTRY(n, v, nc) \
+	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), }
 #else
 #if defined(CONFIG_MPC83xx)
 #define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
diff --git a/include/bcd.h b/include/bcd.h
index c545308..af4aa9c 100644
--- a/include/bcd.h
+++ b/include/bcd.h
@@ -3,18 +3,23 @@
  * at your option.
  */
 
-/* macros to translate to/from binary and binary-coded decimal (frequently
- * found in RTC chips).
+/* inline functions to translate to/from binary and binary-coded decimal
+ * (frequently found in RTC chips).
  */
 
 #ifndef _BCD_H
 #define _BCD_H
 
-#define BCD2BIN(val)	(((val) & 0x0f) + ((val)>>4)*10)
-#define BIN2BCD(val)	((((val)/10)<<4) + (val)%10)
+#include <linux/types.h>
 
-/* backwards compat */
-#define BCD_TO_BIN(val) ((val)=BCD2BIN(val))
-#define BIN_TO_BCD(val) ((val)=BIN2BCD(val))
+static inline unsigned int bcd2bin(u8 val)
+{
+	return ((val) & 0x0f) + ((val) >> 4) * 10;
+}
+
+static inline u8 bin2bcd (unsigned int val)
+{
+	return (((val / 10) << 4) | (val % 10));
+}
 
 #endif /* _BCD_H */
diff --git a/include/common.h b/include/common.h
index a6922fd..35f12c0 100644
--- a/include/common.h
+++ b/include/common.h
@@ -441,6 +441,8 @@ void		ppcDWstore(unsigned int *addr, unsigned int *value);
 #endif
 
 /* $(CPU)/cpu.c */
+int	cpu_numcores  (void);
+int	probecpu      (void);
 int	checkcpu      (void);
 int	checkicache   (void);
 int	checkdcache   (void);
diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h
index b8afc17..2d4fc77 100644
--- a/include/configs/ADNPESC1.h
+++ b/include/configs/ADNPESC1.h
@@ -426,15 +426,17 @@
 	/********************************************/
 	/* !!! CS8900 is __not__ tested on NIOS !!! */
 	/********************************************/
-#define	CONFIG_DRIVER_CS8900			/* Using CS8900		*/
-#define	CS8900_BASE		(CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS)
+#define CONFIG_NET_MULTI
+#define	CONFIG_CS8900		/* Using CS8900		*/
+#define	CONFIG_CS8900_BASE	(CONFIG_SYS_NIOS_CPU_LAN0_BASE + \
+				CONFIG_SYS_NIOS_CPU_LAN0_OFFS)
 
 #if	(CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32)
-#undef	CS8900_BUS16
-#define	CS8900_BUS32		1
+#undef	CONFIG_CS8900_BUS16
+#define	CONFIG_CS8900_BUS32
 #else	/* no */
-#define	CS8900_BUS16		1
-#undef	CS8900_BUS32
+#define	CONFIG_CS8900_BUS16
+#undef	CONFIG_CS8900_BUS32
 #endif
 
 #else
diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
index 7ee05e5..91369a7 100644
--- a/include/configs/ATUM8548.h
+++ b/include/configs/ATUM8548.h
@@ -67,7 +67,6 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_CLEAR_LAW0		/* Clear LAW0 in cpu_init_r */
 
 /*
  * Only possible on E500 Version 2 or newer cores.
diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h
index 45ff2f7..cdc488b 100644
--- a/include/configs/DK1C20.h
+++ b/include/configs/DK1C20.h
@@ -232,15 +232,17 @@
 	/********************************************/
 	/* !!! CS8900 is __not__ tested on NIOS !!! */
 	/********************************************/
-#define	CONFIG_DRIVER_CS8900			/* Using CS8900		*/
-#define	CS8900_BASE		(CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS)
+#define CONFIG_NET_MULTI
+#define	CONFIG_CS8900		/* Using CS8900		*/
+#define	CONFIG_CS8900_BASE	(CONFIG_SYS_NIOS_CPU_LAN0_BASE + \
+				CONFIG_SYS_NIOS_CPU_LAN0_OFFS)
 
 #if	(CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32)
-#undef	CS8900_BUS16
-#define	CS8900_BUS32		1
+#undef	CONFIG_CS8900_BUS16
+#define	CONFIG_CS8900_BUS32
 #else	/* no */
-#define	CS8900_BUS16		1
-#undef	CS8900_BUS32
+#define	CONFIG_CS8900_BUS16
+#undef	CONFIG_CS8900_BUS32
 #endif
 
 #else
diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h
index ae567a3..6e78861 100644
--- a/include/configs/DK1S10.h
+++ b/include/configs/DK1S10.h
@@ -249,15 +249,17 @@
 	/********************************************/
 	/* !!! CS8900 is __not__ tested on NIOS !!! */
 	/********************************************/
-#define	CONFIG_DRIVER_CS8900			/* Using CS8900		*/
-#define	CS8900_BASE		(CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS)
+#define CONFIG_NET_MULTI
+#define	CONFIG_CS8900		/* Using CS8900		*/
+#define	CONFIG_CS8900_BASE	(CONFIG_SYS_NIOS_CPU_LAN0_BASE + \
+				CONFIG_SYS_NIOS_CPU_LAN0_OFFS)
 
 #if	(CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32)
-#undef	CS8900_BUS16
-#define	CS8900_BUS32		1
+#undef	CONFIG_CS8900_BUS16
+#define	CONFIG_CS8900_BUS32
 #else	/* no */
-#define	CS8900_BUS16		1
-#undef	CS8900_BUS32
+#define	CONFIG_CS8900_BUS16
+#undef	CONFIG_CS8900_BUS32
 #endif
 
 #else
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index e7db0cc..1801d9d 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -255,7 +255,6 @@
 #	define CONFIG_ENV_IS_IN_FLASH	1
 #endif
 #define CONFIG_ENV_OVERWRITE		1
-#undef CONFIG_ENV_IS_EMBEDDED
 
 /*-----------------------------------------------------------------------
  * FLASH organization
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index 6b26c0b..2b816ce 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -222,7 +222,6 @@
  * Environment is embedded in u-boot in the second sector of the flash
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_IS_EMBEDDED	1
 #ifdef NORFLASH_PS32BIT
 #	define CONFIG_ENV_OFFSET		(0x8000)
 #	define CONFIG_ENV_SIZE		0x4000
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index fc73d64..f824158 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -55,7 +55,6 @@
 #define CONFIG_ENV_OFFSET		0x4000
 #define CONFIG_ENV_SECT_SIZE	0x2000
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_IS_EMBEDDED	1
 #else
 #define CONFIG_ENV_ADDR		0xffe04000
 #define CONFIG_ENV_SECT_SIZE	0x2000
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 210bb2d..b380159 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -55,7 +55,6 @@
 #define CONFIG_ENV_OFFSET		0x4000
 #define CONFIG_ENV_SECT_SIZE	0x2000
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_IS_EMBEDDED	1
 #else
 #define CONFIG_ENV_ADDR		0xffe04000
 #define CONFIG_ENV_SECT_SIZE	0x2000
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index a2d17c3..8180c05 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -231,7 +231,6 @@
 #define CONFIG_ENV_OFFSET		0x4000
 #define CONFIG_ENV_SECT_SIZE	0x2000
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_IS_EMBEDDED	1
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index 98d800f..8652a80 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -231,7 +231,6 @@
 #define CONFIG_ENV_OFFSET		0x4000
 #define CONFIG_ENV_SECT_SIZE	0x2000
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_IS_EMBEDDED	1
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index fa444c3..a5acfd2 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -277,7 +277,6 @@
 #	define CONFIG_ENV_SECT_SIZE	0x8000
 #endif
 #undef CONFIG_ENV_OVERWRITE
-#undef CONFIG_ENV_IS_EMBEDDED
 
 /* FLASH organization */
 #define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 14d98d6..7737284 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -332,7 +332,6 @@
 #	define CONFIG_ENV_IS_IN_FLASH	1
 #endif
 #undef CONFIG_ENV_OVERWRITE
-#undef CONFIG_ENV_IS_EMBEDDED
 
 /*-----------------------------------------------------------------------
  * FLASH organization
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index e48de15..4534002 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -280,7 +280,6 @@
 #define CONFIG_ENV_OFFSET		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x2000
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_IS_EMBEDDED	1
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index 28bf0ad..971cb67 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -266,7 +266,6 @@
 #define CONFIG_ENV_OFFSET		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x2000
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_IS_EMBEDDED	1
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 9d2b860..4746e2e 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -27,6 +27,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#ifdef CONFIG_MPC8536DS_36BIT
+#define CONFIG_PHYS_64BIT	1
+#endif
+
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
@@ -77,8 +81,13 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 
 #define CONFIG_ENABLE_36BIT_PHYS	1
 
-#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x7fffffff
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00010000	/* skip exception vectors */
+#define CONFIG_SYS_MEMTEST_END		0x1f000000      /* skip u-boot at top of RAM  */
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 
 /*
@@ -87,7 +96,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  */
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS		0xfffe00000ull	/* physical addr of CCSRBAR */
+#else
 #define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#endif
 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
 #define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)
@@ -96,6 +109,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE3_ADDR		(CONFIG_SYS_CCSRBAR+0xb000)
 
 /* DDR Setup */
+#define CONFIG_VERY_BIG_RAM
 #define CONFIG_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
@@ -170,7 +184,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Local Bus Definitions
  */
 #define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
+#else
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
 
 #define CONFIG_SYS_BR0_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
 #define CONFIG_SYS_OR0_PRELIM	0xf8000ff7
@@ -178,7 +196,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 #define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 
@@ -199,7 +217,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 
 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
 #define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
+#ifdef CONFIG_PHYS_64BIT
+#define PIXIS_BASE_PHYS	0xfffdf0000ull
+#else
 #define PIXIS_BASE_PHYS	PIXIS_BASE
+#endif
 
 #define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 #define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
@@ -254,8 +276,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
 
-#define CONFIG_SYS_NAND_BASE           0xffa00000
-#define CONFIG_SYS_NAND_BASE_PHYS      CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
 				CONFIG_SYS_NAND_BASE + 0x40000, \
 				CONFIG_SYS_NAND_BASE + 0x80000, \
@@ -368,42 +394,78 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  */
 
 #define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_MEM_BUS		0xf0000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0xc00000000ull
+#else
 #define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#endif
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI1_IO_VIRT	0xffc00000
-#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS	0xffc00000
-#define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCI1_IO_VIRT		0xffc00000
+#define CONFIG_SYS_PCI1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_IO_PHYS		0xfffc00000ull
+#else
+#define CONFIG_SYS_PCI1_IO_PHYS		0xffc00000
+#endif
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00010000	/* 64k */
 
 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x90000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xf8000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc10000000ull
+#else
 #define CONFIG_SYS_PCIE1_MEM_BUS	0x90000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x90000000
+#endif
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x08000000	/* 128M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc10000
-#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc10000ull
+#else
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc10000
+#endif
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0x98000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xf8000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc18000000ull
+#else
 #define CONFIG_SYS_PCIE2_MEM_BUS	0x98000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0x98000000
+#endif
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x08000000	/* 128M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc20000
-#define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc20000ull
+#else
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc20000
+#endif
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
+#else
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xa0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xa0000000
+#endif
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xffc30000
-#define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc30000ull
+#else
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xffc30000
+#endif
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 
 #if defined(CONFIG_PCI)
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index bebb9e9..e69ba90 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -69,7 +69,6 @@ extern unsigned long get_clock_freq(void);
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_CLEAR_LAW0		/* Clear LAW0 in cpu_init_r */
 
 /*
  * Only possible on E500 Version 2 or newer cores.
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index d0933ba..55c1f29 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -34,7 +34,6 @@
 #define CONFIG_MPC8572		1
 #define CONFIG_MPC8572DS	1
 #define CONFIG_MP		1	/* support multiple processors */
-#define CONFIG_NUM_CPUS		2	/* Number of CPUs in the system */
 
 #define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index a3b5c7c..7619328 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -17,7 +17,6 @@
 #define CONFIG_MPC86xx		1	/* MPC86xx */
 #define CONFIG_MPC8610		1	/* MPC8610 specific */
 #define CONFIG_MPC8610HPCD	1	/* MPC8610HPCD board specific */
-#define CONFIG_NUM_CPUS		1	/* Number of CPUs in the system */
 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
 
 #define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
@@ -81,6 +80,7 @@
 
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
+#define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR_PHYS_LOW
 
 #define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)
 #define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR+0xa000)
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index bf2e359..b0ae25c 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -37,7 +37,6 @@
 #define CONFIG_MPC8641		1	/* MPC8641 specific */
 #define CONFIG_MPC8641HPCN	1	/* MPC8641HPCN board specific */
 #define CONFIG_MP		1	/* support multiple processors */
-#define CONFIG_NUM_CPUS		2	/* Number of CPUs in the system */
 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
 /*#define CONFIG_PHYS_64BIT	1*/	/* Place devices in 36-bit space */
 #define CONFIG_ADDR_MAP		1	/* Use addr map */
diff --git a/include/configs/OXC.h b/include/configs/OXC.h
index 104c23f..74c51f4 100644
--- a/include/configs/OXC.h
+++ b/include/configs/OXC.h
@@ -196,7 +196,6 @@
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		0xFFF30000	/* Offset of Environment Sector	*/
 #define CONFIG_ENV_SIZE		0x00010000	/* Total Size of Environment Sector */
-#define	CONFIG_ENV_IS_EMBEDDED	1		/* short-cut compile-time test	*/
 #define CONFIG_ENV_OVERWRITE    1		/* Allow modifying the environment */
 
 /*
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
new file mode 100644
index 0000000..6d44d6c
--- /dev/null
+++ b/include/configs/P1_P2_RDB.h
@@ -0,0 +1,561 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * P1 P2 RDB board configuration file
+ * This file is intended to address a set of Low End and Ultra Low End
+ * Freescale SOCs of QorIQ series(RDB platforms).
+ * Currently only P2020RDB
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/P1020/P2020,etc*/
+#define CONFIG_FSL_ELBC		1	/* Enable eLBC Support */
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_DDR_CLK_FREQ	66666666 /* DDRCLK on P1_P2 RDB */
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
+
+#if defined(CONFIG_P2020) || defined(CONFIG_P1020)
+#define CONFIG_MP
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
+
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x1fffffff
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of */
+							/* CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses */
+							/* CONFIG_SYS_IMMR */
+#define CONFIG_SYS_PCIE2_ADDR		(CONFIG_SYS_CCSRBAR+0x9000)
+#define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR+0xa000)
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#undef CONFIG_DDR_DLL
+
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_SDRAM_SIZE	1024 	/* DDR size on P1_P2 RDBs */
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+
+#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
+#define CONFIG_SYS_DDR_SBE		0x00FF0000
+
+#define CONFIG_SYS_DDR_TLB_START 9
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x3fff_ffff	DDR			1G cacheablen
+ * 0xa000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
+ * 0xffc2_0000	0xffc5_ffff	PCI IO range		256K non-cacheable
+ *
+ * Localbus cacheable (TBD)
+ * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
+ *
+ * Localbus non-cacheable
+ * 0xef00_0000	0xefff_ffff	FLASH			16M non-cacheable
+ * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
+ * 0xffb0_0000	0xffbf_ffff	VSC7385 switch		1M non-cacheable
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xef000000	/* start of FLASH 16M */
+
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_FLASH_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+					BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM		0xff000ff7
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR      0xffd00000	/* stack in RAM */
+#define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END \
+						- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon*/
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc*/
+
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND			1
+#define CONFIG_NAND_FSL_ELBC		1
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
+
+/* NAND flash config */
+#define CONFIG_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE_PHYS \
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8	/* Port Size = 8 bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+
+#define CONFIG_NAND_OR_PRELIM	(0xFFF80000		/* length 32K */ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
+
+#define CONFIG_SYS_VSC7385_BASE	0xffb00000
+
+#define CONFIG_SYS_VSC7385_BASE_PHYS	CONFIG_SYS_VSC7385_BASE
+
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+				OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
+				OR_GPCM_EHTR | OR_GPCM_EAD)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+//#define CONFIG_CONS_INDEX	2
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SERIAL_MULTI	1 /* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
+
+/* new uImage format support */
+#define CONFIG_FIT		1
+#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{{0,0x29}}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM	1
+
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR                0x68
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc20000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc30000
+#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc30000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#undef CONFIG_RTL8139
+
+#ifdef CONFIG_RTL8139
+/* This macro is used by RTL8139 but not defined in PPC architecture */
+#define KSEG1ADDR(x)		(x)
+#define _IO_BASE	0x00000000
+#endif
+
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+
+#endif	/* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI	1
+#endif
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		0
+#define TSEC3_PHY_ADDR		1
+
+#define CONFIG_VSC7385_ENET
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+/* The size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+#endif
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR		0xfff80000
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#endif
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+#define CONFIG_MMC	1
+
+#ifdef CONFIG_MMC
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FSL_ESDHC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#ifdef CONFIG_P2020
+#define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
+#endif
+#endif
+
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#endif
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+						/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)/* Initial Memory map for Linux*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#endif
+
+#define CONFIG_HOSTNAME		P2020RDB
+#define CONFIG_ROOTPATH		/opt/nfsroot
+#define CONFIG_BOOTFILE		uImage
+#define CONFIG_UBOOTPATH	u-boot.bin/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"netdev=eth0\0"						\
+	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
+	"loadaddr=1000000\0"			\
+	"bootfile=uImage\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot; "			\
+		"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
+		"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
+		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
+		"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
+		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
+	"consoledev=ttyS0\0"				\
+	"ramdiskaddr=2000000\0"			\
+	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
+	"fdtaddr=c00000\0"				\
+	"fdtfile=p2020rdb.dtb\0"		\
+	"bdev=sda1\0"	\
+	"jffs2nor=mtdblock3\0"	\
+	"norbootaddr=ef080000\0"	\
+	"norfdtaddr=ef040000\0"	\
+	"jffs2nand=mtdblock9\0"	\
+	"nandbootaddr=100000\0"	\
+	"nandfdtaddr=80000\0"		\
+	"nandimgsize=400000\0"		\
+	"nandfdtsize=80000\0"		\
+	"usb_phy_type=ulpi\0"		\
+	"vscfw_addr=ef000000\0"	\
+	"othbootargs=ramdisk_size=600000\0" \
+	"usbfatboot=setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"usb start;"			\
+	"fatload usb 0:2 $loadaddr $bootfile;"		\
+	"fatload usb 0:2 $fdtaddr $fdtfile;"	\
+	"fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
+	"usbext2boot=setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"usb start;"			\
+	"ext2load usb 0:4 $loadaddr $bootfile;"		\
+	"ext2load usb 0:4 $fdtaddr $fdtfile;"	\
+	"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"	\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
+	"norboot=setenv bootargs root=/dev/$jffs2nor rw "	\
+	"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
+	"bootm $norbootaddr - $norfdtaddr\0"		\
+	"nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"nand read 2000000 $nandbootaddr $nandimgsize;"	\
+	"nand read 3000000 $nandfdtaddr $nandfdtsize;"	\
+	"bootm 2000000 - 3000000;\0"
+
+#define CONFIG_NFSBOOTCOMMAND		\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_HDBOOT			\
+	"setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"usb start;"			\
+	"ext2load usb 0:1 $loadaddr /boot/$bootfile;"		\
+	"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND		\
+	"setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"tftp $ramdiskaddr $ramdiskfile;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index ad24e0c..46af7b9 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -34,7 +34,6 @@
 #define CONFIG_P2020		1
 #define CONFIG_P2020DS		1
 #define CONFIG_MP		1	/* support multiple processors */
-#define CONFIG_NUM_CPUS		2	/* Number of CPUs in the system */
 
 #define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 6051480..618b7f0 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -108,9 +108,10 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_DRIVER_CS8900	1		/* we have a CS8900 on-board */
-#define CS8900_BASE		0x20000300
-#define CS8900_BUS16		1		/* the Linux driver does accesses as shorts */
+#define CONFIG_NET_MULTI
+#define CONFIG_CS8900		/* we have a CS8900 on-board */
+#define CONFIG_CS8900_BASE	0x20000300
+#define CONFIG_CS8900_BUS16	/* the Linux driver does accesses as shorts */
 
 #define CONFIG_DRIVER_S3C24X0_I2C	1	/* we use the buildin I2C controller */
 
diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h
index 8be9fa0..242466a 100644
--- a/include/configs/XPEDITE5170.h
+++ b/include/configs/XPEDITE5170.h
@@ -34,7 +34,6 @@
 #define CONFIG_MPC8641		1	/* MPC8641 specific */
 #define CONFIG_XPEDITE5140	1	/* MPC8641HPCN board specific */
 #define CONFIG_SYS_BOARD_NAME	"XPedite5170"
-#define CONFIG_NUM_CPUS		1	/* Number of CPUs in the system */
 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
 #define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
 #define CONFIG_RELOC_FIXUP_WORKS	/* Fully relocate to SDRAM */
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index acb62ad..3c58ebe 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -36,7 +36,6 @@
 #define CONFIG_MPC8572		1
 #define CONFIG_XPEDITE5370	1
 #define CONFIG_SYS_BOARD_NAME	"XPedite5370"
-#define CONFIG_NUM_CPUS		2	/* 2 Cores */
 #define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
 #define CONFIG_RELOC_FIXUP_WORKS	/* Fully relocate to SDRAM */
 
diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h
index f7eec27..49ea3a1 100644
--- a/include/configs/armadillo.h
+++ b/include/configs/armadillo.h
@@ -56,10 +56,11 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
-#define CS8900_BASE		0x20000300 /* armadillo board */
-#define CS8900_BUS16		1
-#undef  CS8900_BUS32
+#define CONFIG_NET_MULTI
+#define CONFIG_CS8900		/* we have a CS8900 on-board */
+#define CONFIG_CS8900_BASE	0x20000300 /* armadillo board */
+#define CONFIG_CS8900_BUS16
+#undef  CONFIG_CS8900_BUS32
 
 /*
  * select serial console configuration
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index fb32f3f..1c3ea23 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -127,7 +127,6 @@
 #define CONFIG_ENV_OFFSET		0x4000
 #define CONFIG_ENV_SECT_SIZE	0x2000
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_IS_EMBEDDED	1
 #else
 #define CONFIG_ENV_ADDR		0xffe04000
 #define CONFIG_ENV_SECT_SIZE	0x2000
diff --git a/include/configs/csb226.h b/include/configs/csb226.h
index 12bab47..0661d65 100644
--- a/include/configs/csb226.h
+++ b/include/configs/csb226.h
@@ -150,9 +150,10 @@
 /*
  * Network chip
  */
-#define CONFIG_DRIVER_CS8900	1
-#define CS8900_BUS32		1
-#define CS8900_BASE		0x08000000
+#define CONFIG_NET_MULTI
+#define CONFIG_CS8900
+#define CONFIG_CS8900_BUS32
+#define CONFIG_CS8900_BASE	0x08000000
 
 /*
  * Stack sizes
diff --git a/include/configs/ep7312.h b/include/configs/ep7312.h
index 630fff3..e151faa 100644
--- a/include/configs/ep7312.h
+++ b/include/configs/ep7312.h
@@ -47,10 +47,11 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
-#define CS8900_BASE		0x20000000
-#define CS8900_BUS16		1
-#undef  CS8900_BUS32
+#define CONFIG_NET_MULTI
+#define CONFIG_CS8900		/* we have a CS8900 on-board */
+#define CONFIG_CS8900_BASE	0x20000000
+#define CONFIG_CS8900_BUS16
+#undef  CONFIG_CS8900_BUS32
 
 /*
  * select serial console configuration
diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h
new file mode 100644
index 0000000..8d530d8
--- /dev/null
+++ b/include/configs/galaxy5200.h
@@ -0,0 +1,428 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2006
+ * Eric Schumann, Phytec Messatechnik GmbH
+ *
+ * (C) Copyright 2009
+ * Jon Smirl <jonsmirl@gmail.com>
+ *
+ * (C) Copyright 2009
+ * Eric Millbrandt, DEKA Research and Development Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_BOARDINFO	 "galaxy5200"
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
+#define CONFIG_SYS_MPC5XXX_CLKIN 33333333	/* ... running at 33.333333MHz */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot */
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	4	/* console is on PSC4 -> */
+					/* define gps port conf. */
+					/* register later on to  */
+					/* enable UART function! */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_FAT
+
+#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
+
+#if (TEXT_BASE == 0xFE000000)		/* Boot low */
+#define CONFIG_SYS_LOWBOOT 1
+#endif
+/* RAMBOOT will be defined automatically in memory section */
+
+#define MTDIDS_DEFAULT		"nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=physmap-flash.0:256k(ubootl)," \
+	"1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow stopping of boot process */
+					/* even with bootdelay=0 */
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Welcome to U-Boot;"\
+	"echo"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK	/* define for 133MHz speed */
+#define CONFIG_SYS_XLB_PIPELINING	1
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1		/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE 2		/* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_SPEED 100000	/* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM CAT24WC32 configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52	/* 1010100x */
+#define CONFIG_SYS_I2C_FACT_ADDR	0x52	/* EEPROM CAT24WC32 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address */
+#define CONFIG_SYS_EEPROM_SIZE		4096
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+
+/*
+ * Flash configuration
+ */
+
+#define CONFIG_SYS_FLASH_BASE		0xfe000000
+/*
+ * The flash size is autoconfigured, but cpu/mpc5xxx/cpu_init.c needs this
+ * variable defined
+ */
+#define CONFIG_SYS_FLASH_SIZE		0x02000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_FLASH_CFI 1		/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_MAX_FLASH_SECT 259	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1	/* max num of flash banks */
+					/* (= chip selects) */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * Use hardware protection. This seems required, as the BDI uses hardware
+ * protection. Without this, U-Boot can't work with this sectors as its
+ * protection is software only by default.
+ */
+#define CONFIG_SYS_FLASH_PROTECTION	1
+
+/*
+ * Environment settings
+ */
+
+#define CONFIG_ENV_IS_IN_EEPROM	1
+#define CONFIG_ENV_OFFSET	0x00	/* environment starts at the */
+					/* beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		CONFIG_SYS_EEPROM_SIZE
+
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * SDRAM configuration
+ */
+#define SDRAM_DDR	1
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x71500F00
+#define SDRAM_CONFIG1	0x73711930
+#define SDRAM_CONFIG2	0x47770000
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR	0xF0000000	/* MBAR has to be switched by other */
+					/* bootloader or debugger config */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR		0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+
+/* End of used area in SPRAM */
+#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE
+
+/* Size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
+						CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#	define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN (192 << 10)	/* Reserve 192 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN (128 << 10)	/* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)	/* Initial Memory map for Linux */
+
+/* Chip Select configuration for NAND flash */
+#define CONFIG_SYS_CS1_START		0x20000000
+#define CONFIG_SYS_CS1_SIZE		0x90000
+#define CONFIG_SYS_CS1_CFG		0x0002d900
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC		1
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR			0x01
+#define CONFIG_NO_AUTOLOAD		1
+
+/*
+ * GPIO configuration
+ *
+ * GPS port configuration
+ *
+ * [29:31] = 01x
+ * AC97 on PSC1
+ * PSC1_0 -> AC97 SDATA out
+ * PSC1_1 -> AC97 SDTA in
+ * PSC1_2 -> AC97 SYNC out
+ * PSC1_3 -> AC97 bitclock out
+ * PSC1_4 -> AC97 reset out
+ *
+ * [28] = Reserved
+ *
+ * [25:27] = 110
+ * SPI on PSC2
+ * PSC2_0 -> MOSI
+ * PSC2_1 -> MISO
+ * PSC2_2 -> n/a
+ * PSC2_3 -> CLK
+ * PSC2_4 -> SS
+ *
+ * [24] = Reserved
+ *
+ * [20:23] = 0001
+ * USB on PSC3
+ * PSC3_0 -> USB_OE OE out
+ * PSC3_1 -> USB_TXN Tx- out
+ * PSC3_2 -> USB_TXP Tx+ out
+ * PSC3_3 -> USB_TXD
+ * PSC3_4 -> USB_RXP Rx+ in
+ * PSC3_5 -> USB_RXN Rx- in
+ * PSC3_6 -> USB_PWR PortPower out
+ * PSC3_7 -> USB_SPEED speed out
+ * PSC3_8 -> USB_SUSPEND suspend
+ * PSC3_9 -> USB_OVRCURNT overcurrent in
+ *
+ * [18:19] = 10
+ * Two UARTs
+ *
+ * [17] = 0
+ * USB differential mode
+ *
+ * [16] = 1
+ * PCI disabled
+ *
+ * [12:15] = 0101
+ * Ethernet 100Mbit with MD
+ * ETH_0 -> ETH Txen
+ * ETH_1 -> ETH TxD0
+ * ETH_2 -> ETH TxD1
+ * ETH_3 -> ETH TxD2
+ * ETH_4 -> ETH TxD3
+ * ETH_5 -> ETH Txerr
+ * ETH_6 -> ETH MDC
+ * ETH_7 -> ETH MDIO
+ * ETH_8 -> ETH RxDv
+ * ETH_9 -> ETH RxCLK
+ * ETH_10 -> ETH Collision
+ * ETH_11 -> ETH TxD
+ * ETH_12 -> ETH RxD0
+ * ETH_13 -> ETH RxD1
+ * ETH_14 -> ETH RxD2
+ * ETH_15 -> ETH RxD3
+ * ETH_16 -> ETH Rxerr
+ * ETH_17 -> ETH CRS
+ *
+ * [9:11] = 111
+ * SPI on PSC6
+ * PSC6_0 -> MISO
+ * PSC6_1 -> SS#
+ * PSC6_2 -> MOSI
+ * PSC6_3 -> CLK
+ *
+ * [8] = 0
+ * IrDA/USB 48MHz clock generated internally
+ *
+ * [6:7] = 01
+ * ATA chip selects on csb_4/5
+ * CSB_4 -> ATA_CS0 out
+ * CSB_5 -> ATA_CS1 out
+ *
+ * [5] = 1
+ * PSC3_4 is used as CS6
+ *
+ * [4] = 1
+ * PSC3_5 is used as CS7
+ *
+ * [2:3] = 00
+ * No Alternatives
+ *
+ * [1] = 0
+ * gpio_wkup_7 is GPIO
+ *
+ * [0] = 0
+ * gpio_wkup_6 is GPIO
+ *
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x0d75a162
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT "uboot> "		/* Monitor Command Prompt */
+
+#define CONFIG_CMDLINE_EDITING 1		/* add command line history */
+
+#define CONFIG_SYS_CACHELINE_SIZE 32		/* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT 5		/* log base 2 of the above value */
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024			/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 512			/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+						/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 32			/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00f00000	/* 1 ... 15 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR 0x400000		/* default load address */
+#define CONFIG_SYS_HZ 1000			/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_CRC32_VERIFY  1
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_DNS | \
+				 CONFIG_BOOTP_DNS2 | \
+				 CONFIG_BOOTP_SEND_HOSTNAME )
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+/* no burst access on the LPB */
+#define CONFIG_SYS_CS_BURST		0x00000000
+/* one deadcycle for the 33MHz statemachine */
+#define CONFIG_SYS_CS_DEADCYCLE		0x33333331
+
+#define CONFIG_SYS_BOOTCS_CFG		0x0002d900
+#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+/*
+ * USB settings
+ */
+#define CONFIG_USB_CLOCK		0x0001bbbb
+/* USB is on PSC3 */
+#define CONFIG_PSC3_USB
+#define CONFIG_USB_CONFIG		0x00000100
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/*
+ * IDE/ATA stuff Supports IDE harddisk
+ */
+#undef  CONFIG_IDE_8xx_PCCARD	/* Use IDE with PC Card Adapter */
+#undef	CONFIG_IDE_8xx_DIRECT	/* Direct IDE not supported */
+#undef	CONFIG_IDE_LED		/* LED for ide not supported */
+
+#define	CONFIG_IDE_RESET 1	/* reset for ide supported */
+#define CONFIG_IDE_PREINIT
+#define CONFIG_SYS_IDE_MAXBUS 1	/* max. 1 IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE 2	/* max. 2 drives per IDE bus */
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+/* Interval between registers */
+#define CONFIG_SYS_ATA_STRIDE		4
+#define CONFIG_ATAPI			1
+
+/* we enable IDE and FAT support, so we also need partition support */
+#define CONFIG_DOS_PARTITION 1
+
+/*
+ * Open Firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+
+#define OF_CPU				"PowerPC,5200@0"
+#define OF_TBCLK			CONFIG_SYS_MPC5XXX_CLKIN
+#define OF_SOC				"soc5200@f0000000"
+#define OF_STDOUT_PATH			"/soc5200@f0000000/serial@2600"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/impa7.h b/include/configs/impa7.h
index c7001cc..fdfa022 100644
--- a/include/configs/impa7.h
+++ b/include/configs/impa7.h
@@ -47,9 +47,10 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
-#define CS8900_BASE		0x20000000
-#define CS8900_BUS32		1
+#define CONFIG_NET_MULTI
+#define CONFIG_CS8900		/* we have a CS8900 on-board */
+#define CONFIG_CS8900_BASE	0x20000000
+#define CONFIG_CS8900_BUS32
 
 /*
  * select serial console configuration
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index 869fd4c..79d8638 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -324,6 +324,12 @@
 #define CONFIG_SYS_DTT_HYSTERESIS	3
 #define CONFIG_SYS_DTT_BUS_NUM		(CONFIG_SYS_MAX_I2C_BUS)
 
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_KMETER1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		CONFIG_SYS_PIGGY_BASE
+#endif
+
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
 #endif
diff --git a/include/configs/lart.h b/include/configs/lart.h
index 5d6d460..2d3b369 100644
--- a/include/configs/lart.h
+++ b/include/configs/lart.h
@@ -47,9 +47,10 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
-#define CS8900_BASE		0x20008300
-#define CS8900_BUS16		1
+#define CONFIG_NET_MULTI
+#define CONFIG_CS8900		/* we have a CS8900 on-board */
+#define CONFIG_CS8900_BASE	0x20008300
+#define CONFIG_CS8900_BUS16
 
 /*
  * select serial console configuration
diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h
index 12e567b..b2ffd3e 100644
--- a/include/configs/mx1ads.h
+++ b/include/configs/mx1ads.h
@@ -66,9 +66,10 @@
 /*
  *  CS8900 Ethernet drivers
  */
-#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
-#define CS8900_BASE		0x15000300
-#define CS8900_BUS16		1	/* the Linux driver does accesses as shorts */
+#define CONFIG_NET_MULTI
+#define CONFIG_CS8900		/* we have a CS8900 on-board */
+#define CONFIG_CS8900_BASE	0x15000300
+#define CONFIG_CS8900_BUS16	/* the Linux driver does accesses as shorts */
 
 /*
  * select serial console configuration
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index 363ea1b..ec1c905 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -109,9 +109,10 @@
 		"cp.b ${loadaddr} ${uboot_addr} ${filesize}; "		\
 		"setenv filesize; saveenv\0"
 
-#define CONFIG_DRIVER_CS8900	1
-#define CS8900_BASE		0xb4020300
-#define CS8900_BUS16		1	/* follow the Linux driver */
+#define CONFIG_NET_MULTI
+#define CONFIG_CS8900
+#define CONFIG_CS8900_BASE	0xb4020300
+#define CONFIG_CS8900_BUS16		1	/* follow the Linux driver */
 
 /*
  * The MX31ADS board seems to have a hardware "peculiarity" confirmed under
diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h
index 8a83d92..027e8e1 100644
--- a/include/configs/nhk8815.h
+++ b/include/configs/nhk8815.h
@@ -138,6 +138,10 @@
 #define CONFIG_SMC_USE_32_BIT
 #define CONFIG_BOOTFILE		"uImage"
 
+#define CONFIG_IP_DEFRAG	/* Allows faster download, TFTP and NFS */
+#define CONFIG_TFTP_BLOCKSIZE	4096
+#define CONFIG_NFS_READ_SIZE	4096
+
 /* Storage information: onenand and nand */
 #define CONFIG_CMD_ONENAND
 #define CONFIG_MTD_ONENAND_VERIFY_WRITE
diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h
index 7c2bf1b..6517381 100644
--- a/include/configs/pcu_e.h
+++ b/include/configs/pcu_e.h
@@ -231,7 +231,6 @@
 #define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment		*/
 #define CONFIG_ENV_ADDR	    0xFFFFE000	/* Address    of Environment Sector	*/
 #define CONFIG_ENV_SECT_SIZE	0x2000	/* use the top-most 8k boot sector	*/
-#define	CONFIG_ENV_IS_EMBEDDED	1	/* short-cut compile-time test		*/
 #else
 /* Final version: environment in EEPROM */
 #define CONFIG_ENV_IS_IN_EEPROM	1
diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h
index f3dc7fe..f2ea926 100644
--- a/include/configs/sbc2410x.h
+++ b/include/configs/sbc2410x.h
@@ -63,9 +63,10 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
-#define CS8900_BASE		0x19000300
-#define CS8900_BUS16		1 /* the Linux driver does accesses as shorts */
+#define CONFIG_NET_MULTI
+#define CONFIG_CS8900		/* we have a CS8900 on-board */
+#define CONFIG_CS8900_BASE	0x19000300
+#define CONFIG_CS8900_BUS16	/* the Linux driver does accesses as shorts */
 
 /*
  * select serial console configuration
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index a2ff955..838b4db 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -59,7 +59,6 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_CLEAR_LAW0		/* Clear LAW0 in cpu_init_r */
 
 /*
  * Only possible on E500 Version 2 or newer cores.
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index ef0f627..2865df5 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -41,7 +41,6 @@
 #define CONFIG_MPC8641		1	/* MPC8641 specific */
 #define CONFIG_SBC8641D		1	/* SBC8641D board specific */
 #define CONFIG_MP		1	/* support multiple processors */
-#define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */
 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
 
 #ifdef RUN_DIAG
@@ -107,6 +106,7 @@
 
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
+#define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR_PHYS_LOW
 
 #define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)
 #define CONFIG_SYS_PCI2_ADDR		(CONFIG_SYS_CCSRBAR+0x9000)
diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h
index b712db4..c234177 100644
--- a/include/configs/smdk2400.h
+++ b/include/configs/smdk2400.h
@@ -56,9 +56,10 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
-#define CS8900_BASE		0x07000300 /* agrees with WIN CE PA */
-#define CS8900_BUS16		1 /* the Linux driver does accesses as shorts */
+#define CONFIG_NET_MULTI
+#define CONFIG_CS8900		/* we have a CS8900 on-board */
+#define CONFIG_CS8900_BASE	0x07000300 /* agrees with WIN CE PA */
+#define CONFIG_CS8900_BUS16	/* the Linux driver does accesses as shorts */
 
 /*
  * select serial console configuration
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index a473278..d340098 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -53,9 +53,10 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
-#define CS8900_BASE		0x19000300
-#define CS8900_BUS16		1 /* the Linux driver does accesses as shorts */
+#define CONFIG_NET_MULTI
+#define CONFIG_CS8900		/* we have a CS8900 on-board */
+#define CONFIG_CS8900_BASE	0x19000300
+#define CONFIG_CS8900_BUS16	/* the Linux driver does accesses as shorts */
 
 /*
  * select serial console configuration
diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index ddc8e71..f6e1221 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -74,9 +74,10 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board	*/
-#define CS8900_BASE	  	0x18800300
-#define CS8900_BUS16		1 	/* follow the Linux driver	*/
+#define CONFIG_NET_MULTI
+#define CONFIG_CS8900			/* we have a CS8900 on-board	*/
+#define CONFIG_CS8900_BASE	  	0x18800300
+#define CONFIG_CS8900_BUS16		/* follow the Linux driver	*/
 
 /*
  * select serial console configuration
diff --git a/include/configs/trab.h b/include/configs/trab.h
index 7687ee6..43c191b 100644
--- a/include/configs/trab.h
+++ b/include/configs/trab.h
@@ -99,9 +99,10 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
-#define CS8900_BASE		0x07000300 /* agrees with WIN CE PA */
-#define CS8900_BUS16		1 /* the Linux driver does accesses as shorts */
+#define CONFIG_NET_MULTI
+#define CONFIG_CS8900		/* we have a CS8900 on-board */
+#define CONFIG_CS8900_BASE	0x07000300 /* agrees with WIN CE PA */
+#define CONFIG_CS8900_BUS16	/* the Linux driver does accesses as shorts */
 
 #define CONFIG_DRIVER_S3C24X0_I2C 1	/* we use the buildin I2C controller */
 
diff --git a/include/e500.h b/include/e500.h
index 84b580d..f8c8266 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -8,13 +8,9 @@
 
 #ifndef __ASSEMBLY__
 
-#ifndef CONFIG_NUM_CPUS
-#define CONFIG_NUM_CPUS 1
-#endif
-
 typedef struct
 {
-  unsigned long freqProcessor[CONFIG_NUM_CPUS];
+  unsigned long freqProcessor[CONFIG_MAX_CPUS];
   unsigned long freqSystemBus;
   unsigned long freqDDRBus;
   unsigned long freqLocalBus;
diff --git a/include/environment.h b/include/environment.h
index 5bed32f..b9924fd 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -67,6 +67,10 @@
 # if defined(CONFIG_ENV_ADDR_REDUND) || defined(CONFIG_ENV_OFFSET_REDUND)
 #  define CONFIG_SYS_REDUNDAND_ENVIRONMENT	1
 # endif
+# ifdef CONFIG_ENV_IS_EMBEDDED
+#  error "do not define CONFIG_ENV_IS_EMBEDDED in your board config"
+#  error "it is calculated automatically for you"
+# endif
 #endif	/* CONFIG_ENV_IS_IN_FLASH */
 
 #if defined(CONFIG_ENV_IS_IN_NAND)
@@ -79,9 +83,6 @@
 # ifdef CONFIG_ENV_OFFSET_REDUND
 #  define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 # endif
-# ifdef CONFIG_ENV_IS_EMBEDDED
-#  define ENV_IS_EMBEDDED	1
-# endif
 #endif /* CONFIG_ENV_IS_IN_NAND */
 
 #if defined(CONFIG_ENV_IS_IN_MG_DISK)
@@ -91,11 +92,32 @@
 # ifndef CONFIG_ENV_SIZE
 #  error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_MG_DISK"
 # endif
-# ifdef CONFIG_ENV_IS_EMBEDDED
-#  error "CONFIG_ENV_IS_EMBEDDED not supported when using CONFIG_ENV_IS_IN_MG_DISK"
-# endif
 #endif /* CONFIG_ENV_IS_IN_MG_DISK */
 
+/* Embedded env is only supported for some flash types */
+#ifdef CONFIG_ENV_IS_EMBEDDED
+# if !defined(CONFIG_ENV_IS_IN_FLASH) && \
+     !defined(CONFIG_ENV_IS_IN_NAND) && \
+     !defined(CONFIG_ENV_IS_IN_ONENAND)
+#  error "CONFIG_ENV_IS_EMBEDDED not supported for your flash type"
+# endif
+#endif
+
+/*
+ * For the flash types where embedded env is supported, but it cannot be
+ * calculated automatically (i.e. NAND), take the board opt-in.
+ */
+#if defined(CONFIG_ENV_IS_EMBEDDED) && !defined(ENV_IS_EMBEDDED)
+# define ENV_IS_EMBEDDED 1
+#endif
+
+/* The build system likes to know if the env is embedded */
+#ifdef DO_DEPS_ONLY
+# ifdef ENV_IS_EMBEDDED
+#  define CONFIG_ENV_IS_EMBEDDED
+# endif
+#endif
+
 #include "compiler.h"
 
 #ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
diff --git a/include/flash.h b/include/flash.h
index b016162..8feca1b 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -46,7 +46,7 @@ typedef struct {
 	ushort	cmd_reset;		/* vendor specific reset command	*/
 	ushort	interface;		/* used for x8/x16 adjustments		*/
 	ushort	legacy_unlock;		/* support Intel legacy (un)locking	*/
-	uchar	manufacturer_id;	/* manufacturer id			*/
+	ushort	manufacturer_id;	/* manufacturer id			*/
 	ushort	device_id;		/* device id				*/
 	ushort	device_id2;		/* extended device id			*/
 	ushort	ext_addr;		/* extended query table address		*/
@@ -154,6 +154,7 @@ extern flash_info_t *flash_get_info(ulong base);
  * Device IDs
  */
 
+/* Manufacturers inside bank 0 have ids like 0x00xx00xx */
 #define AMD_MANUFACT	0x00010001	/* AMD	   manuf. ID in D23..D16, D7..D0 */
 #define FUJ_MANUFACT	0x00040004	/* FUJITSU manuf. ID in D23..D16, D7..D0 */
 #define ATM_MANUFACT	0x001F001F	/* ATMEL */
@@ -166,6 +167,13 @@ extern flash_info_t *flash_get_info(ulong base);
 #define TOSH_MANUFACT	0x00980098	/* TOSHIBA manuf. ID in D23..D16, D7..D0 */
 #define MT2_MANUFACT	0x002C002C	/* alternate MICRON manufacturer ID*/
 #define EXCEL_MANUFACT	0x004A004A	/* Excel Semiconductor			*/
+#define AMIC_MANUFACT	0x00370037	/* AMIC    manuf. ID in D23..D16, D7..D0 */
+#define WINB_MANUFACT	0x00DA00DA	/* Winbond manuf. ID in D23..D16, D7..D0 */
+
+/* Manufacturers inside bank 1 have ids like 0x01xx01xx */
+#define EON_MANUFACT	0x011C011C	/* EON     manuf. ID in D23..D16, D7..D0 */
+
+/* Manufacturers inside bank 2 have ids like 0x02xx02xx */
 
 					/* Micron Technologies (INTEL compat.)	*/
 #define MT_ID_28F400_T	0x44704470	/* 28F400B3 ID ( 4 M, top boot sector)	*/
diff --git a/include/linux/mc146818rtc.h b/include/linux/mc146818rtc.h
index 227feeb..0644d92 100644
--- a/include/linux/mc146818rtc.h
+++ b/include/linux/mc146818rtc.h
@@ -83,16 +83,4 @@
 #define RTC_VALID   RTC_REG_D
 # define RTC_VRT 0x80       /* valid RAM and time */
 /**********************************************************************/
-
-/* example: !(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY)
- * determines if the following two #defines are needed
- */
-#ifndef BCD_TO_BIN
-#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
-#endif
-
-#ifndef BIN_TO_BCD
-#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
-#endif
-
 #endif /* _MC146818RTC_H */
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 3e0044b..cb7c19a 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -128,6 +128,7 @@ typedef enum {
 	NAND_ECC_SOFT,
 	NAND_ECC_HW,
 	NAND_ECC_HW_SYNDROME,
+	NAND_ECC_HW_OOB_FIRST,
 } nand_ecc_modes_t;
 
 /*
@@ -268,13 +269,13 @@ struct nand_ecc_ctrl {
 					   uint8_t *calc_ecc);
 	int			(*read_page_raw)(struct mtd_info *mtd,
 						 struct nand_chip *chip,
-						 uint8_t *buf);
+						 uint8_t *buf, int page);
 	void			(*write_page_raw)(struct mtd_info *mtd,
 						  struct nand_chip *chip,
 						  const uint8_t *buf);
 	int			(*read_page)(struct mtd_info *mtd,
 					     struct nand_chip *chip,
-					     uint8_t *buf);
+					     uint8_t *buf, int page);
 	int			(*read_subpage)(struct mtd_info *mtd,
 					     struct nand_chip *chip,
 					     uint32_t offs, uint32_t len,
diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h
index 2597e34..06f7baf 100644
--- a/include/linux/mtd/onenand.h
+++ b/include/linux/mtd/onenand.h
@@ -83,10 +83,9 @@ struct onenand_chip {
 			size_t len);
 	int (*wait) (struct mtd_info *mtd, int state);
 	int (*bbt_wait) (struct mtd_info *mtd, int state);
+	void (*unlock_all)(struct mtd_info *mtd);
 	int (*read_bufferram) (struct mtd_info *mtd, loff_t addr, int area,
 			       unsigned char *buffer, int offset, size_t count);
-	int (*read_spareram) (struct mtd_info *mtd, loff_t addr, int area,
-			       unsigned char *buffer, int offset, size_t count);
 	int (*write_bufferram) (struct mtd_info *mtd, loff_t addr, int area,
 				const unsigned char *buffer, int offset,
 				size_t count);
diff --git a/include/netdev.h b/include/netdev.h
index 50329a3..a50ec67 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -43,6 +43,7 @@ int cpu_eth_init(bd_t *bis);
 /* Driver initialization prototypes */
 int au1x00_enet_initialize(bd_t*);
 int bfin_EMAC_initialize(bd_t *bis);
+int cs8900_initialize(u8 dev_num, int base_addr);
 int dc21x4x_initialize(bd_t *bis);
 int davinci_emac_initialize(void);
 int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
diff --git a/include/pci.h b/include/pci.h
index aaa4554..491f814 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -222,6 +222,7 @@
 #define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
 #define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
 #define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
+#define  PCI_CAP_ID_EXP 	0x10	/* PCI Express */
 #define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
 #define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
 #define PCI_CAP_SIZEOF		4
diff --git a/include/rtc.h b/include/rtc.h
index 785fbe3..772a548 100644
--- a/include/rtc.h
+++ b/include/rtc.h
@@ -27,6 +27,11 @@
 #ifndef _RTC_H_
 #define _RTC_H_
 
+/* bcd<->bin functions are needed by almost all the RTC drivers, let's include
+ * it there instead of in evey single driver */
+
+#include <bcd.h>
+
 /*
  * The struct used to pass data from the generic interface code to
  * the hardware dependend low-level code ande vice versa. Identical