MPC5121e ADS PCI support take 3

Adds PCI support for MPC5121

Tested with drivers/net/rtl8139.c

Support is conditional since PCI on old silicon does not work.

ads5121_PCI_config turns on PCI

In this version, condition compilation of PCI code has been moved
from ifdef in board/ads5121/pci.c to board/ads5121/Makefile as
suggested by Jean-Christophe PLAGNIOL-VILLARD

Signed-off-by: John Rigby <jrigby@freescale.com>

4 files changed, 169 insertions, 7 deletions

diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index f9a3d92..205f7ed 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -103,6 +103,7 @@ typedef	struct	global_data {
 #if defined(CONFIG_MPC512X)
 	u32 ips_clk;
 	u32 csb_clk;
+	u32 pci_clk;
 #endif /* CONFIG_MPC512X */
 #if defined(CONFIG_MPC8220)
 	unsigned long   bExtUart;
diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h
index 23d10d4..cd90945 100644
--- a/include/asm-ppc/immap_512x.h
+++ b/include/asm-ppc/immap_512x.h
@@ -29,7 +29,7 @@
 typedef struct law512x {
 	u32 bar;	/* Base Addr Register */
 	u32 ar;		/* Attributes Register */
-} law521x_t;
+} law512x_t;
 
 /*
  * System configuration registers
@@ -47,9 +47,9 @@ typedef struct sysconf512x {
 	u32 lpcs6aw;		/* LP CS6 Access Window */
 	u32 lpcs7aw;		/* LP CS7 Access Window */
 	u8 res1[0x1c];
-	law521x_t pcilaw[3];	/* PCI Local Access Window 0-2 Registers */
+	law512x_t pcilaw[3];	/* PCI Local Access Window 0-2 Registers */
 	u8 res2[0x28];
-	law521x_t ddrlaw;	/* DDR Local Access Window */
+	law512x_t ddrlaw;	/* DDR Local Access Window */
 	u8 res3[0x18];
 	u32 mbxbar;		/* MBX Base Address */
 	u32 srambar;		/* SRAM Base Address */
@@ -241,21 +241,70 @@ typedef struct dma512x {
  * PCI Software Configuration Registers
  */
 typedef struct pciconf512x {
-	u8 fixme[0x80];
+	u32 config_address;
+	u32 config_data;
+	u32 int_ack;
+	u8 res[116];
 } pciconf512x_t;
 
 /*
+ * PCI Outbound Translation Register
+ */
+typedef struct pci_outbound_window {
+	u32 potar;
+	u8 res0[4];
+	u32 pobar;
+	u8 res1[4];
+	u32 pocmr;
+	u8 res2[4];
+} pot512x_t;
+
+/*
  * Sequencer
  */
 typedef struct ios512x {
-	u8 fixme[0x100];
+	pot512x_t pot[6];
+	u8 res0[0x60];
+	u32 pmcr;
+	u8 res1[4];
+	u32 dtcr;
+	u8 res2[4];
 } ios512x_t;
 
 /*
  * PCI Controller
  */
 typedef struct pcictrl512x {
-	u8 fixme[0x100];
+	u32 esr;
+	u32 ecdr;
+	u32 eer;
+	u32 eatcr;
+	u32 eacr;
+	u32 eeacr;
+	u32 edlcr;
+	u32 edhcr;
+	u32 gcr;
+	u32 ecr;
+	u32 gsr;
+	u8 res0[12];
+	u32 pitar2;
+	u8 res1[4];
+	u32 pibar2;
+	u32 piebar2;
+	u32 piwar2;
+	u8 res2[4];
+	u32 pitar1;
+	u8 res3[4];
+	u32 pibar1;
+	u32 piebar1;
+	u32 piwar1;
+	u8 res4[4];
+	u32 pitar0;
+	u8 res5[4];
+	u32 pibar0;
+	u8 res6[4];
+	u32 piwar0;
+	u8 res7[132];
 } pcictrl512x_t;
 
 
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index 09c3140..65dc97e 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -34,6 +34,9 @@
  * 0x3000_0000 - 0x3001_FFFF	SRAM (128 KB)
  * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
  * 0x8200_0000 - 0x8200_001F	CPLD (32 B)
+ * 0x8400_0000 - 0x82FF_FFFF	PCI I/O space (16 MB)
+ * 0xA000_0000 - 0xAFFF_FFFF	PCI memory space (256 MB)
+ * 0xB000_0000 - 0xBFFF_FFFF	PCI memory mapped I/O space (256 MB)
  * 0xFC00_0000 - 0xFFFF_FFFF	NOR Boot FLASH (64 MB)
  */
 
@@ -43,7 +46,7 @@
 #define CONFIG_E300		1	/* E300 Family */
 #define CONFIG_MPC512X		1	/* MPC512X family */
 
-#undef CONFIG_PCI
+/* CONFIG_PCI is defined at config time */
 
 #define CFG_MPC512X_CLKIN	66000000	/* in Hz */
 
@@ -217,6 +220,31 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
+/*
+ * PCI
+ */
+#ifdef CONFIG_PCI
+
+/*
+ * General PCI
+ */
+#define CFG_PCI_MEM_BASE	0xA0000000
+#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BASE
+#define CFG_PCI_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI_MMIO_BASE	(CFG_PCI_MEM_BASE + CFG_PCI_MEM_SIZE)
+#define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
+#define CFG_PCI_MMIO_SIZE	0x10000000	/* 256M */
+#define CFG_PCI_IO_BASE		0x00000000
+#define CFG_PCI_IO_PHYS		0x84000000
+#define CFG_PCI_IO_SIZE		0x01000000	/* 16M */
+
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif
+
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
 #undef CONFIG_SOFT_I2C			/* so disable bit-banged I2C */
diff --git a/include/mpc512x.h b/include/mpc512x.h
index b51cf78..b4cc2b9 100644
--- a/include/mpc512x.h
+++ b/include/mpc512x.h
@@ -46,6 +46,7 @@
 #define LPCS6AW			0x003C
 #define LPCA7AW			0x0040
 #define SRAMBAR			0x00C4
+#define LAWBAR_BAR		0xFFFFF000	/* Base address mask */
 
 #define LPC_OFFSET		0x10000
 
@@ -189,6 +190,10 @@
 #define SCFR1_IPS_DIV_MASK		0x03800000
 #define SCFR1_IPS_DIV_SHIFT		23
 
+#define SCFR1_PCI_DIV			0x6
+#define SCFR1_PCI_DIV_MASK		0x00700000
+#define SCFR1_PCI_DIV_SHIFT		20
+
 /* SCFR2 System Clock Frequency Register 2
  */
 #define SCFR2_SYS_DIV			0xFC000000
@@ -404,4 +409,83 @@
 #define I2C_IF		0x02
 #define I2C_RXAK	0x01
 
+/* POTAR - PCI Outbound Translation Address Register
+ */
+#define POTAR_TA_MASK			0x000fffff
+
+/* POBAR - PCI Outbound Base Address Register
+ */
+#define POBAR_BA_MASK			0x000fffff
+
+/* POCMR - PCI Outbound Comparision Mask Register
+ */
+#define POCMR_EN	0x80000000
+#define POCMR_IO	0x40000000	/* 0-memory space 1-I/O space */
+#define POCMR_PRE	0x20000000	/* prefetch enable */
+#define POCMR_SBS	0x00100000	/* special byte swap enable */
+#define POCMR_CM_MASK	0x000fffff
+#define POCMR_CM_4G	0x00000000
+#define POCMR_CM_2G	0x00080000
+#define POCMR_CM_1G	0x000C0000
+#define POCMR_CM_512M	0x000E0000
+#define POCMR_CM_256M	0x000F0000
+#define POCMR_CM_128M	0x000F8000
+#define POCMR_CM_64M	0x000FC000
+#define POCMR_CM_32M	0x000FE000
+#define POCMR_CM_16M	0x000FF000
+#define POCMR_CM_8M	0x000FF800
+#define POCMR_CM_4M	0x000FFC00
+#define POCMR_CM_2M	0x000FFE00
+#define POCMR_CM_1M	0x000FFF00
+#define POCMR_CM_512K	0x000FFF80
+#define POCMR_CM_256K	0x000FFFC0
+#define POCMR_CM_128K	0x000FFFE0
+#define POCMR_CM_64K	0x000FFFF0
+#define POCMR_CM_32K	0x000FFFF8
+#define POCMR_CM_16K	0x000FFFFC
+#define POCMR_CM_8K	0x000FFFFE
+#define POCMR_CM_4K	0x000FFFFF
+
+/* PITAR - PCI Inbound Translation Address Register
+ */
+#define PITAR_TA_MASK			0x000fffff
+
+/* PIBAR - PCI Inbound Base/Extended Address Register
+ */
+#define PIBAR_MASK			0xffffffff
+#define PIEBAR_EBA_MASK			0x000fffff
+
+/* PIWAR - PCI Inbound Windows Attributes Register
+ */
+#define PIWAR_EN			0x80000000
+#define PIWAR_SBS			0x40000000
+#define PIWAR_PF			0x20000000
+#define PIWAR_RTT_MASK			0x000f0000
+#define PIWAR_RTT_NO_SNOOP		0x00040000
+#define PIWAR_RTT_SNOOP			0x00050000
+#define PIWAR_WTT_MASK			0x0000f000
+#define PIWAR_WTT_NO_SNOOP		0x00004000
+#define PIWAR_WTT_SNOOP			0x00005000
+#define PIWAR_IWS_MASK			0x0000003F
+#define PIWAR_IWS_4K			0x0000000B
+#define PIWAR_IWS_8K			0x0000000C
+#define PIWAR_IWS_16K			0x0000000D
+#define PIWAR_IWS_32K			0x0000000E
+#define PIWAR_IWS_64K			0x0000000F
+#define PIWAR_IWS_128K			0x00000010
+#define PIWAR_IWS_256K			0x00000011
+#define PIWAR_IWS_512K			0x00000012
+#define PIWAR_IWS_1M			0x00000013
+#define PIWAR_IWS_2M			0x00000014
+#define PIWAR_IWS_4M			0x00000015
+#define PIWAR_IWS_8M			0x00000016
+#define PIWAR_IWS_16M			0x00000017
+#define PIWAR_IWS_32M			0x00000018
+#define PIWAR_IWS_64M			0x00000019
+#define PIWAR_IWS_128M			0x0000001A
+#define PIWAR_IWS_256M			0x0000001B
+#define PIWAR_IWS_512M			0x0000001C
+#define PIWAR_IWS_1G			0x0000001D
+#define PIWAR_IWS_2G			0x0000001E
+
 #endif	/* __MPC512X_H__ */