Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm:
  arm, davinci: add DAVINCI_MMC_CLKID
  arm, davinci_emac: fix driver bug if more then 3 PHYs are detected
  arm, davinci: da850/dm365 lowlevel cleanup
  omap5: Add omap5_evm board build support.
  omap4/5: Add support for booting with CH.
  omap5: emif: Add emif/ddr configurations required for omap5 evm
  omap5: clocks: Add clocks support for omap5 platform.
  omap5: Add minimal support for omap5430.
  omap: Checkpatch fixes
  omap4: make omap4 code common for future reuse
  GCC4.6: Squash warnings in onenand_base.c
  GCC4.6: Fix common/usb.c on xscale
  OneNAND: Add simple OneNAND SPL
  PXA: vpac270: Enable the new generic MMC driver
  PXA: Cleanup serial_pxa
  PXA: Drop csb226 and innokom boards (unmaintained)
  m28evk: Fix comment about the number of RAM banks
  mx31: Fix checkpatch warnings in generic.c
  mx31: Use proper IO accessor for GPR register
  mx31: Remove duplicate definition for GPR register
  qong: Use generic function for configuring GPR register
  M28EVK: Enable USB HOST support
  iMX28: Add USB HOST driver
  iMX28: Add USB and USB PHY register definitions
  M28: Add memory detection into SPL
  iMX28: Fix ARM vector handling
  M28: Add doc/README.m28 documentation
  M28: Add MMC SPL
  iMX28: Add support for DENX M28EVK board
  iMX28: Add u-boot.sb target to Makefile
  iMX28: Add image header generator tool
  iMX28: Add driver for internal RTC
  iMX28: Add GPMI NAND driver
  iMX28: Add APBH DMA driver
  iMX28: Add SPI driver
  iMX28: Add GPIO control
  iMX28: Add I2C bus driver
  iMX28: Add PINMUX control
  FEC: Add support for iMX28 quirks
  iMX28: Add SSP MMC driver
  iMX28: Initial support for iMX28 CPU
  MX25: zmx25: GCC4.6 fix build warnings
  da850: add new config file for AM18xx
  BeagleBoard: config: Switch to ttyO2
  OMAP3: Change omap3_evm maintainer
  devkit8000: Fix NAND SPL on boards with 256MB NAND
  integrator: enable Vpp and disable flash protection
  integrator: add system controller header
  integrator: make flash writeable on boot
  integrator: use io-accessors for board init
  integrator: move text offset to config
  integrator: pass configs for core modules
  ARM: remove superfluous setting of arch_number in board specific code.
  SPL: Allow ARM926EJS to avoid compiling in the CPU support code
  integrator: do not test first part of the memory
  arm: a320: fix broken timer
  ARM: define CONFIG_MACH_TYPE for all ronetix boards
  dm646x: pass board revision info to kernel
  dm646x: add new configuration for dm6467T
  arm, davinci: Fix setting of the SDRAM configuration register
  arm, davinci: Remove the duplication of LPSC functions
  arm, davinci: Rename AM1808 lowlevel functions to DA850
  da8xxevm: fix build error
  ARM: re-add MACH_TYPE_XXXXXX for VCMA9 board and add CONFIG_MACH_TYPE

18 files changed, 1024 insertions, 1016 deletions

diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 8b8113d..a370c15 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -29,6 +29,9 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+
+#define MACH_TYPE_MPL_VCMA9	227
+
 /*
  * High Level Configuration Options
  * (easy to change)
@@ -37,6 +40,7 @@
 #define CONFIG_S3C24X0		/* in a SAMSUNG S3C24x0-type SoC */
 #define CONFIG_S3C2410		/* specifically a SAMSUNG S3C2410 SoC */
 #define CONFIG_VCMA9		/* on a MPL VCMA9 Board  */
+#define CONFIG_MACH_TYPE	MACH_TYPE_MPL_VCMA9 /* Machine type */
 
 #define CONFIG_SYS_TEXT_BASE	0x0
 
diff --git a/include/configs/csb226.h b/include/configs/csb226.h
deleted file mode 100644
index 804469b..0000000
--- a/include/configs/csb226.h
+++ /dev/null
@@ -1,506 +0,0 @@
-/*
- * (C) Copyright 2000, 2001, 2002
- * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
- *
- * Configuration for the Cogent CSB226 board. For details see
- * http://www.cogcomp.com/csb_csb226.htm
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * include/configs/csb226.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define DEBUG 1
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA250		1	/* This is an PXA250 CPU            */
-#define CONFIG_CSB226		1	/* on a CSB226 board                */
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff      */
-					/* for timer/console/ethernet       */
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-#define	CONFIG_SYS_TEXT_BASE	0x0
-/*
- * Hardware drivers
- */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART		1	/* we use FFUART on CSB226          */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		19200
-#undef  CONFIG_MISC_INIT_R		/* not used yet                     */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_CACHE
-
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS		"console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0"
-#define CONFIG_ETHADDR		FF:FF:FF:FF:FF:FF
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_IPADDR		192.168.1.56
-#define CONFIG_SERVERIP		192.168.1.5
-#define CONFIG_BOOTCOMMAND	"bootm 0x40000"
-#define CONFIG_SHOW_BOOT_PROGRESS
-
-#define CONFIG_CMDLINE_TAG	1
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	19200		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-
-/*
- * Size of malloc() pool; this lives below the uppermost 128 KiB which are
- * used for the RAM copy of the uboot code
- *
- */
-#define CONFIG_SYS_MALLOC_LEN		(128*1024)
-
-#define CONFIG_SYS_LONGHELP				/* undef to save memory         */
-#define CONFIG_SYS_PROMPT		"uboot> "	/* Monitor Command Prompt       */
-#define CONFIG_SYS_CBSIZE		128		/* Console I/O Buffer Size      */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args   */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START	0xa0400000      /* memtest works on     */
-#define CONFIG_SYS_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
-
-#define CONFIG_SYS_LOAD_ADDR           0xa3000000	/* default load address */
-						/* RS: where is this documented? */
-						/* RS: is this where U-Boot is  */
-						/* RS: relocated to in RAM?      */
-
-#define CONFIG_SYS_HZ			1000
-						/* RS: the oscillator is actually 3680130?? */
-#define CONFIG_SYS_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
-						/* 0101000001 */
-						/*      ^^^^^ Memory Speed 99.53 MHz         */
-						/*    ^^      Run Mode Speed = 2x Mem Speed  */
-						/* ^^         Turbo Mode Sp. = 1x Run M. Sp. */
-
-#define CONFIG_SYS_MONITOR_LEN		0x1c000		/* 112 KiB */
-
-						/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Network chip
- */
-#define CONFIG_CS8900
-#define CONFIG_CS8900_BUS32
-#define CONFIG_CS8900_BASE	0x08000000
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
-#ifdef  CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM   */
-#define PHYS_SDRAM_1		0xa0000000	/* SDRAM Bank #1            */
-#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB                    */
-
-#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1            */
-#define PHYS_FLASH_SIZE		0x02000000	/* 32 MB                    */
-
-#define CONFIG_SYS_DRAM_BASE		0xa0000000	/* RAM starts here          */
-#define CONFIG_SYS_DRAM_SIZE		0x02000000
-
-#define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-# if 0
-/* FIXME: switch to _documented_ registers */
-/*
- * GPIO settings
- *
- * GP15 == nCS1      is 1
- * GP24 == SFRM      is 1
- * GP25 == TXD       is 1
- * GP33 == nCS5      is 1
- * GP39 == FFTXD     is 1
- * GP41 == RTS       is 1
- * GP47 == TXD       is 1
- * GP49 == nPWE      is 1
- * GP62 == LED_B     is 1
- * GP63 == TDM_OE    is 1
- * GP78 == nCS2      is 1
- * GP79 == nCS3      is 1
- * GP80 == nCS4      is 1
- */
-#define CONFIG_SYS_GPSR0_VAL       0x03008000
-#define CONFIG_SYS_GPSR1_VAL       0xC0028282
-#define CONFIG_SYS_GPSR2_VAL       0x0001C000
-
-/* GP02 == DON_RST   is 0
- * GP23 == SCLK      is 0
- * GP45 == USB_ACT   is 0
- * GP60 == PLLEN     is 0
- * GP61 == LED_A     is 0
- * GP73 == SWUPD_LED is 0
- */
-#define CONFIG_SYS_GPCR0_VAL       0x00800004
-#define CONFIG_SYS_GPCR1_VAL       0x30002000
-#define CONFIG_SYS_GPCR2_VAL       0x00000100
-
-/* GP00 == DON_READY is input
- * GP01 == DON_OK    is input
- * GP02 == DON_RST   is output
- * GP03 == RESET_IND is input
- * GP07 == RES11     is input
- * GP09 == RES12     is input
- * GP11 == SWUPDATE  is input
- * GP14 == nPOWEROK  is input
- * GP15 == nCS1      is output
- * GP17 == RES22     is input
- * GP18 == RDY       is input
- * GP23 == SCLK      is output
- * GP24 == SFRM      is output
- * GP25 == TXD       is output
- * GP26 == RXD       is input
- * GP32 == RES21     is input
- * GP33 == nCS5      is output
- * GP34 == FFRXD     is input
- * GP35 == CTS       is input
- * GP39 == FFTXD     is output
- * GP41 == RTS       is output
- * GP42 == USB_OK    is input
- * GP45 == USB_ACT   is output
- * GP46 == RXD       is input
- * GP47 == TXD       is output
- * GP49 == nPWE      is output
- * GP58 == nCPUBUSINT is input
- * GP59 == LANINT    is input
- * GP60 == PLLEN     is output
- * GP61 == LED_A     is output
- * GP62 == LED_B     is output
- * GP63 == TDM_OE    is output
- * GP64 == nDSPINT   is input
- * GP65 == STRAP0    is input
- * GP67 == STRAP1    is input
- * GP69 == STRAP2    is input
- * GP70 == STRAP3    is input
- * GP71 == STRAP4    is input
- * GP73 == SWUPD_LED is output
- * GP78 == nCS2      is output
- * GP79 == nCS3      is output
- * GP80 == nCS4      is output
- */
-#define CONFIG_SYS_GPDR0_VAL       0x03808004
-#define CONFIG_SYS_GPDR1_VAL       0xF002A282
-#define CONFIG_SYS_GPDR2_VAL       0x0001C200
-
-/* GP15 == nCS1  is AF10
- * GP18 == RDY   is AF01
- * GP23 == SCLK  is AF10
- * GP24 == SFRM  is AF10
- * GP25 == TXD   is AF10
- * GP26 == RXD   is AF01
- * GP33 == nCS5  is AF10
- * GP34 == FFRXD is AF01
- * GP35 == CTS   is AF01
- * GP39 == FFTXD is AF10
- * GP41 == RTS   is AF10
- * GP46 == RXD   is AF10
- * GP47 == TXD   is AF01
- * GP49 == nPWE  is AF10
- * GP78 == nCS2  is AF10
- * GP79 == nCS3  is AF10
- * GP80 == nCS4  is AF10
- */
-#define CONFIG_SYS_GAFR0_L_VAL     0x80000000
-#define CONFIG_SYS_GAFR0_U_VAL     0x001A8010
-#define CONFIG_SYS_GAFR1_L_VAL     0x60088058
-#define CONFIG_SYS_GAFR1_U_VAL     0x00000008
-#define CONFIG_SYS_GAFR2_L_VAL     0xA0000000
-#define CONFIG_SYS_GAFR2_U_VAL     0x00000002
-
-
-/* FIXME: set GPIO_RER/FER */
-
-/* RDH = 1
- * PH  = 1
- * VFS = 1
- * BFS = 1
- * SSS = 1
- */
-#define CONFIG_SYS_PSSR_VAL		0x37
-
-/*
- * Memory settings
- *
- * This is the configuration for nCS0/1 -> flash banks
- * configuration for nCS1:
- * [31]    0    - Slower Device
- * [30:28] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
- * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
- * [19]    1    - 16 Bit bus width
- * [18:16] 000  - nonburst RAM or FLASH
- * configuration for nCS0:
- * [15]    0    - Slower Device
- * [14:12] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
- * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
- * [03]    1    - 16 Bit bus width
- * [02:00] 000  - nonburst RAM or FLASH
- */
-#define CONFIG_SYS_MSC0_VAL		0x25b825b8 /* flash banks                   */
-
-/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
- * configuration for nCS3: DSP
- * [31]    0    - Slower Device
- * [30:28] 001  - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
- * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
- * [19]    1    - 16 Bit bus width
- * [18:16] 100  - variable latency I/O
- * configuration for nCS2: TDM-Switch
- * [15]    0    - Slower Device
- * [14:12] 101  - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
- * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
- * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
- * [03]    1    - 16 Bit bus width
- * [02:00] 100  - variable latency I/O
- */
-#define CONFIG_SYS_MSC1_VAL		0x123C593C /* TDM switch, DSP               */
-
-/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
- *
- * configuration for nCS5: LAN Controller
- * [31]    0    - Slower Device
- * [30:28] 001  - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
- * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
- * [19]    1    - 16 Bit bus width
- * [18:16] 100  - variable latency I/O
- * configuration for nCS4: ExtBus
- * [15]    0    - Slower Device
- * [14:12] 110  - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
- * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
- * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
- * [03]    1    - 16 Bit bus width
- * [02:00] 100  - variable latency I/O
- */
-#define CONFIG_SYS_MSC2_VAL		0x123C6CDC /* extra bus, LAN controller     */
-
-/* MDCNFG: SDRAM Configuration Register
- *
- * [31:29]   000 - reserved
- * [28]      0	 - no SA1111 compatiblity mode
- * [27]      0   - latch return data with return clock
- * [26]      0   - alternate addressing for pair 2/3
- * [25:24]   00  - timings
- * [23]      0   - internal banks in lower partition 2/3 (not used)
- * [22:21]   00  - row address bits for partition 2/3 (not used)
- * [20:19]   00  - column address bits for partition 2/3 (not used)
- * [18]      0   - SDRAM partition 2/3 width is 32 bit
- * [17]      0   - SDRAM partition 3 disabled
- * [16]      0   - SDRAM partition 2 disabled
- * [15:13]   000 - reserved
- * [12]      1	 - SA1111 compatiblity mode
- * [11]      1   - latch return data with return clock
- * [10]      0   - no alternate addressing for pair 0/1
- * [09:08]   01  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
- * [7]       1   - 4 internal banks in lower partition pair
- * [06:05]   10  - 13 row address bits for partition 0/1
- * [04:03]   01  - 9 column address bits for partition 0/1
- * [02]      0   - SDRAM partition 0/1 width is 32 bit
- * [01]      0   - disable SDRAM partition 1
- * [00]      1   - enable  SDRAM partition 0
- */
-/* use the configuration above but disable partition 0 */
-#define CONFIG_SYS_MDCNFG_VAL		0x000019c8
-
-/* MDREFR: SDRAM Refresh Control Register
- *
- * [32:26] 0     - reserved
- * [25]    0     - K2FREE: not free running
- * [24]    0     - K1FREE: not free running
- * [23]    1     - K0FREE: not free running
- * [22]    0     - SLFRSH: self refresh disabled
- * [21]    0     - reserved
- * [20]    0     - APD: no auto power down
- * [19]    0     - K2DB2: SDCLK2 is MemClk
- * [18]    0     - K2RUN: disable SDCLK2
- * [17]    0     - K1DB2: SDCLK1 is MemClk
- * [16]    1     - K1RUN: enable SDCLK1
- * [15]    1     - E1PIN: SDRAM clock enable
- * [14]    1     - K0DB2: SDCLK0 is MemClk
- * [13]    0     - K0RUN: disable SDCLK0
- * [12]    1     - E0PIN: disable SDCKE0
- * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
- */
-#define CONFIG_SYS_MDREFR_VAL		0x0081D018
-
-/* MDMRS: Mode Register Set Configuration Register
- *
- * [31]      0       - reserved
- * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
- * [22:20]   000     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
- * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
- * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
- * [15]      0       - reserved
- * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
- * [06:04]   010     - MDCL0:  SDRAM0/1 Cas Latency.
- * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
- * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
- */
-#define CONFIG_SYS_MDMRS_VAL		0x00020022
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL		0x00000000
-#define CONFIG_SYS_MCMEM0_VAL		0x00000000
-#define CONFIG_SYS_MCMEM1_VAL		0x00000000
-#define CONFIG_SYS_MCATT0_VAL		0x00000000
-#define CONFIG_SYS_MCATT1_VAL		0x00000000
-#define CONFIG_SYS_MCIO0_VAL		0x00000000
-#define CONFIG_SYS_MCIO1_VAL		0x00000000
-#endif
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPSR0_VAL		0xFFFFFFFF
-#define CONFIG_SYS_GPSR1_VAL		0xFFFFFFFF
-#define CONFIG_SYS_GPSR2_VAL		0xFFFFFFFF
-#define CONFIG_SYS_GPCR0_VAL		0x08022080
-#define CONFIG_SYS_GPCR1_VAL		0x00000000
-#define CONFIG_SYS_GPCR2_VAL		0x00000000
-#define CONFIG_SYS_GPDR0_VAL		0xCD82A878
-#define CONFIG_SYS_GPDR1_VAL		0xFCFFAB80
-#define CONFIG_SYS_GPDR2_VAL		0x0001FFFF
-#define CONFIG_SYS_GAFR0_L_VAL		0x80000000
-#define CONFIG_SYS_GAFR0_U_VAL		0xA5254010
-#define CONFIG_SYS_GAFR1_L_VAL		0x599A9550
-#define CONFIG_SYS_GAFR1_U_VAL		0xAAA5AAAA
-#define CONFIG_SYS_GAFR2_L_VAL		0xAAAAAAAA
-#define CONFIG_SYS_GAFR2_U_VAL		0x00000002
-
-/* FIXME: set GPIO_RER/FER */
-
-#define CONFIG_SYS_PSSR_VAL        0x20
-
-#define	CONFIG_SYS_CCCR			CCCR_L27|CCCR_M2|CCCR_N10
-#define	CONFIG_SYS_CKEN			0x0
-
-/*
- * Memory settings
- */
-
-#define CONFIG_SYS_MSC0_VAL            0x2ef15af0
-#define CONFIG_SYS_MSC1_VAL            0x00003ff4
-#define CONFIG_SYS_MSC2_VAL            0x7ff07ff0
-#define CONFIG_SYS_MDCNFG_VAL          0x09a909a9
-#define CONFIG_SYS_MDREFR_VAL          0x038ff030
-#define CONFIG_SYS_MDMRS_VAL           0x00220022
-#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
-#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL        0x00000000
-#define CONFIG_SYS_MCMEM0_VAL      0x00000000
-#define CONFIG_SYS_MCMEM1_VAL      0x00000000
-#define CONFIG_SYS_MCATT0_VAL      0x00000000
-#define CONFIG_SYS_MCATT1_VAL      0x00000000
-#define CONFIG_SYS_MCIO0_VAL       0x00000000
-#define CONFIG_SYS_MCIO1_VAL       0x00000000
-
-#define CSB226_USER_LED0	0x00000008
-#define CSB226_USER_LED1	0x00000010
-#define CSB226_USER_LED2	0x00000020
-
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS     1	/* max number of memory banks       */
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sect. on one chip  */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase       */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Write       */
-
-#define	CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR            (PHYS_FLASH_1 + 0x1C000)
-					/* Addr of Environment Sector       */
-#define CONFIG_ENV_SIZE            0x4000  /* Total Size of Environment Sector */
-
-#endif  /* __CONFIG_H */
diff --git a/include/configs/da850_am18xxevm.h b/include/configs/da850_am18xxevm.h
new file mode 100644
index 0000000..92b83ff
--- /dev/null
+++ b/include/configs/da850_am18xxevm.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_USE_SPIFLASH
+
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_DA850_EVM
+#define CONFIG_ARM926EJS		/* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
+#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ		24000000
+#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE		0xc1080000
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 64MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
+
+#define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE	(256*1024) /* regular stack */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
+#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
+#define CONFIG_SF_DEFAULT_SPEED		30000000
+#define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
+
+/*
+ * I2C Configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED		25000
+#define CONFIG_SYS_I2C_SLAVE		10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
+
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
+#define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
+#define CONFIG_ENV_SIZE			(128 << 10)
+#define	CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define	CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_CS		3
+#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_CLE_MASK		0x10
+#define CONFIG_SYS_ALE_MASK		0x8
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS			1
+#endif
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM	0
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#define CONFIG_NET_MULTI
+#endif
+
+#ifdef CONFIG_USE_NOR
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ	(128 << 10) /* 128KB */
+#define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ * 3)
+#define CONFIG_ENV_SIZE			(10 << 10) /* 10KB */
+#define CONFIG_SYS_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#define PHYS_FLASH_SIZE			(8 << 20) /* Flash size 8MB */
+#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
+	       + 3)
+#define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_FLASH_SECT_SZ
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE			(64 << 10)
+#define CONFIG_ENV_OFFSET		(256 << 10)
+#define CONFIG_ENV_SECT_SIZE		(64 << 10)
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOOTFILE		"uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT	"U-Boot > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
+#define CONFIG_HWCONFIG		/* enable hwconfig */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS		\
+	"mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_EXTRA_ENV_SETTINGS	"hwconfig=dsp:wake=yes"
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SAVEENV
+#endif
+
+#if !defined(CONFIG_USE_NAND) && \
+	!defined(CONFIG_USE_NOR) && \
+	!defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE		(16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ENV
+#endif
+
+/* additions for new relocation code, must added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0xc0000000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+					/* Fix this */ GENERATED_GBL_DATA_SIZE)
+#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_dm6467Tevm.h b/include/configs/davinci_dm6467Tevm.h
new file mode 100644
index 0000000..f7c994e
--- /dev/null
+++ b/include/configs/davinci_dm6467Tevm.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Spectrum Digital TMS320DM6467T EVM board */
+#define DAVINCI_DM6467EVM
+#define DAVINCI_DM6467TEVM
+#define CONFIG_SYS_USE_NAND
+#define CONFIG_SYS_NAND_SMALLPAGE
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* SoC Configuration */
+#define CONFIG_ARM926EJS				/* arm926ejs CPU */
+
+/* Clock rates detection */
+#ifndef __ASSEMBLY__
+extern unsigned int davinci_arm_clk_get(void);
+#endif
+
+#define CFG_REFCLK_FREQ		33000000
+/* Arm Clock frequency    */
+#define CONFIG_SYS_CLK_FREQ	davinci_arm_clk_get()
+/* Timer Input clock freq */
+#define CONFIG_SYS_HZ_CLOCK		(CONFIG_SYS_CLK_FREQ/2)
+#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SOC_DM646X
+
+/* EEPROM definitions for EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+
+/* Memory Info */
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_STACKSIZE		(256 << 10)	/* 256 KiB */
+#define PHYS_SDRAM_1			0x80000000	/* DDR Start */
+#define PHYS_SDRAM_1_SIZE		(256 << 20)	/* DDR size 256MB */
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SYS_BARGSIZE		1024		/* Bootarg Size */
+#define CONFIG_SYS_LOAD_ADDR		0x80700000	/* kernel address */
+#define CONFIG_REVISION_TAG
+
+/* Serial Driver info */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	4
+#define CONFIG_SYS_NS16550_COM1		0x01c20000
+#define CONFIG_SYS_NS16550_CLK		24000000
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* I2C Configuration */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED		80000
+#define CONFIG_SYS_I2C_SLAVE		10
+
+/* Network & Ethernet Configuration */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM	1
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#define CONFIG_CMD_NET
+
+/* Flash & Environment */
+#define CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_SYS_USE_NAND
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS		2
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KiB */
+#define CONFIG_SYS_NAND_BASE_LIST	{0x42000000, }
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_ENV_OFFSET		0
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			(4 << 10)	/* 4 KiB */
+#endif
+
+/* U-Boot general configuration */
+#undef CONFIG_USE_IRQ				/* No IRQ/FIQ in U-Boot */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
+#define CONFIG_SYS_PROMPT	"DM6467 EVM > "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE		\
+			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_BOOTCOMMAND		"source 0x82080000; dhcp; bootm"
+#define CONFIG_BOOTARGS			\
+					"mem=120M console=ttyS0,115200n8 " \
+					"root=/dev/hda1 rw noinitrd ip=dhcp"
+
+/* U-Boot commands */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#ifdef CONFIG_SYS_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#endif
+
+#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h
index ec1c31c..c9a0cd1 100644
--- a/include/configs/davinci_dm6467evm.h
+++ b/include/configs/davinci_dm6467evm.h
@@ -65,6 +65,7 @@ extern unsigned int davinci_arm_clk_get(void);
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_SYS_BARGSIZE		1024		/* Bootarg Size */
 #define CONFIG_SYS_LOAD_ADDR		0x80700000	/* kernel address */
+#define CONFIG_REVISION_TAG
 
 /* Serial Driver info */
 #define CONFIG_SYS_NS16550
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 6c51a27..e1743dc 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -337,6 +337,7 @@
 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
 
 /* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT	64
 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
 #define CONFIG_SYS_NAND_OOBSIZE		64
diff --git a/include/configs/innokom.h b/include/configs/innokom.h
deleted file mode 100644
index a0a3da1..0000000
--- a/include/configs/innokom.h
+++ /dev/null
@@ -1,507 +0,0 @@
-/*
- * (C) Copyright 2000, 2001, 2002
- * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
- *
- * Configuration for the Auerswald Innokom CPU board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * include/configs/innokom.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA250		1	/* This is an PXA250 CPU            */
-#define CONFIG_INNOKOM		1	/* on an Auerswald Innokom board    */
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff      */
-					/* for timer/console/ethernet       */
-
-#define	CONFIG_SYS_TEXT_BASE	0x0
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-/*
- * Hardware drivers
- */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART		1	/* we use FFUART on CSB226 */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		19200
-#define CONFIG_MISC_INIT_R	1	/* we have a misc_init_r() function */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_RUN
-
-
-#define CONFIG_BOOTDELAY	3
-/* #define CONFIG_BOOTARGS	"root=/dev/nfs ip=bootp console=ttyS0,19200" */
-#define CONFIG_BOOTARGS		"console=ttyS0,19200"
-#define CONFIG_ETHADDR		FF:FF:FF:FF:FF:FF
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_IPADDR		192.168.1.56
-#define CONFIG_SERVERIP		192.168.1.2
-#define CONFIG_BOOTCOMMAND	"bootm 0x40000"
-#define CONFIG_SHOW_BOOT_PROGRESS
-
-#define CONFIG_CMDLINE_TAG	1
-
-/*
- * Miscellaneous configurable options
- */
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(256*1024)
-
-#define CONFIG_SYS_LONGHELP				/* undef to save memory         */
-#define CONFIG_SYS_PROMPT		"uboot> "	/* Monitor Command Prompt       */
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size      */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args   */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START	0xa0400000      /* memtest works on     */
-#define CONFIG_SYS_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
-
-#define CONFIG_SYS_LOAD_ADDR           0xa3000000      /* load kernel to this address   */
-
-#define CONFIG_SYS_HZ			1000
-						/* RS: the oscillator is actually 3680130?? */
-
-#define CONFIG_SYS_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
-						/* 0101000001 */
-						/*      ^^^^^ Memory Speed 99.53 MHz         */
-						/*    ^^      Run Mode Speed = 2x Mem Speed  */
-						/* ^^         Turbo Mode Sp. = 1x Run M. Sp. */
-
-#define CONFIG_SYS_MONITOR_LEN		0x20000		/* 128 KiB */
-
-						/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * I2C bus
- */
-#define CONFIG_I2C_MV			1
-#define CONFIG_MV_I2C_REG		0x40301680
-#define CONFIG_HARD_I2C			1
-#define CONFIG_SYS_I2C_SPEED			50000
-#define CONFIG_SYS_I2C_SLAVE			0xfe
-
-#define CONFIG_ENV_IS_IN_EEPROM		1
-
-#define CONFIG_ENV_OFFSET			0x00	/* environment starts here  */
-#define CONFIG_ENV_SIZE			1024	/* 1 KiB                    */
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* A0 = 0 (hardwired)       */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets       */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	15	/* between stop and start   */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* length of address        */
-#define CONFIG_SYS_EEPROM_SIZE			4096	/* size in bytes            */
-#define CONFIG_SYS_I2C_INIT_BOARD		1	/* board has it's own init  */
-
-/*
- * SMSC91C111 Network Card
- */
-#define CONFIG_SMC91111		1
-#define CONFIG_SMC91111_BASE		0x14000000 /* chip select 5         */
-#undef  CONFIG_SMC_USE_32_BIT		           /* 16 bit bus access     */
-#undef  CONFIG_SMC_91111_EXT_PHY		   /* we use internal phy   */
-#define CONFIG_SMC_AUTONEG_TIMEOUT	10	   /* timeout 10 seconds    */
-#undef  CONFIG_SHOW_ACTIVITY
-#define CONFIG_NET_RETRY_COUNT		10	   /* # of retries          */
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
-#ifdef  CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM   */
-#define PHYS_SDRAM_1		0xa0000000	/* SDRAM Bank #1            */
-#define PHYS_SDRAM_1_SIZE	0x04000000	/* 64 MB                    */
-
-#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1            */
-#define PHYS_FLASH_SIZE		0x01000000	/* 16 MB                    */
-
-#define CONFIG_SYS_DRAM_BASE		0xa0000000	/* RAM starts here          */
-#define CONFIG_SYS_DRAM_SIZE		0x04000000
-
-#define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-/*
- * JFFS2 partitions
- *
- */
-/* development flash */
-#define CONFIG_MTD_INNOKOM_16MB	1
-#undef CONFIG_MTD_INNOKOM_64MB
-
-/* production flash */
-/*
-#define CONFIG_MTD_INNOKOM_64MB	1
-#undef CONFIG_MTD_INNOKOM_16MB
-*/
-
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		"nor0=innokom-0"
-*/
-
-/* development flash */
-/*
-#define MTDPARTS_DEFAULT	"mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)"
-*/
-
-/* production flash */
-/*
-#define MTDPARTS_DEFAULT	"mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)"
-*/
-
-/*
- * GPIO settings
- *
- * GP15 == nCS1      is 1
- * GP24 == SFRM      is 1
- * GP25 == TXD       is 1
- * GP33 == nCS5      is 1
- * GP39 == FFTXD     is 1
- * GP41 == RTS       is 1
- * GP47 == TXD       is 1
- * GP49 == nPWE      is 1
- * GP62 == LED_B     is 1
- * GP63 == TDM_OE    is 1
- * GP78 == nCS2      is 1
- * GP79 == nCS3      is 1
- * GP80 == nCS4      is 1
- */
-#define CONFIG_SYS_GPSR0_VAL       0x03008000
-#define CONFIG_SYS_GPSR1_VAL       0xC0028282
-#define CONFIG_SYS_GPSR2_VAL       0x0001C000
-
-/* GP02 == DON_RST   is 0
- * GP23 == SCLK      is 0
- * GP45 == USB_ACT   is 0
- * GP60 == PLLEN     is 0
- * GP61 == LED_A     is 0
- * GP73 == SWUPD_LED is 0
- */
-#define CONFIG_SYS_GPCR0_VAL       0x00800004
-#define CONFIG_SYS_GPCR1_VAL       0x30002000
-#define CONFIG_SYS_GPCR2_VAL       0x00000100
-
-/* GP00 == DON_READY is input
- * GP01 == DON_OK    is input
- * GP02 == DON_RST   is output
- * GP03 == RESET_IND is input
- * GP07 == RES11     is input
- * GP09 == RES12     is input
- * GP11 == SWUPDATE  is input
- * GP14 == nPOWEROK  is input
- * GP15 == nCS1      is output
- * GP17 == RES22     is input
- * GP18 == RDY       is input
- * GP23 == SCLK      is output
- * GP24 == SFRM      is output
- * GP25 == TXD       is output
- * GP26 == RXD       is input
- * GP32 == RES21     is input
- * GP33 == nCS5      is output
- * GP34 == FFRXD     is input
- * GP35 == CTS       is input
- * GP39 == FFTXD     is output
- * GP41 == RTS       is output
- * GP42 == USB_OK    is input
- * GP45 == USB_ACT   is output
- * GP46 == RXD       is input
- * GP47 == TXD       is output
- * GP49 == nPWE      is output
- * GP58 == nCPUBUSINT is input
- * GP59 == LANINT    is input
- * GP60 == PLLEN     is output
- * GP61 == LED_A     is output
- * GP62 == LED_B     is output
- * GP63 == TDM_OE    is output
- * GP64 == nDSPINT   is input
- * GP65 == STRAP0    is input
- * GP67 == STRAP1    is input
- * GP69 == STRAP2    is input
- * GP70 == STRAP3    is input
- * GP71 == STRAP4    is input
- * GP73 == SWUPD_LED is output
- * GP78 == nCS2      is output
- * GP79 == nCS3      is output
- * GP80 == nCS4      is output
- */
-#define CONFIG_SYS_GPDR0_VAL       0x03808004
-#define CONFIG_SYS_GPDR1_VAL       0xF002A282
-#define CONFIG_SYS_GPDR2_VAL       0x0001C200
-
-/* GP15 == nCS1  is AF10
- * GP18 == RDY   is AF01
- * GP23 == SCLK  is AF10
- * GP24 == SFRM  is AF10
- * GP25 == TXD   is AF10
- * GP26 == RXD   is AF01
- * GP33 == nCS5  is AF10
- * GP34 == FFRXD is AF01
- * GP35 == CTS   is AF01
- * GP39 == FFTXD is AF10
- * GP41 == RTS   is AF10
- * GP46 == RXD   is AF10
- * GP47 == TXD   is AF01
- * GP49 == nPWE  is AF10
- * GP78 == nCS2  is AF10
- * GP79 == nCS3  is AF10
- * GP80 == nCS4  is AF10
- */
-#define CONFIG_SYS_GAFR0_L_VAL     0x80000000
-#define CONFIG_SYS_GAFR0_U_VAL     0x001A8010
-#define CONFIG_SYS_GAFR1_L_VAL     0x60088058
-#define CONFIG_SYS_GAFR1_U_VAL     0x00000008
-#define CONFIG_SYS_GAFR2_L_VAL     0xA0000000
-#define CONFIG_SYS_GAFR2_U_VAL     0x00000002
-
-
-/* FIXME: set GPIO_RER/FER */
-
-/* RDH = 1
- * PH  = 1
- * VFS = 1
- * BFS = 1
- * SSS = 1
- */
-#define CONFIG_SYS_PSSR_VAL		0x37
-
-#define	CONFIG_SYS_CCCR			CCCR_L27|CCCR_M2|CCCR_N10
-#define	CONFIG_SYS_CKEN			0x0
-
-/*
- * Memory settings
- *
- * This is the configuration for nCS0/1 -> flash banks
- * configuration for nCS1:
- * [31]    0    - Slower Device
- * [30:28] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
- * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
- * [19]    1    - 16 Bit bus width
- * [18:16] 000  - nonburst RAM or FLASH
- * configuration for nCS0:
- * [15]    0    - Slower Device
- * [14:12] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
- * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
- * [03]    1    - 16 Bit bus width
- * [02:00] 000  - nonburst RAM or FLASH
- */
-#define CONFIG_SYS_MSC0_VAL		0x25b825b8 /* flash banks                   */
-
-/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
- * configuration for nCS3: DSP
- * [31]    0    - Slower Device
- * [30:28] 001  - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
- * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
- * [19]    1    - 16 Bit bus width
- * [18:16] 100  - variable latency I/O
- * configuration for nCS2: TDM-Switch
- * [15]    0    - Slower Device
- * [14:12] 101  - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
- * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
- * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
- * [03]    1    - 16 Bit bus width
- * [02:00] 100  - variable latency I/O
- */
-#define CONFIG_SYS_MSC1_VAL		0x123C593C /* TDM switch, DSP               */
-
-/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
- *
- * configuration for nCS5: LAN Controller
- * [31]    0    - Slower Device
- * [30:28] 001  - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
- * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
- * [19]    1    - 16 Bit bus width
- * [18:16] 100  - variable latency I/O
- * configuration for nCS4: ExtBus
- * [15]    0    - Slower Device
- * [14:12] 110  - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
- * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
- * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
- * [03]    1    - 16 Bit bus width
- * [02:00] 100  - variable latency I/O
- */
-#define CONFIG_SYS_MSC2_VAL		0x123C6CDC /* extra bus, LAN controller     */
-
-/* MDCNFG: SDRAM Configuration Register
- *
- * [31:29]   000 - reserved
- * [28]      0	 - no SA1111 compatiblity mode
- * [27]      0   - latch return data with return clock
- * [26]      0   - alternate addressing for pair 2/3
- * [25:24]   00  - timings
- * [23]      0   - internal banks in lower partition 2/3 (not used)
- * [22:21]   00  - row address bits for partition 2/3 (not used)
- * [20:19]   00  - column address bits for partition 2/3 (not used)
- * [18]      0   - SDRAM partition 2/3 width is 32 bit
- * [17]      0   - SDRAM partition 3 disabled
- * [16]      0   - SDRAM partition 2 disabled
- * [15:13]   000 - reserved
- * [12]      1	 - SA1111 compatiblity mode
- * [11]      1   - latch return data with return clock
- * [10]      0   - no alternate addressing for pair 0/1
- * [09:08]   01  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
- * [7]       1   - 4 internal banks in lower partition pair
- * [06:05]   10  - 13 row address bits for partition 0/1
- * [04:03]   01  - 9 column address bits for partition 0/1
- * [02]      0   - SDRAM partition 0/1 width is 32 bit
- * [01]      0   - disable SDRAM partition 1
- * [00]      1   - enable  SDRAM partition 0
- */
-/* use the configuration above but disable partition 0 */
-#define CONFIG_SYS_MDCNFG_VAL		0x000019c8
-
-/* MDREFR: SDRAM Refresh Control Register
- *
- * [32:26] 0     - reserved
- * [25]    0     - K2FREE: not free running
- * [24]    0     - K1FREE: not free running
- * [23]    1     - K0FREE: not free running
- * [22]    0     - SLFRSH: self refresh disabled
- * [21]    0     - reserved
- * [20]    0     - APD: no auto power down
- * [19]    0     - K2DB2: SDCLK2 is MemClk
- * [18]    0     - K2RUN: disable SDCLK2
- * [17]    0     - K1DB2: SDCLK1 is MemClk
- * [16]    1     - K1RUN: enable SDCLK1
- * [15]    1     - E1PIN: SDRAM clock enable
- * [14]    1     - K0DB2: SDCLK0 is MemClk
- * [13]    0     - K0RUN: disable SDCLK0
- * [12]    1     - E0PIN: disable SDCKE0
- * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
- */
-#define CONFIG_SYS_MDREFR_VAL		0x0081D018
-
-/* MDMRS: Mode Register Set Configuration Register
- *
- * [31]      0       - reserved
- * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
- * [22:20]   000     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
- * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
- * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
- * [15]      0       - reserved
- * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
- * [06:04]   010     - MDCL0:  SDRAM0/1 Cas Latency.
- * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
- * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
- */
-#define CONFIG_SYS_MDMRS_VAL		0x00020022
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL		0x00000000
-#define CONFIG_SYS_MCMEM0_VAL		0x00000000
-#define CONFIG_SYS_MCMEM1_VAL		0x00000000
-#define CONFIG_SYS_MCATT0_VAL		0x00000000
-#define CONFIG_SYS_MCATT1_VAL		0x00000000
-#define CONFIG_SYS_MCIO0_VAL		0x00000000
-#define CONFIG_SYS_MCIO1_VAL		0x00000000
-
-#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
-#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
-
-/*
-#define CSB226_USER_LED0	0x00000008
-#define CSB226_USER_LED1	0x00000010
-#define CSB226_USER_LED2	0x00000020
-*/
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS     1	/* max number of memory banks       */
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sect. on one chip  */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase       */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Write       */
-
-#endif  /* __CONFIG_H */
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
index 61b8761..a1fdbb8 100644
--- a/include/configs/integratorap.h
+++ b/include/configs/integratorap.h
@@ -37,6 +37,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
+#define CONFIG_SYS_TEXT_BASE		0x01000000
 #define CONFIG_SYS_MEMTEST_START	0x100000
 #define CONFIG_SYS_MEMTEST_END		0x10000000
 #define CONFIG_SYS_HZ			1000
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
index 7ae34b7..ccbdf44 100644
--- a/include/configs/integratorcp.h
+++ b/include/configs/integratorcp.h
@@ -37,6 +37,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
+#define CONFIG_SYS_TEXT_BASE		0x01000000
 #define CONFIG_SYS_MEMTEST_START	0x100000
 #define CONFIG_SYS_MEMTEST_END		0x10000000
 #define CONFIG_SYS_HZ			1000
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
new file mode 100644
index 0000000..d4bd207
--- /dev/null
+++ b/include/configs/m28evk.h
@@ -0,0 +1,303 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __M28_H__
+#define __M28_H__
+
+#include <asm/arch/regs-base.h>
+
+/*
+ * SoC configurations
+ */
+#define	CONFIG_MX28				/* i.MX28 SoC */
+#define	CONFIG_MXS_GPIO				/* GPIO control */
+#define	CONFIG_SYS_HZ		1000		/* Ticks per second */
+
+/*
+ * Define M28EVK machine type by hand until it lands in mach-types
+ */
+#define	MACH_TYPE_M28EVK	3613
+
+#define	CONFIG_MACH_TYPE	MACH_TYPE_M28EVK
+
+#define	CONFIG_SYS_NO_FLASH
+#define	CONFIG_SYS_ICACHE_OFF
+#define	CONFIG_SYS_DCACHE_OFF
+#define	CONFIG_BOARD_EARLY_INIT_F
+#define	CONFIG_ARCH_CPU_INIT
+#define	CONFIG_ARCH_MISC_INIT
+
+/*
+ * SPL
+ */
+#define	CONFIG_SPL
+#define	CONFIG_SPL_NO_CPU_SUPPORT_CODE
+#define	CONFIG_SPL_START_S_PATH		"board/denx/m28evk"
+#define	CONFIG_SPL_LDSCRIPT		"board/denx/m28evk/u-boot-spl.lds"
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+#define	CONFIG_DISPLAY_CPUINFO
+#define	CONFIG_DOS_PARTITION
+
+#define	CONFIG_CMD_CACHE
+#define	CONFIG_CMD_DATE
+#define	CONFIG_CMD_DHCP
+#define	CONFIG_CMD_EEPROM
+#define	CONFIG_CMD_EXT2
+#define	CONFIG_CMD_FAT
+#define	CONFIG_CMD_GPIO
+#define	CONFIG_CMD_I2C
+#define	CONFIG_CMD_MII
+#define	CONFIG_CMD_MMC
+#define	CONFIG_CMD_NAND
+#define	CONFIG_CMD_NET
+#define	CONFIG_CMD_NFS
+#define	CONFIG_CMD_PING
+#define	CONFIG_CMD_SETEXPR
+#define	CONFIG_CMD_SF
+#define	CONFIG_CMD_SPI
+#define	CONFIG_CMD_USB
+
+/*
+ * Memory configurations
+ */
+#define	CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
+#define	PHYS_SDRAM_1			0x40000000	/* Base address */
+#define	PHYS_SDRAM_1_SIZE		0x40000000	/* Max 1 GB RAM */
+#define	CONFIG_STACKSIZE		0x00010000	/* 128 KB stack */
+#define	CONFIG_SYS_MALLOC_LEN		0x00400000	/* 4 MB for malloc */
+#define	CONFIG_SYS_GBL_DATA_SIZE	128		/* Initial data */
+#define	CONFIG_SYS_MEMTEST_START	0x40000000	/* Memtest start adr */
+#define	CONFIG_SYS_MEMTEST_END		0x40400000	/* 4 MB RAM test */
+#define	CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+/* Point initial SP in SRAM so SPL can use it too. */
+#define	CONFIG_SYS_INIT_SP_ADDR		0x00002000
+/*
+ * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
+ * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
+ * binary. In case there was more of this mess, 0x100 bytes are skipped.
+ */
+#define	CONFIG_SYS_TEXT_BASE		0x40000100
+
+/*
+ * U-Boot general configurations
+ */
+#define	CONFIG_SYS_LONGHELP
+#define	CONFIG_SYS_PROMPT	"=> "
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
+#define	CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+						/* Print buffer size */
+#define	CONFIG_SYS_MAXARGS	32		/* Max number of command args */
+#define	CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+#define	CONFIG_VERSION_VARIABLE			/* U-BOOT version */
+#define	CONFIG_AUTO_COMPLETE			/* Command auto complete */
+#define	CONFIG_CMDLINE_EDITING			/* Command history etc */
+#define	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/*
+ * Serial Driver
+ */
+#define	CONFIG_PL011_SERIAL
+#define	CONFIG_PL011_CLOCK		24000000
+#define	CONFIG_PL01x_PORTS		{ (void *)MXS_UARTDBG_BASE }
+#define	CONFIG_CONS_INDEX		0
+#define	CONFIG_BAUDRATE			115200	/* Default baud rate */
+#define	CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * MMC Driver
+ */
+#ifdef	CONFIG_CMD_MMC
+#define	CONFIG_MMC
+#define	CONFIG_GENERIC_MMC
+#define	CONFIG_MXS_MMC
+#endif
+
+/*
+ * NAND
+ */
+#ifdef	CONFIG_CMD_NAND
+#define	CONFIG_NAND_MXS
+#define CONFIG_APBH_DMA
+#define	CONFIG_SYS_MAX_NAND_DEVICE	1
+#define	CONFIG_SYS_NAND_BASE		0x60000000
+#define	CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define	NAND_MAX_CHIPS			8
+
+/* Environment is in NAND */
+#define	CONFIG_ENV_IS_IN_NAND
+#define	CONFIG_ENV_SIZE			(16 * 1024)
+#define	CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define	CONFIG_ENV_SECT_SIZE		(128 * 1024)
+#define	CONFIG_ENV_RANGE		(512 * 1024)
+#define	CONFIG_ENV_OFFSET		0x300000
+#define	CONFIG_ENV_OFFSET_REDUND	\
+		(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+
+#define	CONFIG_CMD_UBI
+#define	CONFIG_CMD_UBIFS
+#define	CONFIG_CMD_MTDPARTS
+#define	CONFIG_RBTREE
+#define	CONFIG_LZO
+#define	CONFIG_MTD_DEVICE
+#define	CONFIG_MTD_PARTITIONS
+#define	MTDIDS_DEFAULT			"nand0=gpmi-nand.0"
+#define	MTDPARTS_DEFAULT			\
+	"mtdparts=gpmi-nand.0:"			\
+		"3m(bootloader)ro,"		\
+		"512k(environment),"		\
+		"512k(redundant-environment),"	\
+		"4m(kernel),"			\
+		"-(filesystem)"
+#endif
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#ifdef	CONFIG_CMD_NET
+#define	CONFIG_NET_MULTI
+#define	CONFIG_ETHPRIME			"FEC0"
+#define	CONFIG_FEC_MXC
+#define	CONFIG_FEC_MXC_MULTI
+#define	CONFIG_MII
+#define	CONFIG_DISCOVER_PHY
+#define	CONFIG_FEC_XCV_TYPE		RMII
+#endif
+
+/*
+ * I2C
+ */
+#ifdef	CONFIG_CMD_I2C
+#define	CONFIG_I2C_MXS
+#define	CONFIG_HARD_I2C
+#define	CONFIG_SYS_I2C_SPEED		400000
+#endif
+
+/*
+ * EEPROM
+ */
+#ifdef	CONFIG_CMD_EEPROM
+#define	CONFIG_SYS_I2C_MULTI_EEPROMS
+#define	CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#endif
+
+/*
+ * RTC
+ */
+#ifdef	CONFIG_CMD_DATE
+/* Use the internal RTC in the MXS chip */
+#define	CONFIG_RTC_INTERNAL
+#ifdef	CONFIG_RTC_INTERNAL
+#define	CONFIG_RTC_MXS
+#else
+#define	CONFIG_RTC_M41T62
+#define	CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define	CONFIG_SYS_M41T11_BASE_YEAR	2000
+#endif
+#endif
+
+/*
+ * USB
+ */
+#ifdef	CONFIG_CMD_USB
+#define	CONFIG_USB_EHCI
+#define	CONFIG_USB_EHCI_MXS
+#define	CONFIG_EHCI_MXS_PORT		1
+#define	CONFIG_EHCI_IS_TDI
+#define	CONFIG_USB_STORAGE
+#endif
+
+/*
+ * SPI
+ */
+#ifdef	CONFIG_CMD_SPI
+#define	CONFIG_HARD_SPI
+#define	CONFIG_MXS_SPI
+#define	CONFIG_SPI_HALF_DUPLEX
+#define	CONFIG_DEFAULT_SPI_BUS		2
+#define	CONFIG_DEFAULT_SPI_MODE		SPI_MODE_0
+
+/* SPI FLASH */
+#ifdef	CONFIG_CMD_SF
+#define	CONFIG_SPI_FLASH
+#define	CONFIG_SPI_FLASH_STMICRO
+#define	CONFIG_SPI_FLASH_CS		2
+#define	CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#define	CONFIG_SF_DEFAULT_SPEED		24000000
+
+#define	CONFIG_ENV_SPI_CS		0
+#define	CONFIG_ENV_SPI_BUS		2
+#define	CONFIG_ENV_SPI_MAX_HZ		24000000
+#define	CONFIG_ENV_SPI_MODE		SPI_MODE_0
+#endif
+#endif
+
+/*
+ * Boot Linux
+ */
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+#define	CONFIG_BOOTDELAY	3
+#define	CONFIG_BOOTFILE		"uImage"
+#define	CONFIG_BOOTARGS		"console=ttyAM0,115200n8 "
+#define	CONFIG_BOOTCOMMAND	"run bootcmd_net"
+#define	CONFIG_LOADADDR		0x42000000
+#define	CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/*
+ * Extra Environments
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"update_nand_full_filename=u-boot.nand\0"			\
+	"update_nand_firmware_filename=u-boot.sb\0"			\
+	"update_nand_firmware_maxsz=0x100000\0"				\
+	"update_nand_stride=0x40\0"	/* MX28 datasheet ch. 12.12 */	\
+	"update_nand_count=0x4\0"	/* MX28 datasheet ch. 12.12 */	\
+	"update_nand_get_fcb_size="	/* Get size of FCB blocks */	\
+		"nand device 0 ; "					\
+		"nand info ; "						\
+		"setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \
+		"setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \
+	"update_nand_full="		/* Update FCB, DBBT and FW */	\
+		"if tftp ${update_nand_full_filename} ; then "		\
+		"run update_nand_get_fcb_size ; "			\
+		"nand scrub -y 0x0 ${filesize} ; "			\
+		"nand write.raw ${loadaddr} 0x0 ${update_nand_fcb} ; "	\
+		"setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
+		"setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
+		"nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
+		"fi\0"							\
+	"update_nand_firmware="		/* Update only firmware */	\
+		"if tftp ${update_nand_firmware_filename} ; then "	\
+		"run update_nand_get_fcb_size ; "			\
+		"setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \
+		"setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; "	\
+		"setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \
+		"nand erase ${fcb_sz} ${fw_sz} ; "			\
+		"nand write ${loadaddr} ${fcb_sz} ${filesize} ; "	\
+		"nand write ${loadaddr} ${fw_off} ${filesize} ; "	\
+		"fi\0"
+
+#endif /* __M28_H__ */
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index ebb572e..15e40c5 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -215,7 +215,7 @@
 	"rdaddr=0x81000000\0" \
 	"usbtty=cdc_acm\0" \
 	"bootfile=uImage.beagle\0" \
-	"console=ttyS2,115200n8\0" \
+	"console=tty02,115200n8\0" \
 	"mpurate=auto\0" \
 	"buddy=none "\
 	"optargs=\0" \
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index f535769..42a8f10 100644
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -39,7 +39,7 @@
 
 /* Get CPU defs */
 #include <asm/arch/cpu.h>
-#include <asm/arch/omap4.h>
+#include <asm/arch/omap.h>
 
 /* Display CPU and Board Info */
 #define CONFIG_DISPLAY_CPUINFO		1
@@ -122,6 +122,9 @@
 /* Flash */
 #define CONFIG_SYS_NO_FLASH	1
 
+/* clocks */
+#define CONFIG_SYS_CLOCKS_ENABLE_ALL
+
 /* commands to include */
 #include <config_cmd_default.h>
 
@@ -278,4 +281,6 @@
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
 
+#define CONFIG_SYS_ENABLE_PADS_ALL
+
 #endif /* __CONFIG_OMAP4_COMMON_H */
diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h
new file mode 100644
index 0000000..b763f01
--- /dev/null
+++ b/include/configs/omap5_evm.h
@@ -0,0 +1,284 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated.
+ * Sricharan R	  <r.sricharan@ti.com>
+ *
+ * Derived from OMAP4 done by:
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * Configuration settings for the TI EVM5430 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP	/* in a TI OMAP core */
+#define CONFIG_OMAP54XX	/* which is a 54XX */
+#define CONFIG_OMAP5430	/* which is in a 5430 */
+#define CONFIG_5430EVM	/* working with EVM */
+#define CONFIG_ARCH_CPU_INIT
+
+/* Get CPU defs */
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap.h>
+
+/* Display CPU and Board Info */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK	38400000 /* Clock output from T2 */
+#define V_SCLK	V_OSCK
+
+#undef CONFIG_USE_IRQ	/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ * Total Size Environment - 128k
+ * Malloc - add 256k
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (256 << 10))
+/* Vector Base */
+#define CONFIG_SYS_CA9_VECTOR_BASE	SRAM_ROM_VECT_BASE
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * serial port - NS16550 compatible
+ */
+#define V_NS16550_CLK			48000000
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		UART3_BASE
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+/* I2C  */
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_DRIVER_OMAP34XX_I2C
+#define CONFIG_I2C_MULTI_BUS
+
+/* TWL6030 */
+#define CONFIG_TWL6030_POWER
+#define CONFIG_CMD_BAT
+
+/* MMC */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* MMC ENV related defines */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		1	/* SLOT2: eMMC(1) */
+#define CONFIG_ENV_OFFSET		0xE0000
+
+/* USB */
+#define CONFIG_MUSB_UDC
+#define CONFIG_USB_OMAP3
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE
+#define CONFIG_USB_TTY
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* Flash */
+#define CONFIG_SYS_NO_FLASH
+
+/* Cache */
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#define CONFIG_SYS_CACHELINE_SHIFT	6
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+/* Enabled commands */
+#define CONFIG_CMD_EXT2		/* EXT2 Support                 */
+#define CONFIG_CMD_FAT		/* FAT support                  */
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support                  */
+#define CONFIG_CMD_SAVEENV
+
+/* Disabled commands */
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support   */
+#undef CONFIG_CMD_IMLS		/* List all found images        */
+
+/*
+ * Environment setup
+ */
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyS2,115200n8\0" \
+	"usbtty=cdc_acm\0" \
+	"vram=16M\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"vram=${vram} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc${mmcdev} ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc rescan ${mmcdev}; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"fi; " \
+		"fi; " \
+	"fi"
+
+#define CONFIG_AUTO_COMPLETE		1
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER	/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"OMAP5430 EVM # "
+#define CONFIG_SYS_CBSIZE		256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+/*
+ * memtest setup
+ */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (32 << 20))
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x80000000
+
+/* Use General purpose timer 1 */
+#define CONFIG_SYS_TIMERBASE		GPT2_BASE
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 << 10)	/* Regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack */
+#endif
+
+/*
+ * SDRAM Memory Map
+ * Even though we use two CS all the memory
+ * is mapped to one contiguous block
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4030D800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+
+/* Defines for SDRAM init */
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+#endif
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_TEXT_BASE		0x40304350
+#define CONFIG_SPL_MAX_SIZE		0x1E000	/* 120K */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+#define CONFIG_SYS_SPL_MALLOC_START     0x80200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000        /* 1 MB */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 89e17b8..55455e7 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -52,6 +52,9 @@
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
 #define CONFIG_SYS_TEXT_BASE	0
 
+#define MACH_TYPE_PM9261	1187
+#define CONFIG_MACH_TYPE	MACH_TYPE_PM9261
+
 /* clocks */
 /* CKGR_MOR - enable main osc. */
 #define CONFIG_SYS_MOR_VAL						\
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 1f7543c..43104a3 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -52,6 +52,9 @@
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
 #define CONFIG_SYS_TEXT_BASE	0
 
+#define MACH_TYPE_PM9263	1475
+#define CONFIG_MACH_TYPE	MACH_TYPE_PM9263
+
 /* clocks */
 #define CONFIG_SYS_MOR_VAL						\
 		(AT91_PMC_MOR_MOSCEN |					\
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index acc1204..d3beaf3 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -41,6 +41,9 @@
 #define CONFIG_PM9G45		1	/* It's an Ronetix PM9G45 */
 #define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9G45"
 
+#define MACH_TYPE_PM9G45	2672
+#define CONFIG_MACH_TYPE	MACH_TYPE_PM9G45
+
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	12000000 /* from 12 MHz crystal */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
index 9db4d99..dd68c66 100644
--- a/include/configs/vpac270.h
+++ b/include/configs/vpac270.h
@@ -107,7 +107,8 @@
  */
 #ifdef	CONFIG_CMD_MMC
 #define	CONFIG_MMC
-#define	CONFIG_PXA_MMC
+#define	CONFIG_GENERIC_MMC
+#define	CONFIG_PXA_MMC_GENERIC
 #define	CONFIG_SYS_MMC_BASE		0xF0000000
 #define	CONFIG_CMD_FAT
 #define	CONFIG_CMD_EXT2
diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h
index 92279d5..f321d8a 100644
--- a/include/onenand_uboot.h
+++ b/include/onenand_uboot.h
@@ -52,4 +52,7 @@ extern int flexonenand_set_boundary(struct mtd_info *mtd, int die,
 extern void s3c64xx_onenand_init(struct mtd_info *);
 extern void s3c64xx_set_width_regs(struct onenand_chip *);
 
+/* SPL */
+void onenand_spl_load_image(uint32_t offs, uint32_t size, void *dst);
+
 #endif /* __UBOOT_ONENAND_H */