diff options
| author | wdenk <wdenk> | 2004-08-01 13:09:47 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2004-08-01 13:09:47 +0000 |
| commit | cfca5e604d5692f081cc1a9185ca5dc6dc77599d (patch) | |
| tree | 3e8b3448cbc57a26f1f5ee8d3b28214740f6cedc /include | |
| parent | 45eeb8983c3eca0e82178897c027a34a52295a0f (diff) | |
| download | u-boot-imx-cfca5e604d5692f081cc1a9185ca5dc6dc77599d.zip u-boot-imx-cfca5e604d5692f081cc1a9185ca5dc6dc77599d.tar.gz u-boot-imx-cfca5e604d5692f081cc1a9185ca5dc6dc77599d.tar.bz2 | |
* Fix NSCU config; add ethernet wakeup code.
* Add link for preloader for Motorola Coldfire to RAEDME.m68k
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/NSCU.h | 42 |
1 files changed, 6 insertions, 36 deletions
diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h index 930a5be..f13cb34 100644 --- a/include/configs/NSCU.h +++ b/include/configs/NSCU.h @@ -45,8 +45,6 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */ - #define CONFIG_BOARD_TYPES 1 /* support board types */ #define CONFIG_PREBOOT "echo;" \ @@ -75,6 +73,8 @@ "" #define CONFIG_BOOTCOMMAND "run flash_self" +#define CONFIG_MISC_INIT_R 1 + #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ @@ -252,15 +252,8 @@ *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! */ -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_PLPRCR \ - ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) -#else /* up to 66 MHz we use a 1:1 clock */ #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -269,17 +262,9 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_SCCR (/* SCCR_TBS | */ \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#else /* up to 66 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * PCMCIA stuff @@ -355,19 +340,8 @@ /* * FLASH timing: */ -#if defined(CONFIG_80MHz) -/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) -#elif defined(CONFIG_66MHz) -/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ OR_SCY_3_CLK | OR_EHTR | OR_BI) -#else /* 50 MHz */ -/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -#endif /*CONFIG_??MHz */ #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -437,13 +411,9 @@ * 66 Mhz => 66.000.000 / Divider = 129 * 80 Mhz => 80.000.000 / Divider = 156 */ -#if defined(CONFIG_80MHz) -#define CFG_MAMR_PTA 156 -#elif defined(CONFIG_66MHz) -#define CFG_MAMR_PTA 129 -#else /* 50 MHz */ -#define CFG_MAMR_PTA 98 -#endif /*CONFIG_??MHz */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 /* * For 16 MBit, refresh rates could be 31.3 us |