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| author | Peter Tyser <ptyser@xes-inc.com> | 2010-09-29 13:37:28 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-10-20 02:38:40 -0500 |
| commit | 06412756e76aeceb44168966fd5d5d660162881f (patch) | |
| tree | 593594fb20f3c489e13b4c06c2d4517dad7c3975 /include | |
| parent | 4e339b83e9812a1cff825735a55c8cb21d807b64 (diff) | |
| download | u-boot-imx-06412756e76aeceb44168966fd5d5d660162881f.zip u-boot-imx-06412756e76aeceb44168966fd5d5d660162881f.tar.gz u-boot-imx-06412756e76aeceb44168966fd5d5d660162881f.tar.bz2 | |
tqm85xx: Update PCI code
Update to use the recent, common FSL PCI initialization code.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
CC: sr@denx.de
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/TQM85xx.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 59655b1..d5c116f 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -380,11 +380,11 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE (CONFIG_SYS_CCSRBAR + 0x02000000) -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE +#define CONFIG_SYS_PCI1_IO_BUS (CONFIG_SYS_CCSRBAR + 0x02000000) +#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ #ifdef CONFIG_PCIE1 @@ -393,16 +393,16 @@ * Addresses are mapped 1-1. */ #ifdef CONFIG_TQM_BIGFLASH -#define CONFIG_SYS_PCIE1_MEM_BASE 0xb0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xb0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0xaf000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0xaf000000 #else /* !CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_PCIE1_MEM_BASE 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0xef000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0xef000000 #endif /* CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE -#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BASE +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ #endif /* CONFIG_PCIE1 */ |