diff options
| author | Markus Klotzbuecher <mk@denx.de> | 2006-03-24 15:43:16 +0100 |
|---|---|---|
| committer | Markus Klotzbücher <mk@pollux.denx.de> | 2006-03-24 15:43:16 +0100 |
| commit | 2770bcb21c82835a5351176e5b2a9221d7fc8ef9 (patch) | |
| tree | 78edf9afc584e1a76d219bd64d260224a84f0d10 /include | |
| parent | 0b953ffc653fc5ab3d3fa47abf0dd9b8bd0703f5 (diff) | |
| parent | 05d8dce9d07cf4073ea15fbc448c1ce22b6baf0f (diff) | |
| download | u-boot-imx-2770bcb21c82835a5351176e5b2a9221d7fc8ef9.zip u-boot-imx-2770bcb21c82835a5351176e5b2a9221d7fc8ef9.tar.gz u-boot-imx-2770bcb21c82835a5351176e5b2a9221d7fc8ef9.tar.bz2 | |
Merge with http://www.denx.de/git/u-boot.git
Diffstat (limited to 'include')
86 files changed, 9094 insertions, 191 deletions
diff --git a/include/asm-arm/arch-arm720t/s3c4510b.h b/include/asm-arm/arch-arm720t/s3c4510b.h index 517b1ad..73a3b6d 100644 --- a/include/asm-arm/arch-arm720t/s3c4510b.h +++ b/include/asm-arm/arch-arm720t/s3c4510b.h @@ -267,8 +267,6 @@ struct _irq_handler { void (*m_func)( void *data); }; -extern struct _irq_handler IRQ_HANDLER[]; - #endif #endif /* __S3C4510_h */ diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h new file mode 100644 index 0000000..65d2c25 --- /dev/null +++ b/include/asm-blackfin/bitops.h @@ -0,0 +1,380 @@ +/* + * U-boot - bitops.h Routines for bit operations + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_BITOPS_H +#define _BLACKFIN_BITOPS_H + +/* + * Copyright 1992, Linus Torvalds. + */ + +#include <linux/config.h> +#include <asm/byteorder.h> +#include <asm/system.h> + +#ifdef __KERNEL__ +/* + * Function prototypes to keep gcc -Wall happy + */ + +/* + * The __ functions are not atomic + */ + +/* + * ffz = Find First Zero in word. Undefined if no zero exists, + * so code should check against ~0UL first.. + */ +static __inline__ unsigned long ffz(unsigned long word) +{ + unsigned long result = 0; + + while (word & 1) { + result++; + word >>= 1; + } + return result; +} + +static __inline__ void set_bit(int nr, volatile void *addr) +{ + int *a = (int *) addr; + int mask; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_and_cli(flags); + *a |= mask; + restore_flags(flags); +} + +static __inline__ void __set_bit(int nr, volatile void *addr) +{ + int *a = (int *) addr; + int mask; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a |= mask; +} + +/* + * clear_bit() doesn't provide any barrier for the compiler. + */ +#define smp_mb__before_clear_bit() barrier() +#define smp_mb__after_clear_bit() barrier() + +static __inline__ void clear_bit(int nr, volatile void *addr) +{ + int *a = (int *) addr; + int mask; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_and_cli(flags); + *a &= ~mask; + restore_flags(flags); +} + +static __inline__ void change_bit(int nr, volatile void *addr) +{ + int mask, flags; + unsigned long *ADDR = (unsigned long *) addr; + + ADDR += nr >> 5; + mask = 1 << (nr & 31); + save_and_cli(flags); + *ADDR ^= mask; + restore_flags(flags); +} + +static __inline__ void __change_bit(int nr, volatile void *addr) +{ + int mask; + unsigned long *ADDR = (unsigned long *) addr; + + ADDR += nr >> 5; + mask = 1 << (nr & 31); + *ADDR ^= mask; +} + +static __inline__ int test_and_set_bit(int nr, volatile void *addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_and_cli(flags); + retval = (mask & *a) != 0; + *a |= mask; + restore_flags(flags); + + return retval; +} + +static __inline__ int __test_and_set_bit(int nr, volatile void *addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a |= mask; + return retval; +} + +static __inline__ int test_and_clear_bit(int nr, volatile void *addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_and_cli(flags); + retval = (mask & *a) != 0; + *a &= ~mask; + restore_flags(flags); + + return retval; +} + +static __inline__ int __test_and_clear_bit(int nr, volatile void *addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a &= ~mask; + return retval; +} + +static __inline__ int test_and_change_bit(int nr, volatile void *addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_and_cli(flags); + retval = (mask & *a) != 0; + *a ^= mask; + restore_flags(flags); + + return retval; +} + +static __inline__ int __test_and_change_bit(int nr, volatile void *addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a ^= mask; + return retval; +} + +/* + * This routine doesn't need to be atomic. + */ +static __inline__ int __constant_test_bit(int nr, + const volatile void *addr) +{ + return ((1UL << (nr & 31)) & + (((const volatile unsigned int *) addr)[nr >> 5])) != 0; +} + +static __inline__ int __test_bit(int nr, volatile void *addr) +{ + int *a = (int *) addr; + int mask; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + return ((mask & *a) != 0); +} + +#define test_bit(nr,addr) \ +(__builtin_constant_p(nr) ? \ + __constant_test_bit((nr),(addr)) : \ + __test_bit((nr),(addr))) + +#define find_first_zero_bit(addr, size) \ + find_next_zero_bit((addr), (size), 0) + +static __inline__ int find_next_zero_bit(void *addr, int size, int offset) +{ + unsigned long *p = ((unsigned long *) addr) + (offset >> 5); + unsigned long result = offset & ~31UL; + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if (offset) { + tmp = *(p++); + tmp |= ~0UL >> (32 - offset); + if (size < 32) + goto found_first; + if (~tmp) + goto found_middle; + size -= 32; + result += 32; + } + while (size & ~31UL) { + if (~(tmp = *(p++))) + goto found_middle; + result += 32; + size -= 32; + } + if (!size) + return result; + tmp = *p; + + found_first: + tmp |= ~0UL >> size; + found_middle: + return result + ffz(tmp); +} + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ + +#define ffs(x) generic_ffs(x) + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +static __inline__ int ext2_set_bit(int nr, volatile void *addr) +{ + int mask, retval; + unsigned long flags; + volatile unsigned char *ADDR = (unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + save_and_cli(flags); + retval = (mask & *ADDR) != 0; + *ADDR |= mask; + restore_flags(flags); + return retval; +} + +static __inline__ int ext2_clear_bit(int nr, volatile void *addr) +{ + int mask, retval; + unsigned long flags; + volatile unsigned char *ADDR = (unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + save_and_cli(flags); + retval = (mask & *ADDR) != 0; + *ADDR &= ~mask; + restore_flags(flags); + return retval; +} + +static __inline__ int ext2_test_bit(int nr, const volatile void *addr) +{ + int mask; + const volatile unsigned char *ADDR = (const unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + return ((mask & *ADDR) != 0); +} + +#define ext2_find_first_zero_bit(addr, size) \ + ext2_find_next_zero_bit((addr), (size), 0) + +static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, + unsigned long size, + unsigned long + offset) +{ + unsigned long *p = ((unsigned long *) addr) + (offset >> 5); + unsigned long result = offset & ~31UL; + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if (offset) { + tmp = *(p++); + tmp |= ~0UL >> (32 - offset); + if (size < 32) + goto found_first; + if (~tmp) + goto found_middle; + size -= 32; + result += 32; + } + while (size & ~31UL) { + if (~(tmp = *(p++))) + goto found_middle; + result += 32; + size -= 32; + } + if (!size) + return result; + tmp = *p; + + found_first: + tmp |= ~0UL >> size; + found_middle: + return result + ffz(tmp); +} + +/* Bitmap functions for the minix filesystem. */ +#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) +#define minix_set_bit(nr,addr) set_bit(nr,addr) +#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) +#define minix_test_bit(nr,addr) test_bit(nr,addr) +#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) + +#endif + +#endif diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h new file mode 100644 index 0000000..fbdbf30 --- /dev/null +++ b/include/asm-blackfin/blackfin.h @@ -0,0 +1,46 @@ +/* + * U-boot - blackfin.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_H_ +#define _BLACKFIN_H_ + +#include <asm/cpu/defBF533.h> +#include <asm/cpu/bf533_serial.h> + +#ifndef __ASSEMBLY__ +#ifndef ASSEMBLY + +#ifdef SHARED_RESOURCES + #include <asm/shared_resources.h> +#endif +#include <asm/cpu/cdefBF53x.h> + +#endif +#endif + +#include <asm/cpu/defBF533.h> +#include <asm/cpu/defBF533_extn.h> +#include <asm/cpu/bf533_serial.h> + +#endif diff --git a/include/asm-blackfin/blackfin_defs.h b/include/asm-blackfin/blackfin_defs.h new file mode 100644 index 0000000..2190215 --- /dev/null +++ b/include/asm-blackfin/blackfin_defs.h @@ -0,0 +1,83 @@ +/* + * U-boot - blackfin_defs.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BLACKFIN_DEFS_H__ +#define __BLACKFIN_DEFS_H__ + +#define TS_MAGICKEY 0x5a5a5a5a +#define TASK_STATE 0 +#define TASK_FLAGS 4 +#define TASK_PTRACE 24 +#define TASK_BLOCKED 636 +#define TASK_COUNTER 32 +#define TASK_SIGPENDING 8 +#define TASK_NEEDRESCHED 20 +#define TASK_THREAD 600 +#define TASK_MM 44 +#define TASK_ACTIVE_MM 80 +#define THREAD_KSP 0 +#define THREAD_USP 4 +#define THREAD_SR 8 +#define THREAD_ESP0 12 +#define THREAD_PC 16 +#define PT_ORIG_R0 208 +#define PT_R0 204 +#define PT_R1 200 +#define PT_R2 196 +#define PT_R3 192 +#define PT_R4 188 +#define PT_R5 184 +#define PT_R6 180 +#define PT_R7 176 +#define PT_P0 172 +#define PT_P1 168 +#define PT_P2 164 +#define PT_P3 160 +#define PT_P4 156 +#define PT_P5 152 +#define PT_A0w 72 +#define PT_A1w 64 +#define PT_A0x 76 +#define PT_A1x 68 +#define PT_RETS 28 +#define PT_RESERVED 32 +#define PT_ASTAT 36 +#define PT_SEQSTAT 8 +#define PT_PC 24 +#define PT_IPEND 0 +#define PT_USP 144 +#define PT_FP 148 +#define PT_SYSCFG 4 +#define IRQ_HANDLER 0 +#define IRQ_DEVID 8 +#define IRQ_NEXT 16 +#define STAT_IRQ 5148 +#define SIGSEGV 11 +#define SEGV_MAPERR 196609 +#define SIGTRAP 5 +#define PT_PTRACED 1 +#define PT_TRACESYS 2 +#define PT_DTRACE 4 + +#endif diff --git a/include/asm-blackfin/byteorder.h b/include/asm-blackfin/byteorder.h new file mode 100644 index 0000000..3b4df4e --- /dev/null +++ b/include/asm-blackfin/byteorder.h @@ -0,0 +1,40 @@ +/* + * U-boot - byteorder.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_BYTEORDER_H +#define _BLACKFIN_BYTEORDER_H + +#include <asm/types.h> + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#include <linux/byteorder/little_endian.h> + +#endif diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h new file mode 100644 index 0000000..7715f64 --- /dev/null +++ b/include/asm-blackfin/cplb.h @@ -0,0 +1,48 @@ +/************************************************************************ + * + * cplb.h + * + * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved. + * + ************************************************************************/ + +/* Defines necessary for cplb initialisation routines. */ + +#ifndef _CPLB_H +#define _CPLB_H + +#define CPLB_ENABLE_ICACHE_P 0 +#define CPLB_ENABLE_DCACHE_P 1 +#define CPLB_ENABLE_DCACHE2_P 2 +#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated!*/ +#define CPLB_ENABLE_ICPLBS_P 4 +#define CPLB_ENABLE_DCPLBS_P 5 + +#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P) +#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P) +#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P) +#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P) +#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P) +#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P) +#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \ + CPLB_ENABLE_ICPLBS | \ + CPLB_ENABLE_DCPLBS + +#define CPLB_RELOADED 0x0000 +#define CPLB_NO_UNLOCKED 0x0001 +#define CPLB_NO_ADDR_MATCH 0x0002 +#define CPLB_PROT_VIOL 0x0003 + +#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT +#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY + +#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR + +#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID +#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID +#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID +#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE +#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID +#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL + +#endif /* _CPLB_H */ diff --git a/include/asm-blackfin/cplbtab.h b/include/asm-blackfin/cplbtab.h new file mode 100644 index 0000000..ab7d989 --- /dev/null +++ b/include/asm-blackfin/cplbtab.h @@ -0,0 +1,572 @@ +/*This file is subject to the terms and conditions of the GNU General Public + * License. + * + * Blackfin BF533/2.6 support : LG Soft India + * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd + * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's + * shouldn't be victimized. cplbmgr.S search logic is corrected + * to findout the appropriate victim. + * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC + * : LG Soft India + */ +#include <config.h> + +#ifndef __ARCH_BFINNOMMU_CPLBTAB_H +#define __ARCH_BFINNOMMU_CPLBTAB_H + +/************************************************************************* + * ICPLB TABLE + *************************************************************************/ + +.data + +/* This table is configurable */ + +.align 4; + +/* Data Attibutes*/ + +#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) +#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) + +/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ + +#define ANOMALY_05000158 0x200 +#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ + #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) + #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) + #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) + #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) + #define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) + +#else /*Write Through*/ + #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) + #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) + #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) + #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) + #define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) +#endif + +.global icplb_table +icplb_table: +.byte4 0xFFA00000; +.byte4 (L1_IMEMORY); +.byte4 0x00000000; +.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/ +.byte4 0x00400000; +.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/ +.byte4 0x07C00000; +.byte4 (SDRAM_IKERNEL); /*SDRAM_Page14*/ +.byte4 0x00800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/ +.byte4 0x00C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/ +.byte4 0x01000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/ +.byte4 0x01400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/ +.byte4 0x01800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/ +.byte4 0x01C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/ +#ifndef CONFIG_EZKIT /*STAMP Memory regions*/ +.byte4 0x02000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/ +.byte4 0x02400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/ +.byte4 0x02800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/ +.byte4 0x02C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/ +.byte4 0x03000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/ +.byte4 0x03400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/ +#endif +.byte4 0xffffffff; /* end of section - termination*/ + +.align 4; +.global ipdt_table +ipdt_table: +#ifdef CONFIG_CPLB_INFO +.byte4 0x00000000; +.byte4 (SDRAM_IKERNEL); /*SDRAM_Page0*/ +.byte4 0x00400000; +.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/ +#endif +.byte4 0x00800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/ +.byte4 0x00C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page3*/ +.byte4 0x01000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/ +.byte4 0x01400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/ +.byte4 0x01800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/ +.byte4 0x01C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/ +#ifndef CONFIG_EZKIT /*STAMP Memory regions*/ +.byte4 0x02000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/ +.byte4 0x02400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/ +.byte4 0x02800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/ +.byte4 0x02C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/ +.byte4 0x03000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/ +.byte4 0x03400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/ +.byte4 0x03800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page14*/ +.byte4 0x03C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page15*/ +#endif +.byte4 0x20200000; +.byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/ +.byte4 0x20100000; +.byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/ +.byte4 0x20000000; +.byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/ +.byte4 0x20300000; /*Fix for Network*/ +.byte4 (SDRAM_EBIU); /*Async Memory bank 3*/ + +#ifdef CONFIG_STAMP +.byte4 0x04000000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x04400000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x04800000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x04C00000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x05000000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x05400000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x05800000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x05C00000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x06000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page25*/ +.byte4 0x06400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page26*/ +.byte4 0x06800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page27*/ +.byte4 0x06C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page28*/ +.byte4 0x07000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page29*/ +.byte4 0x07400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page30*/ +.byte4 0x07800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page31*/ +#ifdef CONFIG_CPLB_INFO +.byte4 0x07C00000; +.byte4 (SDRAM_IKERNEL); /*SDRAM_Page32*/ +#endif +#endif +.byte4 0xffffffff; /* end of section - termination*/ + +/********************************************************************* + * DCPLB TABLE + ********************************************************************/ + +.global dcplb_table +dcplb_table: +.byte4 0x00000000; +.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/ +.byte4 0x00400000; +.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/ +.byte4 0x07C00000; +.byte4 (SDRAM_DKERNEL); /*SDRAM_Page15*/ +.byte4 0x00800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/ +.byte4 0x00C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/ +.byte4 0x01000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/ +.byte4 0x01400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/ +.byte4 0x01800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/ +.byte4 0x01C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/ +#ifndef CONFIG_EZKIT +.byte4 0x02000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/ +.byte4 0x02400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/ +.byte4 0x02800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/ +.byte4 0x02C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/ +.byte4 0x03000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/ +.byte4 0x03400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/ +.byte4 0x03800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/ +#endif +.byte4 0xffffffff; /*end of section - termination*/ + +/********************************************************************** + * PAGE DESCRIPTOR TABLE + * + **********************************************************************/ + +/* Till here we are discussing about the static memory management model. + * However, the operating envoronments commonly define more CPLB + * descriptors to cover the entire addressable memory than will fit into + * the available on-chip 16 CPLB MMRs. When this happens, the below table + * will be used which will hold all the potentially required CPLB descriptors + * + * This is how Page descriptor Table is implemented in uClinux/Blackfin. + */ +.global dpdt_table +dpdt_table: +#ifdef CONFIG_CPLB_INFO +.byte4 0x00000000; +.byte4 (SDRAM_DKERNEL); /*SDRAM_Page0*/ +.byte4 0x00400000; +.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/ +#endif +.byte4 0x00800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/ +.byte4 0x00C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/ +.byte4 0x01000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/ +.byte4 0x01400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/ +.byte4 0x01800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/ +.byte4 0x01C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/ + +#ifndef CONFIG_EZKIT +.byte4 0x02000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/ +.byte4 0x02400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/ +.byte4 0x02800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/ +.byte4 0x02C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/ +.byte4 0x03000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/ +.byte4 0x03400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/ +.byte4 0x03800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/ +.byte4 0x03C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page15*/ +#endif +.byte4 0x20200000; +.byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/ +.byte4 0x20100000; +.byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/ +.byte4 0x20000000; +.byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/ +.byte4 0x20300000; /*Fix for Network*/ +.byte4 (SDRAM_EBIU); /*Async Memory bank 3*/ + +#ifdef CONFIG_STAMP +.byte4 0x04000000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x04400000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x04800000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x04C00000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x05000000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x05400000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x05800000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x05C00000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x06000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page25*/ +.byte4 0x06400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page26*/ +.byte4 0x06800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page27*/ +.byte4 0x06C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page28*/ +.byte4 0x07000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page29*/ +.byte4 0x07400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page30*/ +.byte4 0x07800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page31*/ +#ifdef CONFIG_CPLB_INFO +.byte4 0x07C00000; +.byte4 (SDRAM_DKERNEL); /*SDRAM_Page32*/ +#endif +#endif + +.byte4 0xFF900000; +.byte4 (L1_DMEMORY); +.byte4 0xFF901000; +.byte4 (L1_DMEMORY); +.byte4 0xFF902000; +.byte4 (L1_DMEMORY); +.byte4 0xFF903000; +.byte4 (L1_DMEMORY); +.byte4 0xFF904000; +.byte4 (L1_DMEMORY); +.byte4 0xFF905000; +.byte4 (L1_DMEMORY); +.byte4 0xFF906000; +.byte4 (L1_DMEMORY); +.byte4 0xFF907000; +.byte4 (L1_DMEMORY); +.byte4 0xFF800000; +.byte4 (L1_DMEMORY); +.byte4 0xFF801000; +.byte4 (L1_DMEMORY); +.byte4 0xFF802000; +.byte4 (L1_DMEMORY); +.byte4 0xFF803000; +.byte4 (L1_DMEMORY); + +.byte4 0xffffffff; /*end of section - termination*/ + +#ifdef CONFIG_CPLB_INFO +.global ipdt_swapcount_table; /* swapin count first, then swapout count*/ +ipdt_swapcount_table: +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 10 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 20 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 30 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 40 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 50 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 60 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 70 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 80 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 90 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 100 */ + +.global dpdt_swapcount_table; /* swapin count first, then swapout count*/ +dpdt_swapcount_table: +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 10 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 20 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 30 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 40 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 50 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 60 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 70 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 80 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 80 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 100 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 110 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 120 */ + +#endif + +#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/ diff --git a/include/asm-blackfin/cpu/bf533_irq.h b/include/asm-blackfin/cpu/bf533_irq.h new file mode 100644 index 0000000..9c5230d --- /dev/null +++ b/include/asm-blackfin/cpu/bf533_irq.h @@ -0,0 +1,137 @@ +/* + * U-boot bf533_irq.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c + * Changed by HuTao Apr18, 2003 + * + * Copyright was missing when I got the code so took from MIPS arch ...MaTed--- + * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle + * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle + * + * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca> + * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) + * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com> + * + * Adapted for BlackFin BF533 by Bas Vermeulen <bas@buyways.nl> + * Copyright (c) 2003 BuyWays B.V. (www.buyways.nl) + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BF533_IRQ_H_ +#define _BF533_IRQ_H_ + +/* + * Interrupt source definitions + * Event Source Core Event Name Number + * EMU 0 + * Reset RST 1 + * NMI NMI 2 + * Exception EVX 3 + * Reserved -- 4 + * Hardware Error IVHW 5 + * Core Timer IVTMR 6 + * PLL Wakeup Interrupt IVG7 7 + * DMA Error (generic) IVG7 8 + * PPI Error Interrupt IVG7 9 + * SPORT0 Error Interrupt IVG7 10 + * SPORT1 Error Interrupt IVG7 11 + * SPI Error Interrupt IVG7 12 + * UART Error Interrupt IVG7 13 + * RTC Interrupt IVG8 14 + * DMA0 Interrupt (PPI) IVG8 15 + * DMA1 (SPORT0 RX) IVG9 16 + * DMA2 (SPORT0 TX) IVG9 17 + * DMA3 (SPORT1 RX) IVG9 18 + * DMA4 (SPORT1 TX) IVG9 19 + * DMA5 (PPI) IVG10 20 + * DMA6 (UART RX) IVG10 21 + * DMA7 (UART TX) IVG10 22 + * Timer0 IVG11 23 + * Timer1 IVG11 24 + * Timer2 IVG11 25 + * PF Interrupt A IVG12 26 + * PF Interrupt B IVG12 27 + * DMA8/9 Interrupt IVG13 28 + * DMA10/11 Interrupt IVG13 29 + * Watchdog Timer IVG13 30 + * Software Interrupt 1 IVG14 31 + * Software Interrupt 2 -- + * (lowest priority) IVG15 32 + */ + +/* The ABSTRACT IRQ definitions */ + +/* The first seven of the following are fixed, + * the rest you change if you need to + */ + +#define IRQ_EMU 0 /* Emulation */ +#define IRQ_RST 1 /* reset */ +#define IRQ_NMI 2 /* Non Maskable */ +#define IRQ_EVX 3 /* Exception */ +#define IRQ_UNUSED 4 /* - unused interrupt */ +#define IRQ_HWERR 5 /* Hardware Error */ +#define IRQ_CORETMR 6 /* Core timer */ +#define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */ +#define IRQ_DMA_ERROR 8 /* DMA Error (general) */ +#define IRQ_PPI_ERROR 9 /* PPI Error Interrupt */ +#define IRQ_SPORT0_ERROR 10 /* SPORT0 Error Interrupt */ +#define IRQ_SPORT1_ERROR 11 /* SPORT1 Error Interrupt */ +#define IRQ_SPI_ERROR 12 /* SPI Error Interrupt */ +#define IRQ_UART_ERROR 13 /* UART Error Interrupt */ +#define IRQ_RTC 14 /* RTC Interrupt */ +#define IRQ_PPI 15 /* DMA0 Interrupt (PPI) */ +#define IRQ_SPORT0 16 /* DMA1 Interrupt (SPORT0 RX) */ +#define IRQ_SPARE1 17 /* DMA2 Interrupt (SPORT0 TX) */ +#define IRQ_SPORT1 18 /* DMA3 Interrupt (SPORT1 RX) */ +#define IRQ_SPARE2 19 /* DMA4 Interrupt (SPORT1 TX) */ +#define IRQ_SPI 20 /* DMA5 Interrupt (SPI) */ +#define IRQ_UART 21 /* DMA6 Interrupt (UART RX) */ +#define IRQ_SPARE3 22 /* DMA7 Interrupt (UART TX) */ +#define IRQ_TMR0 23 /* Timer 0 */ +#define IRQ_TMR1 24 /* Timer 1 */ +#define IRQ_TMR2 25 /* Timer 2 */ +#define IRQ_PROG_INTA 26 /* Programmable Flags A (8) */ +#define IRQ_PROG_INTB 27 /* Programmable Flags B (8) */ +#define IRQ_MEM_DMA0 28 /* DMA8/9 Interrupt (Memory DMA Stream 0) */ +#define IRQ_MEM_DMA1 29 /* DMA10/11 Interrupt (Memory DMA Stream 1) */ +#define IRQ_WATCH 30 /* Watch Dog Timer */ +#define IRQ_SW_INT1 31 /* Software Int 1 */ +#define IRQ_SW_INT2 32 /* Software Int 2 (reserved for SYSCALL) */ + +#define IRQ_UART_RX_BIT 0x4000 +#define IRQ_UART_TX_BIT 0x8000 +#define IRQ_UART_ERROR_BIT 0x40 + +#define IVG7 7 +#define IVG8 8 +#define IVG9 9 +#define IVG10 10 +#define IVG11 11 +#define IVG12 12 +#define IVG13 13 +#define IVG14 14 +#define IVG15 15 +#define SYS_IRQS 33 + +#endif diff --git a/include/asm-blackfin/cpu/bf533_rtc.h b/include/asm-blackfin/cpu/bf533_rtc.h new file mode 100644 index 0000000..bc09922 --- /dev/null +++ b/include/asm-blackfin/cpu/bf533_rtc.h @@ -0,0 +1,46 @@ +/* + * U-boot - bf533_rtc.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BF533_RTC_H_ +#define _BF533_RTC_H_ + +void rtc_init(void); +void wait_for_complete(void); +void rtc_reset(void); + +#define MIN_TO_SECS(_x_) (60 * _x_) +#define HRS_TO_SECS(_x_) (60 * 60 * _x_) +#define DAYS_TO_SECS(_x_) (24 * 60 * 60 * _x_) + +#define NUM_SECS_IN_DAY (24 * 3600) +#define NUM_SECS_IN_HOUR (3600) +#define NUM_SECS_IN_MIN (60) + +/* Shift values for RTC_STAT register */ +#define DAY_BITS_OFF 17 +#define HOUR_BITS_OFF 12 +#define MIN_BITS_OFF 6 +#define SEC_BITS_OFF 0 + +#endif diff --git a/include/asm-blackfin/cpu/bf533_serial.h b/include/asm-blackfin/cpu/bf533_serial.h new file mode 100644 index 0000000..d5e162a --- /dev/null +++ b/include/asm-blackfin/cpu/bf533_serial.h @@ -0,0 +1,79 @@ +/* + * U-boot bf533_serial.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef _BF533_SERIAL_H_ +#define _BF533_SERIAL_H_ + +#define BYTE_REF(addr) (*((volatile char*)addr)) +#define HALFWORD_REF(addr) (*((volatile short*)addr)) +#define WORD_REF(addr) (*((volatile long*)addr)) + +#define UART_THR_LO HALFWORD_REF(UART_THR) +#define UART_RBR_LO HALFWORD_REF(UART_RBR) +#define UART_DLL_LO HALFWORD_REF(UART_DLL) +#define UART_IER_LO HALFWORD_REF(UART_IER) +#define UART_IER_ERBFI 0x01 +#define UART_IER_ETBEI 0x02 +#define UART_IER_ELSI 0x04 +#define UART_IER_EDDSI 0x08 + +#define UART_DLH_LO HALFWORD_REF(UART_DLH) +#define UART_IIR_LO HALFWORD_REF(UART_IIR) +#define UART_IIR_NOINT 0x01 +#define UART_IIR_STATUS 0x06 +#define UART_IIR_LSR 0x06 +#define UART_IIR_RBR 0x04 +#define UART_IIR_THR 0x02 +#define UART_IIR_MSR 0x00 + +#define UART_LCR_LO HALFWORD_REF(UART_LCR) +#define UART_LCR_WLS5 0 +#define UART_LCR_WLS6 0x01 +#define UART_LCR_WLS7 0x02 +#define UART_LCR_WLS8 0x03 +#define UART_LCR_STB 0x04 +#define UART_LCR_PEN 0x08 +#define UART_LCR_EPS 0x10 +#define UART_LCR_SP 0x20 +#define UART_LCR_SB 0x40 +#define UART_LCR_DLAB 0x80 + +#define UART_MCR_LO HALFWORD_REF(UART_MCR) + +#define UART_LSR_LO HALFWORD_REF(UART_LSR) +#define UART_LSR_DR 0x01 +#define UART_LSR_OE 0x02 +#define UART_LSR_PE 0x04 +#define UART_LSR_FE 0x08 +#define UART_LSR_BI 0x10 +#define UART_LSR_THRE 0x20 +#define UART_LSR_TEMT 0x40 + +#define UART_MSR_LO HALFWORD_REF(UART_MSR) +#define UART_SCR_LO HALFWORD_REF(UART_SCR) +#define UART_GCTL_LO HALFWORD_REF(UART_GCTL) +#define UART_GCTL_UCEN 0x01 + +#endif diff --git a/include/asm-blackfin/cpu/cdefBF531.h b/include/asm-blackfin/cpu/cdefBF531.h new file mode 100644 index 0000000..68d841d --- /dev/null +++ b/include/asm-blackfin/cpu/cdefBF531.h @@ -0,0 +1,24 @@ +/* + * cdefBF531.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _CDEFBF531_H +#define _CDEFBF531_H + +#include <cdefBF532.h> + +#endif /* _CDEFBF531_H */ diff --git a/include/asm-blackfin/cpu/cdefBF532.h b/include/asm-blackfin/cpu/cdefBF532.h new file mode 100644 index 0000000..a4d422f --- /dev/null +++ b/include/asm-blackfin/cpu/cdefBF532.h @@ -0,0 +1,398 @@ +/* + * cdefBF532.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _CDEF_BF532_H +#define _CDEF_BF532_H + +/* + * #if !defined(__ADSPLPBLACKFIN__) + * #warning cdefBF532.h should only be included for 532 compatible chips. + * #endif + */ + +/* include all Core registers and bit definitions */ +#include <asm/cpu/defBF532.h> + +/* include core specific register pointer definitions */ +#include <asm/cpu/cdef_LPBlackfin.h> + +/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ +#define pPLL_CTL ((volatile unsigned short *)PLL_CTL) +#define pPLL_STAT ((volatile unsigned short *)PLL_STAT) +#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT) +#define pCHIPID ((volatile unsigned long *)CHIPID) +#define pSWRST ((volatile unsigned short *)SWRST) +#define pSYSCR ((volatile unsigned short *)SYSCR) +#define pPLL_DIV ((volatile unsigned short *)PLL_DIV) +#define pVR_CTL ((volatile unsigned short *)VR_CTL) + +/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ +#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0) +#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1) +#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2) +#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3) +#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK) +#define pSIC_ISR ((volatile unsigned long *)SIC_ISR) +#define pSIC_IWR ((volatile unsigned long *)SIC_IWR) + +/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */ +#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL) +#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT) +#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT) + +/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */ +#define pRTC_STAT ((volatile unsigned long *)RTC_STAT) +#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL) +#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT) +#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT) +#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM) +#define pRTC_FAST ((volatile unsigned short *)RTC_FAST) +#define pRTC_PREN ((volatile unsigned short *)RTC_PREN) + +/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ +#define pFIO_DIR ((volatile unsigned short *)FIO_DIR) +#define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C) +#define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S) +#define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C) +#define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S) +#define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C) +#define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S) +#define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR) +#define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE) +#define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH) +#define pFIO_INEN ((volatile unsigned short *)FIO_INEN) +#define pFIO_FLAG_D ((volatile unsigned short *)FIO_FLAG_D) +#define pFIO_FLAG_T ((volatile unsigned short *)FIO_FLAG_T) +#define pFIO_MASKA_D ((volatile unsigned short *)FIO_MASKA_D) +#define pFIO_MASKA_T ((volatile unsigned short *)FIO_MASKA_T) +#define pFIO_MASKB_D ((volatile unsigned short *)FIO_MASKB_D) +#define pFIO_MASKB_T ((volatile unsigned short *)FIO_MASKB_T) + +/* DMA Test Registers */ +#define pDMA_CCOMP ((volatile unsigned long *)DMA_CCOMP) +#define pDMA_ACOMP ((volatile unsigned long *)DMA_ACOMP) +#define pDMA_MISR ((volatile unsigned long *)DMA_MISR) +#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER) +#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT) +#define pDMA_TMODE ((volatile unsigned short *)DMA_TMODE) +#define pDMA_TMCHAN ((volatile unsigned short *)DMA_TMCHAN) +#define pDMA_TMSTAT ((volatile unsigned short *)DMA_TMSTAT) +#define pDMA_TMBD ((volatile unsigned short *)DMA_TMBD) +#define pDMA_TMM0D ((volatile unsigned short *)DMA_TMM0D) +#define pDMA_TMM1D ((volatile unsigned short *)DMA_TMM1D) +#define pDMA_TMMA ((volatile void **)DMA_TMMA) + +/* DMA Controller */ +#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG) +#define pDMA0_NEXT_DESC_PTR ((volatile void **)DMA0_NEXT_DESC_PTR) +#define pDMA0_START_ADDR ((volatile void **)DMA0_START_ADDR) +#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT) +#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT) +#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY) +#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY) +#define pDMA0_CURR_DESC_PTR ((volatile void **)DMA0_CURR_DESC_PTR) +#define pDMA0_CURR_ADDR ((volatile void **)DMA0_CURR_ADDR) +#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT) +#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT) +#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS) +#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP) + +#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG) +#define pDMA1_NEXT_DESC_PTR ((volatile void **)DMA1_NEXT_DESC_PTR) +#define pDMA1_START_ADDR ((volatile void **)DMA1_START_ADDR) +#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT) +#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT) +#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY) +#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY) +#define pDMA1_CURR_DESC_PTR ((volatile void **)DMA1_CURR_DESC_PTR) +#define pDMA1_CURR_ADDR ((volatile void **)DMA1_CURR_ADDR) +#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT) +#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT) +#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS) +#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP) + +#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG) +#define pDMA2_NEXT_DESC_PTR ((volatile void **)DMA2_NEXT_DESC_PTR) +#define pDMA2_START_ADDR ((volatile void **)DMA2_START_ADDR) +#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT) +#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT) +#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY) +#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY) +#define pDMA2_CURR_DESC_PTR ((volatile void **)DMA2_CURR_DESC_PTR) +#define pDMA2_CURR_ADDR ((volatile void **)DMA2_CURR_ADDR) +#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT) +#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT) +#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS) +#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP) + +#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG) +#define pDMA3_NEXT_DESC_PTR ((volatile void **)DMA3_NEXT_DESC_PTR) +#define pDMA3_START_ADDR ((volatile void **)DMA3_START_ADDR) +#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT) +#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT) +#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY) +#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY) +#define pDMA3_CURR_DESC_PTR ((volatile void **)DMA3_CURR_DESC_PTR) +#define pDMA3_CURR_ADDR ((volatile void **)DMA3_CURR_ADDR) +#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT) +#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT) +#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS) +#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP) + +#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG) +#define pDMA4_NEXT_DESC_PTR ((volatile void **)DMA4_NEXT_DESC_PTR) +#define pDMA4_START_ADDR ((volatile void **)DMA4_START_ADDR) +#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT) +#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT) +#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY) +#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY) +#define pDMA4_CURR_DESC_PTR ((volatile void **)DMA4_CURR_DESC_PTR) +#define pDMA4_CURR_ADDR ((volatile void **)DMA4_CURR_ADDR) +#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT) +#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT) +#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS) +#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP) + +#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG) +#define pDMA5_NEXT_DESC_PTR ((volatile void **)DMA5_NEXT_DESC_PTR) +#define pDMA5_START_ADDR ((volatile void **)DMA5_START_ADDR) +#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT) +#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT) +#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY) +#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY) +#define pDMA5_CURR_DESC_PTR ((volatile void **)DMA5_CURR_DESC_PTR) +#define pDMA5_CURR_ADDR ((volatile void **)DMA5_CURR_ADDR) +#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT) +#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT) +#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS) +#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP) + +#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG) +#define pDMA6_NEXT_DESC_PTR ((volatile void **)DMA6_NEXT_DESC_PTR) +#define pDMA6_START_ADDR ((volatile void **)DMA6_START_ADDR) +#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT) +#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT) +#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY) +#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY) +#define pDMA6_CURR_DESC_PTR ((volatile void **)DMA6_CURR_DESC_PTR) +#define pDMA6_CURR_ADDR ((volatile void **)DMA6_CURR_ADDR) +#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT) +#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT) +#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS) +#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP) + +#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG) +#define pDMA7_NEXT_DESC_PTR ((volatile void **)DMA7_NEXT_DESC_PTR) +#define pDMA7_START_ADDR ((volatile void **)DMA7_START_ADDR) +#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT) +#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT) +#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY) +#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY) +#define pDMA7_CURR_DESC_PTR ((volatile void **)DMA7_CURR_DESC_PTR) +#define pDMA7_CURR_ADDR ((volatile void **)DMA7_CURR_ADDR) +#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT) +#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT) +#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS) +#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP) + +#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG) +#define pMDMA_D1_NEXT_DESC_PTR ((volatile void **)MDMA_D1_NEXT_DESC_PTR) +#define pMDMA_D1_START_ADDR ((volatile void **)MDMA_D1_START_ADDR) +#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT) +#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT) +#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY) +#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY) +#define pMDMA_D1_CURR_DESC_PTR ((volatile void **)MDMA_D1_CURR_DESC_PTR) +#define pMDMA_D1_CURR_ADDR ((volatile void **)MDMA_D1_CURR_ADDR) +#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT) +#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT) +#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS) +#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP) + +#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG) +#define pMDMA_S1_NEXT_DESC_PTR ((volatile void **)MDMA_S1_NEXT_DESC_PTR) +#define pMDMA_S1_START_ADDR ((volatile void **)MDMA_S1_START_ADDR) +#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT) +#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT) +#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY) +#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY) +#define pMDMA_S1_CURR_DESC_PTR ((volatile void **)MDMA_S1_CURR_DESC_PTR) +#define pMDMA_S1_CURR_ADDR ((volatile void **)MDMA_S1_CURR_ADDR) +#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT) +#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT) +#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS) +#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP) + +#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG) +#define pMDMA_D0_NEXT_DESC_PTR ((volatile void **)MDMA_D0_NEXT_DESC_PTR) +#define pMDMA_D0_START_ADDR ((volatile void **)MDMA_D0_START_ADDR) +#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT) +#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT) +#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY) +#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY) +#define pMDMA_D0_CURR_DESC_PTR ((volatile void **)MDMA_D0_CURR_DESC_PTR) +#define pMDMA_D0_CURR_ADDR ((volatile void **)MDMA_D0_CURR_ADDR) +#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT) +#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT) +#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS) +#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP) + +#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG) +#define pMDMA_S0_NEXT_DESC_PTR ((volatile void **)MDMA_S0_NEXT_DESC_PTR) +#define pMDMA_S0_START_ADDR ((volatile void **)MDMA_S0_START_ADDR) +#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT) +#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT) +#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY) +#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY) +#define pMDMA_S0_CURR_DESC_PTR ((volatile void **)MDMA_S0_CURR_DESC_PTR) +#define pMDMA_S0_CURR_ADDR ((volatile void **)MDMA_S0_CURR_ADDR) +#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT) +#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT) +#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS) +#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP) + +/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */ +#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL) +#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0) +#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1) + +/* System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF) */ +/* #define L1SBAR 0xFFC04840 */ /* L1 SRAM Base Address Register */ +/* #define L1CSR 0xFFC04844 */ /* L1 SRAM Control Initialization Register */ + +/* + * #define pDB_ACOMP ((volatile void **)DB_ACOMP) + * #define pDB_CCOMP ((volatile unsigned long *)DB_CCOMP) + */ + +/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */ +#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL) +#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC) +#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT) +#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL) + +/* UART Controller */ +#define pUART_THR ((volatile unsigned short *)UART_THR) +#define pUART_RBR ((volatile unsigned short *)UART_RBR) +#define pUART_DLL ((volatile unsigned short *)UART_DLL) +#define pUART_IER ((volatile unsigned short *)UART_IER) +#define pUART_DLH ((volatile unsigned short *)UART_DLH) +#define pUART_IIR ((volatile unsigned short *)UART_IIR) +#define pUART_LCR ((volatile unsigned short *)UART_LCR) +#define pUART_MCR ((volatile unsigned short *)UART_MCR) +#define pUART_LSR ((volatile unsigned short *)UART_LSR) + +/* + * #define UART_MSR + */ +#define pUART_SCR ((volatile unsigned short *)UART_SCR) +#define pUART_GCTL ((volatile unsigned short *)UART_GCTL) + +/* SPI Controller */ +#define pSPI_CTL ((volatile unsigned short *)SPI_CTL) +#define pSPI_FLG ((volatile unsigned short *)SPI_FLG) +#define pSPI_STAT ((volatile unsigned short *)SPI_STAT) +#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR) +#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR) +#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD) +#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW) + +/* TIMER 0, 1, 2 Registers */ +#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG) +#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER) +#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD) +#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH) + +#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG) +#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER) +#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD) +#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH) + +#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG) +#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER) +#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD) +#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH) + +#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE) +#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE) +#define pTIMER_STATUS ((volatile unsigned short *)TIMER_STATUS) + +/* SPORT0 Controller */ +#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1) +#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2) +#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV) +#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV) +#define pSPORT0_TX ((volatile long *)SPORT0_TX) +#define pSPORT0_RX ((volatile long *)SPORT0_RX) +#define pSPORT0_TX32 ((volatile long *)SPORT0_TX) +#define pSPORT0_RX32 ((volatile long *)SPORT0_RX) +#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX) +#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX) +#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1) +#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2) +#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV) +#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV) +#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT) +#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL) +#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1) +#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2) +#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0) +#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1) +#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2) +#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3) +#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0) +#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1) +#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2) +#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3) + +/* SPORT1 Controller */ +#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1) +#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2) +#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV) +#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV) +#define pSPORT1_TX ((volatile long *)SPORT1_TX) +#define pSPORT1_RX ((volatile long *)SPORT1_RX) +#define pSPORT1_TX32 ((volatile long *)SPORT1_TX) +#define pSPORT1_RX32 ((volatile long *)SPORT1_RX) +#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX) +#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX) +#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1) +#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2) +#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV) +#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV) +#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT) +#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL) +#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1) +#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2) +#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0) +#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1) +#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2) +#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3) +#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0) +#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1) +#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2) +#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3) + +/* Parallel Peripheral Interface (PPI) */ +#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL) +#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS) +#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY) +#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT) +#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME) + +#endif /* _CDEF_BF532_H */ diff --git a/include/asm-blackfin/cpu/cdefBF533.h b/include/asm-blackfin/cpu/cdefBF533.h new file mode 100644 index 0000000..8c751e6 --- /dev/null +++ b/include/asm-blackfin/cpu/cdefBF533.h @@ -0,0 +1,24 @@ +/* + * cdefBF533.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _CDEFBF533_H +#define _CDEFBF533_H + +#include <asm/cpu/cdefBF532.h> + +#endif /* _CDEFBF533_H */ diff --git a/include/asm-blackfin/cpu/cdefBF53x.h b/include/asm-blackfin/cpu/cdefBF53x.h new file mode 100644 index 0000000..db4eaa9 --- /dev/null +++ b/include/asm-blackfin/cpu/cdefBF53x.h @@ -0,0 +1,32 @@ +/************************************************************************ + * + * cdefBF53x.h + * + * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved. + * + ************************************************************************/ + +#ifndef _CDEFBF53x_H +#define _CDEFBF53x_H + +#if defined(__ADSPBF531__) + #include <asm/cpu/cdefBF531.h> +#elif defined(__ADSPBF532__) + #include <asm/cpu/cdefBF532.h> +#elif defined(__ADSPBF533__) + #include <asm/cpu/cdefBF533.h> +#elif defined(__ADSPBF561__) + #include <asm/cpu/cdefBF561.h> +#elif defined(__ADSPBF535__) + #include <asm/cpu/cdefBF535.h> +#elif defined(__AD6532__) + #include <sam/cpu/cdefAD6532.h> +#else + #if defined(__ADSPLPBLACKFIN__) + #include <asm/cpu/cdefBF532.h> + #else + #include <asm/cpu/cdefBF535.h> + #endif +#endif + +#endif /* _CDEFBF53x_H */ diff --git a/include/asm-blackfin/cpu/cdef_LPBlackfin.h b/include/asm-blackfin/cpu/cdef_LPBlackfin.h new file mode 100644 index 0000000..e6471cb --- /dev/null +++ b/include/asm-blackfin/cpu/cdef_LPBlackfin.h @@ -0,0 +1,185 @@ +/* + * cdef_LPBlackfin.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _CDEF_LPBLACKFIN_H +#define _CDEF_LPBLACKFIN_H + +/* + * #if !defined(__ADSPLPBLACKFIN__) + * #warning cdef_LPBlackfin.h should only be included for 532 compatible chips. + * #endif + */ +#include <asm/cpu/def_LPBlackfin.h> + +/* Cache & SRAM Memory */ +#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS) +#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL) +#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS) +#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR) + +/* #define MMR_TIMEOUT 0xFFE00010 */ /* Memory-Mapped Register Timeout Register */ +#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0) +#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1) +#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2) +#define pDCPLB_ADDR3 ((volatile void **)DCPLB_ADDR3) +#define pDCPLB_ADDR4 ((volatile void **)DCPLB_ADDR4) +#define pDCPLB_ADDR5 ((volatile void **)DCPLB_ADDR5) +#define pDCPLB_ADDR6 ((volatile void **)DCPLB_ADDR6) +#define pDCPLB_ADDR7 ((volatile void **)DCPLB_ADDR7) +#define pDCPLB_ADDR8 ((volatile void **)DCPLB_ADDR8) +#define pDCPLB_ADDR9 ((volatile void **)DCPLB_ADDR9) +#define pDCPLB_ADDR10 ((volatile void **)DCPLB_ADDR10) +#define pDCPLB_ADDR11 ((volatile void **)DCPLB_ADDR11) +#define pDCPLB_ADDR12 ((volatile void **)DCPLB_ADDR12) +#define pDCPLB_ADDR13 ((volatile void **)DCPLB_ADDR13) +#define pDCPLB_ADDR14 ((volatile void **)DCPLB_ADDR14) +#define pDCPLB_ADDR15 ((volatile void **)DCPLB_ADDR15) +#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0) +#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1) +#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2) +#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3) +#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4) +#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5) +#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6) +#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7) +#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8) +#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9) +#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10) +#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11) +#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12) +#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13) +#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14) +#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15) +#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND) + +/* #define DTEST_INDEX 0xFFE00304 */ /* Data Test Index Register */ +#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0) +#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1) + +/* + * # define DTEST_DATA2 0xFFE00408 Data Test Data Register + * #define DTEST_DATA3 0xFFE0040C Data Test Data Register + */ +#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL) +#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS) +#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR) +#define pICPLB_ADDR0 ((volatile void **)ICPLB_ADDR0) +#define pICPLB_ADDR1 ((volatile void **)ICPLB_ADDR1) +#define pICPLB_ADDR2 ((volatile void **)ICPLB_ADDR2) +#define pICPLB_ADDR3 ((volatile void **)ICPLB_ADDR3) +#define pICPLB_ADDR4 ((volatile void **)ICPLB_ADDR4) +#define pICPLB_ADDR5 ((volatile void **)ICPLB_ADDR5) +#define pICPLB_ADDR6 ((volatile void **)ICPLB_ADDR6) +#define pICPLB_ADDR7 ((volatile void **)ICPLB_ADDR7) +#define pICPLB_ADDR8 ((volatile void **)ICPLB_ADDR8) +#define pICPLB_ADDR9 ((volatile void **)ICPLB_ADDR9) +#define pICPLB_ADDR10 ((volatile void **)ICPLB_ADDR10) +#define pICPLB_ADDR11 ((volatile void **)ICPLB_ADDR11) +#define pICPLB_ADDR12 ((volatile void **)ICPLB_ADDR12) +#define pICPLB_ADDR13 ((volatile void **)ICPLB_ADDR13) +#define pICPLB_ADDR14 ((volatile void **)ICPLB_ADDR14) +#define pICPLB_ADDR15 ((volatile void **)ICPLB_ADDR15) +#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0) +#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1) +#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2) +#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3) +#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4) +#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5) +#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6) +#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7) +#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8) +#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9) +#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10) +#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11) +#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12) +#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13) +#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14) +#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15) +#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND) + +/* #define ITEST_INDEX 0xFFE01304 */ /* Instruction Test Index Register */ +#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0) +#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1) + +/* Event/Interrupt Registers */ +#define pEVT0 ((volatile void **)EVT0) +#define pEVT1 ((volatile void **)EVT1) +#define pEVT2 ((volatile void **)EVT2) +#define pEVT3 ((volatile void **)EVT3) +#define pEVT4 ((volatile void **)EVT4) +#define pEVT5 ((volatile void **)EVT5) +#define pEVT6 ((volatile void **)EVT6) +#define pEVT7 ((volatile void **)EVT7) +#define pEVT8 ((volatile void **)EVT8) +#define pEVT9 ((volatile void **)EVT9) +#define pEVT10 ((volatile void **)EVT10) +#define pEVT11 ((volatile void **)EVT11) +#define pEVT12 ((volatile void **)EVT12) +#define pEVT13 ((volatile void **)EVT13) +#define pEVT14 ((volatile void **)EVT14) +#define pEVT15 ((volatile void **)EVT15) +#define pIMASK ((volatile unsigned long *)IMASK) +#define pIPEND ((volatile unsigned long *)IPEND) +#define pILAT ((volatile unsigned long *)ILAT) + +/* Core Timer Registers */ +#define pTCNTL ((volatile unsigned long *)TCNTL) +#define pTPERIOD ((volatile unsigned long *)TPERIOD) +#define pTSCALE ((volatile unsigned long *)TSCALE) +#define pTCOUNT ((volatile unsigned long *)TCOUNT) + +/* Debug/MP/Emulation Registers */ +#define pDSPID ((volatile unsigned long *)DSPID) +#define pDBGCTL ((volatile unsigned long *)DBGCTL) +#define pDBGSTAT ((volatile unsigned long *)DBGSTAT) +#define pEMUDAT ((volatile unsigned long *)EMUDAT) + +/* Trace Buffer Registers */ +#define pTBUFCTL ((volatile unsigned long *)TBUFCTL) +#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT) +#define pTBUF ((volatile void **)TBUF) + +/* Watch Point Control Registers */ +#define pWPIACTL ((volatile unsigned long *)WPIACTL) +#define pWPIA0 ((volatile void **)WPIA0) +#define pWPIA1 ((volatile void **)WPIA1) +#define pWPIA2 ((volatile void **)WPIA2) +#define pWPIA3 ((volatile void **)WPIA3) +#define pWPIA4 ((volatile void **)WPIA4) +#define pWPIA5 ((volatile void **)WPIA5) +#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0) +#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1) +#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2) +#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3) +#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4) +#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5) +#define pWPDACTL ((volatile unsigned long *)WPDACTL) +#define pWPDA0 ((volatile void **)WPDA0) +#define pWPDA1 ((volatile void **)WPDA1) +#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0) +#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1) +#define pWPSTAT ((volatile unsigned long *)WPSTAT) + +/* Performance Monitor Registers */ +#define pPFCTL ((volatile unsigned long *)PFCTL) +#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0) +#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1) + +/* #define IPRIO 0xFFE02110 */ /* Core Interrupt Priority Register */ + +#endif /* _CDEF_LPBLACKFIN_H */ diff --git a/include/asm-blackfin/cpu/defBF531.h b/include/asm-blackfin/cpu/defBF531.h new file mode 100644 index 0000000..6c7cd5a --- /dev/null +++ b/include/asm-blackfin/cpu/defBF531.h @@ -0,0 +1,24 @@ +/* + * defBF531.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _DEFBF531_H +#define _DEFBF531_H + +#include <defBF532.h> + +#endif /* _DEFBF531_H */ diff --git a/include/asm-blackfin/cpu/defBF532.h b/include/asm-blackfin/cpu/defBF532.h new file mode 100644 index 0000000..26a5fe6 --- /dev/null +++ b/include/asm-blackfin/cpu/defBF532.h @@ -0,0 +1,1159 @@ +/* + * defBF532.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */ + +#ifndef _DEF_BF532_H +#define _DEF_BF532_H + +/* + * #if !defined(__ADSPLPBLACKFIN__) + * #warning defBF532.h should only be included for 532 compatible chips + * #endif + */ + +/* include all Core registers and bit definitions */ +#include <asm/cpu/def_LPBlackfin.h> + +/* Helper macros + * usage: + * P0.H = HI(UART_THR); + * P0.L = LO(UART_THR); + */ + +#define LO(con32) ((con32) & 0xFFFF) +#define lo(con32) ((con32) & 0xFFFF) +#define HI(con32) (((con32) >> 16) & 0xFFFF) +#define hi(con32) (((con32) >> 16) & 0xFFFF) + +/* + * System MMR Register Map + */ + +/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ +#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ +#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ +#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ +#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ +#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ +#define CHIPID 0xFFC00014 /* Chip ID register (32-bit) */ +#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ +#define SYSCR 0xFFC00104 /* System Configuration register */ + +/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ +#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ +#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ +#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ +#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ +#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ + +/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ +#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ +#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ +#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ + +/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ +#define RTC_STAT 0xFFC00300 /* RTC Status Register */ +#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ +#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ +#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ +#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ +#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ +#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ + +/* UART Controller (0xFFC00400 - 0xFFC004FF) */ +#define UART_THR 0xFFC00400 /* Transmit Holding register */ +#define UART_RBR 0xFFC00400 /* Receive Buffer register */ +#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ +#define UART_IER 0xFFC00404 /* Interrupt Enable Register */ +#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ +#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */ +#define UART_LCR 0xFFC0040C /* Line Control Register */ +#define UART_MCR 0xFFC00410 /* Modem Control Register */ +#define UART_LSR 0xFFC00414 /* Line Status Register */ +/* #define UART_MSR 0xFFC00418 */ /* Modem Status Register (UNUSED in ADSP-BF532) */ +#define UART_SCR 0xFFC0041C /* SCR Scratch Register */ +#define UART_GCTL 0xFFC00424 /* Global Control Register */ + +/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ +#define SPI_CTL 0xFFC00500 /* SPI Control Register */ +#define SPI_FLG 0xFFC00504 /* SPI Flag register */ +#define SPI_STAT 0xFFC00508 /* SPI Status register */ +#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ +#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ +#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ +#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ + +/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ +#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ +#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ +#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ +#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ + +#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ +#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ +#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ +#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ + +#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ +#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ +#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ +#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ + +#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ +#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ +#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ + +/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */ +#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ +#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ +#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ +#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ +#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ +#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ +#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ +#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ +#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ +#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ +#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ +#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ +#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ +#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ +#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ +#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ +#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ + +/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ +#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ +#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ +#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ +#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ +#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ +#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ +#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ + +/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ +#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ +#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ +#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ +#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ +#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ +#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ +#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ +#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ +#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ +#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ +#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ +#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ +#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ +#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ +#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ +#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ +#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ +#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ + +/* Asynchronous Memory Controller - External Bus Interface Unit */ +#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ +#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ +#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ + +/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ +#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ +#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ +#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ +#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ + +/* DMA Test Registers */ +#define DMA_CCOMP 0xFFC00B04 /* DMA Cycle Count Register */ +#define DMA_ACOMP 0xFFC00B00 /* Debug Compare Address Register */ +#define DMA_MISR 0xFFC00B08 /* MISR Register */ +#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ +#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ +#define DMA_TMODE 0xFFC00B14 /* DMA Test Modes Register */ +#define DMA_TMCHAN 0xFFC00B18 /* DMA Testmode Selected Channel Register */ +#define DMA_TMSTAT 0xFFC00B1C /* DMA Testmode Channel Status Register */ +#define DMA_TMBD 0xFFC00B20 /* DMA Testmode DAB Bus Data Register */ +#define DMA_TMM0D 0xFFC00B24 /* DMA Testmode Mem0 Data Register */ +#define DMA_TMM1D 0xFFC00B28 /* DMA Testmode Mem1 Data Register */ +#define DMA_TMMA 0xFFC00B2C /* DMA Testmode Memory Address Register */ + +/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ +#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ +#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ +#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ +#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ +#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ +#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ +#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ +#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ +#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ +#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ +#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ +#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ +#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ + +#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ +#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ +#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ +#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ +#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ +#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ +#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ +#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ +#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ +#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ +#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ +#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ +#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ + +#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ +#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ +#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ +#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ +#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ +#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ +#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ +#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ +#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ +#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ +#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ +#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ +#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ + +#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ +#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ +#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ +#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ +#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ +#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ +#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ +#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ +#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ +#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ +#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ +#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ +#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ + +#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ +#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ +#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ +#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ +#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ +#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ +#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ +#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ +#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ +#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ +#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ +#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ +#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ + +#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ +#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ +#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ +#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ +#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ +#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ +#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ +#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ +#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ +#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ +#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ +#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ +#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ + +#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ +#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ +#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ +#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ +#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ +#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ +#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ +#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ +#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ +#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ +#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ +#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ +#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ + +#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ +#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ +#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ +#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ +#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ +#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ +#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ +#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ +#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ +#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ +#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ +#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ +#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ + +#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */ +#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ +#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */ +#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */ +#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */ +#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */ +#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */ +#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ +#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */ +#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */ +#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */ +#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ +#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */ + +#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */ +#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ +#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */ +#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */ +#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */ +#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */ +#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */ +#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ +#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */ +#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */ +#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */ +#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ +#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */ + +#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */ +#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ +#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */ +#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */ +#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */ +#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */ +#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */ +#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ +#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */ +#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */ +#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */ +#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ +#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */ + +#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */ +#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ +#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */ +#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */ +#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */ +#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */ +#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */ +#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ +#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */ +#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */ +#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */ +#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */ +#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */ + +/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ +#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ +#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ +#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ +#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ +#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ + +/* + * System MMR Register Bits + */ +/* + * PLL AND RESET MASKS + */ + +/* PLL_CTL Masks */ +#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */ +#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */ +#define PLL_OFF 0x00000002 /* Shut off PLL clocks */ +#define STOPCK_OFF 0x00000008 /* Core clock off */ +#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */ +#define BYPASS 0x00000100 /* Bypass the PLL */ + +/* PLL_DIV Masks */ +#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ + +#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ + +/* SWRST Mask */ +#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */ + +/* + * SYSTEM INTERRUPT CONTROLLER MASKS + */ + +/* SIC_IAR0 Masks */ +#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */ +#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ +#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ +#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */ +#define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ +#define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ +#define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ +#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ + +/* SIC_IAR1 Masks */ +#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */ +#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ +#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ +#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */ +#define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ +#define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ +#define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ +#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ + +/* SIC_IAR2 Masks */ +#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */ +#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ +#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ +#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */ +#define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ +#define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ +#define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ +#define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ + +/* SIC_IMASK Masks */ +#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ +#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ +#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ +#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ + +/* SIC_IWR Masks */ +#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ +#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ +#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ +#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ + +/* + * WATCHDOG TIMER MASKS + */ +/* Watchdog Timer WDOG_CTL Register */ +#define ICTL(x) ((x<<1) & 0x0006) +#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */ +#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */ +#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */ +#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */ + +#define TMR_EN 0x0000 +#define TMR_DIS 0x0AD0 +#define TRO 0x8000 + +#define ICTL_P0 0x01 +#define ICTL_P1 0x02 +#define TRO_P 0x0F + +/* RTC_STAT and RTC_ALARM register */ +#define RTSEC 0x0000003F /* Real-Time Clock Seconds */ +#define RTMIN 0x00000FC0 /* Real-Time Clock Minutes */ +#define RTHR 0x0001F000 /* Real-Time Clock Hours */ +#define RTDAY 0xFFFE0000 /* Real-Time Clock Days */ + +/* RTC_ICTL register */ +#define SWIE 0x0001 /* Stopwatch Interrupt Enable */ +#define AIE 0x0002 /* Alarm Interrupt Enable */ +#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */ +#define MIE 0x0008 /* Minutes Interrupt Enable */ +#define HIE 0x0010 /* Hours Interrupt Enable */ +#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */ +#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ +#define WCIE 0x8000 /* Write Complete Interrupt Enable */ + +/* RTC_ISTAT register */ +#define SWEF 0x0001 /* Stopwatch Event Flag */ +#define AEF 0x0002 /* Alarm Event Flag */ +#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */ +#define MEF 0x0008 /* Minutes Event Flag */ +#define HEF 0x0010 /* Hours Event Flag */ +#define DEF 0x0020 /* 24 Hours (Days) Event Flag */ +#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */ +#define WPS 0x4000 /* Write Pending Status (RO) */ +#define WCOM 0x8000 /* Write Complete */ + +/* RTC_FAST Mask (RTC_PREN Mask) */ +#define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */ +#define PREN 0x00000001 /* ** Must be set after power-up for proper operation of RTC */ + +/* + * UART CONTROLLER MASKS + */ + +/* UART_LCR Register */ +#define DLAB 0x80 +#define SB 0x40 +#define STP 0x20 +#define EPS 0x10 +#define PEN 0x08 +#define STB 0x04 +#define WLS(x) ((x-5) & 0x03) + +#define DLAB_P 0x07 +#define SB_P 0x06 +#define STP_P 0x05 +#define EPS_P 0x04 +#define PEN_P 0x03 +#define STB_P 0x02 +#define WLS_P1 0x01 +#define WLS_P0 0x00 + +/* UART_MCR Register */ +#define LOOP_ENA 0x10 +#define LOOP_ENA_P 0x04 + +/* UART_LSR Register */ +#define TEMT 0x40 +#define THRE 0x20 +#define BI 0x10 +#define FE 0x08 +#define PE 0x04 +#define OE 0x02 +#define DR 0x01 + +#define TEMP_P 0x06 +#define THRE_P 0x05 +#define BI_P 0x04 +#define FE_P 0x03 +#define PE_P 0x02 +#define OE_P 0x01 +#define DR_P 0x00 + +/* UART_IER Register */ +#define ELSI 0x04 +#define ETBEI 0x02 +#define ERBFI 0x01 + +#define ELSI_P 0x02 +#define ETBEI_P 0x01 +#define ERBFI_P 0x00 + +/* UART_IIR Register */ +#define STATUS(x) ((x << 1) & 0x06) +#define NINT 0x01 +#define STATUS_P1 0x02 +#define STATUS_P0 0x01 +#define NINT_P 0x00 + +/* UART_GCTL Register */ +#define FFE 0x20 +#define FPE 0x10 +#define RPOLC 0x08 +#define TPOLC 0x04 +#define IREN 0x02 +#define UCEN 0x01 + +#define FFE_P 0x05 +#define FPE_P 0x04 +#define RPOLC_P 0x03 +#define TPOLC_P 0x02 +#define IREN_P 0x01 +#define UCEN_P 0x00 + +/* + * SERIAL PORT MASKS + */ +/* SPORTx_TCR1 Masks */ +#define TSPEN 0x0001 /* TX enable */ +#define ITCLK 0x0002 /* Internal TX Clock Select */ +#define TDTYPE 0x000C /* TX Data Formatting Select */ +#define TLSBIT 0x0010 /* TX Bit Order */ +#define ITFS 0x0200 /* Internal TX Frame Sync Select */ +#define TFSR 0x0400 /* TX Frame Sync Required Select */ +#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ +#define LTFS 0x1000 /* Low TX Frame Sync Select */ +#define LATFS 0x2000 /* Late TX Frame Sync Select */ +#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ + +/* SPORTx_TCR2 Masks */ +#define SLEN 0x001F /*TX Word Length */ +#define TXSE 0x0100 /*TX Secondary Enable */ +#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */ +#define TRFST 0x0400 /*TX Right-First Data Order */ + +/* SPORTx_RCR1 Masks */ +#define RSPEN 0x0001 /* RX enable */ +#define IRCLK 0x0002 /* Internal RX Clock Select */ +#define RDTYPE 0x000C /* RX Data Formatting Select */ +#define RULAW 0x0008 /* u-Law enable */ +#define RALAW 0x000C /* A-Law enable */ +#define RLSBIT 0x0010 /* RX Bit Order */ +#define IRFS 0x0200 /* Internal RX Frame Sync Select */ +#define RFSR 0x0400 /* RX Frame Sync Required Select */ +#define LRFS 0x1000 /* Low RX Frame Sync Select */ +#define LARFS 0x2000 /* Late RX Frame Sync Select */ +#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ + +/* SPORTx_RCR2 Masks */ +#define SLEN 0x001F /* RX Word Length */ +#define RXSE 0x0100 /* RX Secondary Enable */ +#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ +#define RRFST 0x0400 /* Right-First Data Order */ + +/* SPORTx_STAT Masks */ +#define RXNE 0x0001 /* RX FIFO Not Empty Status */ +#define RUVF 0x0002 /* RX Underflow Status */ +#define ROVF 0x0004 /* RX Overflow Status */ +#define TXF 0x0008 /* TX FIFO Full Status */ +#define TUVF 0x0010 /* TX Underflow Status */ +#define TOVF 0x0020 /* TX Overflow Status */ +#define TXHRE 0x0040 /* TX Hold Register Empty */ + +/* SPORTx_MCMC1 Masks */ +#define WSIZE 0x0000F000 /* Multichannel Window Size Field */ +#define WOFF 0x000003FF /* /Multichannel Window Offset Field */ + +/* SPORTx_MCMC2 Masks */ +#define MCCRM 0x00000003 /* Multichannel Clock Recovery Mode */ +#define MCDTXPE 0x00000004 /* Multichannel DMA Transmit Packing */ +#define MCDRXPE 0x00000008 /* Multichannel DMA Receive Packing */ +#define MCMEN 0x00000010 /* Multichannel Frame Mode Enable */ +#define FSDR 0x00000080 /* Multichannel Frame Sync to Data Relationship */ +#define MFD 0x0000F000 /* Multichannel Frame Delay */ + +/* + * PARALLEL PERIPHERAL INTERFACE (PPI) MASKS + */ + +/* PPI_CONTROL Masks */ +#define PORT_EN 0x00000001 /* PPI Port Enable */ +#define PORT_DIR 0x00000002 /* PPI Port Direction */ +#define XFR_TYPE 0x0000000C /* PPI Transfer Type */ +#define PORT_CFG 0x00000030 /* PPI Port Configuration */ +#define FLD_SEL 0x00000040 /* PPI Active Field Select */ +#define PACK_EN 0x00000080 /* PPI Packing Mode */ +#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */ +#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */ +#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */ +#define DLENGTH 0x00003800 /* PPI Data Length */ +#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ +#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ +#define POL 0x0000C000 /* PPI Signal Polarities */ + +/* PPI_STATUS Masks */ +#define FLD 0x00000400 /* Field Indicator */ +#define FT_ERR 0x00000800 /* Frame Track Error */ +#define OVR 0x00001000 /* FIFO Overflow Error */ +#define UNDR 0x00002000 /* FIFO Underrun Error */ +#define ERR_DET 0x00004000 /* Error Detected Indicator */ +#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */ + +/* + * DMA CONTROLLER MASKS + */ + +/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ +#define DMAEN 0x00000001 /* Channel Enable */ +#define WNR 0x00000002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x00000000 /* Word Size 8 bits */ +#define WDSIZE_16 0x00000004 /* Word Size 16 bits */ +#define WDSIZE_32 0x00000008 /* Word Size 32 bits */ +#define DMA2D 0x00000010 /* 2D/1D* Mode */ +#define RESTART 0x00000020 /* Restart */ +#define DI_SEL 0x00000040 /* Data Interrupt Select */ +#define DI_EN 0x00000080 /* Data Interrupt Enable */ +#define NDSIZE 0x00000900 /* Next Descriptor Size */ +#define FLOW 0x00007000 /* Flow Control */ + +#define DMAEN_P 0 /* Channel Enable */ +#define WNR_P 1 /* Channel Direction (W/R*) */ +#define DMA2D_P 4 /* 2D/1D* Mode */ +#define RESTART_P 5 /* Restart */ +#define DI_SEL_P 6 /* Data Interrupt Select */ +#define DI_EN_P 7 /* Data Interrupt Enable */ + +/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ +#define DMA_DONE 0x00000001 /* DMA Done Indicator */ +#define DMA_ERR 0x00000002 /* DMA Error Indicator */ +#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ +#define DMA_RUN 0x00000008 /* DMA Running Indicator */ + +#define DMA_DONE_P 0 /* DMA Done Indicator */ +#define DMA_ERR_P 1 /* DMA Error Indicator */ +#define DFETCH_P 2 /* Descriptor Fetch Indicator */ +#define DMA_RUN_P 3 /* DMA Running Indicator */ + +/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ +#define CTYPE 0x00000040 /* DMA Channel Type Indicator */ +#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ +#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */ +#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */ +#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */ +#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */ +#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ +#define PMAP 0x00007000 /* DMA Peripheral Map Field */ + +/* + * GENERAL PURPOSE TIMER MASKS + */ + +/* PWM Timer bit definitions */ + +/* TIMER_ENABLE Register */ +#define TIMEN0 0x0001 +#define TIMEN1 0x0002 +#define TIMEN2 0x0004 + +#define TIMEN0_P 0x00 +#define TIMEN1_P 0x01 +#define TIMEN2_P 0x02 + +/* TIMER_DISABLE Register */ +#define TIMDIS0 0x0001 +#define TIMDIS1 0x0002 +#define TIMDIS2 0x0004 + +#define TIMDIS0_P 0x00 +#define TIMDIS1_P 0x01 +#define TIMDIS2_P 0x02 + +/* TIMER_STATUS Register */ +#define TIMIL0 0x0001 +#define TIMIL1 0x0002 +#define TIMIL2 0x0004 +#define TOVL_ERR0 0x0010 +#define TOVL_ERR1 0x0020 +#define TOVL_ERR2 0x0040 +#define TRUN0 0x1000 +#define TRUN1 0x2000 +#define TRUN2 0x4000 + +#define TIMIL0_P 0x00 +#define TIMIL1_P 0x01 +#define TIMIL2_P 0x02 +#define TOVL_ERR0_P 0x04 +#define TOVL_ERR1_P 0x05 +#define TOVL_ERR2_P 0x06 +#define TRUN0_P 0x0C +#define TRUN1_P 0x0D +#define TRUN2_P 0x0E + +/* TIMERx_CONFIG Registers */ +#define PWM_OUT 0x0001 +#define WDTH_CAP 0x0002 +#define EXT_CLK 0x0003 +#define PULSE_HI 0x0004 +#define PERIOD_CNT 0x0008 +#define IRQ_ENA 0x0010 +#define TIN_SEL 0x0020 +#define OUT_DIS 0x0040 +#define CLK_SEL 0x0080 +#define TOGGLE_HI 0x0100 +#define EMU_RUN 0x0200 +#define ERR_TYP(x) ((x & 0x03) << 14) + +#define TMODE_P0 0x00 +#define TMODE_P1 0x01 +#define PULSE_HI_P 0x02 +#define PERIOD_CNT_P 0x03 +#define IRQ_ENA_P 0x04 +#define TIN_SEL_P 0x05 +#define OUT_DIS_P 0x06 +#define CLK_SEL_P 0x07 +#define TOGGLE_HI_P 0x08 +#define EMU_RUN_P 0x09 +#define ERR_TYP_P0 0x0E +#define ERR_TYP_P1 0x0F + +/* + * PROGRAMMABLE FLAG MASKS + */ + +/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ +#define PF0 0x0001 +#define PF1 0x0002 +#define PF2 0x0004 +#define PF3 0x0008 +#define PF4 0x0010 +#define PF5 0x0020 +#define PF6 0x0040 +#define PF7 0x0080 +#define PF8 0x0100 +#define PF9 0x0200 +#define PF10 0x0400 +#define PF11 0x0800 +#define PF12 0x1000 +#define PF13 0x2000 +#define PF14 0x4000 +#define PF15 0x8000 + +/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */ +#define PF0_P 0 +#define PF1_P 1 +#define PF2_P 2 +#define PF3_P 3 +#define PF4_P 4 +#define PF5_P 5 +#define PF6_P 6 +#define PF7_P 7 +#define PF8_P 8 +#define PF9_P 9 +#define PF10_P 10 +#define PF11_P 11 +#define PF12_P 12 +#define PF13_P 13 +#define PF14_P 14 +#define PF15_P 15 + +/* + * SERIAL PERIPHERAL INTERFACE (SPI) MASKS + */ + +/* SPI_CTL Masks */ +#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ +#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ +#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ +#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ +#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ +#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ +#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ +#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ +#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ +#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ +#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ +#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ + +/* SPI_FLG Masks */ +#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ +#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ + +/* SPI_FLG Bit Positions */ +#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ +#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ + +/* SPI_STAT Masks */ +#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ +#define MODF 0x00000002 /* Set(=1)in a master device when some other device tries to become master */ +#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ +#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ +#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ +#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ +#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ + +/* + * ASYNCHRONOUS MEMORY CONTROLLER MASKS + */ + +/* AMGCTL Masks */ +#define AMCKEN 0x00000001 /* Enable CLKOUT */ +#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */ +#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */ +#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ +#define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ + +/* AMGCTL Bit Positions */ +#define AMCKEN_P 0x00000000 /* Enable CLKOUT */ +#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ +#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ +#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ + +/* AMBCTL0 Masks */ +#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ +#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ +#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ +#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ +#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ +#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ +#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ +#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ +#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ +#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ +#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ +#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ +#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ +#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ +#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ +#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ +#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ +#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ +#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ +#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ +#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ +#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ +#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ +#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ +#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ +#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ +#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ +#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ +#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ +#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ +#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ +#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ +#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ +#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ +#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ +#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ +#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ +#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ +#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ +#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ +#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ +#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ +#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ +#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ +#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ +#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ +#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ +#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ +#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ +#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ +#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ +#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ +#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ +#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ +#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ +#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ +#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ +#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ +#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ +#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ +#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ +#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ +#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ +#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ +#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ +#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ +#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ +#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ +#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ +#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ +#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ +#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ +#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ +#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ +#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ +#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ +#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ +#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ +#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ +#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ +#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ +#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ +#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ +#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ +#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ +#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ +#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ +#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ + +/* AMBCTL1 Masks */ +#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ +#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ +#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ +#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ +#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ +#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ +#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ +#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ +#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ +#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ +#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ +#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ +#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ +#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ +#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ +#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ +#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ +#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ +#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ +#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ +#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ +#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ +#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ +#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ +#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ +#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ +#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ +#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ +#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ +#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ +#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ +#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ +#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ +#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ +#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ +#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ +#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ +#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ +#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ +#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ +#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ +#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ +#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ +#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ +#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ +#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ +#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ +#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ +#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ +#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ +#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ +#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ +#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ +#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ +#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ +#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ +#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ +#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ +#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ +#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ +#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ +#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ +#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ +#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ +#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ +#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ +#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ +#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ +#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ +#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ +#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ +#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ +#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ +#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ +#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ +#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ +#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ +#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ +#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ +#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ +#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ +#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ +#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ +#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ +#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ +#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ +#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ +#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ + +/* + * SDRAM CONTROLLER MASKS + */ + +/* SDGCTL Masks */ +#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ +#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ +#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ +#define PFE 0x00000010 /* Enable SDRAM prefetch */ +#define PFP 0x00000020 /* Prefetch has priority over AMC requests */ +#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ +#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ +#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ +#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ +#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ +#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ +#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ +#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ +#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ +#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ +#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ +#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ +#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ +#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ +#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ +#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ +#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ +#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ +#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ +#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ +#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ +#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ +#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ +#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ +#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ +#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ +#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ +#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ +#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ +#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ +#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ +#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ +#define PUPSD 0x00200000 /* Power-up start delay */ +#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ +#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ +#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ +#define EBUFE 0x02000000 /* Enable external buffering timing */ +#define FBBRW 0x04000000 /* Fast back-to-back read write enable */ +#define EMREN 0x10000000 /* Extended mode register enable */ +#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ +#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ + +/* EBIU_SDBCTL Masks */ +#define EBE 0x00000001 /* Enable SDRAM external bank */ +#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */ +#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */ +#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */ +#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */ +#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ +#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ +#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ +#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ + +/* EBIU_SDSTAT Masks */ +#define SDCI 0x00000001 /* SDRAM controller is idle */ +#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ +#define SDPUA 0x00000004 /* SDRAM power up active */ +#define SDRS 0x00000008 /* SDRAM is in reset state */ +#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ +#define BGSTAT 0x00000020 /* Bus granted */ + +#endif /* _DEF_BF532_H */ diff --git a/include/asm-blackfin/cpu/defBF533.h b/include/asm-blackfin/cpu/defBF533.h new file mode 100644 index 0000000..90e50af --- /dev/null +++ b/include/asm-blackfin/cpu/defBF533.h @@ -0,0 +1,24 @@ +/* + * defBF533.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _DEFBF533_H +#define _DEFBF533_H + +#include <asm/cpu/defBF532.h> + +#endif /* _DEFBF533_H */ diff --git a/include/asm-blackfin/cpu/defBF533_extn.h b/include/asm-blackfin/cpu/defBF533_extn.h new file mode 100644 index 0000000..a9a1c7c --- /dev/null +++ b/include/asm-blackfin/cpu/defBF533_extn.h @@ -0,0 +1,76 @@ +/* + * defBF533_extn.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _DEF_BF533_EXTN_H +#define _DEF_BF533_EXTN_H + +#define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */ +/* Delay inserted for PLL transition */ +#define DELAY 0x1000 + +#define L1_ISRAM 0xFFA00000 +#define L1_ISRAM_END 0xFFA10000 +#define DATA_BANKA_SRAM 0xFF800000 +#define DATA_BANKA_SRAM_END 0xFF808000 +#define DATA_BANKB_SRAM 0xFF900000 +#define DATA_BANKB_SRAM_END 0xFF908000 +#define SYSMMR_BASE 0xFFC00000 +#define WDSIZE16 0x00000004 + +/* Event Vector Table Address */ +#define EVT_EMULATION_ADDR 0xffe02000 +#define EVT_RESET_ADDR 0xffe02004 +#define EVT_NMI_ADDR 0xffe02008 +#define EVT_EXCEPTION_ADDR 0xffe0200c +#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010 +#define EVT_HARDWARE_ERROR_ADDR 0xffe02014 +#define EVT_TIMER_ADDR 0xffe02018 +#define EVT_IVG7_ADDR 0xffe0201c +#define EVT_IVG8_ADDR 0xffe02020 +#define EVT_IVG9_ADDR 0xffe02024 +#define EVT_IVG10_ADDR 0xffe02028 +#define EVT_IVG11_ADDR 0xffe0202c +#define EVT_IVG12_ADDR 0xffe02030 +#define EVT_IVG13_ADDR 0xffe02034 +#define EVT_IVG14_ADDR 0xffe02038 +#define EVT_IVG15_ADDR 0xffe0203c +#define EVT_OVERRIDE_ADDR 0xffe02100 + +/* IMASK Bit values */ +#define IVG15_POS 0x00008000 +#define IVG14_POS 0x00004000 +#define IVG13_POS 0x00002000 +#define IVG12_POS 0x00001000 +#define IVG11_POS 0x00000800 +#define IVG10_POS 0x00000400 +#define IVG9_POS 0x00000200 +#define IVG8_POS 0x00000100 +#define IVG7_POS 0x00000080 +#define IVGTMR_POS 0x00000040 +#define IVGHW_POS 0x00000020 + +#define WDOG_TMR_DISABLE (0xAD << 4) +#define ICTL_RST 0x00000000 +#define ICTL_NMI 0x00000002 +#define ICTL_GP 0x00000004 +#define ICTL_DISABLE 0x00000003 + +/* Watch Dog timer values setup */ +#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE + +#endif /* _DEF_BF533_EXTN_H */ diff --git a/include/asm-blackfin/cpu/def_LPBlackfin.h b/include/asm-blackfin/cpu/def_LPBlackfin.h new file mode 100644 index 0000000..9ac78c8 --- /dev/null +++ b/include/asm-blackfin/cpu/def_LPBlackfin.h @@ -0,0 +1,445 @@ +/* + * def_LPBlackfin.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */ + +#ifndef _DEF_LPBLACKFIN_H +#define _DEF_LPBLACKFIN_H + +/* + * #if !defined(__ADSPLPBLACKFIN__) + * #warning def_LPBlackfin.h should only be included for 532 compatible chips. + * #endif + */ + +#define MK_BMSK_( x ) (1<<x) /* Make a bit mask from a bit position */ + +/* + * System Register Bits + */ + +/* + * ASTAT register + */ + +/* definitions of ASTAT bit positions */ +#define ASTAT_AZ_P 0x00000000 /* Result of last ALU0 or shifter operation is zero */ +#define ASTAT_AN_P 0x00000001 /* Result of last ALU0 or shifter operation is negative */ +#define ASTAT_CC_P 0x00000005 /* Condition Code, used for holding comparison results */ +#define ASTAT_AQ_P 0x00000006 /* Quotient Bit */ +#define ASTAT_RND_MOD_P 0x00000008 /* Rounding mode, set for biased, clear for unbiased */ +#define ASTAT_AC0_P 0x0000000C /* Result of last ALU0 operation generated a carry */ +#define ASTAT_AC0_COPY_P 0x00000002 /* Result of last ALU0 operation generated a carry */ +#define ASTAT_AC1_P 0x0000000D /* Result of last ALU1 operation generated a carry */ +#define ASTAT_AV0_P 0x00000010 /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */ +#define ASTAT_AV0S_P 0x00000011 /* Sticky version of ASTAT_AV0 */ +#define ASTAT_AV1_P 0x00000012 /* Result of last MAC1 operation overflowed, sticky for MAC */ +#define ASTAT_AV1S_P 0x00000013 /* Sticky version of ASTAT_AV1 */ +#define ASTAT_V_P 0x00000018 /* Result of last ALU0 or MAC0 operation overflowed */ +#define ASTAT_V_COPY_P 0x00000003 /* Result of last ALU0 or MAC0 operation overflowed */ +#define ASTAT_VS_P 0x00000019 /* Sticky version of ASTAT_V */ + +/* ** Masks */ +#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P) /* Result of last ALU0 or shifter operation is zero */ +#define ASTAT_AN MK_BMSK_(ASTAT_AN_P) /* Result of last ALU0 or shifter operation is negative */ +#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P) /* Result of last ALU0 operation generated a carry */ +#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P) /* Result of last ALU0 operation generated a carry */ +#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P) /* Result of last ALU0 operation generated a carry */ +#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P) /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */ +#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P) /* Result of last MAC1 operation overflowed, sticky for MAC */ +#define ASTAT_CC MK_BMSK_(ASTAT_CC_P) /* Condition Code, used for holding comparison results */ +#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P) /* Quotient Bit */ +#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P) /* Rounding mode, set for biased, clear for unbiased */ +#define ASTAT_V MK_BMSK_(ASTAT_V_P) /* Overflow Bit */ +#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P) /* Overflow Bit */ + +/* + * SEQSTAT register + */ + +/* ** Bit Positions */ +#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */ +#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */ +#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */ +#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */ +#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */ +#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */ +#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request, set by IDLE instruction */ +#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last reset was a software reset (=1) */ +#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */ +#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */ +#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */ +#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */ +#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */ +#define SEQSTAT_HWERRCAUSE5_P 0x00000013 /* Last hw error cause bit 5 */ +#define SEQSTAT_HWERRCAUSE6_P 0x00000014 /* Last hw error cause bit 6 */ +#define SEQSTAT_HWERRCAUSE7_P 0x00000015 /* Last hw error cause bit 7 */ + +/* ** Masks */ +/* Exception cause */ +#define SEQSTAT_EXCAUSE MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \ + MK_BMSK_(SEQSTAT_EXCAUSE1_P ) | \ + MK_BMSK_(SEQSTAT_EXCAUSE2_P ) | \ + MK_BMSK_(SEQSTAT_EXCAUSE3_P ) | \ + MK_BMSK_(SEQSTAT_EXCAUSE4_P ) | \ + MK_BMSK_(SEQSTAT_EXCAUSE5_P ) | \ + 0 + +/* Indicates whether the last reset was a software reset (=1) */ +#define SEQSTAT_SFTRESET MK_BMSK_(SEQSTAT_SFTRESET_P ) + +/* Last hw error cause */ +#define SEQSTAT_HWERRCAUSE MK_BMSK_(SEQSTAT_HWERRCAUSE0_P ) | \ + MK_BMSK_(SEQSTAT_HWERRCAUSE1_P ) | \ + MK_BMSK_(SEQSTAT_HWERRCAUSE2_P ) | \ + MK_BMSK_(SEQSTAT_HWERRCAUSE3_P ) | \ + MK_BMSK_(SEQSTAT_HWERRCAUSE4_P ) | \ + 0 + +/* + * SYSCFG register + */ + +/* ** Bit Positions */ +#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when set it forces an exception for each instruction executed */ +#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */ +#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */ + +/* ** Masks */ +#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P) /* Supervisor single step, when set it forces an exception for each instruction executed */ +#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P) /* Enable cycle counter (=1) */ +#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P /* Self Nesting Interrupt Enable */ + +/* Backward-compatibility for typos in prior releases */ +#define SYSCFG_SSSSTEP SYSCFG_SSSTEP +#define SYSCFG_CCCEN SYSCFG_CCEN + +/* + * Core MMR Register Map + */ + +/* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */ +#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */ +#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ +#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ +#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */ +#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ +#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ +#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ +#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ +#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection Lookaside Buffer 3 */ +#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection Lookaside Buffer 4 */ +#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection Lookaside Buffer 5 */ +#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection Lookaside Buffer 6 */ +#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection Lookaside Buffer 7 */ +#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection Lookaside Buffer 8 */ +#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection Lookaside Buffer 9 */ +#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection Lookaside Buffer 10 */ +#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection Lookaside Buffer 11 */ +#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection Lookaside Buffer 12 */ +#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection Lookaside Buffer 13 */ +#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection Lookaside Buffer 14 */ +#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection Lookaside Buffer 15 */ +#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ +#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ +#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ +#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ +#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ +#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ +#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ +#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ +#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ +#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ +#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ +#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ +#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ +#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ +#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ +#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ +#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ +#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ +#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ + +/* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */ +#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ +#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */ +#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */ +#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */ +#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */ +#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ +#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ +#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ +#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ +#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ +#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ +#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ +#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ +#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ +#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ +#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ +#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ +#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ +#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ +#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ +#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ +#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ +#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ +#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ +#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ +#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ +#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ +#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ +#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ +#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ +#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ +#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ +#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ +#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ +#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ +#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ +#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ +#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ +#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ +#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ + +/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */ +#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ +#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ +#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ +#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ +#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ +#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ +#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ +#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ +#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ +#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ +#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ +#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ +#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ +#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ +#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ +#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ +#define IMASK 0xFFE02104 /* Interrupt Mask Register */ +#define IPEND 0xFFE02108 /* Interrupt Pending Register */ +#define ILAT 0xFFE0210C /* Interrupt Latch Register */ +#define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */ + +/* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */ +#define TCNTL 0xFFE03000 /* Core Timer Control Register */ +#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ +#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ +#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ + +/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */ +#define DSPID 0xFFE05000 /* DSP Processor ID Register for MP implementations */ +#define DBGSTAT 0xFFE05008 /* Debug Status Register */ + +/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */ +#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ +#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ +#define TBUF 0xFFE06100 /* Trace Buffer */ + +/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */ +#define WPIACTL 0xFFE07000 /* Watchpoint Instruction Address Control Register */ +#define WPIA0 0xFFE07040 /* Watchpoint Instruction Address Register 0 */ +#define WPIA1 0xFFE07044 /* Watchpoint Instruction Address Register 1 */ +#define WPIA2 0xFFE07048 /* Watchpoint Instruction Address Register 2 */ +#define WPIA3 0xFFE0704C /* Watchpoint Instruction Address Register 3 */ +#define WPIA4 0xFFE07050 /* Watchpoint Instruction Address Register 4 */ +#define WPIA5 0xFFE07054 /* Watchpoint Instruction Address Register 5 */ +#define WPIACNT0 0xFFE07080 /* Watchpoint Instruction Address Count Register 0 */ +#define WPIACNT1 0xFFE07084 /* Watchpoint Instruction Address Count Register 1 */ +#define WPIACNT2 0xFFE07088 /* Watchpoint Instruction Address Count Register 2 */ +#define WPIACNT3 0xFFE0708C /* Watchpoint Instruction Address Count Register 3 */ +#define WPIACNT4 0xFFE07090 /* Watchpoint Instruction Address Count Register 4 */ +#define WPIACNT5 0xFFE07094 /* Watchpoint Instruction Address Count Register 5 */ +#define WPDACTL 0xFFE07100 /* Watchpoint Data Address Control Register */ +#define WPDA0 0xFFE07140 /* Watchpoint Data Address Register 0 */ +#define WPDA1 0xFFE07144 /* Watchpoint Data Address Register 1 */ +#define WPDACNT0 0xFFE07180 /* Watchpoint Data Address Count Value Register 0 */ +#define WPDACNT1 0xFFE07184 /* Watchpoint Data Address Count Value Register 1 */ +#define WPSTAT 0xFFE07200 /* Watchpoint Status Register */ + +/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */ +#define PFCTL 0xFFE08000 /* Performance Monitor Control Register */ +#define PFCNTR0 0xFFE08100 /* Performance Monitor Counter Register 0 */ +#define PFCNTR1 0xFFE08104 /* Performance Monitor Counter Register 1 */ + +/* + * Core MMR Register Bits + */ + +/* + * EVT registers (ILAT, IMASK, and IPEND). + */ + +/* ** Bit Positions */ +#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */ +#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */ +#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */ +#define EVT_EVX_P 0x00000003 /* Exception bit position */ +#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */ +#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */ +#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */ +#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */ +#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */ +#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */ +#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */ +#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */ +#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */ +#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */ +#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */ +#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */ + +/* ** Masks */ +#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */ +#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */ +#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */ +#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */ +#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */ +#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */ +#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */ +#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */ +#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */ +#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */ +#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */ +#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */ +#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */ +#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */ +#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */ +#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */ + +/* + * DMEM_CONTROL Register + */ + +/* ** Bit Positions */ +#define ENDM_P 0x00 /* (doesn't really exist) Enable Data Memory L1 */ +#define DMCTL_ENDM_P 0x00 /* "" (older define) */ +#define DMC0_P 0x01 /* Data Memory Configuration, 00 - A SRAM, B SRAM */ +#define DMCTL_DMC0_P 0x01 /* "" (older define) */ +#define DMC1_P 0x02 /* Data Memory Configuration, 10 - A SRAM, B SRAM */ +#define DMCTL_DMC1_P 0x02 /* "" (older define) */ +#define DMC2_P 0x03 /* Data Memory Configuration, 11 - A CACHE, B CACHE */ +#define DMCTL_DMC2_P 0x03 /* "" (older define) */ +#define DCBS_P 0x04 /* L1 Data Cache Bank Select */ +#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */ +#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */ + +/* ** Masks */ +#define ENDM 0x00000001 /* (doesn't really exist) Enable Data Memory L1 */ +#define ENDCPLB 0x00000002 /* Enable DCPLB */ +#define ASRAM_BSRAM 0x00000000 +#define ACACHE_BSRAM 0x00000008 +#define ACACHE_BCACHE 0x0000000C +#define DCBS 0x00000010 /* L1 Data Cache Bank Select */ +#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */ +#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */ + +/* IMEM_CONTROL Register */ +/* ** Bit Positions */ +#define ENIM_P 0x00 /* Enable L1 Code Memory */ +#define IMCTL_ENIM_P 0x00 /* "" (older define) */ +#define ENICPLB_P 0x01 /* Enable ICPLB */ +#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */ +#define IMC_P 0x02 /* Enable */ +#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as cache (0=SRAM) */ +#define ILOC0_P 0x03 /* Lock Way 0 */ +#define ILOC1_P 0x04 /* Lock Way 1 */ +#define ILOC2_P 0x05 /* Lock Way 2 */ +#define ILOC3_P 0x06 /* Lock Way 3 */ +#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement Priority */ + +/* ** Masks */ +#define ENIM 0x00000001 /* Enable L1 Code Memory */ +#define ENICPLB 0x00000002 /* Enable ICPLB */ +#define IMC 0x00000004 /* Configure L1 code memory as cache (0=SRAM) */ +#define ILOC0 0x00000008 /* Lock Way 0 */ +#define ILOC1 0x00000010 /* Lock Way 1 */ +#define ILOC2 0x00000020 /* Lock Way 2 */ +#define ILOC3 0x00000040 /* Lock Way 3 */ +#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement Priority */ + +/* TCNTL Masks */ +#define TMPWR 0x00000001 /* Timer Low Power Control, 0=low power mode, 1=active state */ +#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */ +#define TAUTORLD 0x00000004 /* Timer auto reload */ +#define TINT 0x00000008 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */ + +/* TCNTL Bit Positions */ +#define TMPWR_P 0x00000000 /* Timer Low Power Control, 0=low power mode, 1=active state */ +#define TMREN_P 0x00000001 /* Timer enable, 0=disable, 1=enable */ +#define TAUTORLD_P 0x00000002 /* Timer auto reload */ +#define TINT_P 0x00000003 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */ + +/* DCPLB_DATA and ICPLB_DATA Registers */ +/* ** Bit Positions */ +#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */ +#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */ +#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */ + +/* ** Masks */ +#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ +#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */ +#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */ +#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ +#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ +#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ +#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ +#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */ +#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */ +#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */ + +/* ICPLB_DATA only */ +#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */ + +/* DCPLB_DATA only */ +#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */ +#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */ +#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */ +#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes */ + /* 1= allocate cache lines on write-through writes. */ +#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ + +/* ITEST_COMMAND and DTEST_COMMAND Registers */ +/* ** Masks */ +#define TEST_READ 0x00000000 /* Read Access */ +#define TEST_WRITE 0x00000002 /* Write Access */ +#define TEST_TAG 0x00000000 /* Access TAG */ +#define TEST_DATA 0x00000004 /* Access DATA */ +#define TEST_DW0 0x00000000 /* Select Double Word 0 */ +#define TEST_DW1 0x00000008 /* Select Double Word 1 */ +#define TEST_DW2 0x00000010 /* Select Double Word 2 */ +#define TEST_DW3 0x00000018 /* Select Double Word 3 */ +#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */ +#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */ +#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */ +#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */ +#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */ +#define TEST_WAY0 0x00000000 /* Access Way0 */ +#define TEST_WAY1 0x04000000 /* Access Way1 */ + +/* ** ITEST_COMMAND only */ +#define TEST_WAY2 0x08000000 /* Access Way2 */ +#define TEST_WAY3 0x0C000000 /* Access Way3 */ + +/* ** DTEST_COMMAND only */ +#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */ +#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */ + +#endif /* _DEF_LPBLACKFIN_H */ diff --git a/include/asm-blackfin/current.h b/include/asm-blackfin/current.h new file mode 100644 index 0000000..108c279 --- /dev/null +++ b/include/asm-blackfin/current.h @@ -0,0 +1,40 @@ +/* + * U-boot - current.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_CURRENT_H +#define _BLACKFIN_CURRENT_H +/* + * current.h + * (C) Copyright 2000, Lineo, David McCullough <davidm@lineo.com> + * + * rather than dedicate a register (as the m68k source does), we + * just keep a global, we should probably just change it all to be + * current and lose _current_task. + */ + +extern struct task_struct *_current_task; +#define get_current() _current_task +#define current _current_task + +#endif diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h new file mode 100644 index 0000000..dbb7388 --- /dev/null +++ b/include/asm-blackfin/delay.h @@ -0,0 +1,55 @@ +/* + * U-boot - delay.h Routines for introducing delays + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_DELAY_H +#define _BLACKFIN_DELAY_H + +/* + * Changes made by akbar.hussain@Lineo.com, for BLACKFIN + * Copyright (C) 1994 Hamish Macdonald + * + * Delay routines, using a pre-computed "loops_per_second" value. + */ + +extern __inline__ void __delay(unsigned long loops) +{ + __asm__ __volatile__("1:\t%0 += -1;\n\t" + "cc = %0 == 0;\n\t" + "if ! cc jump 1b;\n":"=d"(loops) + :"0"(loops)); +} + +/* + * Use only for very small delays ( < 1 msec). Should probably use a + * lookup table, really, as the multiplications take much too long with + * short delays. This is a "reasonable" implementation, though (and the + * first constant multiplications gets optimized away if the delay is + * a constant) + */ +extern __inline__ void udelay(unsigned long usecs) +{ + __delay(usecs); +} + +#endif diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h new file mode 100644 index 0000000..607a5b8 --- /dev/null +++ b/include/asm-blackfin/entry.h @@ -0,0 +1,385 @@ +/* + * U-boot - entry.h Routines for context saving and restoring + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BLACKFIN_ENTRY_H +#define __BLACKFIN_ENTRY_H + +#include <linux/config.h> +#include <asm/setup.h> +#include <asm/page.h> + +/* + * Stack layout in 'ret_from_exception': + * + */ + +/* + * Register %p2 is now set to the current task throughout + * the whole kernel. + */ + +#ifdef __ASSEMBLY__ + +#define LFLUSH_I_AND_D 0x00000808 +#define LSIGTRAP 5 + +/* process bits for task_struct.flags */ +#define PF_TRACESYS_OFF 3 +#define PF_TRACESYS_BIT 5 +#define PF_PTRACED_OFF 3 +#define PF_PTRACED_BIT 4 +#define PF_DTRACE_OFF 1 +#define PF_DTRACE_BIT 5 + +#define NEW_PT_REGS + +#if defined(NEW_PT_REGS) + +#define SAVE_ALL_INT save_context_no_interrupts +#define SAVE_ALL_SYS save_context_no_interrupts +#define SAVE_CONTEXT save_context_with_interrupts + +#define RESTORE_ALL restore_context_no_interrupts +#define RESTORE_ALL_SYS restore_context_no_interrupts +#define RESTORE_CONTEXT restore_context_with_interrupts + +#else + +#define SAVE_ALL_INT save_all_int +#define SAVE_ALL_SYS save_all_sys +#define SAVE_CONTEXT save_context +#define RESTORE_ALL restore_context +#define RESTORE_CONTEXT restore_context + +#endif + +/* + * Code to save processor context. + * We even save the register which are preserved by a function call + * - r4, r5, r6, r7, p3, p4, p5 + */ +.macro save_context_with_interrupts + [--sp] = R0; + [--sp] = ( R7:0, P5:0 ); + [--sp] = fp; + [--sp] = usp; + + [--sp] = i0; + [--sp] = i1; + [--sp] = i2; + [--sp] = i3; + + [--sp] = m0; + [--sp] = m1; + [--sp] = m2; + [--sp] = m3; + + [--sp] = l0; + [--sp] = l1; + [--sp] = l2; + [--sp] = l3; + + [--sp] = b0; + [--sp] = b1; + [--sp] = b2; + [--sp] = b3; + [--sp] = a0.x; + [--sp] = a0.w; + [--sp] = a1.x; + [--sp] = a1.w; + + [--sp] = LC0; + [--sp] = LC1; + [--sp] = LT0; + [--sp] = LT1; + [--sp] = LB0; + [--sp] = LB1; + + [--sp] = ASTAT; + + [--sp] = r0; /* Skip reserved */ + [--sp] = RETS; + [--sp] = RETI; + [--sp] = RETX; + [--sp] = RETN; + [--sp] = RETE; + [--sp] = SEQSTAT; + [--sp] = SYSCFG; + [--sp] = r0; /* Skip IPEND as well. */ +.endm + +.macro save_context_no_interrupts + [--sp] = R0; + [--sp] = ( R7:0, P5:0 ); + [--sp] = fp; + [--sp] = usp; + + [--sp] = i0; + [--sp] = i1; + [--sp] = i2; + [--sp] = i3; + + [--sp] = m0; + [--sp] = m1; + [--sp] = m2; + [--sp] = m3; + + [--sp] = l0; + [--sp] = l1; + [--sp] = l2; + [--sp] = l3; + + [--sp] = b0; + [--sp] = b1; + [--sp] = b2; + [--sp] = b3; + [--sp] = a0.x; + [--sp] = a0.w; + [--sp] = a1.x; + [--sp] = a1.w; + + [--sp] = LC0; + [--sp] = LC1; + [--sp] = LT0; + [--sp] = LT1; + [--sp] = LB0; + [--sp] = LB1; + + [--sp] = ASTAT; + + [--sp] = r0; /* Skip reserved */ + [--sp] = RETS; + r0 = RETI; + [--sp] = r0; + [--sp] = RETX; + [--sp] = RETN; + [--sp] = RETE; + [--sp] = SEQSTAT; + [--sp] = SYSCFG; + [--sp] = r0; /* Skip IPEND as well. */ +.endm + +.macro restore_context_no_interrupts + sp += 4; + SYSCFG = [sp++]; + SEQSTAT = [sp++]; + RETE = [sp++]; + RETN = [sp++]; + RETX = [sp++]; + r0 = [sp++]; + RETI = r0; + RETS = [sp++]; + + sp += 4; + + ASTAT = [sp++]; + + LB1 = [sp++]; + LB0 = [sp++]; + LT1 = [sp++]; + LT0 = [sp++]; + LC1 = [sp++]; + LC0 = [sp++]; + + a1.w = [sp++]; + a1.x = [sp++]; + a0.w = [sp++]; + a0.x = [sp++]; + b3 = [sp++]; + b2 = [sp++]; + b1 = [sp++]; + b0 = [sp++]; + + l3 = [sp++]; + l2 = [sp++]; + l1 = [sp++]; + l0 = [sp++]; + + m3 = [sp++]; + m2 = [sp++]; + m1 = [sp++]; + m0 = [sp++]; + + i3 = [sp++]; + i2 = [sp++]; + i1 = [sp++]; + i0 = [sp++]; + + sp += 4; + fp = [sp++]; + + ( R7 : 0, P5 : 0) = [ SP ++ ]; + sp += 4; +.endm + +.macro restore_context_with_interrupts + sp += 4; + SYSCFG = [sp++]; + SEQSTAT = [sp++]; + RETE = [sp++]; + RETN = [sp++]; + RETX = [sp++]; + RETI = [sp++]; + RETS = [sp++]; + + sp += 4; + + ASTAT = [sp++]; + + LB1 = [sp++]; + LB0 = [sp++]; + LT1 = [sp++]; + LT0 = [sp++]; + LC1 = [sp++]; + LC0 = [sp++]; + + a1.w = [sp++]; + a1.x = [sp++]; + a0.w = [sp++]; + a0.x = [sp++]; + b3 = [sp++]; + b2 = [sp++]; + b1 = [sp++]; + b0 = [sp++]; + + l3 = [sp++]; + l2 = [sp++]; + l1 = [sp++]; + l0 = [sp++]; + + m3 = [sp++]; + m2 = [sp++]; + m1 = [sp++]; + m0 = [sp++]; + + i3 = [sp++]; + i2 = [sp++]; + i1 = [sp++]; + i0 = [sp++]; + + sp += 4; + fp = [sp++]; + + ( R7 : 0, P5 : 0) = [ SP ++ ]; + sp += 4; +.endm + +#if !defined(NEW_PT_REGS) +/* + * a -1 in the orig_r0 field signifies + * that the stack frame is NOT for syscall + */ +.macro save_all_int +/* reserved and disable the single step of SYSCFG, by Steven Chen 03/07/10 */ + [--sp] = r0; + r0.l = 0x30; /* Errata for BF533 */ + r0.h = 0x0; + syscfg = r0; /* disable single step flag in SYSCFG */ + r0 = [sp++]; + [--sp] = syscfg; /* store SYSCFG */ + + [--sp] = r0; /* Reserved for IPEND */ + [--sp] = fp; + [--sp] = usp; + [--sp] = r0; + + [--sp] = r0; + r0 = [sp + 8]; + [--sp] = a0.x; + [--sp] = a1.x; + [--sp] = a0.w; + [--sp] = a1.w; + [--sp] = rets; + [--sp] = astat; + [--sp] = seqstat; + [--sp] = retx; /* current pc when exception happens */ + [--sp] = ( r7:5, p5:0 ); + [--sp] = r1; + [--sp] = r2; + [--sp] = r4; + [--sp] = r3; +.endm + +.macro save_all_sys + [--sp] = r0; + [--sp] = r0; + [--sp] = a0.x; + [--sp] = a1.x; + [--sp] = a0.w; + [--sp] = a1.w; + [--sp] = rets; + [--sp] = astat; + [--sp] = seqstat; + [--sp] = retx; /* current pc when exception happens */ + [--sp] = ( r7:5, p5:0 ); + [--sp] = r1; + [--sp] = r2; + [--sp] = r4; + [--sp] = r3; +.endm + +.macro restore_all + r3 = [sp++]; + r4 = [sp++]; + r2 = [sp++]; + r1 = [sp++]; + ( r7:5, p5:0 ) = [sp++]; + retx = [sp++]; + seqstat = [sp++]; + astat = [sp++]; + rets = [sp++]; + a1.w = [sp++]; + a0.w = [sp++]; + a1.x = [sp++]; + a0.x = [sp++]; + sp += 4; /* orig r0 */ + r0 = [sp++]; + + sp += 4; + fp = [sp++]; + sp +=4; /* Skip the IPEND */ + + syscfg = [sp++]; + +.endm + +#endif + +#define STR(X) STR1(X) +#define STR1(X) #X + +#if defined(NEW_PT_REGS) + +#define PT_OFF_ORIG_R0 208 +#define PT_OFF_SR 8 + +#else + +#define PT_OFF_ORIG_R0 0x54 +#define PT_OFF_SR 0x38 /* seqstat in pt_regs */ + +#endif +#endif + +#endif diff --git a/include/asm-blackfin/errno.h b/include/asm-blackfin/errno.h new file mode 100644 index 0000000..713bba0 --- /dev/null +++ b/include/asm-blackfin/errno.h @@ -0,0 +1,156 @@ +/* + * U-boot - errno.h Error number defines + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_ERRNO_H +#define _BLACKFIN_ERRNO_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Arg list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + +#endif diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h new file mode 100644 index 0000000..56a12f0 --- /dev/null +++ b/include/asm-blackfin/global_data.h @@ -0,0 +1,64 @@ +/* + * U-boot - global_data.h Declarations for global data of u-boot + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_GBL_DATA_H +#define __ASM_GBL_DATA_H + +#include <asm/irq.h> + +/* + * The following data structure is placed in some memory wich is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t) + */ +typedef struct global_data { + bd_t *bd; + unsigned long flags; + unsigned long board_type; + unsigned long baudrate; + unsigned long have_console; /* serial_init() was called */ + unsigned long ram_size; /* RAM size */ + unsigned long reloc_off; /* Relocation Offset */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid? */ + void **jt; /* jump table */ +} gd_t; + +/* + * Global Data Flags + */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ + +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("P5") + +#endif diff --git a/include/asm-blackfin/hw_irq.h b/include/asm-blackfin/hw_irq.h new file mode 100644 index 0000000..1ee050e --- /dev/null +++ b/include/asm-blackfin/hw_irq.h @@ -0,0 +1,37 @@ +/* + * U-boot - hw_irq.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * linux/arch/$(ARCH)/platform/$(PLATFORM)/hw_irq.h + * BlackFin (ADI) assembler restricted values by Ted Ma <mated@sympatico.ca> + * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) + * Copyright (c) 2002 Lineo, Inc <mattw@lineo.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <linux/config.h> +#ifdef CONFIG_EZKIT533 +#include <asm/board/bf533_irq.h> +#endif +#ifdef CONFIG_STAMP +#include <asm/board/bf533_irq.h> +#endif diff --git a/include/asm-blackfin/io-kernel.h b/include/asm-blackfin/io-kernel.h new file mode 100644 index 0000000..0b0572f --- /dev/null +++ b/include/asm-blackfin/io-kernel.h @@ -0,0 +1,135 @@ +/* + * U-boot - io-kernel.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_IO_H +#define _BLACKFIN_IO_H + +#ifdef __KERNEL__ + +#include <linux/config.h> + +/* + * These are for ISA/PCI shared memory _only_ and should never be used + * on any other type of memory, including Zorro memory. They are meant to + * access the bus in the bus byte order which is little-endian!. + * + * readX/writeX() are used to access memory mapped devices. On some + * architectures the memory mapped IO stuff needs to be accessed + * differently. On the m68k architecture, we just read/write the + * memory location directly. + */ +/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates + * two accesses to memory, which may be undesireable for some devices. + */ +#define readb(addr) ({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; }) +#define readw(addr) ({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; }) +#define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; }) +#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b)) +#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b)) +#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b)) +#define __raw_readb readb +#define __raw_readw readw +#define __raw_readl readl +#define __raw_writeb writeb +#define __raw_writew writew +#define __raw_writel writel +#define memset_io(a,b,c) memset((void *)(a),(b),(c)) +#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) +#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) +#define inb(addr) cf_inb((volatile unsigned char*)(addr)) +#define inw(addr) readw(addr) +#define inl(addr) readl(addr) +#define outb(x,addr) cf_outb((unsigned char)(x), (volatile unsigned char*)(addr)) +#define outw(x,addr) ((void) writew(x,addr)) +#define outl(x,addr) ((void) writel(x,addr)) +#define inb_p(addr) inb(addr) +#define inw_p(addr) inw(addr) +#define inl_p(addr) inl(addr) +#define outb_p(x,addr) outb(x,addr) +#define outw_p(x,addr) outw(x,addr) +#define outl_p(x,addr) outl(x,addr) +#define insb(port, addr, count) memcpy((void*)addr, (void*)port, count) +#define insw(port, addr, count) cf_insw((unsigned short*)addr, (unsigned short*)(port), (count)) +#define insl(port, addr, count) memcpy((void*)addr, (void*)port, (4*count)) +#define outsb(port, addr, count) memcpy((void*)port, (void*)addr, count) +#define outsw(port,addr,count) cf_outsw((unsigned short*)(port), (unsigned short*)addr, (count)) +#define outsl(port, addr, count) memcpy((void*)port, (void*)addr, (4*count)) +#define IO_SPACE_LIMIT 0xffff + +/* Values for nocacheflag and cmode */ +#define IOMAP_FULL_CACHING 0 +#define IOMAP_NOCACHE_SER 1 +#define IOMAP_NOCACHE_NONSER 2 +#define IOMAP_WRITETHROUGH 3 + +#ifndef __ASSEMBLY__ +extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag); +extern void __iounmap(void *addr, unsigned long size); +extern inline void *ioremap(unsigned long physaddr, unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); +} +extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); +} +extern inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_WRITETHROUGH); +} +extern inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_FULL_CACHING); +} + +extern void iounmap(void *addr); + +/* Nothing to do */ + +extern void blkfin_inv_cache_all(void); + +#endif + +#define dma_cache_inv(_start,_size) do { blkfin_inv_cache_all();} while (0) +#define dma_cache_wback(_start,_size) do { } while (0) +#define dma_cache_wback_inv(_start,_size) do { blkfin_inv_cache_all();} while (0) + +/* Pages to physical address... */ +#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT) +#define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT) + +#define mm_ptov(vaddr) ((void *) (vaddr)) +#define mm_vtop(vaddr) ((unsigned long) (vaddr)) +#define phys_to_virt(vaddr) ((void *) (vaddr)) +#define virt_to_phys(vaddr) ((unsigned long) (vaddr)) + +#define virt_to_bus virt_to_phys +#define bus_to_virt phys_to_virt + +#endif + +#endif diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h new file mode 100644 index 0000000..e5b388e --- /dev/null +++ b/include/asm-blackfin/io.h @@ -0,0 +1,122 @@ +/* + * U-boot - io.h IO routines + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_IO_H +#define _BLACKFIN_IO_H + +#ifdef __KERNEL__ + +#include <linux/config.h> + +/* function prototypes for CF support */ +extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words); +extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words); +extern unsigned char cf_inb(volatile unsigned char *addr); +extern void cf_outb(unsigned char val, volatile unsigned char* addr); + +/* + * These are for ISA/PCI shared memory _only_ and should never be used + * on any other type of memory, including Zorro memory. They are meant to + * access the bus in the bus byte order which is little-endian!. + * + * readX/writeX() are used to access memory mapped devices. On some + * architectures the memory mapped IO stuff needs to be accessed + * differently. On the m68k architecture, we just read/write the + * memory location directly. + */ + + +#define readb(addr) ({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; }) +#define readw(addr) ({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; }) +#define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; }) + +#define writeb(b,addr) {((*(volatile unsigned char *) (addr)) = (b)); asm("ssync;");} +#define writew(b,addr) {((*(volatile unsigned short *) (addr)) = (b)); asm("ssync;");} +#define writel(b,addr) {((*(volatile unsigned int *) (addr)) = (b)); asm("ssync;");} + +#define memset_io(a,b,c) memset((void *)(a),(b),(c)) +#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) +#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) + +#define inb_p(addr) readb((addr) + BF533_PCIIO_BASE) +#define inb(addr) cf_inb((volatile unsigned char*)(addr)) + +#define outb(x,addr) cf_outb((unsigned char)(x), (volatile unsigned char*)(addr)) +#define outb_p(x,addr) outb(x, (addr) + BF533_PCIIO_BASE) + +#define inw(addr) readw((addr) + BF533_PCIIO_BASE) +#define inl(addr) readl((addr) + BF533_PCIIO_BASE) + +#define outw(x,addr) writew(x, (addr) + BF533_PCIIO_BASE) +#define outl(x,addr) writel(x, (addr) + BF533_PCIIO_BASE) + +#define insb(port, addr, count) memcpy((void*)addr, (void*)(BF533_PCIIO_BASE + port), count) +#define insw(port, addr, count) cf_insw((unsigned short*)addr, (unsigned short*)(port), (count)) +#define insl(port, addr, count) memcpy((void*)addr, (void*)(BF533_PCIIO_BASE + port), (4*count)) + +#define outsb(port,addr,count) memcpy((void*)(BF533_PCIIO_BASE + port), (void*)addr, count) +#define outsw(port,addr,count) cf_outsw((unsigned short*)(port), (unsigned short*)addr, (count)) +#define outsl(port,addr,count) memcpy((void*)(BF533_PCIIO_BASE + port), (void*)addr, (4*count)) + +#define IO_SPACE_LIMIT 0xffff + +/* Values for nocacheflag and cmode */ +#define IOMAP_FULL_CACHING 0 +#define IOMAP_NOCACHE_SER 1 +#define IOMAP_NOCACHE_NONSER 2 +#define IOMAP_WRITETHROUGH 3 + +extern void *__ioremap(unsigned long physaddr, unsigned long size, + int cacheflag); +extern void __iounmap(void *addr, unsigned long size); + +extern inline void *ioremap(unsigned long physaddr, unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); +} +extern inline void *ioremap_nocache(unsigned long physaddr, + unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); +} +extern inline void *ioremap_writethrough(unsigned long physaddr, + unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_WRITETHROUGH); +} +extern inline void *ioremap_fullcache(unsigned long physaddr, + unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_FULL_CACHING); +} + +extern void iounmap(void *addr); + +extern void blkfin_inv_cache_all(void); +#define dma_cache_inv(_start,_size) do { blkfin_inv_cache_all();} while (0) +#define dma_cache_wback(_start,_size) do { } while (0) +#define dma_cache_wback_inv(_start,_size) do { blkfin_inv_cache_all();} while (0) + +#endif +#endif diff --git a/include/asm-blackfin/irq.h b/include/asm-blackfin/irq.h new file mode 100644 index 0000000..5fbc5a3 --- /dev/null +++ b/include/asm-blackfin/irq.h @@ -0,0 +1,142 @@ +/* + * U-boot - irq.h Interrupt related header file + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file was based on + * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c + * + * Changed by HuTao Apr18, 2003 + * + * Copyright was missing when I got the code so took from MIPS arch ...MaTed--- + * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle + * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle + * + * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca> + * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) + * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_IRQ_H_ +#define _BLACKFIN_IRQ_H_ + +#include <linux/config.h> +#include <asm/cpu/bf533_irq.h> + +/* + * On the Blackfin, the interrupt structure allows remmapping of the hardware + * levels. + * - I'm going to assume that the H/W level is going to stay at the default + * settings. If someone wants to go through and abstart this out, feel free + * to mod the interrupt numbering scheme. + * - I'm abstracting the interrupts so that uClinux does not know anything + * about the H/W levels. If you want to change the H/W AND keep the abstracted + * levels that uClinux sees, you should be able to do most of it here. + * - I've left the "abstract" numbering sparce in case someone wants to pull the + * interrupts apart (just the TX/RX for the various devices) + */ + +#define NR_IRQS SYS_IRQS +/* + * "Generic" interrupt sources + */ +#define IRQ_SCHED_TIMER (8) /* interrupt source for scheduling timer */ + +static __inline__ int irq_cannonicalize(int irq) +{ + return irq; +} + +/* + * Machine specific interrupt sources. + * + * Adding an interrupt service routine for a source with this bit + * set indicates a special machine specific interrupt source. + * The machine specific files define these sources. + * + * The IRQ_MACHSPEC bit is now gone - the only thing it did was to + * introduce unnecessary overhead. + * + * All interrupt handling is actually machine specific so it is better + * to use function pointers, as used by the Sparc port, and select the + * interrupt handling functions when initializing the kernel. This way + * we save some unnecessary overhead at run-time. + * 01/11/97 - Jes + */ + +extern void (*mach_enable_irq) (unsigned int); +extern void (*mach_disable_irq) (unsigned int); +extern int sys_request_irq(unsigned int, + void (*)(int, void *, struct pt_regs *), + unsigned long, const char *, void *); +extern void sys_free_irq(unsigned int, void *); + +/* + * various flags for request_irq() - the Amiga now uses the standard + * mechanism like all other architectures - SA_INTERRUPT and SA_SHIRQ + * are your friends. + */ +#define IRQ_FLG_LOCK (0x0001) /* handler is not replaceable */ +#define IRQ_FLG_REPLACE (0x0002) /* replace existing handler */ +#define IRQ_FLG_FAST (0x0004) +#define IRQ_FLG_SLOW (0x0008) +#define IRQ_FLG_STD (0x8000) /* internally used */ + +/* + * This structure is used to chain together the ISRs for a particular + * interrupt source (if it supports chaining). + */ +typedef struct irq_node { + void (*handler) (int, void *, struct pt_regs *); + unsigned long flags; + void *dev_id; + const char *devname; + struct irq_node *next; +} irq_node_t; + +/* + * This structure has only 4 elements for speed reasons + */ +typedef struct irq_handler { + void (*handler) (int, void *, struct pt_regs *); + unsigned long flags; + void *dev_id; + const char *devname; +} irq_handler_t; + +/* count of spurious interrupts */ +extern volatile unsigned int num_spurious; + +/* + * This function returns a new irq_node_t + */ +extern irq_node_t *new_irq_node(void); + +/* + * Some drivers want these entry points + */ +#define enable_irq(x) (mach_enable_irq ? (*mach_enable_irq)(x) : 0) +#define disable_irq(x) (mach_disable_irq ? (*mach_disable_irq)(x) : 0) + +#define enable_irq_nosync(x) enable_irq(x) +#define disable_irq_nosync(x) disable_irq(x) + +#endif diff --git a/include/asm-blackfin/linkage.h b/include/asm-blackfin/linkage.h new file mode 100644 index 0000000..18f0c36 --- /dev/null +++ b/include/asm-blackfin/linkage.h @@ -0,0 +1,60 @@ +/* + * U-boot - linkage.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _LINUX_LINKAGE_H +#define _LINUX_LINKAGE_H + +#include <linux/config.h> + +#ifdef __cplusplus +#define CPP_ASMLINKAGE extern "C" +#else +#define CPP_ASMLINKAGE +#endif + +#define asmlinkage CPP_ASMLINKAGE + +#define SYMBOL_NAME_STR(X) #X +#define SYMBOL_NAME(X) X +#ifdef __STDC__ +#define SYMBOL_NAME_LABEL(X) X##: +#else +#define SYMBOL_NAME_LABEL(X) X: +#endif + +#define __ALIGN .align 4 +#define __ALIGN_STR ".align 4" + +#ifdef __ASSEMBLY__ + +#define ALIGN __ALIGN +#define ALIGN_STR __ALIGN_STR + +#define ENTRY(name) \ + .globl SYMBOL_NAME(name); \ + ALIGN; \ + SYMBOL_NAME_LABEL(name) +#endif + +#endif diff --git a/include/asm-blackfin/machdep.h b/include/asm-blackfin/machdep.h new file mode 100644 index 0000000..0a43ba1 --- /dev/null +++ b/include/asm-blackfin/machdep.h @@ -0,0 +1,89 @@ +/* + * U-boot - machdep.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_MACHDEP_H +#define _BLACKFIN_MACHDEP_H + +/* Machine dependent initial routines: + * + * Based on include/asm-m68knommu/machdep.h + * For blackfin, just now we only have bfin, so they'd point to the default bfin + * + */ + +struct pt_regs; +struct kbd_repeat; +struct mktime; +struct hwclk_time; +struct gendisk; +struct buffer_head; + +extern void (*mach_sched_init) (void (*handler) (int, void *, struct pt_regs *)); + +/* machine dependent keyboard functions */ +extern int (*mach_keyb_init) (void); +extern int (*mach_kbdrate) (struct kbd_repeat *); +extern void (*mach_kbd_leds) (unsigned int); + +/* machine dependent irq functions */ +extern void (*mach_init_IRQ) (void); +extern void (*(*mach_default_handler)[]) (int, void *, struct pt_regs *); +extern int (*mach_request_irq) (unsigned int irq, + void (*handler) (int, void *, + struct pt_regs *), + unsigned long flags, const char *devname, + void *dev_id); +extern void (*mach_free_irq) (unsigned int irq, void *dev_id); +extern void (*mach_get_model) (char *model); +extern int (*mach_get_hardware_list) (char *buffer); +extern int (*mach_get_irq_list) (char *buf); +extern void (*mach_process_int) (int irq, struct pt_regs * fp); + +/* machine dependent timer functions */ +extern unsigned long (*mach_gettimeoffset) (void); +extern void (*mach_gettod) (int *year, int *mon, int *day, int *hour, + int *min, int *sec); +extern int (*mach_hwclk) (int, struct hwclk_time *); +extern int (*mach_set_clock_mmss) (unsigned long); +extern void (*mach_reset) (void); +extern void (*mach_halt) (void); +extern void (*mach_power_off) (void); +extern unsigned long (*mach_hd_init) (unsigned long, unsigned long); +extern void (*mach_hd_setup) (char *, int *); +extern long mach_max_dma_address; +extern void (*mach_floppy_setup) (char *, int *); +extern void (*mach_floppy_eject) (void); +extern void (*mach_heartbeat) (int); +extern void (*mach_l2_flush) (int); +extern int mach_sysrq_key; +extern int mach_sysrq_shift_state; +extern int mach_sysrq_shift_mask; +extern char *mach_sysrq_xlate; + +#ifdef CONFIG_UCLINUX +extern void config_BSP(char *command, int len); +extern void (*mach_tick) (void); +#endif + +#endif diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h new file mode 100644 index 0000000..1a13d90 --- /dev/null +++ b/include/asm-blackfin/mem_init.h @@ -0,0 +1,287 @@ +/* + * U-boot - mem_init.h Header file for memory initialization + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#if ( CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E ) + #if ( CONFIG_SCLK_HZ > 119402985 ) + #define SDRAM_tRP TRP_2 + #define SDRAM_tRP_num 2 + #define SDRAM_tRAS TRAS_7 + #define SDRAM_tRAS_num 7 + #define SDRAM_tRCD TRCD_2 + #define SDRAM_tWR TWR_2 + #endif + #if ( CONFIG_SCLK_HZ > 104477612 ) && ( CONFIG_SCLK_HZ <= 119402985 ) + #define SDRAM_tRP TRP_2 + #define SDRAM_tRP_num 2 + #define SDRAM_tRAS TRAS_6 + #define SDRAM_tRAS_num 6 + #define SDRAM_tRCD TRCD_2 + #define SDRAM_tWR TWR_2 + #endif + #if ( CONFIG_SCLK_HZ > 89552239 ) && ( CONFIG_SCLK_HZ <= 104477612 ) + #define SDRAM_tRP TRP_2 + #define SDRAM_tRP_num 2 + #define SDRAM_tRAS TRAS_5 + #define SDRAM_tRAS_num 5 + #define SDRAM_tRCD TRCD_2 + #define SDRAM_tWR TWR_2 + #endif + #if ( CONFIG_SCLK_HZ > 74626866 ) && ( CONFIG_SCLK_HZ <= 89552239 ) + #define SDRAM_tRP TRP_2 + #define SDRAM_tRP_num 2 + #define SDRAM_tRAS TRAS_4 + #define SDRAM_tRAS_num 4 + #define SDRAM_tRCD TRCD_2 + #define SDRAM_tWR TWR_2 + #endif + #if ( CONFIG_SCLK_HZ > 66666667 ) && ( CONFIG_SCLK_HZ <= 74626866 ) + #define SDRAM_tRP TRP_2 + #define SDRAM_tRP_num 2 + #define SDRAM_tRAS TRAS_3 + #define SDRAM_tRAS_num 3 + #define SDRAM_tRCD TRCD_2 + #define SDRAM_tWR TWR_2 + #endif + #if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 ) + #define SDRAM_tRP TRP_1 + #define SDRAM_tRP_num 1 + #define SDRAM_tRAS TRAS_4 + #define SDRAM_tRAS_num 3 + #define SDRAM_tRCD TRCD_1 + #define SDRAM_tWR TWR_2 + #endif + #if ( CONFIG_SCLK_HZ > 44776119 ) && ( CONFIG_SCLK_HZ <= 59701493 ) + #define SDRAM_tRP TRP_1 + #define SDRAM_tRP_num 1 + #define SDRAM_tRAS TRAS_3 + #define SDRAM_tRAS_num 3 + #define SDRAM_tRCD TRCD_1 + #define SDRAM_tWR TWR_2 + #endif + #if ( CONFIG_SCLK_HZ > 29850746 ) && ( CONFIG_SCLK_HZ <= 44776119 ) + #define SDRAM_tRP TRP_1 + #define SDRAM_tRP_num 1 + #define SDRAM_tRAS TRAS_2 + #define SDRAM_tRAS_num 2 + #define SDRAM_tRCD TRCD_1 + #define SDRAM_tWR TWR_2 + #endif + #if ( CONFIG_SCLK_HZ <= 29850746 ) + #define SDRAM_tRP TRP_1 + #define SDRAM_tRP_num 1 + #define SDRAM_tRAS TRAS_1 + #define SDRAM_tRAS_num 1 + #define SDRAM_tRCD TRCD_1 + #define SDRAM_tWR TWR_2 + #endif +#endif + +#if (CONFIG_MEM_MT48LC16M16A2TG_75) + /*SDRAM INFORMATION: */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ + #define SDRAM_CL CL_3 +#endif + +#if (CONFIG_MEM_MT48LC64M4A2FB_7E) + /*SDRAM INFORMATION: */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ + #define SDRAM_CL CL_2 +#endif + +#if ( CONFIG_MEM_SIZE == 128 ) + #define SDRAM_SIZE EBSZ_128 +#endif +#if ( CONFIG_MEM_SIZE == 64 ) + #define SDRAM_SIZE EBSZ_64 +#endif +#if ( CONFIG_MEM_SIZE == 32 ) + #define SDRAM_SIZE EBSZ_32 +#endif +#if ( CONFIG_MEM_SIZE == 16 ) + #define SDRAM_SIZE EBSZ_16 +#endif +#if ( CONFIG_MEM_ADD_WDTH == 11 ) + #define SDRAM_WIDTH EBCAW_11 +#endif +#if ( CONFIG_MEM_ADD_WDTH == 10 ) + #define SDRAM_WIDTH EBCAW_10 +#endif +#if ( CONFIG_MEM_ADD_WDTH == 9 ) + #define SDRAM_WIDTH EBCAW_9 +#endif +#if ( CONFIG_MEM_ADD_WDTH == 8 ) + #define SDRAM_WIDTH EBCAW_8 +#endif + +#define mem_SDBCTL SDRAM_WIDTH | SDRAM_SIZE | EBE + +/* Equation from section 17 (p17-46) of BF533 HRM */ +#define mem_SDRRC ((( CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) + +/* Enable SCLK Out */ +#define mem_SDGCTL ( SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS ) + +#define flash_EBIU_AMBCTL_WAT ( ( CONFIG_FLASH_SPEED_BWAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 +#define flash_EBIU_AMBCTL_RAT ( ( CONFIG_FLASH_SPEED_BRAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 +#define flash_EBIU_AMBCTL_HT ( ( CONFIG_FLASH_SPEED_BHT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) +#define flash_EBIU_AMBCTL_ST ( ( CONFIG_FLASH_SPEED_BST * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 +#define flash_EBIU_AMBCTL_TT ( ( CONFIG_FLASH_SPEED_BTT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 + +#if (flash_EBIU_AMBCTL_TT > 3 ) + #define flash_EBIU_AMBCTL0_TT B0TT_4 +#endif +#if (flash_EBIU_AMBCTL_TT == 3 ) + #define flash_EBIU_AMBCTL0_TT B0TT_3 +#endif +#if (flash_EBIU_AMBCTL_TT == 2 ) + #define flash_EBIU_AMBCTL0_TT B0TT_2 +#endif +#if (flash_EBIU_AMBCTL_TT < 2 ) + #define flash_EBIU_AMBCTL0_TT B0TT_1 +#endif + +#if (flash_EBIU_AMBCTL_ST > 3 ) + #define flash_EBIU_AMBCTL0_ST B0ST_4 +#endif +#if (flash_EBIU_AMBCTL_ST == 3 ) + #define flash_EBIU_AMBCTL0_ST B0ST_3 +#endif +#if (flash_EBIU_AMBCTL_ST == 2 ) + #define flash_EBIU_AMBCTL0_ST B0ST_2 +#endif +#if (flash_EBIU_AMBCTL_ST < 2 ) + #define flash_EBIU_AMBCTL0_ST B0ST_1 +#endif + +#if (flash_EBIU_AMBCTL_HT > 2 ) + #define flash_EBIU_AMBCTL0_HT B0HT_3 +#endif +#if (flash_EBIU_AMBCTL_HT == 2 ) + #define flash_EBIU_AMBCTL0_HT B0HT_2 +#endif +#if (flash_EBIU_AMBCTL_HT == 1 ) + #define flash_EBIU_AMBCTL0_HT B0HT_1 +#endif +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) + #define flash_EBIU_AMBCTL0_HT B0HT_0 +#endif +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) + #define flash_EBIU_AMBCTL0_HT B0HT_1 +#endif + +#if (flash_EBIU_AMBCTL_WAT > 14) + #define flash_EBIU_AMBCTL0_WAT B0WAT_15 +#endif +#if (flash_EBIU_AMBCTL_WAT == 14) + #define flash_EBIU_AMBCTL0_WAT B0WAT_14 +#endif +#if (flash_EBIU_AMBCTL_WAT == 13) + #define flash_EBIU_AMBCTL0_WAT B0WAT_13 +#endif +#if (flash_EBIU_AMBCTL_WAT == 12) + #define flash_EBIU_AMBCTL0_WAT B0WAT_12 +#endif +#if (flash_EBIU_AMBCTL_WAT == 11) + #define flash_EBIU_AMBCTL0_WAT B0WAT_11 +#endif +#if (flash_EBIU_AMBCTL_WAT == 10) + #define flash_EBIU_AMBCTL0_WAT B0WAT_10 +#endif +#if (flash_EBIU_AMBCTL_WAT == 9) + #define flash_EBIU_AMBCTL0_WAT B0WAT_9 +#endif +#if (flash_EBIU_AMBCTL_WAT == 8) + #define flash_EBIU_AMBCTL0_WAT B0WAT_8 +#endif +#if (flash_EBIU_AMBCTL_WAT == 7) + #define flash_EBIU_AMBCTL0_WAT B0WAT_7 +#endif +#if (flash_EBIU_AMBCTL_WAT == 6) + #define flash_EBIU_AMBCTL0_WAT B0WAT_6 +#endif +#if (flash_EBIU_AMBCTL_WAT == 5) + #define flash_EBIU_AMBCTL0_WAT B0WAT_5 +#endif +#if (flash_EBIU_AMBCTL_WAT == 4) + #define flash_EBIU_AMBCTL0_WAT B0WAT_4 +#endif +#if (flash_EBIU_AMBCTL_WAT == 3) + #define flash_EBIU_AMBCTL0_WAT B0WAT_3 +#endif +#if (flash_EBIU_AMBCTL_WAT == 2) + #define flash_EBIU_AMBCTL0_WAT B0WAT_2 +#endif +#if (flash_EBIU_AMBCTL_WAT == 1) + #define flash_EBIU_AMBCTL0_WAT B0WAT_1 +#endif + +#if (flash_EBIU_AMBCTL_RAT > 14) + #define flash_EBIU_AMBCTL0_RAT B0RAT_15 +#endif +#if (flash_EBIU_AMBCTL_RAT == 14) + #define flash_EBIU_AMBCTL0_RAT B0RAT_14 +#endif +#if (flash_EBIU_AMBCTL_RAT == 13) + #define flash_EBIU_AMBCTL0_RAT B0RAT_13 +#endif +#if (flash_EBIU_AMBCTL_RAT == 12) + #define flash_EBIU_AMBCTL0_RAT B0RAT_12 +#endif +#if (flash_EBIU_AMBCTL_RAT == 11) + #define flash_EBIU_AMBCTL0_RAT B0RAT_11 +#endif +#if (flash_EBIU_AMBCTL_RAT == 10) + #define flash_EBIU_AMBCTL0_RAT B0RAT_10 +#endif +#if (flash_EBIU_AMBCTL_RAT == 9) + #define flash_EBIU_AMBCTL0_RAT B0RAT_9 +#endif +#if (flash_EBIU_AMBCTL_RAT == 8) + #define flash_EBIU_AMBCTL0_RAT B0RAT_8 +#endif +#if (flash_EBIU_AMBCTL_RAT == 7) + #define flash_EBIU_AMBCTL0_RAT B0RAT_7 +#endif +#if (flash_EBIU_AMBCTL_RAT == 6) + #define flash_EBIU_AMBCTL0_RAT B0RAT_6 +#endif +#if (flash_EBIU_AMBCTL_RAT == 5) + #define flash_EBIU_AMBCTL0_RAT B0RAT_5 +#endif +#if (flash_EBIU_AMBCTL_RAT == 4) + #define flash_EBIU_AMBCTL0_RAT B0RAT_4 +#endif +#if (flash_EBIU_AMBCTL_RAT == 3) + #define flash_EBIU_AMBCTL0_RAT B0RAT_3 +#endif +#if (flash_EBIU_AMBCTL_RAT == 2) + #define flash_EBIU_AMBCTL0_RAT B0RAT_2 +#endif +#if (flash_EBIU_AMBCTL_RAT == 1) + #define flash_EBIU_AMBCTL0_RAT B0RAT_1 +#endif + +#define flash_EBIU_AMBCTL0 flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h new file mode 100644 index 0000000..406ece5 --- /dev/null +++ b/include/asm-blackfin/page.h @@ -0,0 +1,128 @@ +/* + * U-boot - page.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_PAGE_H +#define _BLACKFIN_PAGE_H + +#include <linux/config.h> + +/* PAGE_SHIFT determines the page size */ + +#define PAGE_SHIFT (12) +#define PAGE_SIZE (4096) +#define PAGE_MASK (~(PAGE_SIZE-1)) + +#ifdef __KERNEL__ + +#include <asm/setup.h> + +#if PAGE_SHIFT < 13 +#define KTHREAD_SIZE (8192) +#else +#define KTHREAD_SIZE PAGE_SIZE +#endif + +#ifndef __ASSEMBLY__ + +#define get_user_page(vaddr) __get_free_page(GFP_KERNEL) +#define free_user_page(page, addr) free_page(addr) + +#define clear_page(page) memset((page), 0, PAGE_SIZE) +#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE) + +#define clear_user_page(page, vaddr) clear_page(page) +#define copy_user_page(to, from, vaddr) copy_page(to, from) + +/* + * These are used to make use of C type-checking.. + */ +typedef struct { + unsigned long pte; +} pte_t; +typedef struct { + unsigned long pmd[16]; +} pmd_t; +typedef struct { + unsigned long pgd; +} pgd_t; +typedef struct { + unsigned long pgprot; +} pgprot_t; + +#define pte_val(x) ((x).pte) +#define pmd_val(x) ((&x)->pmd[0]) +#define pgd_val(x) ((x).pgd) +#define pgprot_val(x) ((x).pgprot) + +#define __pte(x) ((pte_t) { (x) } ) +#define __pmd(x) ((pmd_t) { (x) } ) +#define __pgd(x) ((pgd_t) { (x) } ) +#define __pgprot(x) ((pgprot_t) { (x) } ) + +/* to align the pointer to the (next) page boundary */ +#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) + +/* Pure 2^n version of get_order */ +extern __inline__ int get_order(unsigned long size) +{ + int order; + + size = (size - 1) >> (PAGE_SHIFT - 1); + order = -1; + do { + size >>= 1; + order++; + } while (size); + return order; +} + +#endif /* !__ASSEMBLY__ */ + +#include <asm/page_offset.h> + +#define PAGE_OFFSET (PAGE_OFFSET_RAW) + +#ifndef __ASSEMBLY__ + +#define __pa(vaddr) virt_to_phys((void *)vaddr) +#define __va(paddr) phys_to_virt((unsigned long)paddr) + +#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT) +#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)) +#define VALID_PAGE(page) ((page - mem_map) < max_mapnr) + +#define BUG() do { \ + \ + while (1); /* dead-loop */ \ +} while (0) + +#define PAGE_BUG(page) do { \ + BUG(); \ +} while (0) + +#endif + +#endif + +#endif diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h new file mode 100644 index 0000000..262473f --- /dev/null +++ b/include/asm-blackfin/page_offset.h @@ -0,0 +1,35 @@ +/* + * U-boot - page_offset.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Changes made by Akbar Hussain April 10, 2001 + */ + +#include <linux/config.h> + +/* This handles the memory map.. */ + +#ifdef CONFIG_BLACKFIN +#define PAGE_OFFSET_RAW 0x00000000 +#endif diff --git a/include/asm-blackfin/posix_types.h b/include/asm-blackfin/posix_types.h new file mode 100644 index 0000000..f1f2b5f --- /dev/null +++ b/include/asm-blackfin/posix_types.h @@ -0,0 +1,90 @@ +/* + * U-boot - posix_types.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ARCH_BLACKFIN_POSIX_TYPES_H +#define __ARCH_BLACKFIN_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char *__kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) + +#undef __FD_CLR +#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) + +#undef __FD_ISSET +#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) + +#undef __FD_ZERO +#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) + +#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ + +#endif diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h new file mode 100644 index 0000000..19bd720 --- /dev/null +++ b/include/asm-blackfin/processor.h @@ -0,0 +1,174 @@ +/* + * U-boot - processor.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * include/asm-m68k/processor.h + * Changes made by Akbar Hussain Lineo, Inc, May 2001 for BLACKFIN + * Copyright (C) 1995 Hamish Macdonald + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_BLACKFIN_PROCESSOR_H +#define __ASM_BLACKFIN_PROCESSOR_H + +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ __label__ _l; _l: &&_l;}) + +#include <linux/config.h> +#include <asm/segment.h> +#include <asm/ptrace.h> +#include <asm/current.h> + +extern inline unsigned long rdusp(void) +{ + unsigned long usp; + + __asm__ __volatile__("%0 = usp;\n\t":"=da"(usp)); + return usp; +} + +extern inline void wrusp(unsigned long usp) +{ + __asm__ __volatile__("usp = %0;\n\t"::"da"(usp)); +} + +/* + * User space process size: 3.75GB. This is hardcoded into a few places, + * so don't change it unless you know what you are doing. + */ +#define TASK_SIZE (0xF0000000UL) + +/* + * Bus types + */ +#define EISA_bus 0 +#define MCA_bus 0 + +/* There is no pc register avaliable for BLACKFIN, so we are going to get + * it indirectly + */ + +#if 0 +inline unsigned long obtain_pc_indirectly(void) +{ + unsigned long pc; + __asm__ __volatile__("%0 = rets;\n":"=d"(pc)); + return (pc - 4); /* call pcrel24 is 4 bytes long */ +} +#endif + +/* + * if you change this structure, you must change the code and offsets + * in m68k/machasm.S + */ + +struct thread_struct { + unsigned long ksp; /* kernel stack pointer */ + unsigned long usp; /* user stack pointer */ + unsigned short seqstat; /* saved status register */ + unsigned long esp0; /* points to SR of stack frame pt_regs */ + unsigned long pc; /* instruction pointer */ +}; + +#define INIT_MMAP { &init_mm, 0, 0x40000000, NULL, __pgprot(_PAGE_PRESENT|_PAGE_ACCESSED), VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL } + +#define INIT_THREAD { \ + sizeof(init_stack) + (unsigned long) init_stack, 0, \ + PS_S, 0\ +} + +/* + * Do necessary setup to start up a newly executed thread. + * + * pass the data segment into user programs if it exists, + * it can't hurt anything as far as I can tell + */ +#define start_thread(_regs, _pc, _usp) \ +do { \ + set_fs(USER_DS); /* reads from user space */ \ + (_regs)->pc = (_pc); \ + if (current->mm) \ + (_regs)->r5 = current->mm->start_data; \ + (_regs)->seqstat &= ~0x0c00; \ + wrusp(_usp); \ + /* Adde by HuTao, May 26, 2003 3:39PM */\ + if ((_regs)->ipend & 0x8000) /* check whether system in supper mode - StChen */\ + (_regs)->ipend = 0x0;\ +} while(0) + +/* Forward declaration, a strange C thing */ +struct task_struct; + +/* Free all resources held by a thread. */ +static inline void release_thread(struct task_struct *dead_task) +{ +} + +extern int kernel_thread(int (*fn) (void *), void *arg, + unsigned long flags); + +#define copy_segments(tsk, mm) do { } while (0) +#define release_segments(mm) do { } while (0) +#define forget_segments() do { } while (0) + +/* + * Free current thread data structures etc.. + */ +static inline void exit_thread(void) +{ +} + +/* + * Return saved PC of a blocked thread. + */ +extern inline unsigned long thread_saved_pc(struct thread_struct *t) +{ + extern void scheduling_functions_start_here(void); + extern void scheduling_functions_end_here(void); + return 0; +} + +unsigned long get_wchan(struct task_struct *p); + +#define KSTK_EIP(tsk) \ + ({ \ + unsigned long eip = 0; \ + if ((tsk)->thread.esp0 > PAGE_SIZE && \ + MAP_NR((tsk)->thread.esp0) < max_mapnr) \ + eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \ + eip; }) +#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) +#define THREAD_SIZE (2*PAGE_SIZE) + +/* Allocation and freeing of basic task resources. */ +#define alloc_task_struct() \ + ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) +#define free_task_struct(p) free_pages((unsigned long)(p),1) +#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) + +#define init_task (init_task_union.task) +#define init_stack (init_task_union.stack) + +#endif diff --git a/include/asm-blackfin/ptrace.h b/include/asm-blackfin/ptrace.h new file mode 100644 index 0000000..afd5777 --- /dev/null +++ b/include/asm-blackfin/ptrace.h @@ -0,0 +1,269 @@ +/* + * U-boot - ptrace.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_PTRACE_H +#define _BLACKFIN_PTRACE_H + +#define NEW_PT_REGS + +/* + * GCC defines register number like this: + * ----------------------------- + * 0 - 7 are data registers R0-R7 + * 8 - 15 are address registers P0-P7 + * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3 + * 32 - 33 A registers A0 & A1 + * 34 - status register + * + * We follows above, except: + * 32-33 --- Low 32-bit of A0&1 + * 34-35 --- High 8-bit of A0&1 + */ + +#if defined(NEW_PT_REGS) + +#define PT_IPEND 0 +#define PT_SYSCFG (PT_IPEND+4) +#define PT_SEQSTAT (PT_SYSCFG+4) +#define PT_RETE (PT_SEQSTAT+4) +#define PT_RETN (PT_RETE+4) +#define PT_RETX (PT_RETN+4) +#define PT_RETI (PT_RETX+4) +#define PT_PC PT_RETI +#define PT_RETS (PT_RETI+4) +#define PT_RESERVED (PT_RETS+4) +#define PT_ASTAT (PT_RESERVED+4) +#define PT_LB1 (PT_ASTAT+4) +#define PT_LB0 (PT_LB1+4) +#define PT_LT1 (PT_LB0+4) +#define PT_LT0 (PT_LT1+4) +#define PT_LC1 (PT_LT0+4) +#define PT_LC0 (PT_LC1+4) +#define PT_A1W (PT_LC0+4) +#define PT_A1X (PT_A1W+4) +#define PT_A0W (PT_A1X+4) +#define PT_A0X (PT_A0W+4) +#define PT_B3 (PT_A0X+4) +#define PT_B2 (PT_B3+4) +#define PT_B1 (PT_B2+4) +#define PT_B0 (PT_B1+4) +#define PT_L3 (PT_B0+4) +#define PT_L2 (PT_L3+4) +#define PT_L1 (PT_L2+4) +#define PT_L0 (PT_L1+4) +#define PT_M3 (PT_L0+4) +#define PT_M2 (PT_M3+4) +#define PT_M1 (PT_M2+4) +#define PT_M0 (PT_M1+4) +#define PT_I3 (PT_M0+4) +#define PT_I2 (PT_I3+4) +#define PT_I1 (PT_I2+4) +#define PT_I0 (PT_I1+4) +#define PT_USP (PT_I0+4) +#define PT_FP (PT_USP+4) +#define PT_P5 (PT_FP+4) +#define PT_P4 (PT_P5+4) +#define PT_P3 (PT_P4+4) +#define PT_P2 (PT_P3+4) +#define PT_P1 (PT_P2+4) +#define PT_P0 (PT_P1+4) +#define PT_R7 (PT_P0+4) +#define PT_R6 (PT_R7+4) +#define PT_R5 (PT_R6+4) +#define PT_R4 (PT_R5+4) +#define PT_R3 (PT_R4+4) +#define PT_R2 (PT_R3+4) +#define PT_R1 (PT_R2+4) +#define PT_R0 (PT_R1+4) +#define PT_ORIG_R0 (PT_R0+4) +#define PT_SR PT_SEQSTAT + +#else +/* + * Here utilize blackfin : dpregs = [pregs + imm16s4] + * [pregs + imm16s4] = dpregs + * to access defferent saved reg in stack + */ +#define PT_R3 0 +#define PT_R4 4 +#define PT_R2 8 +#define PT_R1 12 +#define PT_P5 16 +#define PT_P4 20 +#define PT_P3 24 +#define PT_P2 28 +#define PT_P1 32 +#define PT_P0 36 +#define PT_R7 40 +#define PT_R6 44 +#define PT_R5 48 +#define PT_PC 52 +#define PT_SEQSTAT 56 /* so-called SR reg */ +#define PT_SR PT_SEQSTAT +#define PT_ASTAT 60 +#define PT_RETS 64 +#define PT_A1w 68 +#define PT_A0w 72 +#define PT_A1x 76 +#define PT_A0x 80 +#define PT_ORIG_R0 84 +#define PT_R0 88 +#define PT_USP 92 +#define PT_FP 96 +#define PT_SP 100 + +/* Added by HuTao, May26 2003 3:18PM */ +#define PT_IPEND 100 + +/* Add SYSCFG register for single stepping support */ +#define PT_SYSCFG 104 + +#endif + +#ifndef __ASSEMBLY__ + +#if defined(NEW_PT_REGS) +/* this struct defines the way the registers are stored on the + * stack during a system call. + */ +struct pt_regs { + long ipend; + long syscfg; + long seqstat; + long rete; + long retn; + long retx; + long pc; + long rets; + long reserved; + long astat; + long lb1; + long lb0; + long lt1; + long lt0; + long lc1; + long lc0; + long a1w; + long a1x; + long a0w; + long a0x; + long b3; + long b2; + long b1; + long b0; + long l3; + long l2; + long l1; + long l0; + long m3; + long m2; + long m1; + long m0; + long i3; + long i2; + long i1; + long i0; + long usp; + long fp; + long p5; + long p4; + long p3; + long p2; + long p1; + long p0; + long r7; + long r6; + long r5; + long r4; + long r3; + long r2; + long r1; + long r0; + long orig_r0; +}; + +#else +/* now we don't know what regs the system call will use */ +struct pt_regs { + long r3; + long r4; + long r2; + long r1; + long p5; + long p4; + long p3; + long p2; + long p1; + long p0; + long r7; + long r6; + long r5; + unsigned long pc; + unsigned long seqstat; + unsigned long astat; + unsigned long rets; + long a1w; + long a0w; + long a1x; + long a0x; + long orig_r0; + long r0; + long usp; + long fp; +/* + * Added for supervisor/user mode switch. + * + * HuTao May26 03 3:23PM + */ + long ipend; + long syscfg; +}; + +#endif + +/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ +#define PTRACE_GETREGS 12 +#define PTRACE_SETREGS 13 /* ptrace signal */ + +#ifdef __KERNEL__ + +#ifndef PS_S +#define PS_S (0x0c00) + +/* Bit 11:10 of SEQSTAT defines user/supervisor/debug mode + * 00: user + * 01: supervisor + * 1x: debug + */ + +#define PS_M (0x1000) /* I am not sure why this is required here Akbar */ +#endif + +#define user_mode(regs) (!((regs)->seqstat & PS_S)) +#define instruction_pointer(regs) ((regs)->pc) +extern void show_regs(struct pt_regs *); + +#endif +#endif +#endif diff --git a/include/asm-blackfin/segment.h b/include/asm-blackfin/segment.h new file mode 100644 index 0000000..9e6d817 --- /dev/null +++ b/include/asm-blackfin/segment.h @@ -0,0 +1,46 @@ +/* + * U-boot - segment.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_SEGMENT_H +#define _BLACKFIN_SEGMENT_H + +/* define constants */ +typedef unsigned long mm_segment_t; /* domain register */ + +#define KERNEL_CS 0x0 +#define KERNEL_DS 0x0 +#define __KERNEL_CS 0x0 +#define __KERNEL_DS 0x0 + +#define USER_CS 0x1 +#define USER_DS 0x1 +#define __USER_CS 0x1 +#define __USER_DS 0x1 + +#define get_ds() (KERNEL_DS) +#define get_fs() (__USER_DS) +#define segment_eq(a,b) ((a) == (b)) +#define set_fs(val) + +#endif diff --git a/include/asm-blackfin/setup.h b/include/asm-blackfin/setup.h new file mode 100644 index 0000000..6ce9688 --- /dev/null +++ b/include/asm-blackfin/setup.h @@ -0,0 +1,86 @@ +/* + * U-boot - setup.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * asm/setup.h -- Definition of the Linux/Blackfin setup information + * Copyright Lineo, Inc 2001 Tony Kou + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_SETUP_H +#define _BLACKFIN_SETUP_H + +#include <linux/config.h> + +/* + * Linux/Blackfin Architectures + */ + +#define MACH_BFIN 1 + +#ifdef __KERNEL__ + +#ifndef __ASSEMBLY__ +extern unsigned long blackfin_machtype; +#endif + +#if defined(CONFIG_BFIN) +#define MACH_IS_BFIN (blackfin_machtype == MACH_BFIN) +#endif + +#ifndef MACH_TYPE +#define MACH_TYPE (blackfin_machtype) +#endif + +#endif + +/* + * CPU, FPU and MMU types + * + * Note: we don't need now: + * + */ + +#ifndef __ASSEMBLY__ +extern unsigned long blackfin_cputype; +#ifdef CONFIG_VME +extern unsigned long vme_brdtype; +#endif + +/* + * Miscellaneous + */ + +#define NUM_MEMINFO 4 +#define CL_SIZE 256 + +extern int blackfin_num_memory; /* # of memory blocks found (and used) */ +extern int blackfin_realnum_memory; /* real # of memory blocks found */ +extern struct mem_info blackfin_memory[NUM_MEMINFO]; /* memory description */ + +struct mem_info { + unsigned long addr; /* physical address of memory chunk */ + unsigned long size; /* length of memory chunk (in bytes) */ +}; +#endif + +#endif diff --git a/include/asm-blackfin/shared_resources.h b/include/asm-blackfin/shared_resources.h new file mode 100644 index 0000000..fbef186 --- /dev/null +++ b/include/asm-blackfin/shared_resources.h @@ -0,0 +1,33 @@ +/* + * U-boot - setup.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SHARED_RESOURCES_H_ +#define _SHARED_RESOURCES_H_ + +void swap_to(int device_id); + +#define FLASH 0 +#define ETHERNET 1 + +#endif /* _SHARED_RESOURCES_H_ */ diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h new file mode 100644 index 0000000..ffd81d6 --- /dev/null +++ b/include/asm-blackfin/string.h @@ -0,0 +1,79 @@ +/* + * U-boot - string.h String functions + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Changed by Lineo Inc. May 2001 */ + +#ifndef _BLACKFINNOMMU_STRING_H_ +#define _BLACKFINNOMMU_STRING_H_ + +#ifdef __KERNEL__ /* only set these up for kernel code */ + +#include <asm/setup.h> +#include <asm/page.h> +#include <asm/cpu/defBF533.h> + +#define __HAVE_ARCH_STRCPY +#define __HAVE_ARCH_STRNCPY +#define __HAVE_ARCH_STRCMP +#define __HAVE_ARCH_STRNCMP +#define __HAVE_ARCH_MEMCPY + +extern char *strcpy(char *dest, const char *src); +extern char *strncpy(char *dest, const char *src, size_t n); +extern int strcmp(const char *cs, const char *ct); +extern int strncmp(const char *cs, const char *ct, size_t count); +extern void * memcpy(void * dest,const void *src,size_t count); +extern void *memset(void *s, int c, size_t count); +extern int memcmp(const void *, const void *, __kernel_size_t); + +#else /* KERNEL */ + +/* + * let user libraries deal with these, + * IMHO the kernel has no place defining these functions for user apps + */ + +#define __HAVE_ARCH_STRCPY 1 +#define __HAVE_ARCH_STRNCPY 1 +#define __HAVE_ARCH_STRCAT 1 +#define __HAVE_ARCH_STRNCAT 1 +#define __HAVE_ARCH_STRCMP 1 +#define __HAVE_ARCH_STRNCMP 1 +#define __HAVE_ARCH_STRNICMP 1 +#define __HAVE_ARCH_STRCHR 1 +#define __HAVE_ARCH_STRRCHR 1 +#define __HAVE_ARCH_STRSTR 1 +#define __HAVE_ARCH_STRLEN 1 +#define __HAVE_ARCH_STRNLEN 1 +#define __HAVE_ARCH_MEMSET 1 +#define __HAVE_ARCH_MEMCPY 1 +#define __HAVE_ARCH_MEMMOVE 1 +#define __HAVE_ARCH_MEMSCAN 1 +#define __HAVE_ARCH_MEMCMP 1 +#define __HAVE_ARCH_MEMCHR 1 +#define __HAVE_ARCH_STRTOK 1 + +#endif /* KERNEL */ + +#endif /* _BLACKFIN_STRING_H_ */ diff --git a/include/asm-blackfin/system.h b/include/asm-blackfin/system.h new file mode 100644 index 0000000..0e53adf --- /dev/null +++ b/include/asm-blackfin/system.h @@ -0,0 +1,182 @@ +/* + * U-boot - system.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_SYSTEM_H +#define _BLACKFIN_SYSTEM_H + +#include <linux/config.h> /* get configuration macros */ +#include <asm/linkage.h> +#include <asm/blackfin.h> +#include <asm/segment.h> +#include <asm/entry.h> + +#define prepare_to_switch() do { } while(0) + +/* + * switch_to(n) should switch tasks to task ptr, first checking that + * ptr isn't the current task, in which case it does nothing. This + * also clears the TS-flag if the task we switched to has used the + * math co-processor latest. + * + * 05/25/01 - Tony Kou (tonyko@lineo.ca) + * + * Adapted for BlackFin (ADI) by Ted Ma, Metrowerks, and Motorola GSG + * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) + * Copyright (c) 2003 Metrowerks (www.metrowerks.com) + */ + +asmlinkage void resume(void); + +#define switch_to(prev,next,last) { \ + void *_last; \ + __asm__ __volatile__( \ + "r0 = %1;\n\t" \ + "r1 = %2;\n\t" \ + "call resume;\n\t" \ + "%0 = r0;\n\t" \ + : "=d" (_last) \ + : "d" (prev), \ + "d" (next) \ + : "CC", "R0", "R1", "R2", "R3", "R4", "R5", "P0", "P1");\ + (last) = _last; \ +} + +/* Force kerenl switch to user mode -- Steven Chen */ +#define switch_to_user_mode() { \ + __asm__ __volatile__( \ + "call kernel_to_user_mode;\n\t" \ + :: \ + : "CC", "R0", "R1", "R2", "R3", "R4", "R5", "P0", "P1");\ +} + +/* + * Interrupt configuring macros. + */ + +extern int irq_flags; + +#define __sti() { \ + __asm__ __volatile__ ( \ + "r3 = %0;" \ + "sti r3;" \ + ::"m"(irq_flags):"R3"); \ +} + +#define __cli() { \ + __asm__ __volatile__ ( \ + "cli r3;" \ + :::"R3"); \ +} + +#define __save_flags(x) { \ + __asm__ __volatile__ ( \ + "cli r3;" \ + "%0 = r3;" \ + "sti r3;" \ + ::"m"(x):"R3"); \ +} + +#define __save_and_cli(x) { \ + __asm__ __volatile__ ( \ + "cli r3;" \ + "%0 = r3;" \ + ::"m"(x):"R3"); \ +} + +#define __restore_flags(x) { \ + __asm__ __volatile__ ( \ + "r3 = %0;" \ + "sti r3;" \ + ::"m"(x):"R3"); \ +} + +/* For spinlocks etc */ +#define local_irq_save(x) __save_and_cli(x) +#define local_irq_restore(x) __restore_flags(x) +#define local_irq_disable() __cli() +#define local_irq_enable() __sti() + +#define cli() __cli() +#define sti() __sti() +#define save_flags(x) __save_flags(x) +#define restore_flags(x) __restore_flags(x) +#define save_and_cli(x) __save_and_cli(x) + +/* + * Force strict CPU ordering. + */ +#define nop() asm volatile ("nop;\n\t"::) +#define mb() asm volatile ("" : : :"memory") +#define rmb() asm volatile ("" : : :"memory") +#define wmb() asm volatile ("" : : :"memory") +#define set_rmb(var, value) do { xchg(&var, value); } while (0) +#define set_mb(var, value) set_rmb(var, value) +#define set_wmb(var, value) do { var = value; wmb(); } while (0) + +#ifdef CONFIG_SMP +#define smp_mb() mb() +#define smp_rmb() rmb() +#define smp_wmb() wmb() +#else +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() +#endif + +#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) +#define tas(ptr) (xchg((ptr),1)) + +struct __xchg_dummy { + unsigned long a[100]; +}; +#define __xg(x) ((volatile struct __xchg_dummy *)(x)) + +static inline unsigned long __xchg(unsigned long x, volatile void *ptr, + int size) +{ + unsigned long tmp; + unsigned long flags = 0; + + save_and_cli(flags); + + switch (size) { + case 1: + __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory"); + break; + case 2: + __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory"); + break; + case 4: + __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory"); + break; + } + restore_flags(flags); + return tmp; +} + +/* Depend on whether Blackfin has hard reset function */ +/* YES it does, but it is tricky to implement - FIXME later ...MaTed--- */ +#define HARD_RESET_NOW() ({}) + +#endif /* _BLACKFIN_SYSTEM_H */ diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h new file mode 100644 index 0000000..29e6eba --- /dev/null +++ b/include/asm-blackfin/traps.h @@ -0,0 +1,86 @@ +/* + * U-boot - traps.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * linux/include/asm/traps.h + * Copyright (C) 1993 Hamish Macdonald + * Lineo, Inc Jul 2001 Tony Kou + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + */ + +#ifndef _BLACKFIN_TRAPS_H +#define _BLACKFIN_TRAPS_H + +#ifndef __ASSEMBLY__ +typedef void (*e_vector) (void); +extern e_vector vectors[]; +#endif + +#define VEC_SYS (0) +#define VEC_EXCPT01 (1) +#define VEC_EXCPT02 (2) +#define VEC_EXCPT03 (3) +#define VEC_EXCPT04 (4) +#define VEC_EXCPT05 (5) +#define VEC_EXCPT06 (6) +#define VEC_EXCPT07 (7) +#define VEC_EXCPT08 (8) +#define VEC_EXCPT09 (9) +#define VEC_EXCPT10 (10) +#define VEC_EXCPT11 (11) +#define VEC_EXCPT12 (12) +#define VEC_EXCPT13 (13) +#define VEC_EXCPT14 (14) +#define VEC_EXCPT15 (15) +#define VEC_STEP (16) +#define VEC_OVFLOW (17) +#define VEC_UNDEF_I (33) +#define VEC_ILGAL_I (34) +#define VEC_CPLB_VL (35) +#define VEC_MISALI_D (36) +#define VEC_UNCOV (37) +#define VEC_CPLB_M (38) +#define VEC_CPLB_MHIT (39) +#define VEC_WATCH (40) +#define VEC_ISTRU_VL (41) +#define VEC_MISALI_I (42) +#define VEC_CPLB_I_VL (43) +#define VEC_CPLB_I_M (44) +#define VEC_CPLB_I_MHIT (45) +#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */ + +#define VECOFF(vec) ((vec)<<2) + +#ifndef __ASSEMBLY__ + +/* Status register bits */ +#define PS_T (0x8000) +#define PS_S (0x0c00) /* Supervisor mode = 0b01 */ +#define PS_D (0x0c00) /* Debug mode = 0b1x */ +#define PS_M (0x1000) +#define PS_C (0x0001) + +#endif +#endif diff --git a/include/asm-blackfin/types.h b/include/asm-blackfin/types.h new file mode 100644 index 0000000..942ed27 --- /dev/null +++ b/include/asm-blackfin/types.h @@ -0,0 +1,83 @@ +/* + * U-boot - types.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_TYPES_H +#define _BLACKFIN_TYPES_H + +/* + * This file is never included by application software unless + * explicitly requested (e.g., via linux/types.h) in which case the + * application is Linux specific so (user-) name space pollution is + * not a major issue. However, for interoperability, libraries still + * need to be careful to avoid a name clashes. + */ + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +/* HK0617 -- Changes to unsigned long temporarily */ +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +#endif + +#endif diff --git a/include/asm-blackfin/u-boot.h b/include/asm-blackfin/u-boot.h new file mode 100644 index 0000000..ec39338 --- /dev/null +++ b/include/asm-blackfin/u-boot.h @@ -0,0 +1,47 @@ +/* + * U-boot - u-boot.h Structure declarations for board specific data + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _U_BOOT_H_ +#define _U_BOOT_H_ 1 + +typedef struct bd_info { + int bi_baudrate; /* serial console baudrate */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned long bi_arch_number; /* unique id for this board */ + unsigned long bi_boot_params; /* where this board expects params */ + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ +} bd_t; + +#define bi_env_data bi_env->data +#define bi_env_crc bi_env->crc + +#endif /* _U_BOOT_H_ */ diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h new file mode 100644 index 0000000..8578166 --- /dev/null +++ b/include/asm-blackfin/uaccess.h @@ -0,0 +1,207 @@ +/* + * U-boot - uaccess.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * Based on: include/asm-m68knommu/uaccess.h + * Changes made by Lineo Inc. May 2001 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BLACKFIN_UACCESS_H +#define __BLACKFIN_UACCESS_H + +/* + * User space memory access functions + */ +#include <asm/segment.h> +#include <asm/errno.h> + +#define VERIFY_READ 0 +#define VERIFY_WRITE 1 + +/* We let the MMU do all checking */ +static inline int access_ok(int type, const void *addr, unsigned long size) +{ + return ((unsigned long) addr < 0x10f00000); /* need final decision - Tony */ +} + +static inline int verify_area(int type, const void *addr, + unsigned long size) +{ + return access_ok(type, addr, size) ? 0 : -EFAULT; +} + +/* + * The exception table consists of pairs of addresses: the first is the + * address of an instruction that is allowed to fault, and the second is + * the address at which the program should continue. No registers are + * modified, so it is entirely up to the continuation code to figure out + * what to do. + * + * All the routines below use bits of fixup code that are out of line + * with the main instruction path. This means when everything is well, + * we don't even have to jump over them. Further, they do not intrude + * on our cache or tlb entries. + */ + +struct exception_table_entry { + unsigned long insn, fixup; +}; + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + +/* + * These are the main single-value transfer routines. They automatically + * use the right size if we just have the right pointer type. + */ + +#define put_user(x, ptr) \ +({ \ + int __pu_err = 0; \ + typeof(*(ptr)) __pu_val = (x); \ + switch (sizeof (*(ptr))) { \ + case 1: \ + __put_user_asm(__pu_err, __pu_val, ptr, B); \ + break; \ + case 2: \ + __put_user_asm(__pu_err, __pu_val, ptr, W); \ + break; \ + case 4: \ + __put_user_asm(__pu_err, __pu_val, ptr, ); \ + break; \ + default: \ + __pu_err = __put_user_bad(); \ + break; \ + } \ + __pu_err; \ +}) +/* + * [pregs] = dregs ==> 32bits + * H[pregs] = dregs ==> 16bits + * B[pregs] = dregs ==> 8 bits + */ + +#define __put_user(x, ptr) put_user(x, ptr) + +static inline int bad_user_access_length(void) +{ + panic("bad_user_access_length"); + return -1; +} + +#define __put_user_bad() (bad_user_access_length(), (-EFAULT)) + +/* + * Tell gcc we read from memory instead of writing: this is because + * we do not write to any memory gcc knows about, so there are no + * aliasing issues. + */ + +#define __ptr(x) ((unsigned long *)(x)) + +#define __put_user_asm(err,x,ptr,bhw) \ + __asm__ (#bhw"[%1] = %0;\n\t" \ + : /* no outputs */ \ + :"d" (x),"a" (__ptr(ptr)) : "memory") + +#define get_user(x, ptr) \ +({ \ + int __gu_err = 0; \ + typeof(*(ptr)) __gu_val = 0; \ + switch (sizeof(*(ptr))) { \ + case 1: \ + __get_user_asm(__gu_err, __gu_val, ptr, B, "=d",(Z)); \ + break; \ + case 2: \ + __get_user_asm(__gu_err, __gu_val, ptr, W, "=r",(Z)); \ + break; \ + case 4: \ + __get_user_asm(__gu_err, __gu_val, ptr, , "=r",); \ + break; \ + default: \ + __gu_val = 0; \ + __gu_err = __get_user_bad(); \ + break; \ + } \ + (x) = __gu_val; \ + __gu_err; \ +}) + +/* dregs = [pregs] ==> 32bits + * H[pregs] ==> 16bits + * B[pregs] ==> 8 bits + */ + +#define __get_user(x, ptr) get_user(x, ptr) +#define __get_user_bad() (bad_user_access_length(), (-EFAULT)) + +#define __get_user_asm(err,x,ptr,bhw,reg,option) \ + __asm__ ("%0 =" #bhw "[%1]"#option";\n\t" \ + : "=d" (x) \ + : "a" (__ptr(ptr))) + +#define copy_from_user(to, from, n) (memcpy(to, from, n), 0) +#define copy_to_user(to, from, n) (memcpy(to, from, n), 0) + +#define __copy_from_user(to, from, n) copy_from_user(to, from, n) +#define __copy_to_user(to, from, n) copy_to_user(to, from, n) + +#define copy_to_user_ret(to,from,n,retval) ({ if (copy_to_user(to,from,n)) return retval; }) +#define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n)) return retval; }) + +/* + * Copy a null terminated string from userspace. + */ + +static inline long strncpy_from_user(char *dst, const char *src, + long count) +{ + char *tmp; + strncpy(dst, src, count); + for (tmp = dst; *tmp && count > 0; tmp++, count--); + return (tmp - dst); /* DAVIDM should we count a NUL ? check getname */ +} + +/* + * Return the size of a string (including the ending 0) + * + * Return 0 on exception, a value greater than N if too long + */ +static inline long strnlen_user(const char *src, long n) +{ + return (strlen(src) + 1); /* DAVIDM make safer */ +} + +#define strlen_user(str) strnlen_user(str, 32767) + +/* + * Zero Userspace + */ + +static inline unsigned long clear_user(void *to, unsigned long n) +{ + memset(to, 0, n); + return (0); +} + +#endif diff --git a/include/asm-blackfin/virtconvert.h b/include/asm-blackfin/virtconvert.h new file mode 100644 index 0000000..769f5a0 --- /dev/null +++ b/include/asm-blackfin/virtconvert.h @@ -0,0 +1,47 @@ +/* + * U-boot - virtconvert.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BLACKFIN_VIRT_CONVERT__ +#define __BLACKFIN_VIRT_CONVERT__ + +/* + * Macros used for converting between virtual and physical mappings. + */ + +#ifdef __KERNEL__ + +#include <linux/config.h> +#include <asm/setup.h> +#include <asm/page.h> + +#define mm_vtop(vaddr) ((unsigned long) vaddr) +#define mm_ptov(vaddr) ((unsigned long) vaddr) +#define phys_to_virt(vaddr) ((unsigned long) vaddr) +#define virt_to_phys(vaddr) ((unsigned long) vaddr) + +#define virt_to_bus virt_to_phys +#define bus_to_virt phys_to_virt + +#endif +#endif diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 6c2c712..c2b4c5c 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -71,8 +71,8 @@ typedef struct sysconf8349 { | SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP) u32 sicrl; /* System General Purpose Register Low */ #define SICRL_LDP_A 0x80000000 -#define SICRL_USB0 0x40000000 -#define SICRL_USB1 0x20000000 +#define SICRL_USB1 0x40000000 +#define SICRL_USB0 0x20000000 #define SICRL_UART 0x0C000000 #define SICRL_GPIO1_A 0x02000000 #define SICRL_GPIO1_B 0x01000000 @@ -675,24 +675,76 @@ typedef struct ddr8349{ u8 res9[8]; u32 sdram_clk_cntl; #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 u8 res4[0xCCC]; u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */ u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */ u32 ecc_err_inject; /**< Memory Data Path Error Injection Mask ECC */ +#define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ +#define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ +#define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ +#define ECC_ERR_INJECT_EEIM_SHIFT 0 u8 res5[0x14]; u32 capture_data_hi; /**< Memory Data Path Read Capture High */ u32 capture_data_lo; /**< Memory Data Path Read Capture Low */ u32 capture_ecc; /**< Memory Data Path Read Capture ECC */ +#define CAPTURE_ECC_ECE (0xff000000>>24) +#define CAPTURE_ECC_ECE_SHIFT 0 u8 res6[0x14]; u32 err_detect; /**< Memory Error Detect */ +#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ +#define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ +#define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ +#define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ u32 err_disable; /**< Memory Error Disable */ +#define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ +#define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ +#define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ +#define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED|ECC_ERROR_DISABLE_SBED|ECC_ERROR_DISABLE_MBED) u32 err_int_en; /**< Memory Error Interrupt Enable */ +#define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ +#define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ +#define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ +#define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE|ECC_ERR_INT_EN_SBEE|ECC_ERR_INT_EN_MSEE) u32 capture_attributes; /**< Memory Error Attributes Capture */ +#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ +#define ECC_CAPT_ATTR_BNUM_SHIFT 28 +#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ +#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 +#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 +#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 +#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 +#define ECC_CAPT_ATTR_TSIZ_SHIFT 24 +#define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ +#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 +#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 +#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 +#define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 +#define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) +#define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 +#define ECC_CAPT_ATTR_TSRC_I2C 0x9 +#define ECC_CAPT_ATTR_TSRC_JTAG 0xA +#define ECC_CAPT_ATTR_TSRC_PCI1 0xD +#define ECC_CAPT_ATTR_TSRC_PCI2 0xE +#define ECC_CAPT_ATTR_TSRC_DMA 0xF +#define ECC_CAPT_ATTR_TSRC_SHIFT 16 +#define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ +#define ECC_CAPT_ATTR_TTYP_WRITE 0x1 +#define ECC_CAPT_ATTR_TTYP_READ 0x2 +#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 +#define ECC_CAPT_ATTR_TTYP_SHIFT 12 +#define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ u32 capture_address; /**< Memory Error Address Capture */ u32 capture_ext_address;/**< Memory Error Extended Address Capture */ u32 err_sbe; /**< Memory Single-Bit ECC Error Management */ +#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255*/ +#define ECC_ERROR_MAN_SBET_SHIFT 16 +#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255*/ +#define ECC_ERROR_MAN_SBEC_SHIFT 0 u8 res7[0xA4]; u32 debug_reg; u8 res8[0xFC]; @@ -795,10 +847,95 @@ typedef struct spi8349 u8 res1[0xD8]; } spi8349_t; + +/* + * DMA/Messaging Unit + */ typedef struct dma8349 { - u8 fixme[0x300]; + u32 res0[0xC]; /* 0x0-0x29 reseverd */ + u32 omisr; /* 0x30 Outbound message interrupt status register */ + u32 omimr; /* 0x34 Outbound message interrupt mask register */ + u32 res1[0x6]; /* 0x38-0x49 reserved */ + + u32 imr0; /* 0x50 Inbound message register 0 */ + u32 imr1; /* 0x54 Inbound message register 1 */ + u32 omr0; /* 0x58 Outbound message register 0 */ + u32 omr1; /* 0x5C Outbound message register 1 */ + + u32 odr; /* 0x60 Outbound doorbell register */ + u32 res2; /* 0x64-0x67 reserved */ + u32 idr; /* 0x68 Inbound doorbell register */ + u32 res3[0x5]; /* 0x6C-0x79 reserved */ + + u32 imisr; /* 0x80 Inbound message interrupt status register */ + u32 imimr; /* 0x84 Inbound message interrupt mask register */ + u32 res4[0x1E]; /* 0x88-0x99 reserved */ + + u32 dmamr0; /* 0x100 DMA 0 mode register */ + u32 dmasr0; /* 0x104 DMA 0 status register */ + u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */ + u32 res5; /* 0x10C reserved */ + u32 dmasar0; /* 0x110 DMA 0 source address register */ + u32 res6; /* 0x114 reserved */ + u32 dmadar0; /* 0x118 DMA 0 destination address register */ + u32 res7; /* 0x11C reserved */ + u32 dmabcr0; /* 0x120 DMA 0 byte count register */ + u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */ + u32 res8[0x16]; /* 0x128-0x179 reserved */ + + u32 dmamr1; /* 0x180 DMA 1 mode register */ + u32 dmasr1; /* 0x184 DMA 1 status register */ + u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */ + u32 res9; /* 0x18C reserved */ + u32 dmasar1; /* 0x190 DMA 1 source address register */ + u32 res10; /* 0x194 reserved */ + u32 dmadar1; /* 0x198 DMA 1 destination address register */ + u32 res11; /* 0x19C reserved */ + u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */ + u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */ + u32 res12[0x16];/* 0x1A8-0x199 reserved */ + + u32 dmamr2; /* 0x200 DMA 2 mode register */ + u32 dmasr2; /* 0x204 DMA 2 status register */ + u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */ + u32 res13; /* 0x20C reserved */ + u32 dmasar2; /* 0x210 DMA 2 source address register */ + u32 res14; /* 0x214 reserved */ + u32 dmadar2; /* 0x218 DMA 2 destination address register */ + u32 res15; /* 0x21C reserved */ + u32 dmabcr2; /* 0x220 DMA 2 byte count register */ + u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */ + u32 res16[0x16];/* 0x228-0x279 reserved */ + + u32 dmamr3; /* 0x280 DMA 3 mode register */ + u32 dmasr3; /* 0x284 DMA 3 status register */ + u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */ + u32 res17; /* 0x28C reserved */ + u32 dmasar3; /* 0x290 DMA 3 source address register */ + u32 res18; /* 0x294 reserved */ + u32 dmadar3; /* 0x298 DMA 3 destination address register */ + u32 res19; /* 0x29C reserved */ + u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */ + u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */ + + u32 dmagsr; /* 0x2A8 DMA general status register */ + u32 res20[0x15];/* 0x2AC-0x2FF reserved */ } dma8349_t; +/* DMAMRn bits */ +#define DMA_CHANNEL_START (0x00000001) /* Bit - DMAMRn CS */ +#define DMA_CHANNEL_TRANSFER_MODE_DIRECT (0x00000004) /* Bit - DMAMRn CTM */ +#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN (0x00001000) /* Bit - DMAMRn SAHE */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B (0x00000000) /* 2Bit- DMAMRn SAHTS 1byte */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B (0x00004000) /* 2Bit- DMAMRn SAHTS 2bytes */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B (0x00008000) /* 2Bit- DMAMRn SAHTS 4bytes */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B (0x0000c000) /* 2Bit- DMAMRn SAHTS 8bytes */ +#define DMA_CHANNEL_SNOOP (0x00010000) /* Bit - DMAMRn DMSEN */ + +/* DMASRn bits */ +#define DMA_CHANNEL_BUSY (0x00000004) /* Bit - DMASRn CB */ +#define DMA_CHANNEL_TRANSFER_ERROR (0x00000080) /* Bit - DMASRn TE */ + /* * PCI Software Configuration Registers */ diff --git a/include/asm-ppc/iopin_85xx.h b/include/asm-ppc/iopin_85xx.h new file mode 100644 index 0000000..f854df6 --- /dev/null +++ b/include/asm-ppc/iopin_85xx.h @@ -0,0 +1,146 @@ +/* + * MPC85xx I/O port pin manipulation functions + */ + +#ifndef _ASM_IOPIN_85xx_H_ +#define _ASM_IOPIN_85xx_H_ + +#include <linux/types.h> +#include <asm/immap_85xx.h> + +#ifdef __KERNEL__ + +typedef struct { + u_char port:2; /* port number (A=0, B=1, C=2, D=3) */ + u_char pin:5; /* port pin (0-31) */ + u_char flag:1; /* for whatever */ +} iopin_t; + +#define IOPIN_PORTA 0 +#define IOPIN_PORTB 1 +#define IOPIN_PORTC 2 +#define IOPIN_PORTD 3 + +extern __inline__ void iopin_set_high (iopin_t * iopin) +{ + volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; + datp[iopin->port * 8] |= (1 << (31 - iopin->pin)); +} + +extern __inline__ void iopin_set_low (iopin_t * iopin) +{ + volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; + datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); +} + +extern __inline__ uint iopin_is_high (iopin_t * iopin) +{ + volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; + return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1; +} + +extern __inline__ uint iopin_is_low (iopin_t * iopin) +{ + volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; + return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; +} + +extern __inline__ void iopin_set_out (iopin_t * iopin) +{ + volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; + dirp[iopin->port * 8] |= (1 << (31 - iopin->pin)); +} + +extern __inline__ void iopin_set_in (iopin_t * iopin) +{ + volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; + dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); +} + +extern __inline__ uint iopin_is_out (iopin_t * iopin) +{ + volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; + return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1; +} + +extern __inline__ uint iopin_is_in (iopin_t * iopin) +{ + volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; + return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; +} + +extern __inline__ void iopin_set_odr (iopin_t * iopin) +{ + volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; + odrp[iopin->port * 8] |= (1 << (31 - iopin->pin)); +} + +extern __inline__ void iopin_set_act (iopin_t * iopin) +{ + volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; + odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); +} + +extern __inline__ uint iopin_is_odr (iopin_t * iopin) +{ + volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; + return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1; +} + +extern __inline__ uint iopin_is_act (iopin_t * iopin) +{ + volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; + return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; +} + +extern __inline__ void iopin_set_ded (iopin_t * iopin) +{ + volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; + parp[iopin->port * 8] |= (1 << (31 - iopin->pin)); +} + +extern __inline__ void iopin_set_gen (iopin_t * iopin) +{ + volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; + parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); +} + +extern __inline__ uint iopin_is_ded (iopin_t * iopin) +{ + volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; + return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1; +} + +extern __inline__ uint iopin_is_gen (iopin_t * iopin) +{ + volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; + return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; +} + +extern __inline__ void iopin_set_opt2 (iopin_t * iopin) +{ + volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; + sorp[iopin->port * 8] |= (1 << (31 - iopin->pin)); +} + +extern __inline__ void iopin_set_opt1 (iopin_t * iopin) +{ + volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; + sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); +} + +extern __inline__ uint iopin_is_opt2 (iopin_t * iopin) +{ + volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; + return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1; +} + +extern __inline__ uint iopin_is_opt1 (iopin_t * iopin) +{ + volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; + return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; +} + +#endif /* __KERNEL__ */ + +#endif /* _ASM_IOPIN_85xx_H_ */ diff --git a/include/asm-ppc/mpc8349_pci.h b/include/asm-ppc/mpc8349_pci.h index 48255a3..7a1adba 100644 --- a/include/asm-ppc/mpc8349_pci.h +++ b/include/asm-ppc/mpc8349_pci.h @@ -77,6 +77,7 @@ #define POCMR_ENABLE 0x80000000 #define POCMR_PCI_IO 0x40000000 #define POCMR_PREFETCH_EN 0x20000000 +#define POCMR_PCI2 0x10000000 /* Soft PCI reset */ diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h index 9ee4849..cf36583 100644 --- a/include/cmd_confdefs.h +++ b/include/cmd_confdefs.h @@ -112,7 +112,6 @@ CFG_CMD_DISPLAY | \ CFG_CMD_DOC | \ CFG_CMD_DTT | \ - CFG_CMD_ECHO | \ CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ CFG_CMD_EXT2 | \ diff --git a/include/common.h b/include/common.h index d2570a8..5d8b156 100644 --- a/include/common.h +++ b/include/common.h @@ -365,7 +365,8 @@ void trap_init (ulong); defined (CONFIG_75x) || \ defined (CONFIG_74xx) || \ defined (CONFIG_MPC8220) || \ - defined(CONFIG_MPC85xx) + defined (CONFIG_MPC85xx) || \ + defined (CONFIG_MPC83XX) unsigned char in8(unsigned int); void out8(unsigned int, unsigned char); unsigned short in16(unsigned int); diff --git a/include/configs/Adder.h b/include/configs/Adder.h index f807546..0e6b50f 100644 --- a/include/configs/Adder.h +++ b/include/configs/Adder.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004 Arabella Software Ltd. + * Copyright (C) 2004-2005 Arabella Software Ltd. * Yuli Barcohen <yuli@arabellasw.com> * * Support for Analogue&Micro Adder boards family. @@ -35,11 +35,13 @@ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_BAUDRATE 38400 -#define CONFIG_FEC_ENET /* Ethernet is on FEC */ -#ifdef CONFIG_FEC_ENET +#define CONFIG_ETHER_ON_FEC1 +#define CONFIG_ETHER_ON_FEC2 + +#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) #define CFG_DISCOVER_PHY #define FEC_ENET -#endif /* CONFIG_FEC_ENET */ +#endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */ #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ #define CONFIG_8xx_CPUCLK_DEFAULT 50000000 @@ -47,7 +49,7 @@ #ifdef CONFIG_MPC852T #define CFG_8xx_CPUCLK_MAX 50000000 #else -#define CFG_8xx_CPUCLK_MAX 120000000 +#define CFG_8xx_CPUCLK_MAX 133000000 #endif /* CONFIG_MPC852T */ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ @@ -62,7 +64,7 @@ #define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw" +#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)" #define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ #undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ @@ -79,7 +81,7 @@ #define CFG_MAXARGS 16 /* Max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x100000 /* Default load address */ +#define CFG_LOAD_ADDR 0x400000 /* Default load address */ #define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ @@ -89,24 +91,21 @@ * RAM configuration (note that CFG_SDRAM_BASE must be zero) */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ - -#define CFG_OR1_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_ACS_DIV2) -#define CFG_BR1_PRELIM (CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V) +#define CFG_SDRAM_MAX_SIZE 0x01000000 /* Up to 16 Mbyte */ -#define CFG_MAMR 0x00802114 +#define CFG_MAMR 0x00002114 /* - * 2048 SDRAM rows + * 4096 Up to 4096 SDRAM rows * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 32 PTP (pre-divider from MPTPR) * 4 Number of refresh cycles per period * 64 Refresh cycle in ms per number of rows */ -#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64)) +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00700000 /* 1 ... 7 MB in SDRAM */ +#define CFG_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */ #define CFG_RESET_ADDRESS 0x09900000 @@ -139,6 +138,8 @@ #define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CONFIG_ENV_OVERWRITE + #define CFG_OR0_PRELIM 0xFF000774 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V) diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h new file mode 100644 index 0000000..738763b --- /dev/null +++ b/include/configs/EP88x.h @@ -0,0 +1,205 @@ +/* + * Copyright (C) 2005 Arabella Software Ltd. + * Yuli Barcohen <yuli@arabellasw.com> + * + * Support for Embedded Planet EP88x boards. + * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MPC885 + +#define CONFIG_EP88X /* Embedded Planet EP88x board */ + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */ + +/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_ETHER_ON_FEC1 /* Enable Ethernet on FEC1 */ +#define CONFIG_ETHER_ON_FEC2 /* Enable Ethernet on FEC2 */ +#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) +#define CFG_DISCOVER_PHY +#define FEC_ENET +#endif /* CONFIG_FEC_ENET */ + +#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ +#define CONFIG_8xx_CPUCLK_DEFAULT 100000000 +#define CFG_8xx_CPUCLK_MIN 40000000 +#define CFG_8xx_CPUCLK_MAX 133000000 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + ) + +/* This must be included AFTER the definition of CONFIG_COMMANDS */ +#include <cmd_confdefs.h> + +#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ +#define CONFIG_BOOTCOMMAND "bootm fe060000" /* Autoboot command */ +#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:2M(ROM)ro,-(root)" + +#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ +#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_LONGHELP /* #undef to save memory */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* Max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR 0x400000 /* Default load address */ + +#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * RAM configuration (note that CFG_SDRAM_BASE must be zero) + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_MAX_SIZE 0x08000000 /* Up to 128 Mbyte */ + +#define CFG_MAMR 0x00805000 + +/* + * 4096 Up to 4096 SDRAM rows + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + */ +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */ + +#define CFG_RESET_ADDRESS 0x09900000 + +/*----------------------------------------------------------------------- + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */ +#ifdef CONFIG_BZIP2 +#define CFG_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */ +#else +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ +#endif /* CONFIG_BZIP2 */ + +/*----------------------------------------------------------------------- + * Flash organisation + */ +#define CFG_FLASH_BASE 0xFC000000 +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 512 /* Max num of sects on one chip */ + +/* Environment is in flash */ +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + +#define CFG_OR0_PRELIM 0xFC000160 +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_32 | BR_MS_GPCM | BR_V) + +#define CFG_DIRECT_FLASH_TFTP + +/*----------------------------------------------------------------------- + * BCSR + */ +#define CFG_OR3_PRELIM 0xFF0005B0 +#define CFG_BR3_PRELIM (0xFA000000 |BR_PS_16 | BR_MS_GPCM | BR_V) + +#define CFG_BCSR 0xFA400000 + +/*----------------------------------------------------------------------- + * Internal Memory Map Register + */ +#define CFG_IMMR 0xF0000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Configuration registers + */ +#ifdef CONFIG_WATCHDOG +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ + SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \ + SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ + SYPCR_SWF | SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +#define CFG_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11) + +/* TBSCR - Time Base Status and Control Register */ +#define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE) + +/* PISCR - Periodic Interrupt Status and Control */ +#define CFG_PISCR PISCR_PS + +/* SCCR - System Clock and reset Control Register */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR SCCR_RTSEL + +#define CFG_DER 0 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx chips */ + +/*----------------------------------------------------------------------- + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h index 65056a2..706bdb9 100644 --- a/include/configs/ISPAN.h +++ b/include/configs/ISPAN.h @@ -109,7 +109,6 @@ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL \ | CFG_CMD_ASKENV \ | CFG_CMD_DHCP \ - | CFG_CMD_ECHO \ | CFG_CMD_IMMAP \ | CFG_CMD_MII \ | CFG_CMD_PING \ diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index afba5c6..596e52c 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -122,9 +122,13 @@ # define CFG_LOWBOOT16 1 #endif #if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ +#if defined(CONFIG_LITE5200B) +# error CFG_LOWBOOT08 is incompatible with the Lite5200B +#else # define CFG_LOWBOOT 1 # define CFG_LOWBOOT08 1 #endif +#endif /* * Autobooting @@ -160,8 +164,12 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#if defined(CONFIG_LITE5200B) +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ +#else +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ #endif +#endif /* CONFIG_MPC5200 */ /* * I2C configuration */ @@ -182,6 +190,20 @@ /* * Flash configuration */ +#if defined(CONFIG_LITE5200B) +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FLASH_SIZE 0x01000000 +#if !defined(CFG_LOWBOOT) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01760000 + 0x00800000) +#else /* CFG_LOWBOOT */ +#if defined(CFG_LOWBOOT08) +# error CFG_LOWBOOT08 is incompatible with the Lite5200B +#endif +#if defined(CFG_LOWBOOT16) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01060000) +#endif +#endif /* CFG_LOWBOOT */ +#else /* !CONFIG_LITE5200B (IceCube)*/ #define CFG_FLASH_BASE 0xFF000000 #define CFG_FLASH_SIZE 0x01000000 #if !defined(CFG_LOWBOOT) @@ -194,6 +216,7 @@ #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) #endif #endif /* CFG_LOWBOOT */ +#endif /* CONFIG_LITE5200B */ #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ @@ -203,13 +226,23 @@ #undef CONFIG_FLASH_16BIT /* Flash is 8-bit */ +#if defined(CONFIG_LITE5200B) +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_BANKS_LIST {CFG_CS1_START,CFG_CS0_START} +#endif + /* * Environment settings */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 0x10000 +#if defined(CONFIG_LITE5200B) +#define CFG_ENV_SECT_SIZE 0x20000 +#else #define CFG_ENV_SECT_SIZE 0x10000 +#endif #define CONFIG_ENV_OVERWRITE 1 /* @@ -246,6 +279,9 @@ */ /* #define CONFIG_FEC_10MBIT 1 */ #define CONFIG_PHY_ADDR 0x00 +#if defined(CONFIG_LITE5200B) +#define CONFIG_FEC_MII100 1 +#endif /* * GPIO configuration @@ -288,6 +324,16 @@ #define CFG_HID0_FINAL 0 #endif +#if defined(CONFIG_LITE5200B) +#define CFG_CS1_START CFG_FLASH_BASE +#define CFG_CS1_SIZE CFG_FLASH_SIZE +#define CFG_CS1_CFG 0x00047800 +#define CFG_CS0_START (CFG_FLASH_BASE + CFG_FLASH_SIZE) +#define CFG_CS0_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_START CFG_CS0_START +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00047800 +#else /* IceCube aka Lite5200 */ #ifdef CONFIG_MPC5200_DDR #define CFG_BOOTCS_START (CFG_CS1_START + CFG_CS1_SIZE) @@ -306,6 +352,7 @@ #define CFG_CS0_SIZE CFG_FLASH_SIZE #endif /* CONFIG_MPC5200_DDR */ +#endif /*CONFIG_LITE5200B */ #define CFG_CS_BURST 0x00000000 #define CFG_CS_DEADCYCLE 0x33333333 diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 1f01e7b..7e57a0f 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -58,7 +58,6 @@ CFG_CMD_CACHE | \ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ CFG_CMD_FAT | \ diff --git a/include/configs/MPC8349ADS.h b/include/configs/MPC8349ADS.h index d6d2fab..1e9a1f7 100644 --- a/include/configs/MPC8349ADS.h +++ b/include/configs/MPC8349ADS.h @@ -41,9 +41,8 @@ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_MPC8349ADS 1 /* MPC8349ADS board specific */ -/* FIXME: Real PCI support will come in a follow-up update. */ -#undef CONFIG_PCI - +#define CONFIG_PCI +#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -150,7 +149,7 @@ #define CONFIG_L1_INIT_RAM #define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ @@ -324,19 +323,26 @@ * General PCI * Addresses are mapped 1-1. */ + #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_MMIO_BASE 0x90000000 +#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE +#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ #define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ -#define CFG_PCI2_MEM_BASE 0xA0000000 +#define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_MMIO_BASE 0xb0000000 +#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE +#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ #define CFG_PCI2_IO_BASE 0x00000000 -#define CFG_PCI2_IO_PHYS 0xe3000000 -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) #define PCI_ALL_PCI1 @@ -506,6 +512,10 @@ HRCWH_TSEC2M_IN_GMII ) #endif +/* System IO Config */ +#define CFG_SICRH SICRH_TSOBI1 +#define CFG_SICRL SICRL_LDP_A + #define CFG_HID0_INIT 0x000000000 #define CFG_HID0_FINAL CFG_HID0_INIT @@ -515,7 +525,66 @@ HID0_ENABLE_M_BIT |\ HID0_ENABLE_ADDRESS_BROADCAST ) */ -#define CFG_HID2 0x000000000 +#define CFG_HID2 HID2_HBE + +/* DDR 0 - 256MB */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* stack in DCACHE @ 1GB (no backing mem) */ +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +/* 2G - 3G PCI */ +#ifdef CONFIG_PCI +#define CFG_IBAT2L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT2U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT3U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT2L (0) +#define CFG_IBAT2U (0) +#define CFG_IBAT3L (0) +#define CFG_IBAT3U (0) +#endif + +#ifdef CONFIG_MPC83XX_PCI2 +#define CFG_IBAT4L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT4U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT5L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT4L (0) +#define CFG_IBAT4U (0) +#define CFG_IBAT5L (0) +#define CFG_IBAT5U (0) +#endif + +/* IMMRBAR */ +#define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT6U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP) + +/* SDRAM, BCSR & FLASH */ +#define CFG_IBAT7L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + /* * Internal Definitions diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h new file mode 100644 index 0000000..39e3d95 --- /dev/null +++ b/include/configs/MPC8349EMDS.h @@ -0,0 +1,716 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8349emds board configuration file + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define DEBUG +#undef DEBUG + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC8349 1 /* MPC8349 specific */ +#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ + +/* FIXME: Real PCI support will come in a follow-up update. */ +#undef CONFIG_PCI + +#define PCI_66M +#ifdef PCI_66M +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#ifdef PCI_66M +#define CONFIG_SYS_CLK_FREQ 66000000 +#else +#define CONFIG_SYS_CLK_FREQ 33000000 +#endif +#endif + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ + +#define CFG_IMMRBAR 0xE0000000 + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00000000 /* memtest region */ +#define CFG_MEMTEST_END 0x00100000 + +/* + * DDR Setup + */ +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ +#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ + +/* + * 32-bit data path mode. + * + * Please note that using this mode for devices with the real density of 64-bit + * effectively reduces the amount of available memory due to the effect of + * wrapping around while translating address to row/columns, for example in the + * 256MB module the upper 128MB get aliased with contents of the lower + * 128MB); normally this define should be used for devices with real 32-bit + * data path. + */ +#undef CONFIG_DDR_32BIT + +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#undef CONFIG_DDR_2T_TIMING + +#if defined(CONFIG_SPD_EEPROM) +/* + * Determine DDR configuration from I2C interface. + */ +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ +#else +/* + * Manually set up DDR parameters + */ +#define CFG_DDR_SIZE 256 /* MB */ +#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) +#define CFG_DDR_TIMING_1 0x36332321 +#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +#define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ + +#if defined(CONFIG_DDR_32BIT) +/* set burst length to 8 for 32-bit data path */ +#define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ +#else +/* the default burst length is 4 - for 64-bit data path */ +#define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ +#endif +#endif + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CFG_FLASH_SIZE 8 /* flash size in MB */ +/* #define CFG_FLASH_USE_BUFFER_WRITE */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ + BR_V) /* valid */ + +#define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MID_FLASH_JUMP 0x7F000000 +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +/* + * BCSR register on local bus 32KB, 8-bit wide for MDS config reg + */ +#define CFG_BCSR 0xF8000000 +#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ +#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ +#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ +#define CFG_OR1_PRELIM 0xFFFFE8F0 /* length 32K */ + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xE8000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + * LCRR: DLL bypass, Clock divider is 4 + * External Local Bus rate is + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CFG_LBC_LBCR 0x00000000 + +#define CFG_LB_SDRAM /* if board has SRDAM on local bus */ + +#ifdef CFG_LB_SDRAM +/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 + * + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ +#define CFG_LBLAWBAR2_PRELIM 0xF0000000 +#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 + */ + +#define CFG_OR2_PRELIM 0xFC006901 + +#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ + | CFG_LBC_LSDMR_BSMA1516 \ + | CFG_LBC_LSDMR_RFCR8 \ + | CFG_LBC_LSDMR_PRETOACT6 \ + | CFG_LBC_LSDMR_ACTTORW3 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC3 \ + | CFG_LBC_LSDMR_CL3 \ + ) + +/* + * SDRAM Controller configuration sequence. + */ +#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_PCHALL) +#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_MRW) +#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_NORMAL) +#endif + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 + +/* TSEC */ +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET) +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET) + +/* IO Configuration */ +#define CFG_IO_CONF (\ + IO_CONF_UART |\ + IO_CONF_TSEC1 |\ + IO_CONF_IRQ0 |\ + IO_CONF_IRQ1 |\ + IO_CONF_IRQ2 |\ + IO_CONF_IRQ3 |\ + IO_CONF_IRQ4 |\ + IO_CONF_IRQ5 |\ + IO_CONF_IRQ6 |\ + IO_CONF_IRQ7 ) + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#define CFG_PCI2_MEM_BASE 0xA0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe3000000 +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ + +#if defined(CONFIG_PCI) + +#define PCI_ALL_PCI1 +#if defined(PCI_64BIT) +#undef PCI_ALL_PCI1 +#undef PCI_TWO_PCI1 +#undef PCI_ONE_PCI1 +#endif + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xFIXME + #define PCI_ENET0_MEMADDR 0xFIXME + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + +/* + * TSEC configuration + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ + +#if defined(CONFIG_TSEC_ENET) +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_GMII 1 /* MII PHY management */ +#define CONFIG_MPC83XX_TSEC1 1 +#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC83XX_TSEC2 1 +#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C \ + | CFG_CMD_DATE) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_DATE) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#endif +#else +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_DATE \ + ) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII \ + | CFG_CMD_DATE \ + ) +#endif +#endif + +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#if 1 /*528/264*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_VCO_1X2 |\ + HRCWL_CORE_TO_CSB_2X1) +#elif 0 /*396/132*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_3X1) +#elif 0 /*264/132*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_2X1) +#elif 0 /*132/132*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_1X1) +#elif 0 /*264/264 */ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_1X1) +#endif + +#if defined(PCI_64BIT) +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_64_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_32_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#endif + +/* System IO Config */ +#define CFG_SICRH SICRH_TSOBI1 +#define CFG_SICRL SICRL_LDP_A + +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL CFG_HID0_INIT + +/* #define CFG_HID0_FINAL (\ + HID0_ENABLE_INSTRUCTION_CACHE |\ + HID0_ENABLE_M_BIT |\ + HID0_ENABLE_ADDRESS_BROADCAST ) */ + + +#define CFG_HID2 HID2_HBE + +/* DDR @ 0x00000000 */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI @ 0x80000000 */ +#ifdef CONFIG_PCI +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT1L (0) +#define CFG_IBAT1U (0) +#define CFG_IBAT2L (0) +#define CFG_IBAT2U (0) +#endif + +/* IMMRBAR @ 0xE0000000 */ +#define CFG_IBAT3L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT3U (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP) + +/* stack in DCACHE (no backing mem) @ 0xE8000000 */ +#define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +/* LBC SDRAM @ 0xF0000000 */ +#define CFG_IBAT5L (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT5U (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) + +/* BCSR @ 0xF8000000 */ +#define CFG_IBAT6L (CFG_BCSR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT6U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) + +/* FLASH @ 0xFE000000 */ +#define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT7U (CFG_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:04:9f:ef:23:33 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 +#endif + +#define CONFIG_IPADDR 192.168.205.5 + +#define CONFIG_HOSTNAME mpc8349emds +#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx +#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=mpc8349emds\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "bootfile=/tftpboot/mpc8349emds/uImage\0" \ + "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ + "update=protect off fe000000 fe03ffff; " \ + "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ + "upd=run load;run update\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h index 565f9bb..831cc5e 100644 --- a/include/configs/MPC86xADS.h +++ b/include/configs/MPC86xADS.h @@ -21,7 +21,7 @@ #define CONFIG_MPC86xADS 1 /* new ADS */ #define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ -/* New MPC86xADS - pick one of these */ +/* CPU type - pick one of these */ #define CONFIG_MPC866T 1 #undef CONFIG_MPC866P #undef CONFIG_MPC859T @@ -33,7 +33,10 @@ #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 38400 -#define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */ +#define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */ +#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 +#define CFG_8xx_CPUCLK_MIN 40000000 +#define CFG_8xx_CPUCLK_MAX 80000000 #define CONFIG_DRAM_50MHZ 1 #define CONFIG_SDRAM_50MHZ 1 diff --git a/include/configs/MPC885ADS.h b/include/configs/MPC885ADS.h index 74318e5..1867c5b 100644 --- a/include/configs/MPC885ADS.h +++ b/include/configs/MPC885ADS.h @@ -1,44 +1,34 @@ /* * A collection of structures, addresses, and values associated with - * the Motorola DUET ADS board. Values common to all FADS family boards + * the Motorola MPC885ADS board. Values common to all FADS family boards * are in board/fads/fads.h * - * Copyright (C) 2003 Arabella Software Ltd. + * Copyright (C) 2003-2004 Arabella Software Ltd. * Yuli Barcohen <yuli@arabellasw.com> */ #ifndef __CONFIG_H #define __CONFIG_H -/* Board type */ -#define CONFIG_MPC885ADS 1 /* Duet (MPC87x/88x) ADS */ +#define CONFIG_MPC885ADS 1 /* MPC885ADS board */ #define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ -#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */ +#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */ -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 38400 -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ - -#define CFG_PLPRCR ((1 << PLPRCR_MFD_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS) +#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ +#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 +#define CFG_8xx_CPUCLK_MIN 40000000 +#define CFG_8xx_CPUCLK_MAX 133000000 #define CONFIG_SDRAM_50MHZ 1 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) - #include "fads.h" -#undef CFG_SCCR -#define CFG_SCCR (SCCR_TBS|SCCR_EBDF11) - #define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ #define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 091b768..806e95f 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -50,7 +50,6 @@ CFG_CMD_PCI | \ CFG_CMD_CACHE | \ CFG_CMD_IRQ | \ - CFG_CMD_ECHO | \ CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_REGINFO | \ diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h index 6b65031..48ada0e 100644 --- a/include/configs/RPXlite.h +++ b/include/configs/RPXlite.h @@ -21,10 +21,6 @@ * MA 02111-1307 USA */ -/* - * board/config.h - configuration options, board specific - */ - /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr * U-Boot port on RPXlite board */ @@ -53,8 +49,6 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp; " \ @@ -65,6 +59,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) @@ -86,12 +81,14 @@ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x0040000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_RESET_ADDRESS 0x09900000 -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_LOAD_ADDR 0x400000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } @@ -120,16 +117,14 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFC00000 -/*%%% #define CFG_FLASH_BASE 0xFFF00000 */ -#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) +#define CFG_FLASH_BASE 0xFFC00000 +#define CFG_MONITOR_BASE TEXT_BASE #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#ifdef CONFIG_BZIP2 +#define CFG_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */ #else -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE 0xFFF00000 -/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ +#endif /* CONFIG_BZIP2 */ /* * For booting Linux, the board info and command line data @@ -147,9 +142,13 @@ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_DIRECT_FLASH_TFTP + #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + +#define CONFIG_ENV_OVERWRITE /*----------------------------------------------------------------------- * Cache Configuration @@ -352,12 +351,12 @@ #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ #define BCSR0_ENNVRAM 0x02 /* CS4# Control */ -#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ -#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ +#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ +#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ #define BCSR0_COLTEST 0x20 #define BCSR0_ETHLPBK 0x40 -#define BCSR0_ETHEN 0x80 +#define BCSR0_ETHEN 0x80 #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ #define BCSR1_PCVCTL6 0x02 @@ -371,22 +370,13 @@ #define BCSR2_USBSPD 0x40 #define BCSR2_USBSUSP 0x80 -#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ -#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ +#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ +#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ #define BCSR3_RDY_BSY 0x04 /* Flash Operation */ -#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ -#define BCSR3_D27 0x10 /* Dip Switch settings */ -#define BCSR3_D26 0x20 -#define BCSR3_D25 0x40 -#define BCSR3_D24 0x80 - - -/* - * Environment setting - */ - -#define CONFIG_ETHADDR 00:10:EC:00:1D:0B -#define CONFIG_IPADDR 192.168.1.65 -#define CONFIG_SERVERIP 192.168.1.27 +#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ +#define BCSR3_D27 0x10 /* Dip Switch settings */ +#define BCSR3_D26 0x20 +#define BCSR3_D25 0x40 +#define BCSR3_D24 0x80 #endif /* __CONFIG_H */ diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h index 8cd7df1..3102547 100644 --- a/include/configs/RPXlite_DW.h +++ b/include/configs/RPXlite_DW.h @@ -45,7 +45,7 @@ */ /* #define DEBUG 1 */ -/* #ifdef DEPLOYMENT 1 */ +/* #define DEPLOYMENT 1 */ #undef CONFIG_MPC860 #define CONFIG_MPC823 1 /* This is a MPC823e CPU. */ @@ -61,23 +61,23 @@ #define CONFIG_BAUDRATE 9600 /* console default baudrate = 9600bps */ #ifdef DEBUG -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ #else -#define CONFIG_BOOTDELAY 6 /* autoboot after 6 seconds */ +#define CONFIG_BOOTDELAY 6 /* autoboot after 6 seconds */ #ifdef DEPLOYMENT -#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_BOOT_RETRY_TIME -1 #define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 'st')...\n" -#define CONFIG_AUTOBOOT_STOP_STR "st" +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 'st')...\n" +#define CONFIG_AUTOBOOT_STOP_STR "st" #define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_RESET_TO_RETRY 1 -#define CONFIG_BOOT_RETRY_MIN 1 +#define CONFIG_RESET_TO_RETRY 1 +#define CONFIG_BOOT_RETRY_MIN 1 #endif /* DEPLOYMENT */ #endif /* DEBUG */ /* pre-boot commands */ -#define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial" +#define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial" #undef CONFIG_BOOTARGS #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -117,6 +117,36 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +#if 1 /* Enable this stuff could make image enlarge about 25KB. Mask it if you + don't want the advanced function */ + +#ifdef CONFIG_SPLASH_SCREEN +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BMP | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_REGINFO | \ + CFG_CMD_DHCP ) +#else +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_REGINFO | \ + CFG_CMD_DHCP ) +#endif /* CONFIG_SPLASH_SCREEN */ + +/* test-only */ +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ + +#define CONFIG_NETCONSOLE + +#endif /* 1 */ + /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -280,7 +310,7 @@ #if defined(RPXlite_64MHz) #define CFG_SCCR ( SCCR_TBS | SCCR_EBDF01 ) /* %%%SCCR:0x02020000 */ #else -#define CFG_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */ +#define CFG_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */ #endif /*----------------------------------------------------------------------- @@ -446,5 +476,6 @@ #define CONFIG_SERVERIP 172.16.115.6 #define CONFIG_ROOTPATH /workspace/myfilesystem/target/ #define CONFIG_BOOTFILE uImage.rpxusb +#define CONFIG_HOSTNAME LITE_H1_DW #endif /* __CONFIG_H */ diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h index 6ae9403..45907aa 100644 --- a/include/configs/RPXsuper.h +++ b/include/configs/RPXsuper.h @@ -154,7 +154,6 @@ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ CFG_CMD_IMMAP | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_I2C | \ CFG_CMD_REGINFO & \ ~CFG_CMD_KGDB ) diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h index a170f29..dbc57e8 100644 --- a/include/configs/Rattler.h +++ b/include/configs/Rattler.h @@ -127,7 +127,6 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_DHCP \ - | CFG_CMD_ECHO \ | CFG_CMD_IMMAP \ | CFG_CMD_JFFS2 \ | CFG_CMD_MII \ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 5ad1939..6020998 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -161,7 +161,6 @@ CFG_CMD_ASKENV | \ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_JFFS2 | \ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 41f44c5..cec7e3e 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -417,11 +417,58 @@ extern int tqm834x_num_flash_banks; HRCWH_TSEC2M_IN_GMII ) #endif +/* System IO Config */ +#define CFG_SICRH SICRH_TSOBI1 +#define CFG_SICRL SICRL_LDP_A + /* i-cache and d-cache disabled */ #define CFG_HID0_INIT 0x000000000 #define CFG_HID0_FINAL CFG_HID0_INIT #define CFG_HID2 0x000000000 +/* DDR 0 - 512M */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT1L (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +/* stack in DCACHE @ 512M (no backing mem) */ +#define CFG_IBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +/* PCI */ +#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP) + +/* IMMRBAR */ +#define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT6U (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP) + +/* FLASH */ +#define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + /* * Internal Definitions * diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h index f71e691..a5085cf 100644 --- a/include/configs/ZPC1900.h +++ b/include/configs/ZPC1900.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2003-2004 Arabella Software Ltd. + * Copyright (C) 2003-2005 Arabella Software Ltd. * Yuli Barcohen <yuli@arabellasw.com> * * U-Boot configuration for Zephyr Engineering ZPC.1900 board. @@ -32,11 +32,7 @@ #define CPU_ID_STR "MPC8265" #define CONFIG_CPM2 1 /* Has a CPM2 */ -#undef DEBUG - -#undef CONFIG_BOARD_EARLY_INIT_F /* Don't call board_early_init_f */ - -/* Allow serial number (serial) and MAC address (ethaddr) to be overwritten */ +/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ #define CONFIG_ENV_OVERWRITE /* @@ -113,7 +109,6 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_ASKENV \ | CFG_CMD_DHCP \ - | CFG_CMD_ECHO \ | CFG_CMD_IMMAP \ | CFG_CMD_MII \ | CFG_CMD_PING \ @@ -154,31 +149,30 @@ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ +#define CFG_MEMTEST_END 0x03800000 /* 1 ... 56 MB in DRAM */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_LOAD_ADDR 0x400000 /* default load address */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#define CFG_FLASH_BASE 0xFFE00000 -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ - -#define CFG_DEFAULT_IMMR 0x0F010000 - -#define CFG_IMMR 0xF0000000 #define CFG_SDRAM_BASE 0x00000000 #define CFG_SDRAM_SIZE 64 -#define CFG_FLSIMM_BASE 0xFC000000 -#define CFG_LSDRAM_BASE 0xFE000000 + +#define CFG_IMMR 0xF0000000 +#define CFG_LSDRAM_BASE 0xFC000000 +#define CFG_FLASH_BASE 0xFE000000 #define CFG_BCSR 0xFEA00000 #define CFG_EEPROM 0xFEB00000 +#define CFG_FLSIMM_BASE 0xFF000000 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLSIMM_BASE } #define BCSR_PCI_MODE 0x01 @@ -190,10 +184,10 @@ /* Hard reset configuration word */ #define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01| HRCW_CIP |\ - HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB010 |\ - HRCW_BMS | HRCW_LBPC01 | HRCW_APPC10 |\ - HRCW_MODCK_H0101 \ - ) /* 0x16828605 */ + HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\ + HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10 |\ + HRCW_MODCK_H0111 \ + ) /* 0x16848207 */ /* No slaves */ #define CFG_HRCW_SLAVE1 0 #define CFG_HRCW_SLAVE2 0 @@ -211,7 +205,7 @@ #define CFG_RAMBOOT #endif -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ @@ -233,14 +227,14 @@ # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) +#define CFG_HID0_INIT (HID0_ICFI) +#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) #define CFG_HID2 0 #define CFG_SIUMCR 0x42200000 #define CFG_SYPCR 0xFFFFFFC3 -#define CFG_BCR 0x90400000 +#define CFG_BCR 0x90000000 #define CFG_SCCR SCCR_DFBRG01 #define CFG_RMR RMR_CSRE @@ -248,18 +242,23 @@ #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) #define CFG_RCCR 0 -#define CFG_PSDMR 0x014EB45A -#define CFG_PSRT 0x0C -#define CFG_LSDMR 0x008AB552 -#define CFG_LSRT 0x0E +#define CFG_PSDMR /* 0x834DA43B */0x014DA43A +#define CFG_PSRT 0x0F/* 0x0C */ +#define CFG_LSDMR 0x0085A562 +#define CFG_LSRT 0x0F #define CFG_MPTPR 0x4000 +#define CFG_PSDRAM_BR CFG_SDRAM_BASE | 0x00000041 +#define CFG_PSDRAM_OR 0xFC0028C0 +#define CFG_LSDRAM_BR CFG_LSDRAM_BASE | 0x00001861 +#define CFG_LSDRAM_OR 0xFF803480 + #define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00000801 #define CFG_OR0_PRELIM 0xFFE00856 #define CFG_BR5_PRELIM CFG_EEPROM | 0x00000801 #define CFG_OR5_PRELIM 0xFFFF03F6 -#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00000801 -#define CFG_OR6_PRELIM 0xFE000856 +#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00001801 +#define CFG_OR6_PRELIM 0xFF000856 #define CFG_BR7_PRELIM CFG_BCSR | 0x00000801 #define CFG_OR7_PRELIM 0xFFFF83F6 diff --git a/include/configs/ezkit533.h b/include/configs/ezkit533.h new file mode 100644 index 0000000..5eda673 --- /dev/null +++ b/include/configs/ezkit533.h @@ -0,0 +1,188 @@ +#ifndef __CONFIG_EZKIT533_H__ +#define __CONFIG_EZKIT533_H__ + +#define CFG_LONGHELP 1 +#define CONFIG_BAUDRATE 57600 +#define CONFIG_STAMP 1 +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x20310300 +#if 0 +#define CONFIG_MII +#define CFG_DISCOVER_PHY +#endif + +#define CONFIG_RTC_BF533 1 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ + +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 27000000 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 22 +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + +#if ( CONFIG_CLKIN_HALF == 0 ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#else +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#endif + +#if (CONFIG_PLL_BYPASS == 0) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#else +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#endif + +#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_MT48LC16M16A2TG_75 1 + +#define CONFIG_LOADS_ECHO 1 + + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_DATE) +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off" + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01F00000 /* 1 ... 31 MB in DRAM */ +#define CFG_LOAD_ADDR 0x01000000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE 0x02000000 +#define CFG_FLASH_BASE 0x20000000 + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_SIZE 0x4000 +#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) + +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_FLASH0_BASE 0x20000000 +#define CFG_FLASH1_BASE 0x20200000 +#define CFG_FLASH2_BASE 0x20280000 +#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x20020000 +#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ + +/* JFFS Partition offset set */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CFG_JFFS2_FIRST_SECTOR 11 + + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +#define POLL_MODE 1 +#define FLASH_TOT_SECT 40 +#define FLASH_SIZE 0x220000 +#define CFG_FLASH_SIZE 0x220000 + +/* + * Initialize PSD4256 registers for using I2C + */ +#define CONFIG_MISC_INIT_R + +/* + * I2C settings + * By default PF1 is used as SDA and PF0 as SCL on the Stamp board + */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +/* + * Software (bit-bang) I2C driver configuration + */ +#define PF_SCL PF0 +#define PF_SDA PF1 + +#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") +#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") +#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") +#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") +#define I2C_SDA(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SDA; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SDA; \ + asm("ssync;"); \ + } +#define I2C_SCL(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SCL; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SCL; \ + asm("ssync;"); \ + } +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xFE + + +#define __ADSPLPBLACKFIN__ 1 +#define __ADSPBF533__ 1 + +/* 0xFF, 0x7BB07BB0, 0x22547BB0 */ +/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) +#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ + ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN) +#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \ + B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN) +*/ +#define AMGCTLVAL 0xFF +#define AMBCTL0VAL 0x7BB07BB0 +#define AMBCTL1VAL 0xFFC27BB0 + +#define CONFIG_VDSP 1 + +#ifdef CONFIG_VDSP +#define ET_EXEC_VDSP 0x8 +#define SHT_STRTAB_VDSP 0x1 +#define ELFSHDRSIZE_VDSP 0x2C +#define VDSP_ENTRY_ADDR 0xFFA00000 +#endif + +#endif diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h index 6c08043..4f83b19 100644 --- a/include/configs/gw8260.h +++ b/include/configs/gw8260.h @@ -305,7 +305,6 @@ CFG_CMD_BEDBUG | \ CFG_CMD_ELF | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_REGINFO | \ CFG_CMD_IMMAP | \ CFG_CMD_MII) diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index d4dee3b..67c2483 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -67,13 +67,8 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ ADD_USB_CMD | \ CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) + CFG_CMD_I2C) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -131,26 +126,12 @@ * I2C configuration */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ +#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */ #define CFG_I2C_SPEED 100000 /* 100 kHz */ #define CFG_I2C_SLAVE 0x7F /* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x58 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CFG_I2C_RTC_ADDR 0x51 - -/* * Flash configuration (8,16 or 32 MB) * TEXT base always at 0xFFF00000 * ENV_ADDR always at 0xFFF40000 @@ -231,7 +212,7 @@ */ /* 0x10000004 = 32MB SDRAM */ /* 0x90000004 = 64MB SDRAM */ -#define CFG_GPS_PORT_CONFIG 0x10000004 +#define CFG_GPS_PORT_CONFIG 0x00000004 /* * Miscellaneous configurable options @@ -266,6 +247,11 @@ #define CFG_CS0_START CFG_FLASH_BASE #define CFG_CS0_SIZE CFG_FLASH_SIZE +/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ +#define CFG_CS2_START 0x80000000 +#define CFG_CS2_SIZE 0x00001000 +#define CFG_CS2_CFG 0x1d800 + #define CFG_CS_BURST 0x00000000 #define CFG_CS_DEADCYCLE 0x33333333 diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h index 75792221..d671dcc 100644 --- a/include/configs/ppmc8260.h +++ b/include/configs/ppmc8260.h @@ -279,7 +279,6 @@ #define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ CFG_CMD_ELF | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_REGINFO | \ CFG_CMD_MEMTEST | \ CFG_CMD_MII | \ diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index 4e0cfdb..97b52fa 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -507,7 +507,6 @@ # define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ CFG_CMD_ELF | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_I2C | \ CFG_CMD_SPI | \ CFG_CMD_SDRAM | \ @@ -520,7 +519,6 @@ # define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ CFG_CMD_ELF | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_I2C | \ CFG_CMD_SPI | \ CFG_CMD_SDRAM | \ diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h index 180ce05..9cf0654 100644 --- a/include/configs/sbc8260.h +++ b/include/configs/sbc8260.h @@ -448,7 +448,6 @@ #ifdef CONFIG_ETHER_ON_FCC # define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_ELF | \ CFG_CMD_I2C | \ CFG_CMD_IMMAP | \ @@ -459,7 +458,6 @@ #else # define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_ELF | \ CFG_CMD_I2C | \ CFG_CMD_IMMAP | \ diff --git a/include/configs/stamp.h b/include/configs/stamp.h new file mode 100644 index 0000000..248ca70 --- /dev/null +++ b/include/configs/stamp.h @@ -0,0 +1,333 @@ +/* + * U-boot - stamp.h Configuration file for STAMP board + * having BF533 processor + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_STAMP_H__ +#define __CONFIG_STAMP_H__ + +/* + * Board settings + * + */ + +#define __ADSPLPBLACKFIN__ 1 +#define __ADSPBF533__ 1 +#define CONFIG_STAMP 1 +#define CONFIG_RTC_BF533 1 + +/* FLASH/ETHERNET uses the same address range */ +#define SHARED_RESOURCES 1 + +#define CONFIG_VDSP 1 + +/* + * Clock settings + * + */ + +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 11059200 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 45 +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 6 + +/* + * Network Settings + */ +/* network support */ +#define CONFIG_IPADDR 192.168.0.15 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_HOSTNAME STAMP +#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs + +/* To remove hardcoding and enable MAC storage in EEPROM */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ + +/* + * Command settings + * + */ + +#define CFG_LONGHELP 1 + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ +#define CONFIG_BOOTCOMMAND "run ramboot" +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_CACHE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_DATE) +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):eth0:off\0" \ + "ramboot=tftpboot 0x1000000 linux;" \ + "run ramargs;run addip;bootelf\0" \ + "nfsboot=tftpboot 0x1000000 linux;" \ + "run nfsargs;run addip;bootelf\0" \ + "flashboot=bootm 0x20100000\0" \ + "" + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Console settings + * + */ + +#define CONFIG_BAUDRATE 57600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_PROMPT "stamp>" /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_LOADS_ECHO 1 + +/* + * Network settings + * + */ + +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x20300300 +/* To remove hardcoding and enable MAC storage in EEPROM */ +/* #define HARDCODE_MAC 1 */ + +/* + * Flash settings + * + */ + +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET + +#define CFG_ENV_IS_IN_FLASH 1 + +#define CFG_FLASH_BASE 0x20000000 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_ENV_ADDR 0x20020000 +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ + +#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */ +#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ + +/* JFFS Partition offset set */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CFG_JFFS2_FIRST_SECTOR 11 + +/* + * following timeouts shall be used once the + * Flash real protection is enabled + */ +#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ +#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ + +/* + * I2C settings + * By default PF2 is used as SDA and PF3 as SCL on the Stamp board + */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +/* + * Software (bit-bang) I2C driver configuration + */ +#define PF_SCL PF3 +#define PF_SDA PF2 + +#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") +#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") +#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") +#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") +#define I2C_SDA(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SDA; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SDA; \ + asm("ssync;"); \ + } +#define I2C_SCL(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SCL; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SCL; \ + asm("ssync;"); \ + } +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xFE + +/* + * Compact Flash settings + */ + +/* Enabled below option for CF support */ +/* #define CONFIG_STAMP_CF 1 */ + +#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE) + +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_DOS_PARTITION 1 + +/* + * IDE/ATA stuff + */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0x20200000 +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */ + +#define CFG_ATA_STRIDE 2 +#endif + +/* + * SDRAM settings + * + */ + +#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_MT48LC64M4A2FB_7E 1 + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x07EFFFFF /* 1 ... 127 MB in DRAM */ +#define CFG_LOAD_ADDR 0x01000000 /* default load address */ + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE 0x08000000 + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) + +#if ( CONFIG_CLKIN_HALF == 0 ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#else +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#endif + +#if (CONFIG_PLL_BYPASS == 0) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#else +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HZ 1000 /* 1ms time tick */ + +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_SIZE 0x4000 +#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) + +#define CFG_LARGE_IMAGE_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ + +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +/* + * FLASH organization and environment definitions + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* 0xFF, 0xBBC3BBc3, 0x99B39983 */ +/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) +#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \ + B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN) +#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \ + B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN) +*/ +#define AMGCTLVAL 0xFF +#define AMBCTL0VAL 0xBBC3BBC3 +#define AMBCTL1VAL 0x99B39983 +#define CF_AMBCTL1VAL 0x99B3ffc2 + +#ifdef CONFIG_VDSP +#define ET_EXEC_VDSP 0x8 +#define SHT_STRTAB_VDSP 0x1 +#define ELFSHDRSIZE_VDSP 0x2C +#define VDSP_ENTRY_ADDR 0xFFA00000 +#endif + +#endif diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index 3ffe6b2..be6c36c 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -584,5 +584,7 @@ typedef unsigned int led_id_t; #define OF_CPU "PowerPC,MPC870@0" #define OF_TBCLK (MPC8XX_HZ / 16) +#define CONFIG_OF_HAS_BD_T 1 +#define CONFIG_OF_HAS_UBOOT_ENV 1 #endif /* __CONFIG_H */ diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h index d312b65..e5d4397 100644 --- a/include/configs/utx8245.h +++ b/include/configs/utx8245.h @@ -91,7 +91,6 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}" | CFG_CMD_ENV | CFG_CMD_CONSOLE \ | CFG_CMD_LOADS | CFG_CMD_LOADB \ | CFG_CMD_IMI | CFG_CMD_CACHE \ - | CFG_CMD_RUN | CFG_CMD_ECHO \ | CFG_CMD_REGINFO | CFG_CMD_NET\ | CFG_CMD_DHCP | CFG_CMD_I2C \ | CFG_CMD_DATE) diff --git a/include/flash.h b/include/flash.h index 8493191..4c68c68 100644 --- a/include/flash.h +++ b/include/flash.h @@ -242,6 +242,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */ #define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */ #define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */ +#define FLASH_PSD4256GV 0x00E9 /* PSD4256 Flash and CPLD combination */ #define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */ #define INTEL_ID_28F800B3T 0x88928892 /* 8M = 512K x 16 top boot sector */ diff --git a/include/ft_build.h b/include/ft_build.h index 9104b1a..47ca575 100644 --- a/include/ft_build.h +++ b/include/ft_build.h @@ -57,10 +57,12 @@ void ft_prop_int(struct ft_cxt *cxt, const char *name, int val); void ft_begin(struct ft_cxt *cxt, void *blob, int max_size); void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size); -void ft_setup(void *blob, int size, bd_t * bd); +void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end); void ft_dump_blob(const void *bphp); void ft_merge_blob(struct ft_cxt *cxt, void *blob); void *ft_get_prop(void *bphp, const char *propname, int *szp); +void ft_board_setup(void *blob, bd_t *bd); + #endif diff --git a/include/image.h b/include/image.h index af37bca..139df0b 100644 --- a/include/image.h +++ b/include/image.h @@ -75,6 +75,7 @@ #define IH_CPU_NIOS 13 /* Nios-32 */ #define IH_CPU_MICROBLAZE 14 /* MicroBlaze */ #define IH_CPU_NIOS2 15 /* Nios-II */ +#define IH_CPU_BLACKFIN 16 /* Blackfin */ /* * Image Types diff --git a/include/linux/stat.h b/include/linux/stat.h index 2f7a3b3..f9422cb 100644 --- a/include/linux/stat.h +++ b/include/linux/stat.h @@ -67,7 +67,7 @@ struct stat { #endif /* __PPC__ */ -#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) +#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__blackfin__) struct stat { unsigned short st_dev; diff --git a/include/mpc85xx.h b/include/mpc85xx.h index 60b6c61..a4d99b2 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -25,4 +25,39 @@ #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ +/* + * Local Bus Controller - memory controller registers + */ +#define BRx_V 0x00000001 /* Bank Valid */ +#define BRx_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */ +#define BRx_MS_SDRAM 0x00000000 /* SDRAM Machine Select */ +#define BRx_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ +#define BRx_MS_UPMB 0x000000a0 /* U.P.M.B Machine Select */ +#define BRx_MS_UPMC 0x000000c0 /* U.P.M.C Machine Select */ +#define BRx_PS_8 0x00000800 /* 8 bit port size */ +#define BRx_PS_32 0x00001800 /* 32 bit port size */ +#define BRx_BA_MSK 0xffff8000 /* Base Address Mask */ + +#define ORxG_EAD 0x00000001 /* External addr latch delay */ +#define ORxG_EHTR 0x00000002 /* Extended hold time on read */ +#define ORxG_TRLX 0x00000004 /* Timing relaxed */ +#define ORxG_SETA 0x00000008 /* External address termination */ +#define ORxG_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */ +#define ORxG_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */ +#define ORxG_XACS 0x00000100 /* Extra addr to CS setup */ +#define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/ +#define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */ + +#define ORxU_BI 0x00000100 /* Burst Inhibit */ +#define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */ + +#define MxMR_OP_NORM 0x00000000 /* Normal Operation */ +#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */ +#define MxMR_OP_WARR 0x10000000 /* Write to Array */ +#define MxMR_BSEL 0x80000000 /* Bus Select */ + +/* helpers to convert values into an OR address mask (GPCM mode) */ +#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ +#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20) + #endif /* __MPC85xx_H__ */ diff --git a/include/ns16550.h b/include/ns16550.h index e17a11e..d987a8b 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -45,15 +45,15 @@ struct NS16550 { } __attribute__ ((packed)); #elif (CFG_NS16550_REG_SIZE == 4) struct NS16550 { - unsigned long rbr; /* 0 */ - unsigned long ier; /* 1 */ - unsigned long fcr; /* 2 */ - unsigned long lcr; /* 3 */ - unsigned long mcr; /* 4 */ - unsigned long lsr; /* 5 */ - unsigned long msr; /* 6 */ - unsigned long scr; /* 7 */ -} __attribute__ ((packed)); + unsigned long rbr; /* 0 r */ + unsigned long ier; /* 1 rw */ + unsigned long fcr; /* 2 w */ + unsigned long lcr; /* 3 rw */ + unsigned long mcr; /* 4 rw */ + unsigned long lsr; /* 5 r */ + unsigned long msr; /* 6 r */ + unsigned long scr; /* 7 rw */ +}; /* No need to pack an already aligned struct */ #elif (CFG_NS16550_REG_SIZE == -4) struct NS16550 { unsigned char rbr; /* 0 */ @@ -102,7 +102,7 @@ typedef volatile struct NS16550 *NS16550_t; #define MCR_DMA_EN 0x04 #define MCR_TX_DFR 0x08 -#define LCR_WLS_MSK 0x03 /* character length slect mask */ +#define LCR_WLS_MSK 0x03 /* character length select mask */ #define LCR_WLS_5 0x00 /* 5 bit character length */ #define LCR_WLS_6 0x01 /* 6 bit character length */ #define LCR_WLS_7 0x02 /* 7 bit character length */ diff --git a/include/pci.h b/include/pci.h index 8f19997..0fc00e4 100644 --- a/include/pci.h +++ b/include/pci.h @@ -309,6 +309,7 @@ struct pci_region { #define PCI_REGION_MEM 0x00000000 /* PCI memory space */ #define PCI_REGION_IO 0x00000001 /* PCI IO space */ #define PCI_REGION_TYPE 0x00000001 +#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */ #define PCI_REGION_MEMORY 0x00000100 /* System memory */ #define PCI_REGION_RO 0x00000200 /* Read-only memory */ @@ -351,8 +352,8 @@ struct pci_config_table { unsigned long priv[3]; }; -extern void pci_cfgfunc_nothing(struct pci_controller* hose, pci_dev_t dev, - struct pci_config_table *); +extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, + struct pci_config_table *); extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *); @@ -386,7 +387,7 @@ struct pci_controller { int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32); /* Used by auto config */ - struct pci_region *pci_mem, *pci_io; + struct pci_region *pci_mem, *pci_io, *pci_prefetch; /* Used by ppc405 autoconfig*/ struct pci_region *pci_fb; @@ -472,6 +473,7 @@ extern int pciauto_region_allocate(struct pci_region* res, unsigned int size, un extern void pciauto_setup_device(struct pci_controller *hose, pci_dev_t dev, int bars_num, struct pci_region *mem, + struct pci_region *prefetch, struct pci_region *io); int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); diff --git a/include/spd_sdram.h b/include/spd_sdram.h index 4e754ec..a2be96c 100644 --- a/include/spd_sdram.h +++ b/include/spd_sdram.h @@ -1,6 +1,6 @@ #ifndef _SPD_SDRAM_H_ #define _SPD_SDRAM_H_ -long int spd_sdram(int(read_spd)(uint addr)); +long int spd_sdram(void); #endif |