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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-08-26 23:14:14 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2008-08-27 11:43:51 -0500 |
| commit | a947e4c7eb15cea1d9fb633955c516aab5ad35dd (patch) | |
| tree | c5bafc6d590130a8fe07ecdf9242bc43aef8a73a /include | |
| parent | be0bd8234b9777ecd63c4c686f72af070d886517 (diff) | |
| download | u-boot-imx-a947e4c7eb15cea1d9fb633955c516aab5ad35dd.zip u-boot-imx-a947e4c7eb15cea1d9fb633955c516aab5ad35dd.tar.gz u-boot-imx-a947e4c7eb15cea1d9fb633955c516aab5ad35dd.tar.bz2 | |
FSL DDR: Convert atum8548 to new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/ATUM8548.h | 62 |
1 files changed, 30 insertions, 32 deletions
diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index 6aa881c..5bc28f1 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -55,18 +55,11 @@ #define CONFIG_TSEC_ENET 1 /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/ -#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ - #define CONFIG_SYS_CLK_FREQ 33000000 /* @@ -104,33 +97,38 @@ #define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +/* DDR Setup */ +#define CONFIG_FSL_DDR2 +#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD -#if defined(CONFIG_SPD_EEPROM) - /* - * Determine DDR configuration from I2C interface. - */ - #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#else - /* - * Manually set up DDR parameters - */ - #define CFG_SDRAM_SIZE 1024 /* DDR is 1024MB */ - #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-1024 */ - #define CFG_DDR_CS0_CONFIG 0x80000102 - #define CFG_DDR_TIMING_0 0x00260802 - #define CFG_DDR_TIMING_1 0x38355322 - #define CFG_DDR_TIMING_2 0x039048c7 - #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ - #define CFG_DDR_MODE 0x00000432 - #define CFG_DDR_INTERVAL 0x05150100 - #define DDR_SDRAM_CFG 0x43000000 -#endif +#define CFG_DDR_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 + +/* I2C addresses of SPD EEPROMs */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ + +/* Manually set up DDR parameters */ +#define CFG_SDRAM_SIZE 1024 /* DDR is 1024MB */ +#define CFG_DDR_CS0_BNDS 0x0000000f /* 0-1024 */ +#define CFG_DDR_CS0_CONFIG 0x80000102 +#define CFG_DDR_TIMING_0 0x00260802 +#define CFG_DDR_TIMING_1 0x38355322 +#define CFG_DDR_TIMING_2 0x039048c7 +#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +#define CFG_DDR_MODE 0x00000432 +#define CFG_DDR_INTERVAL 0x05150100 +#define DDR_SDRAM_CFG 0x43000000 #undef CONFIG_CLOCKS_IN_MHZ |