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authorMatthias Fuchs <matthias.fuchs@esd-electronics.com>2007-12-28 17:10:36 +0100
committerStefan Roese <sr@denx.de>2007-12-28 17:21:45 +0100
commitf6e0f1f61896ce7729ba1bcea2ffbd138d3947f5 (patch)
tree589d920f0a9f4bb6ca29a637d56dcf7976719e61 /include
parent77660c4b59055d621d2a8595bd4c18bb277268fc (diff)
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ppc4xx: Add EEPROM write protection for PLU405 boards + misc. updates
- add EEPROM write protection for esd PLU405 boards. - initialize NAND GPIOs - use correct io accessors - cleanup Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/PLU405.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 6b16654..0bd77c0 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -288,6 +288,7 @@
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
+#define CFG_EEPROM_WREN 1
/* CAT24WC08/16... */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
@@ -379,15 +380,16 @@
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
-#define CFG_GPIO0_OSRH 0x40000550
+#define CFG_GPIO0_OSRH 0x00000550
#define CFG_GPIO0_OSRL 0x00000110
#define CFG_GPIO0_ISR1H 0x00000000
#define CFG_GPIO0_ISR1L 0x15555445
#define CFG_GPIO0_TSRH 0x00000000
#define CFG_GPIO0_TSRL 0x00000000
-#define CFG_GPIO0_TCR 0xF7FE0014
+#define CFG_GPIO0_TCR 0x77FE0014
#define CFG_DUART_RST (0x80000000 >> 14)
+#define CFG_EEPROM_WP (0x80000000 >> 0)
/*
* Internal Definitions