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authorWolfgang Denk <wd@denx.de>2011-04-27 21:48:09 +0200
committerWolfgang Denk <wd@denx.de>2011-04-27 21:48:09 +0200
commitf38536f9138c253b0c1f9c72093a7ec6808e638f (patch)
tree43bd82d4f1f96f549821d5fd941dfdc70712b501 /include
parent34b5fc4d8bba594d53a15be970ca78b03db9d7f5 (diff)
parentd32a1a4caa2a2ca7c385f4489167e170bf7fb5c1 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'include')
-rw-r--r--include/configs/a320evb.h9
-rw-r--r--include/configs/am3517_crane.h332
-rw-r--r--include/configs/am3517_evm.h18
-rw-r--r--include/configs/aspenite.h1
-rw-r--r--include/configs/ca9x4_ct_vxp.h1
-rw-r--r--include/configs/cm_t35.h57
-rw-r--r--include/configs/cpu9260.h265
-rw-r--r--include/configs/cpuat91.h141
-rw-r--r--include/configs/devkit8000.h10
-rw-r--r--include/configs/dig297.h311
-rw-r--r--include/configs/dkb.h2
-rw-r--r--include/configs/edminiv2.h2
-rw-r--r--include/configs/harmony.h1
-rw-r--r--include/configs/igep0020.h57
-rw-r--r--include/configs/igep0030.h57
-rw-r--r--include/configs/imx31_litekit.h2
-rw-r--r--include/configs/innokom.h2
-rw-r--r--include/configs/mx31ads.h2
-rw-r--r--include/configs/mx31pdk.h2
-rw-r--r--include/configs/mx51evk.h5
-rw-r--r--include/configs/mx53evk.h3
-rw-r--r--include/configs/nhk8815.h5
-rw-r--r--include/configs/omap3_beagle.h65
-rw-r--r--include/configs/omap3_evm.h26
-rw-r--r--include/configs/omap3_overo.h16
-rw-r--r--include/configs/omap3_pandora.h16
-rw-r--r--include/configs/omap3_sdp3430.h10
-rw-r--r--include/configs/omap3_zoom1.h16
-rw-r--r--include/configs/omap3_zoom2.h16
-rw-r--r--include/configs/qong.h3
-rw-r--r--include/configs/seaboard.h1
-rw-r--r--include/configs/tegra2-common.h2
-rw-r--r--include/configs/xm250.h2
-rw-r--r--include/faraday/ftpmu010.h244
-rw-r--r--include/faraday/ftsdmc020.h103
-rw-r--r--include/faraday/ftsmc020.h79
-rw-r--r--include/faraday/fttmr010.h73
37 files changed, 1644 insertions, 313 deletions
diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h
index 27f137f..4b297f0 100644
--- a/include/configs/a320evb.h
+++ b/include/configs/a320evb.h
@@ -32,6 +32,11 @@
#undef CONFIG_SKIP_LOWLEVEL_INIT
/*-----------------------------------------------------------------------
+ * Power Management Unit
+ */
+#define CONFIG_FTPMU010_POWER
+
+/*-----------------------------------------------------------------------
* Timer
*/
#define CONFIG_SYS_HZ 1000 /* timer ticks per second */
@@ -158,7 +163,8 @@
* Static memory controller configuration
*/
-#include <asm/arch/ftsmc020.h>
+#define CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
@@ -191,6 +197,7 @@
{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
}
+#endif /* CONFIG_FTSMC020 */
/*-----------------------------------------------------------------------
* FLASH and environment organization
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
new file mode 100644
index 0000000..09cb951
--- /dev/null
+++ b/include/configs/am3517_crane.h
@@ -0,0 +1,332 @@
+/*
+ * am3517_crane.h - Default configuration for AM3517 CraneBoard.
+ *
+ * Author: Srinath.R <srinath@mistralsolutions.com>
+ *
+ * Based on include/configs/am3517evm.h
+ *
+ * Copyright (C) 2011 Mistral Solutions pvt Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
+
+#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+ /* initial data */
+/*
+ * DDR related
+ */
+#define CONFIG_OMAP3_MICRON_DDR 1 /* Micron DDR */
+#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+#define CONFIG_MMC 1
+#define CONFIG_OMAP3_MMC 1
+#define CONFIG_DOS_PARTITION 1
+
+/*
+ * USB configuration
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDC for Device functionalities.
+ */
+#define CONFIG_USB_AM35X 1
+#define CONFIG_MUSB_HCD 1
+
+#ifdef CONFIG_USB_AM35X
+
+#ifdef CONFIG_MUSB_HCD
+#define CONFIG_CMD_USB
+
+#define CONFIG_USB_STORAGE
+#define CONGIG_CMD_STORAGE
+#define CONFIG_CMD_FAT
+
+#ifdef CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_PREBOOT "usb start"
+#endif /* CONFIG_USB_KEYBOARD */
+
+#endif /* CONFIG_MUSB_HCD */
+
+#ifdef CONFIG_MUSB_UDC
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID 0x0451
+#define CONFIG_USBD_PRODUCTID 0x5678
+#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE"
+#endif /* CONFIG_MUSB_UDC */
+
+#endif /* CONFIG_USB_AM35X */
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_NAND /* NAND support */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
+ /* to access nand */
+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
+ /* to access */
+ /* nand at CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
+ /* NAND devices */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV "nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET 0x680000
+#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY 10
+
+#define CONFIG_BOOTFILE uImage
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "console=ttyS2,115200n8\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "root=/dev/mmcblk0p2 rw " \
+ "rootfstype=ext3 rootwait\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "root=/dev/mtdblock4 rw " \
+ "rootfstype=jffs2\0" \
+ "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${loadaddr} 280000 400000; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc init; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run nandboot; " \
+ "fi; " \
+ "fi; " \
+ "else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE 1
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT "AM3517_CRANE # "
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT V_PROMPT
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 32 /* max number of command */
+ /* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
+ 0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
+ /* address */
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
+
+#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
+ /* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
+#define CONFIG_ENV_IS_IN_NAND 1
+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
+ CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS 1
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#endif /* __CONFIG_H */
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 70e8f07..f5d5821 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -294,7 +294,9 @@
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_SYS_FLASH_BASE boot_flash_base
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
@@ -304,9 +306,9 @@
#define CONFIG_ENV_IS_IN_NAND 1
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
-#define CONFIG_ENV_OFFSET boot_flash_off
-#define CONFIG_ENV_ADDR boot_flash_env_addr
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
/*-----------------------------------------------------------------------
* CFI FLASH driver setup
@@ -323,14 +325,6 @@
#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
-
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h
index fd35f3e..1619db5 100644
--- a/include/configs/aspenite.h
+++ b/include/configs/aspenite.h
@@ -52,6 +52,7 @@
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
+#define CONFIG_CMD_I2C
#define CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
diff --git a/include/configs/ca9x4_ct_vxp.h b/include/configs/ca9x4_ct_vxp.h
index 63f003d..2a87a79 100644
--- a/include/configs/ca9x4_ct_vxp.h
+++ b/include/configs/ca9x4_ct_vxp.h
@@ -30,6 +30,7 @@
/* Board info register */
#define SYS_ID 0x10000000
#define CONFIG_REVISION_TAG 1
+#define CONFIG_SYS_TEXT_BASE 0x60800000
/* High Level Configuration Options */
#define CONFIG_ARMV7 1
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 510c6d4..e07e8b3 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -1,7 +1,8 @@
/*
- * (C) Copyright 2010
+ * (C) Copyright 2011
* CompuLab, Ltd.
* Mike Rapoport <mike@compulab.co.il>
+ * Igor Grinberg <grinberg@compulab.co.il>
*
* Based on omap3_beagle.h
* (C) Copyright 2006-2008
@@ -9,7 +10,7 @@
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <x0khasim@ti.com>
*
- * Configuration settings for the CompuLab CM-T35 board
+ * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -26,8 +27,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc.
*/
#ifndef __CONFIG_H
@@ -40,7 +40,7 @@
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
-#define CONFIG_CM_T35 1 /* working with CM-T35 */
+#define CONFIG_CM_T3X 1 /* working with CM-T35 and CM-T3730 */
#define CONFIG_SYS_TEXT_BASE 0x80008000
@@ -110,9 +110,8 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
-#define CONFIG_GENERIC_MMC 1
#define CONFIG_MMC 1
-#define CONFIG_OMAP_HSMMC 1
+#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
/* DDR - I use Micron DDR */
@@ -244,14 +243,17 @@
"fi; " \
"else run nandboot; fi"
-#define CONFIG_AUTO_COMPLETE 1
/*
* Miscellaneous configurable options
*/
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_TIMESTAMP
+#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_PROMPT "CM-T35 # "
+#define CONFIG_SYS_PROMPT "CM-T3x # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
@@ -310,7 +312,9 @@
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_SYS_FLASH_BASE boot_flash_base
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
@@ -320,25 +324,17 @@
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
-#define CONFIG_ENV_OFFSET boot_flash_off
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
-
#if defined(CONFIG_CMD_NET)
#define CONFIG_NET_MULTI
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
-#define CM_T35_SMC911X_BASE 0x2C000000
-#define SB_T35_SMC911X_BASE (CM_T35_SMC911X_BASE + (16 << 20))
-#define CONFIG_SMC911X_BASE CM_T35_SMC911X_BASE
+#define CM_T3X_SMC911X_BASE 0x2C000000
+#define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20))
+#define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE
#endif /* (CONFIG_CMD_NET) */
/* additions for new relocation code, must be added to all boards */
@@ -349,4 +345,19 @@ extern unsigned int boot_flash_type;
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
+/* Status LED */
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED 1
+#define STATUS_LED_GREEN 0
+#define STATUS_LED_BIT STATUS_LED_GREEN
+#define STATUS_LED_STATE STATUS_LED_ON
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BOOT STATUS_LED_BIT
+#define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
+
+/* GPIO banks */
+#ifdef CONFIG_STATUS_LED
+#define CONFIG_OMAP3_GPIO_6 1 /* GPIO186 is in GPIO bank 6 */
+#endif
+
#endif /* __CONFIG_H */
diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h
index d239423..a8ada2d 100644
--- a/include/configs/cpu9260.h
+++ b/include/configs/cpu9260.h
@@ -31,35 +31,39 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_AT91_LEGACY
-
-#define CONFIG_DISPLAY_CPUINFO 1
+/* to be removed once maemory-map.h is fixed */
+#define AT91_BASE_SYS 0xffffe800
+#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
#define CONFIG_SYS_HZ 1000
-#define CONFIG_ARM926EJS 1
-
-#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9260)
-#define CONFIG_CPU9260 1
-#elif defined(CONFIG_CPU9G20_128M) || defined(CONFIG_CPU9G20)
-#define CONFIG_CPU9G20 1
-#endif
+#define CONFIG_ARM926EJS
#if defined(CONFIG_CPU9G20)
-#define CONFIG_AT91SAM9G20 1
+#define CONFIG_AT91SAM9G20
#elif defined(CONFIG_CPU9260)
-#define CONFIG_AT91SAM9260 1
+#define CONFIG_AT91SAM9260
#else
#error "Unknown board"
#endif
+#define CONFIG_AT91FAMILY
#define CONFIG_ARCH_CPU_INIT
#undef CONFIG_USE_IRQ
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_CMDLINE_TAG 1
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#if defined(CONFIG_NANDBOOT)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE 0x23f00000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+#endif
/* clocks */
#if defined(CONFIG_CPU9G20)
@@ -113,8 +117,8 @@
/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
#define CONFIG_SYS_MATRIX_EBICSA_VAL \
- (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC |\
- AT91_MATRIX_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_VDDIOMSEL)
+ (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \
+ AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V)
/* SDRAM */
/* SDRAMC_MR Mode register */
@@ -199,67 +203,68 @@
/* setup SMC0, CS0 (NOR Flash) - 16-bit */
#if defined(CONFIG_CPU9G20)
#define CONFIG_SYS_SMC0_SETUP0_VAL \
- (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \
- AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
+ (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
+ AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
#define CONFIG_SYS_SMC0_PULSE0_VAL \
- (AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(8) | \
- AT91_SMC_NRDPULSE_(14) | AT91_SMC_NCS_RDPULSE_(14))
+ (AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) | \
+ AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14))
#define CONFIG_SYS_SMC0_CYCLE0_VAL \
- (AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(14))
+ (AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14))
#define CONFIG_SYS_SMC0_MODE0_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(3))
+ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
+ AT91_SMC_MODE_DBW_16 | \
+ AT91_SMC_MODE_TDF | \
+ AT91_SMC_MODE_TDF_CYCLE(3))
#elif defined(CONFIG_CPU9260)
#define CONFIG_SYS_SMC0_SETUP0_VAL \
- (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \
- AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
+ (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
+ AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
#define CONFIG_SYS_SMC0_PULSE0_VAL \
- (AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(6) | \
- AT91_SMC_NRDPULSE_(10) | AT91_SMC_NCS_RDPULSE_(10))
+ (AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) | \
+ AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10))
#define CONFIG_SYS_SMC0_CYCLE0_VAL \
- (AT91_SMC_NWECYCLE_(6) | AT91_SMC_NRDCYCLE_(10))
+ (AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10))
#define CONFIG_SYS_SMC0_MODE0_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(2))
+ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
+ AT91_SMC_MODE_DBW_16 | \
+ AT91_SMC_MODE_TDF | \
+ AT91_SMC_MODE_TDF_CYCLE(2))
#endif
/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \
- AT91_RSTC_PROCRST | \
- AT91_RSTC_RSTTYP_WAKEUP | \
- AT91_RSTC_RSTTYP_WATCHDOG)
+ AT91_RSTC_CR_PROCRST | \
+ AT91_RSTC_MR_ERSTL(1) | \
+ AT91_RSTC_MR_ERSTL(2))
/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
- AT91_WDT_WDV | \
- AT91_WDT_WDDIS | \
- AT91_WDT_WDD)
+ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
+ AT91_WDT_MR_WDV(0xfff) | \
+ AT91_WDT_MR_WDDIS | \
+ AT91_WDT_MR_WDD(0xfff))
/*
* Hardware drivers
*/
-#define CONFIG_AT91_GPIO 1
-#define CONFIG_ATMEL_USART 1
+#define CONFIG_AT91SAM9_WATCHDOG
+#define CONFIG_AT91_GPIO
+#define CONFIG_ATMEL_USART
#undef CONFIG_USART0
#undef CONFIG_USART1
#undef CONFIG_USART2
-#define CONFIG_USART3 1 /* USART 3 is DBGU */
+#define CONFIG_USART3
#define CONFIG_BOOTDELAY 3
/*
* BOOTP options
*/
-#define CONFIG_BOOTP_BOOTFILESIZE 1
-#define CONFIG_BOOTP_BOOTPATH 1
-#define CONFIG_BOOTP_GATEWAY 1
-#define CONFIG_BOOTP_HOSTNAME 1
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
@@ -271,37 +276,41 @@
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
-#define CONFIG_CMD_PING 1
-#define CONFIG_CMD_DHCP 1
-#define CONFIG_CMD_NAND 1
-#define CONFIG_CMD_USB 1
-#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MII
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM 0x20000000
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
-#define PHYS_SDRAM_SIZE 0x08000000 /* 128 MB */
+#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB
#else
-#define PHYS_SDRAM_SIZE 0x04000000 /* 64 MB */
+#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB
#endif
/* NAND flash */
-#define CONFIG_NAND_ATMEL 1
+#define CONFIG_NAND_ATMEL
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTC, 13
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
/* NOR flash */
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_FLASH_CFI_DRIVER 1
+#if defined(CONFIG_NANDBOOT)
+#define CONFIG_SYS_NO_FLASH
+#else
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
#define PHYS_FLASH_1 0x10000000
#define PHYS_FLASH_2 0x12000000
#define CONFIG_SYS_FLASH_BANKS_LIST \
@@ -310,23 +319,23 @@
#define CONFIG_SYS_MAX_FLASH_SECT (255+4)
#define CONFIG_SYS_MAX_FLASH_BANKS 2
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_EMPTY_INFO 1
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-#define CONFIG_SYS_FLASH_PROTECTION 1
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
+#endif
/* Ethernet */
-#define CONFIG_MACB 1
-#define CONFIG_RMII 1
-#define CONFIG_RESET_PHY_R 1
-#define CONFIG_NET_MULTI 1
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_MULTI
#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_MACB_SEARCH_PHY 1
+#define CONFIG_MACB_SEARCH_PHY
/* LEDS */
/* Status LED */
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-#define CONFIG_BOARD_SPECIFIC_LED 1
+#define CONFIG_STATUS_LED
+#define CONFIG_BOARD_SPECIFIC_LED
#define STATUS_LED_RED 0
#define STATUS_LED_GREEN 1
#define STATUS_LED_YELLOW 2
@@ -350,39 +359,56 @@
/* Optional value */
#define STATUS_LED_BOOT STATUS_LED_BIT
-#define CONFIG_RED_LED AT91_PIN_PC11
-#define CONFIG_GREEN_LED AT91_PIN_PC12
-#define CONFIG_YELLOW_LED AT91_PIN_PC7
-#define CONFIG_BLUE_LED AT91_PIN_PC9
+#define CONFIG_RED_LED AT91_PIO_PORTC, 11
+#define CONFIG_GREEN_LED AT91_PIO_PORTC, 12
+#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 7
+#define CONFIG_BLUE_LED AT91_PIO_PORTC, 9
/* USB */
-#define CONFIG_USB_ATMEL 1
-#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g20"
+#elif defined(CONFIG_CPU9260)
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
+#endif
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_USB_STORAGE 1
+#define CONFIG_USB_STORAGE
#define CONFIG_SYS_LOAD_ADDR 0x21000000
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
-#define CONFIG_SYS_MEMTEST_END 0x21e00000
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END \
+ (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
+#if defined(CONFIG_NANDBOOT)
+#define CONFIG_SYS_USE_NANDFLASH
+#undef CONFIG_SYS_USE_FLASH
+#else
+#define CONFIG_SYS_USE_FLASH
#undef CONFIG_SYS_USE_NANDFLASH
-#define CONFIG_SYS_USE_FLASH 1
+#endif
+
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_SYS_BASEDIR "cpu9G20"
+#elif defined(CONFIG_CPU9260)
+#define CONFIG_SYS_BASEDIR "cpu9260"
+#endif
#if defined(CONFIG_SYS_USE_FLASH)
-#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_ENV_OVERWRITE
#define CONFIG_BOOTCOMMAND "run flashboot"
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
#define MTDPARTS_DEFAULT \
"mtdparts=physmap-flash.0:" \
"256k(u-boot)ro," \
@@ -393,18 +419,12 @@
#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_BASEDIR "cpu9G20"
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_BASEDIR "cpu9260"
-#endif
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"partition=nand0,0\0" \
"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
- "ramboot=tftpboot 0x22000000 cpu9260/uImage;" \
+ "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
"run ramargs;bootm 22000000\0" \
"flashboot=run ramargs;bootm 0x10060000\0" \
"basedir=" CONFIG_SYS_BASEDIR "\0" \
@@ -421,6 +441,52 @@
"0x10220000 0x13ffffff;cp.b 0x24000000 " \
"0x10220000 $(filesize)\0" \
""
+#elif defined(CONFIG_NANDBOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x60000
+#define CONFIG_ENV_OFFSET_REDUND 0x80000
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BOOTCOMMAND "run flashboot"
+
+#define MTDIDS_DEFAULT "nand0=atmel_nand"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=atmel_nand:" \
+ "128k(bootstrap)ro," \
+ "256k(u-boot)ro," \
+ "128k(u-boot-env)ro," \
+ "128k(u-boot-env2)ro," \
+ "2M(kernel)," \
+ "-(rootfs)"
+
+#define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs " \
+ "ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "partition=nand0,5\0" \
+ "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
+ "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
+ "run ramargs;bootm 22000000\0" \
+ "flashboot=run ramargs; nand read 0x22000000 0xA0000 " \
+ "0x200000; bootm 0x22000000\0" \
+ "basedir=" CONFIG_SYS_BASEDIR "\0" \
+ "u-boot=u-boot-eukrea-cpu9260.bin\0" \
+ "kernel=uImage-eukrea-cpu9260.bin\0" \
+ "rootfs=image-eukrea-cpu9260.ubi\0" \
+ "updtub=tftp ${loadaddr} $(basedir)/${u-boot}; " \
+ "nand erase 20000 40000; " \
+ "nand write ${loadaddr} 20000 40000\0" \
+ "updtui=tftp ${loadaddr} $(basedir)/${kernel}; " \
+ "nand erase a0000 200000; " \
+ "nand write ${loadaddr} a0000 200000\0" \
+ "updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; " \
+ "nand erase 2a0000 fd60000; " \
+ "nand write ${loadaddr} 2a0000 ${filesize}\0"
#endif
#define CONFIG_BAUDRATE 115200
@@ -435,10 +501,10 @@
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_SILENT_CONSOLE 1
-#define CONFIG_NETCONSOLE 1
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_NETCONSOLE
/*
* Size of malloc() pool
@@ -446,6 +512,9 @@
#define CONFIG_SYS_MALLOC_LEN \
ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
+ GENERATED_GBL_DATA_SIZE)
+
#define CONFIG_STACKSIZE (32 * 1024)
#if defined(CONFIG_USE_IRQ)
diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h
index f31081d..cfaef15 100644
--- a/include/configs/cpuat91.h
+++ b/include/configs/cpuat91.h
@@ -26,30 +26,36 @@
#ifndef _CONFIG_CPUAT91_H
#define _CONFIG_CPUAT91_H
-#ifdef CONFIG_CPUAT91_RAM
-#define CONFIG_SKIP_LOWLEVEL_INIT 1
+#include <asm/sizes.h>
+
+#ifdef CONFIG_RAMBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE 0x21F00000
#else
#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_TEXT_BASE 0
#endif
-#define AT91C_MAIN_CLOCK 179712000
-#define AT91C_MASTER_CLOCK 59904000
-
-#define AT91_SLOW_CLOCK 32768
+#define AT91C_XTAL_CLOCK 18432000
+#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
+#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
+#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
+#define CONFIG_SYS_HZ 1000
-#define CONFIG_ARM920T 1
-#define CONFIG_AT91RM9200 1
-#define CONFIG_CPUAT91 1
+#define CONFIG_ARM920T
+#define CONFIG_AT91RM9200
+#define CONFIG_CPUAT91
+#define CONFIG_AT91FAMILY
#undef CONFIG_USE_IRQ
-#define USE_920T_MMU 1
+#define USE_920T_MMU
-#define CONFIG_CMDLINE_TAG 1
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR
/* flash */
#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
#define CONFIG_SYS_MC_PUP_VAL 0x00000000
@@ -81,17 +87,15 @@
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
/* define one of these to choose the DBGU, USART0 or USART1 as console */
-#define CONFIG_AT91RM9200_USART 1
-#define CONFIG_DBGU 1
-#undef CONFIG_USART0
-#undef CONFIG_USART1
+#define CONFIG_AT91RM9200_USART
+#define CONFIG_DBGU
#undef CONFIG_HARD_I2C
-#define CONFIG_SOFT_I2C 1
+#undef CONFIG_SOFT_I2C
#define AT91_PIN_SDA (1<<25)
#define AT91_PIN_SCL (1<<26)
-#define CONFIG_SYS_I2C_INIT_BOARD 1
+#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_SYS_I2C_SLAVE 0
@@ -117,70 +121,77 @@
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CONFIG_BOOTP_BOOTFILESIZE 1
-#define CONFIG_BOOTP_BOOTPATH 1
-#define CONFIG_BOOTP_GATEWAY 1
-#define CONFIG_BOOTP_HOSTNAME 1
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
#include <config_cmd_default.h>
-#define CONFIG_CMD_DHCP 1
-#define CONFIG_CMD_PING 1
-#define CONFIG_CMD_MII 1
-#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_USB
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM 1
-#define CONFIG_CMD_I2C 1
+#ifdef CONFIG_SOFT_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#endif
#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM 0x20000000
-#define PHYS_SDRAM_SIZE 0x02000000
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END \
- (CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512 * 1024)
+ (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
-#define CONFIG_NET_MULTI 1
-#define CONFIG_DRIVER_AT91EMAC 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8
-#define CONFIG_RMII 1
-#define CONFIG_MII 1
+#define CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC
+#define CONFIG_SYS_RX_ETH_BUFFER 16
+#define CONFIG_RMII
+#define CONFIG_MII
#define CONFIG_DRIVER_AT91EMAC_PHYADDR 1
#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_KS8721_PHY 1
+#define CONFIG_KS8721_PHY
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_SYS_FLASH_EMPTY_INFO 1
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_PROTECTION 1
+#define CONFIG_SYS_FLASH_PROTECTION
#define PHYS_FLASH_1 0x10000000
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_SECT 128
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
+#define PHYS_FLASH_SIZE (16 * 1024 * 1024)
+#define CONFIG_SYS_FLASH_BANKS_LIST \
+ { PHYS_FLASH_1 }
#if defined(CONFIG_CMD_USB)
-#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_USB_STORAGE 1
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_AT91C_PQFP_UHPBU 1
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_AT91C_PQFP_UHPBU
#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
#endif
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000)
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 128 * 1024)
+#define CONFIG_ENV_SIZE (128 * 1024)
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_SYS_LOAD_ADDR 0x21000000
@@ -192,29 +203,33 @@
#define CONFIG_SYS_MAXARGS 32
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
+#define CONFIG_SYS_MALLOC_LEN \
+ ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 4 * 1024)
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
+ GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
#define CONFIG_STACKSIZE (32 * 1024)
+#define CONFIG_STACKSIZE_IRQ (4 * 1024)
+#define CONFIG_STACKSIZE_FIQ (4 * 1024)
+
#if defined(CONFIG_USE_IRQ)
#error CONFIG_USE_IRQ not supported
#endif
-#define CONFIG_DEVICE_NULLDEV 1
-#define CONFIG_SILENT_CONSOLE 1
+#define CONFIG_DEVICE_NULLDEV
+#define CONFIG_SILENT_CONSOLE
-#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT \
"Press SPACE to abort autoboot\n"
#define CONFIG_AUTOBOOT_STOP_STR " "
#define CONFIG_AUTOBOOT_DELAY_STR "d"
-#define CONFIG_VERSION_VARIABLE 1
+#define CONFIG_VERSION_VARIABLE
#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
#define MTDPARTS_DEFAULT \
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index d898b77..4ba3d91 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -297,15 +297,7 @@
#define CONFIG_ENV_IS_IN_NAND 1
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_ENV_OFFSET boot_flash_off
-
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
diff --git a/include/configs/dig297.h b/include/configs/dig297.h
new file mode 100644
index 0000000..7aeb24e
--- /dev/null
+++ b/include/configs/dig297.h
@@ -0,0 +1,311 @@
+/*
+ * (C) Copyright 2011 Comelit Group SpA
+ * Luca Ceresoli <luca.ceresoli@comelit.it>
+ *
+ * Based on omap3_beagle.h:
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the Comelit DIG297 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP /* in a TI OMAP core */
+#define CONFIG_OMAP34XX /* which is a 34XX */
+#define CONFIG_OMAP3430 /* which is in a 3430 */
+
+#define CONFIG_SYS_TEXT_BASE 0x80008000
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+ /* Sector */
+#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* UBI needs >= 512 kB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration: UART3 (ttyO2)
+ */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+#define CONFIG_MMC
+#define CONFIG_OMAP3_MMC
+#define CONFIG_DOS_PARTITION
+
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR
+
+/* library portions to compile in */
+#define CONFIG_RBTREE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_UBI /* UBI Support */
+#define CONFIG_CMD_UBIFS /* UBIFS Support */
+#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:896k(uboot),"\
+ "128k(uboot-env),3m(kernel),252m(ubi)"
+
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_NAND /* NAND support */
+
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#undef CONFIG_CMD_NFS /* NFS support */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER
+#define CONFIG_TWL4030_LED
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
+ /* to access nand */
+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
+ /* to access nand at */
+ /* CS0 */
+#define GPMC_NAND_ECC_LP_x16_LAYOUT
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
+
+#if defined(CONFIG_CMD_NET)
+/*
+ * SMSC9220 Ethernet
+ */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE 0x2C000000
+
+#endif /* (CONFIG_CMD_NET) */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY 1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "console=ttyO2,115200n8\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "partition=nand0,3\0"\
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "nandroot=ubi0:rootfs ro\0" \
+ "nandrootfstype=ubifs\0" \
+ "nfspath=/srv/nfs\0" \
+ "tftpfilename=uImage\0" \
+ "gatewayip=0.0.0.0\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "${mtdparts} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}::off\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "${mtdparts} " \
+ "ubi.mtd=3 " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}::off\0" \
+ "netargs=setenv bootargs console=${console} " \
+ "${mtdparts} " \
+ "root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${nfspath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}::off\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${loadaddr} 100000 300000; " \
+ "bootm ${loadaddr}\0" \
+ "netboot=echo Booting from network ...; " \
+ "run netargs; " \
+ "tftp ${loadaddr} ${serverip}:${tftpfilename}; " \
+ "bootm ${loadaddr}\0" \
+ "resetenv=nand erase e0000 20000\0"\
+
+#define CONFIG_BOOTCOMMAND \
+ "run nandboot"
+
+#define CONFIG_AUTO_COMPLETE
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "DIG297# "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
+ /* works on */
+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
+ 0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
+ /* load address */
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE boot_flash_base
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_ENV_IS_IN_NAND
+#define SMNAND_ENV_OFFSET 0x0E0000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/dkb.h b/include/configs/dkb.h
index 638af5e..b400d0a 100644
--- a/include/configs/dkb.h
+++ b/include/configs/dkb.h
@@ -47,6 +47,7 @@
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_I2C
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
/*
@@ -56,6 +57,7 @@
#include "mv-common.h"
#undef CONFIG_ARCH_MISC_INIT
+
/*
* Environment variables configurations
*/
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index a75f06a..19b6544 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* Based on original Kirkwood support which is
* (C) Copyright 2009
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index d004f31..34bd899 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -46,4 +46,5 @@
#define CONFIG_MACH_TYPE MACH_TYPE_HARMONY
#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
+#define CONFIG_BOARD_EARLY_INIT_F
#endif /* __CONFIG_H */
diff --git a/include/configs/igep0020.h b/include/configs/igep0020.h
index c19ecc0..fc15a9c 100644
--- a/include/configs/igep0020.h
+++ b/include/configs/igep0020.h
@@ -129,14 +129,61 @@
*/
#define CONFIG_TWL4030_POWER 1
-/* Environment information */
-#define CONFIG_BOOTCOMMAND \
- "mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0"
-
#define CONFIG_BOOTDELAY 3
#define CONFIG_EXTRA_ENV_SETTINGS \
- "usbtty=cdc_acm\0"
+ "usbtty=cdc_acm\0" \
+ "loadaddr=0x82000000\0" \
+ "usbtty=cdc_acm\0" \
+ "console=ttyS2,115200n8\0" \
+ "mpurate=500\0" \
+ "vram=12M\0" \
+ "dvimode=1024x768MR-16@60\0" \
+ "defaultdisplay=dvi\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "nandroot=/dev/mtdblock4 rw\0" \
+ "nandrootfstype=jffs2\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "nandboot=echo Booting from onenand ...; " \
+ "run nandargs; " \
+ "onenand read ${loadaddr} 280000 400000; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc rescan ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run nandboot; " \
+ "fi; " \
+ "fi; " \
+ "else run nandboot; fi"
#define CONFIG_AUTO_COMPLETE 1
diff --git a/include/configs/igep0030.h b/include/configs/igep0030.h
index 1325bfa..713b1b9 100644
--- a/include/configs/igep0030.h
+++ b/include/configs/igep0030.h
@@ -127,14 +127,61 @@
*/
#define CONFIG_TWL4030_POWER 1
-/* Environment information */
-#define CONFIG_BOOTCOMMAND \
- "mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0"
-
#define CONFIG_BOOTDELAY 3
#define CONFIG_EXTRA_ENV_SETTINGS \
- "usbtty=cdc_acm\0"
+ "usbtty=cdc_acm\0" \
+ "loadaddr=0x82000000\0" \
+ "usbtty=cdc_acm\0" \
+ "console=ttyS2,115200n8\0" \
+ "mpurate=500\0" \
+ "vram=12M\0" \
+ "dvimode=1024x768MR-16@60\0" \
+ "defaultdisplay=dvi\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "nandroot=/dev/mtdblock4 rw\0" \
+ "nandrootfstype=jffs2\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "nandboot=echo Booting from onenand ...; " \
+ "run nandargs; " \
+ "onenand read ${loadaddr} 280000 400000; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc rescan ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run nandboot; " \
+ "fi; " \
+ "fi; " \
+ "else run nandboot; fi"
#define CONFIG_AUTO_COMPLETE 1
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 5023638..9405f56 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -28,7 +28,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
diff --git a/include/configs/innokom.h b/include/configs/innokom.h
index d8fcbdb..744d65c 100644
--- a/include/configs/innokom.h
+++ b/include/configs/innokom.h
@@ -140,6 +140,8 @@
/*
* I2C bus
*/
+#define CONFIG_I2C_MV 1
+#define CONFIG_MV_I2C_REG 0x40301680
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_SYS_I2C_SLAVE 0xfe
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index d2798e97..5ea59b4 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -22,7 +22,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 86c758f..d4c6d16 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -30,7 +30,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 591d6e1..50caacd 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -33,6 +33,8 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_TEXT_BASE 0x97800000
+
#define CONFIG_L2_OFF
#include <asm/arch/imx-regs.h>
@@ -222,4 +224,7 @@
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_OF_LIBFDT
+#define CONFIG_SYS_BOOTMAPSZ 0x800000
+
#endif
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index f2a5752..6ac910b 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -190,4 +190,7 @@
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_OF_LIBFDT
+#define CONFIG_SYS_BOOTMAPSZ 0x800000
+
#endif /* __CONFIG_H */
diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h
index 49a16ab..758f19d 100644
--- a/include/configs/nhk8815.h
+++ b/include/configs/nhk8815.h
@@ -80,6 +80,11 @@
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
#define PHYS_SDRAM_2 0x08000000 /* SDR-SDRAM BANK #2*/
#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+/* The IPL loads us at 0, tell so to u-boot. Put stack pointer 1M into RAM */
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + (1<<20))
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index a0f6829..bc3c45b 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -101,6 +101,18 @@
#define CONFIG_OMAP_HSMMC 1
#define CONFIG_DOS_PARTITION 1
+/* Status LED */
+#define CONFIG_STATUS_LED 1
+#define CONFIG_BOARD_SPECIFIC_LED 1
+#define STATUS_LED_BIT 0x01
+#define STATUS_LED_STATE STATUS_LED_ON
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT1 0x02
+#define STATUS_LED_STATE1 STATUS_LED_ON
+#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BOOT STATUS_LED_BIT
+#define STATUS_LED_GREEN STATUS_LED_BIT1
+
/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR 1
@@ -114,6 +126,11 @@
#define CONFIG_USB_TTY 1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+/* USB EHCI */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+
/* commands to include */
#include <config_cmd_default.h>
@@ -130,7 +147,9 @@
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_USB_STORAGE /* USB storage support */
#define CONFIG_CMD_NAND /* NAND support */
+#define CONFIG_CMD_LED /* LED support */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
@@ -183,7 +202,7 @@
"loadaddr=0x82000000\0" \
"usbtty=cdc_acm\0" \
"console=ttyS2,115200n8\0" \
- "mpurate=500\0" \
+ "mpurate=auto\0" \
"vram=12M\0" \
"dvimode=1024x768MR-16@60\0" \
"defaultdisplay=dvi\0" \
@@ -208,9 +227,9 @@
"omapdss.def_disp=${defaultdisplay} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source ${loadaddr}\0" \
+ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t $loadaddr $filesize\0" \
"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
@@ -222,15 +241,19 @@
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run nandboot; " \
- "fi; " \
- "fi; " \
- "else run nandboot; fi"
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "run importbootenv;" \
+ "fi;" \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loaduimage; then " \
+ "run mmcboot;" \
+ "fi;" \
+ "fi;" \
+ "run nandboot;" \
#define CONFIG_AUTO_COMPLETE 1
/*
@@ -299,7 +322,9 @@
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_SYS_FLASH_BASE boot_flash_base
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
@@ -309,18 +334,10 @@
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
-#define CONFIG_ENV_OFFSET boot_flash_off
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
-
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 5bdb3fd..5ec079c 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -298,33 +298,31 @@
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_SYS_FLASH_BASE boot_flash_base
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#elif defined(CONFIG_CMD_ONENAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
+#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
+#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+
#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_OMAP_GPMC
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#elif defined(CONFIG_CMD_ONENAND)
#define CONFIG_ENV_IS_IN_ONENAND 1
+#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
#endif
-#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
-#define CONFIG_ENV_OFFSET boot_flash_off
-#define CONFIG_ENV_ADDR boot_flash_env_addr
-
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
/*
* Support for relocation
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 1b3d439..44a6eb7 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -271,7 +271,9 @@
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_SYS_FLASH_BASE boot_flash_base
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
@@ -281,18 +283,10 @@
#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
-#define CONFIG_ENV_OFFSET boot_flash_off
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
-
#if defined(CONFIG_CMD_NET)
/*----------------------------------------------------------------------------
* SMSC9211 Ethernet from SMSC9118 family
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 72b0cc2..7b6883c 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -262,7 +262,9 @@
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_SYS_FLASH_BASE boot_flash_base
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
@@ -270,16 +272,8 @@
#define CONFIG_ENV_IS_IN_NAND 1
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
-#define CONFIG_ENV_OFFSET boot_flash_off
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
-
#endif /* __CONFIG_H */
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index 4708981..5ddf920 100644
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -358,14 +358,4 @@
* - rest for filesystem
*/
-/*--------------------------------------------------------------------------*/
-
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
-
#endif /* __CONFIG_H */
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index f7d0652..2bfda4b 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -285,7 +285,9 @@
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_SYS_FLASH_BASE boot_flash_base
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
@@ -295,16 +297,8 @@
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
-#define CONFIG_ENV_OFFSET boot_flash_off
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
-
#endif /* __CONFIG_H */
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index 7377933..dadca28 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -254,7 +254,9 @@
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_SYS_FLASH_BASE boot_flash_base
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
@@ -262,16 +264,8 @@
#define CONFIG_ENV_IS_IN_NAND 1
#define SMNAND_ENV_OFFSET 0x0c0000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
-#define CONFIG_ENV_OFFSET boot_flash_off
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
-
#endif /* __CONFIG_H */
diff --git a/include/configs/qong.h b/include/configs/qong.h
index e2f7a5e..c61a689 100644
--- a/include/configs/qong.h
+++ b/include/configs/qong.h
@@ -22,7 +22,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
@@ -52,6 +52,7 @@
#define CONFIG_SYS_MX31_UART1 1
#define CONFIG_MXC_GPIO
+#define CONFIG_HW_WATCHDOG
#define CONFIG_MXC_SPI
#define CONFIG_DEFAULT_SPI_BUS 1
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 59eef56..06ce3e2 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -40,4 +40,5 @@
#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
+#define CONFIG_BOARD_EARLY_INIT_F
#endif /* __CONFIG_H */
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
index 4f4374a..2924325 100644
--- a/include/configs/tegra2-common.h
+++ b/include/configs/tegra2-common.h
@@ -33,6 +33,8 @@
#define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */
#define CONFIG_L2_OFF /* No L2 cache */
+#define CONFIG_ENABLE_CORTEXA9 /* enable CPU (A9 complex) */
+
#include <asm/arch/tegra2.h> /* get chip and board defs */
/*
diff --git a/include/configs/xm250.h b/include/configs/xm250.h
index 497cb91..232baf3 100644
--- a/include/configs/xm250.h
+++ b/include/configs/xm250.h
@@ -61,6 +61,8 @@
/*
* I2C bus
*/
+#define CONFIG_I2C_MV 1
+#define CONFIG_MV_I2C_REG 0x40301680
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_SYS_I2C_SLAVE 0xfe
diff --git a/include/faraday/ftpmu010.h b/include/faraday/ftpmu010.h
new file mode 100644
index 0000000..77c29a9
--- /dev/null
+++ b/include/faraday/ftpmu010.h
@@ -0,0 +1,244 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Power Management Unit
+ */
+#ifndef __FTPMU010_H
+#define __FTPMU010_H
+
+#ifndef __ASSEMBLY__
+struct ftpmu010 {
+ unsigned int IDNMBR0; /* 0x00 */
+ unsigned int reserved0; /* 0x04 */
+ unsigned int OSCC; /* 0x08 */
+ unsigned int PMODE; /* 0x0C */
+ unsigned int PMCR; /* 0x10 */
+ unsigned int PED; /* 0x14 */
+ unsigned int PEDSR; /* 0x18 */
+ unsigned int reserved1; /* 0x1C */
+ unsigned int PMSR; /* 0x20 */
+ unsigned int PGSR; /* 0x24 */
+ unsigned int MFPSR; /* 0x28 */
+ unsigned int MISC; /* 0x2C */
+ unsigned int PDLLCR0; /* 0x30 */
+ unsigned int PDLLCR1; /* 0x34 */
+ unsigned int AHBMCLKOFF; /* 0x38 */
+ unsigned int APBMCLKOFF; /* 0x3C */
+ unsigned int DCSRCR0; /* 0x40 */
+ unsigned int DCSRCR1; /* 0x44 */
+ unsigned int DCSRCR2; /* 0x48 */
+ unsigned int SDRAMHTC; /* 0x4C */
+ unsigned int PSPR0; /* 0x50 */
+ unsigned int PSPR1; /* 0x54 */
+ unsigned int PSPR2; /* 0x58 */
+ unsigned int PSPR3; /* 0x5C */
+ unsigned int PSPR4; /* 0x60 */
+ unsigned int PSPR5; /* 0x64 */
+ unsigned int PSPR6; /* 0x68 */
+ unsigned int PSPR7; /* 0x6C */
+ unsigned int PSPR8; /* 0x70 */
+ unsigned int PSPR9; /* 0x74 */
+ unsigned int PSPR10; /* 0x78 */
+ unsigned int PSPR11; /* 0x7C */
+ unsigned int PSPR12; /* 0x80 */
+ unsigned int PSPR13; /* 0x84 */
+ unsigned int PSPR14; /* 0x88 */
+ unsigned int PSPR15; /* 0x8C */
+ unsigned int AHBDMA_RACCS; /* 0x90 */
+ unsigned int reserved2; /* 0x94 */
+ unsigned int reserved3; /* 0x98 */
+ unsigned int JSS; /* 0x9C */
+ unsigned int CFC_RACC; /* 0xA0 */
+ unsigned int SSP1_RACC; /* 0xA4 */
+ unsigned int UART1TX_RACC; /* 0xA8 */
+ unsigned int UART1RX_RACC; /* 0xAC */
+ unsigned int UART2TX_RACC; /* 0xB0 */
+ unsigned int UART2RX_RACC; /* 0xB4 */
+ unsigned int SDC_RACC; /* 0xB8 */
+ unsigned int I2SAC97_RACC; /* 0xBC */
+ unsigned int IRDATX_RACC; /* 0xC0 */
+ unsigned int reserved4; /* 0xC4 */
+ unsigned int USBD_RACC; /* 0xC8 */
+ unsigned int IRDARX_RACC; /* 0xCC */
+ unsigned int IRDA_RACC; /* 0xD0 */
+ unsigned int ED0_RACC; /* 0xD4 */
+ unsigned int ED1_RACC; /* 0xD8 */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * ID Number 0 Register
+ */
+#define FTPMU010_ID_A320A 0x03200000
+#define FTPMU010_ID_A320C 0x03200010
+#define FTPMU010_ID_A320D 0x03200030
+
+/*
+ * OSC Control Register
+ */
+#define FTPMU010_OSCC_OSCH_TRI (1 << 11)
+#define FTPMU010_OSCC_OSCH_STABLE (1 << 9)
+#define FTPMU010_OSCC_OSCH_OFF (1 << 8)
+
+#define FTPMU010_OSCC_OSCL_TRI (1 << 3)
+#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2)
+#define FTPMU010_OSCC_OSCL_STABLE (1 << 1)
+#define FTPMU010_OSCC_OSCL_OFF (1 << 0)
+
+/*
+ * Power Mode Register
+ */
+#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7)
+#define FTPMU010_PMODE_FCS (1 << 2)
+#define FTPMU010_PMODE_TURBO (1 << 1)
+#define FTPMU010_PMODE_SLEEP (1 << 0)
+
+/*
+ * Power Manager Status Register
+ */
+#define FTPMU010_PMSR_SMR (1 << 10)
+
+#define FTPMU010_PMSR_RDH (1 << 2)
+#define FTPMU010_PMSR_PH (1 << 1)
+#define FTPMU010_PMSR_CKEHLOW (1 << 0)
+
+/*
+ * Multi-Function Port Setting Register
+ */
+#define FTPMU010_MFPSR_DEBUGSEL (1 << 17)
+#define FTPMU010_MFPSR_DMA0PINSEL (1 << 16)
+#define FTPMU010_MFPSR_DMA1PINSEL (1 << 15)
+#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14)
+#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13)
+#define FTPMU010_MFPSR_PWM1PINSEL (1 << 11)
+#define FTPMU010_MFPSR_PWM0PINSEL (1 << 10)
+#define FTPMU010_MFPSR_IRDACLKSEL (1 << 9)
+#define FTPMU010_MFPSR_UARTCLKSEL (1 << 8)
+#define FTPMU010_MFPSR_SSPCLKSEL (1 << 6)
+#define FTPMU010_MFPSR_I2SCLKSEL (1 << 5)
+#define FTPMU010_MFPSR_AC97CLKSEL (1 << 4)
+#define FTPMU010_MFPSR_AC97PINSEL (1 << 3)
+#define FTPMU010_MFPSR_TRIAHBDIS (1 << 1)
+#define FTPMU010_MFPSR_TRIAHBDBG (1 << 0)
+
+/*
+ * PLL/DLL Control Register 0
+ * Note:
+ * 1. FTPMU010_PDLLCR0_HCLKOUTDIS:
+ * Datasheet indicated it starts at bit #21 which was wrong.
+ * 2. FTPMU010_PDLLCR0_DLLFRAG:
+ * Datasheet indicated it has 2 bit which was wrong.
+ */
+#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20)
+#define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19)
+#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18)
+#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17)
+#define FTPMU010_PDLLCR0_DLLDIS (1 << 16)
+#define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12)
+#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3)
+#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2)
+#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1)
+#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0)
+
+/*
+ * SDRAM Signal Hold Time Control Register
+ */
+#define FTPMU010_SDRAMHTC_RCLK_DLY(x) (((x) & 0xf) << 28)
+#define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x) (((x) & 0xf) << 24)
+#define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x) (((x) & 0xf) << 20)
+#define FTPMU010_SDRAMHTC_EBICTRL_DCSR (1 << 18)
+#define FTPMU010_SDRAMHTC_EBIDATA_DCSR (1 << 17)
+#define FTPMU010_SDRAMHTC_SDRAMCS_DCSR (1 << 16)
+#define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR (1 << 15)
+#define FTPMU010_SDRAMHTC_CKE_DCSR (1 << 14)
+#define FTPMU010_SDRAMHTC_DQM_DCSR (1 << 13)
+#define FTPMU010_SDRAMHTC_SDCLK_DCSR (1 << 12)
+
+#ifndef __ASSEMBLY__
+void ftpmu010_32768osc_enable(void);
+void ftpmu010_dlldis_disable(void);
+void ftpmu010_sdram_clk_disable(unsigned int cr0);
+#endif
+
+#ifdef __ASSEMBLY__
+#define FTPMU010_IDNMBR0 0x00
+#define FTPMU010_reserved0 0x04
+#define FTPMU010_OSCC 0x08
+#define FTPMU010_PMODE 0x0C
+#define FTPMU010_PMCR 0x10
+#define FTPMU010_PED 0x14
+#define FTPMU010_PEDSR 0x18
+#define FTPMU010_reserved1 0x1C
+#define FTPMU010_PMSR 0x20
+#define FTPMU010_PGSR 0x24
+#define FTPMU010_MFPSR 0x28
+#define FTPMU010_MISC 0x2C
+#define FTPMU010_PDLLCR0 0x30
+#define FTPMU010_PDLLCR1 0x34
+#define FTPMU010_AHBMCLKOFF 0x38
+#define FTPMU010_APBMCLKOFF 0x3C
+#define FTPMU010_DCSRCR0 0x40
+#define FTPMU010_DCSRCR1 0x44
+#define FTPMU010_DCSRCR2 0x48
+#define FTPMU010_SDRAMHTC 0x4C
+#define FTPMU010_PSPR0 0x50
+#define FTPMU010_PSPR1 0x54
+#define FTPMU010_PSPR2 0x58
+#define FTPMU010_PSPR3 0x5C
+#define FTPMU010_PSPR4 0x60
+#define FTPMU010_PSPR5 0x64
+#define FTPMU010_PSPR6 0x68
+#define FTPMU010_PSPR7 0x6C
+#define FTPMU010_PSPR8 0x70
+#define FTPMU010_PSPR9 0x74
+#define FTPMU010_PSPR10 0x78
+#define FTPMU010_PSPR11 0x7C
+#define FTPMU010_PSPR12 0x80
+#define FTPMU010_PSPR13 0x84
+#define FTPMU010_PSPR14 0x88
+#define FTPMU010_PSPR15 0x8C
+#define FTPMU010_AHBDMA_RACCS 0x90
+#define FTPMU010_reserved2 0x94
+#define FTPMU010_reserved3 0x98
+#define FTPMU010_JSS 0x9C
+#define FTPMU010_CFC_RACC 0xA0
+#define FTPMU010_SSP1_RACC 0xA4
+#define FTPMU010_UART1TX_RACC 0xA8
+#define FTPMU010_UART1RX_RACC 0xAC
+#define FTPMU010_UART2TX_RACC 0xB0
+#define FTPMU010_UART2RX_RACC 0xB4
+#define FTPMU010_SDC_RACC 0xB8
+#define FTPMU010_I2SAC97_RACC 0xBC
+#define FTPMU010_IRDATX_RACC 0xC0
+#define FTPMU010_reserved4 0xC4
+#define FTPMU010_USBD_RACC 0xC8
+#define FTPMU010_IRDARX_RACC 0xCC
+#define FTPMU010_IRDA_RACC 0xD0
+#define FTPMU010_ED0_RACC 0xD4
+#define FTPMU010_ED1_RACC 0xD8
+#endif /* __ASSEMBLY__ */
+
+#endif /* __FTPMU010_H */
diff --git a/include/faraday/ftsdmc020.h b/include/faraday/ftsdmc020.h
new file mode 100644
index 0000000..0699772
--- /dev/null
+++ b/include/faraday/ftsdmc020.h
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * SDRAM Controller
+ */
+#ifndef __FTSDMC020_H
+#define __FTSDMC020_H
+
+#define FTSDMC020_OFFSET_TP0 0x00
+#define FTSDMC020_OFFSET_TP1 0x04
+#define FTSDMC020_OFFSET_CR 0x08
+#define FTSDMC020_OFFSET_BANK0_BSR 0x0C
+#define FTSDMC020_OFFSET_BANK1_BSR 0x10
+#define FTSDMC020_OFFSET_BANK2_BSR 0x14
+#define FTSDMC020_OFFSET_BANK3_BSR 0x18
+#define FTSDMC020_OFFSET_BANK4_BSR 0x1C
+#define FTSDMC020_OFFSET_BANK5_BSR 0x20
+#define FTSDMC020_OFFSET_BANK6_BSR 0x24
+#define FTSDMC020_OFFSET_BANK7_BSR 0x28
+#define FTSDMC020_OFFSET_ACR 0x34
+
+/*
+ * Timing Parametet 0 Register
+ */
+#define FTSDMC020_TP0_TCL(x) ((x) & 0x3)
+#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4)
+#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8)
+#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12)
+#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16)
+#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20)
+
+/*
+ * Timing Parametet 1 Register
+ */
+#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff)
+#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16)
+#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20)
+
+/*
+ * Configuration Register
+ */
+#define FTSDMC020_CR_SREF (1 << 0)
+#define FTSDMC020_CR_PWDN (1 << 1)
+#define FTSDMC020_CR_ISMR (1 << 2)
+#define FTSDMC020_CR_IREF (1 << 3)
+#define FTSDMC020_CR_IPREC (1 << 4)
+#define FTSDMC020_CR_REFTYPE (1 << 5)
+
+/*
+ * SDRAM External Bank Base/Size Register
+ */
+#define FTSDMC020_BANK_ENABLE (1 << 28)
+
+#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16)
+
+#define FTSDMC020_BANK_DDW_X4 (0 << 12)
+#define FTSDMC020_BANK_DDW_X8 (1 << 12)
+#define FTSDMC020_BANK_DDW_X16 (2 << 12)
+#define FTSDMC020_BANK_DDW_X32 (3 << 12)
+
+#define FTSDMC020_BANK_DSZ_16M (0 << 8)
+#define FTSDMC020_BANK_DSZ_64M (1 << 8)
+#define FTSDMC020_BANK_DSZ_128M (2 << 8)
+#define FTSDMC020_BANK_DSZ_256M (3 << 8)
+
+#define FTSDMC020_BANK_MBW_8 (0 << 4)
+#define FTSDMC020_BANK_MBW_16 (1 << 4)
+#define FTSDMC020_BANK_MBW_32 (2 << 4)
+
+#define FTSDMC020_BANK_SIZE_1M 0x0
+#define FTSDMC020_BANK_SIZE_2M 0x1
+#define FTSDMC020_BANK_SIZE_4M 0x2
+#define FTSDMC020_BANK_SIZE_8M 0x3
+#define FTSDMC020_BANK_SIZE_16M 0x4
+#define FTSDMC020_BANK_SIZE_32M 0x5
+#define FTSDMC020_BANK_SIZE_64M 0x6
+#define FTSDMC020_BANK_SIZE_128M 0x7
+#define FTSDMC020_BANK_SIZE_256M 0x8
+
+/*
+ * Arbiter Control Register
+ */
+#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f)
+#define FTSDMC020_ACR_TOE (1 << 8)
+
+#endif /* __FTSDMC020_H */
diff --git a/include/faraday/ftsmc020.h b/include/faraday/ftsmc020.h
new file mode 100644
index 0000000..95d9500
--- /dev/null
+++ b/include/faraday/ftsmc020.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Static Memory Controller
+ */
+#ifndef __FTSMC020_H
+#define __FTSMC020_H
+
+#ifndef __ASSEMBLY__
+
+struct ftsmc020 {
+ struct {
+ unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */
+ unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */
+ } bank[4];
+ unsigned int pad[8]; /* 0x20 - 0x3c */
+ unsigned int ssr; /* 0x40 */
+};
+
+void ftsmc020_init(void);
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Memory Bank Configuration Register
+ */
+#define FTSMC020_BANK_ENABLE (1 << 28)
+#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000)
+
+#define FTSMC020_BANK_WPROT (1 << 11)
+
+#define FTSMC020_BANK_SIZE_32K (0xb << 4)
+#define FTSMC020_BANK_SIZE_64K (0xc << 4)
+#define FTSMC020_BANK_SIZE_128K (0xd << 4)
+#define FTSMC020_BANK_SIZE_256K (0xe << 4)
+#define FTSMC020_BANK_SIZE_512K (0xf << 4)
+#define FTSMC020_BANK_SIZE_1M (0x0 << 4)
+#define FTSMC020_BANK_SIZE_2M (0x1 << 4)
+#define FTSMC020_BANK_SIZE_4M (0x2 << 4)
+#define FTSMC020_BANK_SIZE_8M (0x3 << 4)
+#define FTSMC020_BANK_SIZE_16M (0x4 << 4)
+#define FTSMC020_BANK_SIZE_32M (0x5 << 4)
+
+#define FTSMC020_BANK_MBW_8 (0x0 << 0)
+#define FTSMC020_BANK_MBW_16 (0x1 << 0)
+#define FTSMC020_BANK_MBW_32 (0x2 << 0)
+
+/*
+ * Memory Bank Timing Parameter Register
+ */
+#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28)
+#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24)
+#define FTSMC020_TPR_RBE (1 << 20)
+#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18)
+#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16)
+#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12)
+#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8)
+#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6)
+#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4)
+#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0)
+
+#endif /* __FTSMC020_H */
diff --git a/include/faraday/fttmr010.h b/include/faraday/fttmr010.h
new file mode 100644
index 0000000..72abcb3
--- /dev/null
+++ b/include/faraday/fttmr010.h
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Timer
+ */
+#ifndef __FTTMR010_H
+#define __FTTMR010_H
+
+struct fttmr010 {
+ unsigned int timer1_counter; /* 0x00 */
+ unsigned int timer1_load; /* 0x04 */
+ unsigned int timer1_match1; /* 0x08 */
+ unsigned int timer1_match2; /* 0x0c */
+ unsigned int timer2_counter; /* 0x10 */
+ unsigned int timer2_load; /* 0x14 */
+ unsigned int timer2_match1; /* 0x18 */
+ unsigned int timer2_match2; /* 0x1c */
+ unsigned int timer3_counter; /* 0x20 */
+ unsigned int timer3_load; /* 0x24 */
+ unsigned int timer3_match1; /* 0x28 */
+ unsigned int timer3_match2; /* 0x2c */
+ unsigned int cr; /* 0x30 */
+ unsigned int interrupt_state; /* 0x34 */
+ unsigned int interrupt_mask; /* 0x38 */
+};
+
+/*
+ * Timer Control Register
+ */
+#define FTTMR010_TM3_UPDOWN (1 << 11)
+#define FTTMR010_TM2_UPDOWN (1 << 10)
+#define FTTMR010_TM1_UPDOWN (1 << 9)
+#define FTTMR010_TM3_OFENABLE (1 << 8)
+#define FTTMR010_TM3_CLOCK (1 << 7)
+#define FTTMR010_TM3_ENABLE (1 << 6)
+#define FTTMR010_TM2_OFENABLE (1 << 5)
+#define FTTMR010_TM2_CLOCK (1 << 4)
+#define FTTMR010_TM2_ENABLE (1 << 3)
+#define FTTMR010_TM1_OFENABLE (1 << 2)
+#define FTTMR010_TM1_CLOCK (1 << 1)
+#define FTTMR010_TM1_ENABLE (1 << 0)
+
+/*
+ * Timer Interrupt State & Mask Registers
+ */
+#define FTTMR010_TM3_OVERFLOW (1 << 8)
+#define FTTMR010_TM3_MATCH2 (1 << 7)
+#define FTTMR010_TM3_MATCH1 (1 << 6)
+#define FTTMR010_TM2_OVERFLOW (1 << 5)
+#define FTTMR010_TM2_MATCH2 (1 << 4)
+#define FTTMR010_TM2_MATCH1 (1 << 3)
+#define FTTMR010_TM1_OVERFLOW (1 << 2)
+#define FTTMR010_TM1_MATCH2 (1 << 1)
+#define FTTMR010_TM1_MATCH1 (1 << 0)
+
+#endif /* __FTTMR010_H */