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authorHaijun.Zhang <Haijun.Zhang@freescale.com>2014-01-10 13:52:18 +0800
committerYork Sun <yorksun@freescale.com>2014-01-22 08:56:34 -0800
commitd47e3d27078dd7419c41e1f8f56dcc221511dd5d (patch)
tree4c20938c8d78343fd3c97af3959800e1cbdc1c59 /include
parentf7e27cc5ee13aebce4e81fcf908d22d2d55d61e0 (diff)
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esdhc: Detecting 8 bit width before mmc initialization
The upper 4 data signals of esdhc are shared with spi flash. So detect if the upper 4 pins are assigned to esdhc before enable sdhc 8 bit width. Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/T4240QDS.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 5b1ed63..0d43c27 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -167,6 +167,7 @@ unsigned long get_board_ddr_clk(void);
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_BRDCFG5 0x55
#define QIXIS_MUX_SDHC 2
+#define QIXIS_MUX_SDHC_WIDTH8 1
#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
#define CONFIG_SYS_CSPR3_EXT (0xf)
@@ -471,6 +472,8 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_ESDHC_DETECT_QUIRK \
(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
IS_SVR_REV(get_svr(), 1, 0))
+#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
+ (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
#endif
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */