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authorNobuhiro Iwamatsu <iwamatsu@nigauri.org>2007-09-23 01:29:43 +0900
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>2007-09-23 01:29:43 +0900
commitb8685affe614ccf5f4ec66252b30e2e524d18948 (patch)
tree05bc55b8a4a0451e6500f1f52651d81c0f48f012 /include
parent69df3c4da0c93017cceb25a366e794570bd0ed98 (diff)
parent66dcad3a9a53e0766d90e0084123bd8529522fb0 (diff)
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Merge git://www.denx.de/git/u-boot
Conflicts: CREDITS
Diffstat (limited to 'include')
-rw-r--r--include/74xx_7xx.h1
-rw-r--r--include/_exports.h9
-rw-r--r--include/asm-arm/arch-arm720t/hardware.h2
-rw-r--r--include/asm-arm/arch-at91rm9200/AT91RM9200.h139
-rw-r--r--include/asm-arm/arch-davinci/emac_defs.h311
-rw-r--r--include/asm-arm/arch-davinci/emif_defs.h61
-rw-r--r--include/asm-arm/arch-davinci/hardware.h166
-rw-r--r--include/asm-arm/arch-davinci/i2c_defs.h94
-rw-r--r--include/asm-arm/arch-davinci/nand_defs.h161
-rw-r--r--include/asm-arm/arch-lpc2292/hardware.h33
-rw-r--r--include/asm-arm/arch-lpc2292/lpc2292_registers.h (renamed from include/asm-arm/arch-arm720t/lpc2292_registers.h)0
-rw-r--r--include/asm-arm/arch-lpc2292/mmc.h (renamed from include/asm-arm/arch-arm720t/mmc.h)0
-rw-r--r--include/asm-arm/arch-lpc2292/spi.h82
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-rw-r--r--include/asm-arm/mach-types.h69
-rw-r--r--include/asm-m68k/bitops.h39
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-rw-r--r--include/asm-m68k/immap.h242
-rw-r--r--include/asm-m68k/immap_5235.h378
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-rw-r--r--include/configs/FPS860L.h85
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-rw-r--r--include/configs/GTH.h26
-rw-r--r--include/configs/HH405.h97
-rw-r--r--include/configs/HIDDEN_DRAGON.h31
-rw-r--r--include/configs/HMI10.h52
-rw-r--r--include/configs/HUB405.h80
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-rw-r--r--include/configs/M5235EVB.h261
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-rw-r--r--include/configs/M54455EVB.h391
-rw-r--r--include/configs/MBX.h28
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-rw-r--r--include/configs/MPC8548CDS.h397
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-rw-r--r--include/configs/MPC8568MDS.h128
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-rw-r--r--include/configs/MUSENKI.h17
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-rw-r--r--include/configs/pcu_e.h32
-rw-r--r--include/configs/pdnb3.h42
-rw-r--r--include/configs/pf5200.h60
-rw-r--r--include/configs/pleb2.h21
-rw-r--r--include/configs/ppmc7xx.h291
-rw-r--r--include/configs/ppmc8260.h48
-rw-r--r--include/configs/purple.h19
-rw-r--r--include/configs/pxa255_idp.h23
-rw-r--r--include/configs/quantum.h36
-rw-r--r--include/configs/r5200.h55
-rw-r--r--include/configs/rmu.h35
-rw-r--r--include/configs/rsdproto.h30
-rw-r--r--include/configs/sacsng.h76
-rw-r--r--include/configs/sbc2410x.h47
-rw-r--r--include/configs/sbc405.h40
-rw-r--r--include/configs/sbc8240.h39
-rw-r--r--include/configs/sbc8260.h70
-rw-r--r--include/configs/sbc8349.h76
-rw-r--r--include/configs/sbc8560.h53
-rw-r--r--include/configs/sbc8641d.h606
-rw-r--r--include/configs/sc3.h65
-rw-r--r--include/configs/sc520_cdp.h40
-rw-r--r--include/configs/sc520_spunk.h26
-rw-r--r--include/configs/scb9328.h33
-rw-r--r--include/configs/sequoia.h114
-rw-r--r--include/configs/shannon.h23
-rw-r--r--include/configs/smdk2400.h38
-rw-r--r--include/configs/smdk2410.h38
-rw-r--r--include/configs/smmaco4.h77
-rw-r--r--include/configs/sorcery.h62
-rw-r--r--include/configs/spc1920.h48
-rw-r--r--include/configs/spieval.h119
-rw-r--r--include/configs/stxgp3.h72
-rw-r--r--include/configs/stxssa.h232
-rw-r--r--include/configs/stxxtc.h39
-rw-r--r--include/configs/suzaku.h17
-rw-r--r--include/configs/svm_sc8xx.h32
-rw-r--r--include/configs/taihu.h476
-rw-r--r--include/configs/taishan.h63
-rw-r--r--include/configs/tb0229.h28
-rw-r--r--include/configs/trab.h81
-rw-r--r--include/configs/trizepsiv.h325
-rw-r--r--include/configs/uc100.h54
-rw-r--r--include/configs/uc101.h61
-rw-r--r--include/configs/utx8245.h42
-rw-r--r--include/configs/v37.h29
-rw-r--r--include/configs/v38b.h59
-rw-r--r--include/configs/versatile.h25
-rw-r--r--include/configs/virtlab2.h50
-rw-r--r--include/configs/voiceblue.h57
-rw-r--r--include/configs/walnut.h58
-rw-r--r--include/configs/wepep250.h30
-rw-r--r--include/configs/xaeniax.h32
-rw-r--r--include/configs/xm250.h28
-rw-r--r--include/configs/xsengine.h22
-rw-r--r--include/configs/xupv2p.h64
-rw-r--r--include/configs/yosemite.h78
-rw-r--r--include/configs/yucca.h71
-rw-r--r--include/configs/zeus.h382
-rw-r--r--include/configs/zylonite.h33
-rw-r--r--include/da9030.h12
-rw-r--r--include/dataflash.h43
-rw-r--r--include/div64.h (renamed from include/asm-avr32/div64.h)0
-rw-r--r--include/dm9161.h4
-rw-r--r--include/dp83848.h88
-rw-r--r--include/dtt.h8
-rw-r--r--include/exports.h11
-rw-r--r--include/fdt_support.h6
-rw-r--r--include/flash.h5
-rw-r--r--include/ide.h2
-rw-r--r--include/image.h1
-rw-r--r--include/lcd.h4
-rw-r--r--include/led.h45
-rw-r--r--include/libfdt.h10
-rw-r--r--include/libfdt_env.h2
-rw-r--r--include/linux/mtd/nand.h1
-rw-r--r--include/linux/stat.h3
-rw-r--r--include/logbuff.h26
-rw-r--r--include/mk48t59.h2
-rw-r--r--include/mpc512x.h398
-rw-r--r--include/mpc5xx.h43
-rw-r--r--include/mpc5xxx.h1
-rw-r--r--include/mpc8220.h1
-rw-r--r--include/mpc824x.h8
-rw-r--r--include/mpc8260.h18
-rw-r--r--include/mpc83xx.h265
-rw-r--r--include/mpc85xx.h7
-rw-r--r--include/mpc86xx.h2
-rw-r--r--include/mpc8xx.h14
-rw-r--r--include/nand.h1
-rw-r--r--include/net.h42
-rw-r--r--include/pci.h6
-rw-r--r--include/pcmcia.h8
-rw-r--r--include/post.h2
-rw-r--r--include/ppc405.h55
-rw-r--r--include/ppc440.h105
-rw-r--r--include/ppc4xx.h2
-rw-r--r--include/ppc_asm.tmpl104
-rw-r--r--include/radeon.h1984
-rw-r--r--include/s3c2410.h36
-rw-r--r--include/sata.h108
-rw-r--r--include/serial.h4
-rw-r--r--include/sha1.h115
-rw-r--r--include/spartan3.h24
-rw-r--r--include/status_led.h19
-rw-r--r--include/usb.h21
-rw-r--r--include/usb_cdc_acm.h43
-rw-r--r--include/usbdcore.h3
-rw-r--r--include/usbdcore_mpc8xx.h210
-rw-r--r--include/usbdcore_omap1510.h18
-rw-r--r--include/usbdescriptors.h38
477 files changed, 33408 insertions, 8880 deletions
diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h
index ba73bae..4a03cec 100644
--- a/include/74xx_7xx.h
+++ b/include/74xx_7xx.h
@@ -34,6 +34,7 @@
* Exception offsets (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */
+#define _START_OFFSET EXC_OFF_SYS_RESET
/*----------------------------------------------------------------
* l2cr values
diff --git a/include/_exports.h b/include/_exports.h
index 2b8ec3d..af43885 100644
--- a/include/_exports.h
+++ b/include/_exports.h
@@ -14,8 +14,13 @@ EXPORT_FUNC(vprintf)
EXPORT_FUNC(do_reset)
EXPORT_FUNC(getenv)
EXPORT_FUNC(setenv)
+#ifdef CONFIG_HAS_UID
+EXPORT_FUNC(forceenv)
+#endif
EXPORT_FUNC(simple_strtoul)
-#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+EXPORT_FUNC(simple_strtol)
+EXPORT_FUNC(strcmp)
+#if defined(CONFIG_CMD_I2C)
EXPORT_FUNC(i2c_write)
EXPORT_FUNC(i2c_read)
-#endif /* CFG_CMD_I2C */
+#endif
diff --git a/include/asm-arm/arch-arm720t/hardware.h b/include/asm-arm/arch-arm720t/hardware.h
index 1e9cd41..3056ca7 100644
--- a/include/asm-arm/arch-arm720t/hardware.h
+++ b/include/asm-arm/arch-arm720t/hardware.h
@@ -36,8 +36,6 @@
/* include armadillo specific hardware file if there was one */
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* include IntegratorCP/CM720T specific hardware file if there was one */
-#elif defined(CONFIG_LPC2292)
-#include <asm-arm/arch-arm720t/lpc2292_registers.h>
#else
#error No hardware file defined for this configuration
#endif
diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
index 97d4704..0e01005 100644
--- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h
+++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
@@ -27,9 +27,9 @@
typedef volatile unsigned int AT91_REG; /* Hardware register definition */
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
-/******************************************************************************/
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
+/*****************************************************************************/
typedef struct _AT91S_TC
{
AT91_REG TC_CCR; /* Channel Control Register */
@@ -45,24 +45,24 @@ typedef struct _AT91S_TC
AT91_REG TC_IMR; /* Interrupt Mask Register */
} AT91S_TC, *AT91PS_TC;
-#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
-#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */
-#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */
-#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */
-#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */
-#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */
-#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */
-#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */
-#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */
-#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */
-#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */
-#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */
-#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */
-#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */
-
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Usart */
-/******************************************************************************/
+#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
+#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */
+#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */
+#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */
+#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK*/
+#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */
+#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */
+#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */
+
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Usart */
+/*****************************************************************************/
typedef struct _AT91S_USART
{
AT91_REG US_CR; /* Control Register */
@@ -94,9 +94,9 @@ typedef struct _AT91S_USART
AT91_REG US_PTSR; /* PDC Transfer Status Register */
} AT91S_USART, *AT91PS_USART;
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
-/******************************************************************************/
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
+/*****************************************************************************/
typedef struct _AT91S_CKGR
{
AT91_REG CKGR_MOR; /* Main Oscillator Register */
@@ -141,9 +141,9 @@ typedef struct _AT91S_CKGR
#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */
#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
-/******************************************************************************/
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
+/*****************************************************************************/
typedef struct _AT91S_PIO
{
AT91_REG PIO_PER; /* PIO Enable Register */
@@ -184,9 +184,9 @@ typedef struct _AT91S_PIO
} AT91S_PIO, *AT91PS_PIO;
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Debug Unit */
-/******************************************************************************/
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Debug Unit */
+/*****************************************************************************/
typedef struct _AT91S_DBGU
{
AT91_REG DBGU_CR; /* Control Register */
@@ -242,9 +242,9 @@ typedef struct _AT91S_DBGU
#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */
#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */
-/******************************************************************************/
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */
+/*****************************************************************************/
typedef struct _AT91S_SMC2
{
AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */
@@ -267,9 +267,9 @@ typedef struct _AT91S_SMC2
#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */
#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Power Management Controler */
-/******************************************************************************/
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Power Management Controler */
+/*****************************************************************************/
typedef struct _AT91S_PMC
{
AT91_REG PMC_SCER; /* System Clock Enable Register */
@@ -341,9 +341,9 @@ typedef struct _AT91S_PMC
/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/
/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Ethernet MAC */
-/******************************************************************************/
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Ethernet MAC */
+/*****************************************************************************/
typedef struct _AT91S_EMAC
{
AT91_REG EMAC_CTL; /* Network Control Register */
@@ -424,11 +424,11 @@ typedef struct _AT91S_EMAC
#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */
-/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */
+/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register ------- */
#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */
#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */
-/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */
+/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register ------- */
#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */
#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */
@@ -442,7 +442,7 @@ typedef struct _AT91S_EMAC
#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */
-/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
+/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register ------- */
#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */
#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */
@@ -456,8 +456,8 @@ typedef struct _AT91S_EMAC
#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */
#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */
-/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
-/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
+/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register ------- */
+/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register ------ */
/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */
@@ -471,9 +471,9 @@ typedef struct _AT91S_EMAC
#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */
#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
-/******************************************************************************/
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
+/*****************************************************************************/
typedef struct _AT91S_SPI
{
AT91_REG SPI_CR; /* Control Register */
@@ -536,7 +536,7 @@ typedef struct _AT91S_SPI
#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */
/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
-/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register ------- */
/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */
@@ -555,9 +555,9 @@ typedef struct _AT91S_SPI
#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */
#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */
-/******************************************************************************/
-/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */
-/******************************************************************************/
+/*****************************************************************************/
+/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */
+/*****************************************************************************/
typedef struct _AT91S_PDC
{
AT91_REG PDC_RPR; /* Receive Pointer Register */
@@ -692,11 +692,15 @@ typedef struct _AT91S_PDC
#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */
#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */
+#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) /* Pin Controlled by PB3 */
+#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB3 */
+#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) /* Pin Controlled by PB3 */
#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB3 */
#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB4 */
#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */
#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */
#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */
+#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) /* Pin Controlled by PB22 */
#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */
#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */
#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */
@@ -737,19 +741,36 @@ typedef struct _AT91S_PDC
#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */
#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */
-#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */
-#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) /* (AIC) Base Address */
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */
+#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */
+#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */
+#define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFFA00) /* (PIOC) Base Address */
#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */
+#if 0
+#define AT91C_BASE_ST ((AT91PS_ST) 0xFFFFFD00) /* (PMC) Base Address */
+#define AT91C_BASE_RTC ((AT91PS_RTC) 0xFFFFFE00) /* (PMC) Base Address */
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) /* (PMC) Base Address */
+#endif
+
#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */
-#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA4000) /* (TC0) Base Address */
+#if 0
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) /* (TC0) Base Address */
+#define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFB4000) /* (TC0) Base Address */
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) /* (TC0) Base Address */
+#endif
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */
+#define AT91C_BASE_US2 ((AT91PS_USART) 0xFFFC8000) /* (US1) Base Address */
+#define AT91C_BASE_US3 ((AT91PS_USART) 0xFFFCC000) /* (US1) Base Address */
+#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */
+
#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */
-#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */
-#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */
-#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */
#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */
-#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */
-#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */
#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */
#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */
#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */
diff --git a/include/asm-arm/arch-davinci/emac_defs.h b/include/asm-arm/arch-davinci/emac_defs.h
new file mode 100644
index 0000000..0e10116
--- /dev/null
+++ b/include/asm-arm/arch-davinci/emac_defs.h
@@ -0,0 +1,311 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Based on:
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * dm644x_emac.h
+ *
+ * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
+ *
+ * Copyright (C) 2005 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+
+ * Modifications:
+ * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
+ *
+ */
+
+#ifndef _DM644X_EMAC_H_
+#define _DM644X_EMAC_H_
+
+#include <asm/arch/hardware.h>
+
+#define EMAC_BASE_ADDR (0x01c80000)
+#define EMAC_WRAPPER_BASE_ADDR (0x01c81000)
+#define EMAC_WRAPPER_RAM_ADDR (0x01c82000)
+#define EMAC_MDIO_BASE_ADDR (0x01c84000)
+
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
+
+/* Ethernet Min/Max packet size */
+#define EMAC_MIN_ETHERNET_PKT_SIZE 60
+#define EMAC_MAX_ETHERNET_PKT_SIZE 1518
+#define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */
+
+/* Number of RX packet buffers
+ * NOTE: Only 1 buffer supported as of now
+ */
+#define EMAC_MAX_RX_BUFFERS 10
+
+
+/***********************************************
+ ******** Internally used macros ***************
+ ***********************************************/
+
+#define EMAC_CH_TX 1
+#define EMAC_CH_RX 0
+
+/* Each descriptor occupies 4 words, lets start RX desc's at 0 and
+ * reserve space for 64 descriptors max
+ */
+#define EMAC_RX_DESC_BASE 0x0
+#define EMAC_TX_DESC_BASE 0x1000
+
+/* EMAC Teardown value */
+#define EMAC_TEARDOWN_VALUE 0xfffffffc
+
+/* MII Status Register */
+#define MII_STATUS_REG 1
+
+/* Number of statistics registers */
+#define EMAC_NUM_STATS 36
+
+
+/* EMAC Descriptor */
+typedef volatile struct _emac_desc
+{
+ u_int32_t next; /* Pointer to next descriptor in chain */
+ u_int8_t *buffer; /* Pointer to data buffer */
+ u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
+ u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
+} emac_desc;
+
+/* CPPI bit positions */
+#define EMAC_CPPI_SOP_BIT (0x80000000)
+#define EMAC_CPPI_EOP_BIT (0x40000000)
+#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000)
+#define EMAC_CPPI_EOQ_BIT (0x10000000)
+#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000)
+#define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
+
+#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
+
+#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
+#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
+
+#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
+#define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
+
+
+#define MDIO_CONTROL_IDLE (0x80000000)
+#define MDIO_CONTROL_ENABLE (0x40000000)
+#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
+#define MDIO_CONTROL_FAULT (0x80000)
+#define MDIO_USERACCESS0_GO (0x80000000)
+#define MDIO_USERACCESS0_WRITE_READ (0x0)
+#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
+#define MDIO_USERACCESS0_ACK (0x20000000)
+
+/* Ethernet MAC Registers Structure */
+typedef struct {
+ dv_reg TXIDVER;
+ dv_reg TXCONTROL;
+ dv_reg TXTEARDOWN;
+ u_int8_t RSVD0[4];
+ dv_reg RXIDVER;
+ dv_reg RXCONTROL;
+ dv_reg RXTEARDOWN;
+ u_int8_t RSVD1[100];
+ dv_reg TXINTSTATRAW;
+ dv_reg TXINTSTATMASKED;
+ dv_reg TXINTMASKSET;
+ dv_reg TXINTMASKCLEAR;
+ dv_reg MACINVECTOR;
+ u_int8_t RSVD2[12];
+ dv_reg RXINTSTATRAW;
+ dv_reg RXINTSTATMASKED;
+ dv_reg RXINTMASKSET;
+ dv_reg RXINTMASKCLEAR;
+ dv_reg MACINTSTATRAW;
+ dv_reg MACINTSTATMASKED;
+ dv_reg MACINTMASKSET;
+ dv_reg MACINTMASKCLEAR;
+ u_int8_t RSVD3[64];
+ dv_reg RXMBPENABLE;
+ dv_reg RXUNICASTSET;
+ dv_reg RXUNICASTCLEAR;
+ dv_reg RXMAXLEN;
+ dv_reg RXBUFFEROFFSET;
+ dv_reg RXFILTERLOWTHRESH;
+ u_int8_t RSVD4[8];
+ dv_reg RX0FLOWTHRESH;
+ dv_reg RX1FLOWTHRESH;
+ dv_reg RX2FLOWTHRESH;
+ dv_reg RX3FLOWTHRESH;
+ dv_reg RX4FLOWTHRESH;
+ dv_reg RX5FLOWTHRESH;
+ dv_reg RX6FLOWTHRESH;
+ dv_reg RX7FLOWTHRESH;
+ dv_reg RX0FREEBUFFER;
+ dv_reg RX1FREEBUFFER;
+ dv_reg RX2FREEBUFFER;
+ dv_reg RX3FREEBUFFER;
+ dv_reg RX4FREEBUFFER;
+ dv_reg RX5FREEBUFFER;
+ dv_reg RX6FREEBUFFER;
+ dv_reg RX7FREEBUFFER;
+ dv_reg MACCONTROL;
+ dv_reg MACSTATUS;
+ dv_reg EMCONTROL;
+ dv_reg FIFOCONTROL;
+ dv_reg MACCONFIG;
+ dv_reg SOFTRESET;
+ u_int8_t RSVD5[88];
+ dv_reg MACSRCADDRLO;
+ dv_reg MACSRCADDRHI;
+ dv_reg MACHASH1;
+ dv_reg MACHASH2;
+ dv_reg BOFFTEST;
+ dv_reg TPACETEST;
+ dv_reg RXPAUSE;
+ dv_reg TXPAUSE;
+ u_int8_t RSVD6[16];
+ dv_reg RXGOODFRAMES;
+ dv_reg RXBCASTFRAMES;
+ dv_reg RXMCASTFRAMES;
+ dv_reg RXPAUSEFRAMES;
+ dv_reg RXCRCERRORS;
+ dv_reg RXALIGNCODEERRORS;
+ dv_reg RXOVERSIZED;
+ dv_reg RXJABBER;
+ dv_reg RXUNDERSIZED;
+ dv_reg RXFRAGMENTS;
+ dv_reg RXFILTERED;
+ dv_reg RXQOSFILTERED;
+ dv_reg RXOCTETS;
+ dv_reg TXGOODFRAMES;
+ dv_reg TXBCASTFRAMES;
+ dv_reg TXMCASTFRAMES;
+ dv_reg TXPAUSEFRAMES;
+ dv_reg TXDEFERRED;
+ dv_reg TXCOLLISION;
+ dv_reg TXSINGLECOLL;
+ dv_reg TXMULTICOLL;
+ dv_reg TXEXCESSIVECOLL;
+ dv_reg TXLATECOLL;
+ dv_reg TXUNDERRUN;
+ dv_reg TXCARRIERSENSE;
+ dv_reg TXOCTETS;
+ dv_reg FRAME64;
+ dv_reg FRAME65T127;
+ dv_reg FRAME128T255;
+ dv_reg FRAME256T511;
+ dv_reg FRAME512T1023;
+ dv_reg FRAME1024TUP;
+ dv_reg NETOCTETS;
+ dv_reg RXSOFOVERRUNS;
+ dv_reg RXMOFOVERRUNS;
+ dv_reg RXDMAOVERRUNS;
+ u_int8_t RSVD7[624];
+ dv_reg MACADDRLO;
+ dv_reg MACADDRHI;
+ dv_reg MACINDEX;
+ u_int8_t RSVD8[244];
+ dv_reg TX0HDP;
+ dv_reg TX1HDP;
+ dv_reg TX2HDP;
+ dv_reg TX3HDP;
+ dv_reg TX4HDP;
+ dv_reg TX5HDP;
+ dv_reg TX6HDP;
+ dv_reg TX7HDP;
+ dv_reg RX0HDP;
+ dv_reg RX1HDP;
+ dv_reg RX2HDP;
+ dv_reg RX3HDP;
+ dv_reg RX4HDP;
+ dv_reg RX5HDP;
+ dv_reg RX6HDP;
+ dv_reg RX7HDP;
+ dv_reg TX0CP;
+ dv_reg TX1CP;
+ dv_reg TX2CP;
+ dv_reg TX3CP;
+ dv_reg TX4CP;
+ dv_reg TX5CP;
+ dv_reg TX6CP;
+ dv_reg TX7CP;
+ dv_reg RX0CP;
+ dv_reg RX1CP;
+ dv_reg RX2CP;
+ dv_reg RX3CP;
+ dv_reg RX4CP;
+ dv_reg RX5CP;
+ dv_reg RX6CP;
+ dv_reg RX7CP;
+} emac_regs;
+
+/* EMAC Wrapper Registers Structure */
+typedef struct {
+ u_int8_t RSVD0[4100];
+ dv_reg EWCTL;
+ dv_reg EWINTTCNT;
+} ewrap_regs;
+
+
+/* EMAC MDIO Registers Structure */
+typedef struct {
+ dv_reg VERSION;
+ dv_reg CONTROL;
+ dv_reg ALIVE;
+ dv_reg LINK;
+ dv_reg LINKINTRAW;
+ dv_reg LINKINTMASKED;
+ u_int8_t RSVD0[8];
+ dv_reg USERINTRAW;
+ dv_reg USERINTMASKED;
+ dv_reg USERINTMASKSET;
+ dv_reg USERINTMASKCLEAR;
+ u_int8_t RSVD1[80];
+ dv_reg USERACCESS0;
+ dv_reg USERPHYSEL0;
+ dv_reg USERACCESS1;
+ dv_reg USERPHYSEL1;
+} mdio_regs;
+
+int dm644x_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
+int dm644x_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
+
+typedef struct
+{
+ char name[64];
+ int (*init)(int phy_addr);
+ int (*is_phy_connected)(int phy_addr);
+ int (*get_link_speed)(int phy_addr);
+ int (*auto_negotiate)(int phy_addr);
+} phy_t;
+
+#define PHY_LXT972 (0x001378e2)
+int lxt972_is_phy_connected(int phy_addr);
+int lxt972_get_link_speed(int phy_addr);
+int lxt972_init_phy(int phy_addr);
+int lxt972_auto_negotiate(int phy_addr);
+
+#define PHY_DP83848 (0x20005c90)
+int dp83848_is_phy_connected(int phy_addr);
+int dp83848_get_link_speed(int phy_addr);
+int dp83848_init_phy(int phy_addr);
+int dp83848_auto_negotiate(int phy_addr);
+
+#endif /* _DM644X_EMAC_H_ */
diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h
new file mode 100644
index 0000000..646fc77
--- /dev/null
+++ b/include/asm-arm/arch-davinci/emif_defs.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _EMIF_DEFS_H_
+#define _EMIF_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+typedef struct {
+ dv_reg ERCSR;
+ dv_reg AWCCR;
+ dv_reg SDBCR;
+ dv_reg SDRCR;
+ dv_reg AB1CR;
+ dv_reg AB2CR;
+ dv_reg AB3CR;
+ dv_reg AB4CR;
+ dv_reg SDTIMR;
+ dv_reg DDRSR;
+ dv_reg DDRPHYCR;
+ dv_reg DDRPHYSR;
+ dv_reg TOTAR;
+ dv_reg TOTACTR;
+ dv_reg DDRPHYID_REV;
+ dv_reg SDSRETR;
+ dv_reg EIRR;
+ dv_reg EIMR;
+ dv_reg EIMSR;
+ dv_reg EIMCR;
+ dv_reg IOCTRLR;
+ dv_reg IOSTATR;
+ u_int8_t RSVD0[8];
+ dv_reg NANDFCR;
+ dv_reg NANDFSR;
+ u_int8_t RSVD1[8];
+ dv_reg NANDF1ECC;
+ dv_reg NANDF2ECC;
+ dv_reg NANDF3ECC;
+ dv_reg NANDF4ECC;
+} emif_registers;
+
+typedef emif_registers *emifregs;
+#endif
diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h
new file mode 100644
index 0000000..ebcdcfe
--- /dev/null
+++ b/include/asm-arm/arch-davinci/hardware.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Based on:
+ *
+ * -------------------------------------------------------------------------
+ *
+ * linux/include/asm-arm/arch-davinci/hardware.h
+ *
+ * Copyright (C) 2006 Texas Instruments.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <config.h>
+#include <asm/sizes.h>
+
+#define REG(addr) (*(volatile unsigned int *)(addr))
+#define REG_P(addr) ((volatile unsigned int *)(addr))
+
+typedef volatile unsigned int dv_reg;
+typedef volatile unsigned int * dv_reg_p;
+
+/*
+ * Base register addresses
+ */
+#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
+#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
+#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
+#define DAVINCI_UART0_BASE (0x01c20000)
+#define DAVINCI_UART1_BASE (0x01c20400)
+#define DAVINCI_UART2_BASE (0x01c20800)
+#define DAVINCI_I2C_BASE (0x01c21000)
+#define DAVINCI_TIMER0_BASE (0x01c21400)
+#define DAVINCI_TIMER1_BASE (0x01c21800)
+#define DAVINCI_WDOG_BASE (0x01c21c00)
+#define DAVINCI_PWM0_BASE (0x01c22000)
+#define DAVINCI_PWM1_BASE (0x01c22400)
+#define DAVINCI_PWM2_BASE (0x01c22800)
+#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
+#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
+#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
+#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
+#define DAVINCI_SYSTEM_DFT_BASE (0x01c42000)
+#define DAVINCI_ARM_INTC_BASE (0x01c48000)
+#define DAVINCI_IEEE1394_BASE (0x01c60000)
+#define DAVINCI_USB_OTG_BASE (0x01c64000)
+#define DAVINCI_CFC_ATA_BASE (0x01c66000)
+#define DAVINCI_SPI_BASE (0x01c66800)
+#define DAVINCI_GPIO_BASE (0x01c67000)
+#define DAVINCI_UHPI_BASE (0x01c67800)
+#define DAVINCI_VPSS_REGS_BASE (0x01c70000)
+#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01c80000)
+#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01c81000)
+#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01c82000)
+#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01c84000)
+#define DAVINCI_IMCOP_BASE (0x01cc0000)
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01e00000)
+#define DAVINCI_VLYNQ_BASE (0x01e01000)
+#define DAVINCI_MCBSP_BASE (0x01e02000)
+#define DAVINCI_MMC_SD_BASE (0x01e10000)
+#define DAVINCI_MS_BASE (0x01e20000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
+#define DAVINCI_VLYNQ_REMOTE_BASE (0x0c000000)
+
+/* Power and Sleep Controller (PSC) Domains */
+#define DAVINCI_GPSC_ARMDOMAIN 0
+#define DAVINCI_GPSC_DSPDOMAIN 1
+
+#define DAVINCI_LPSC_VPSSMSTR 0
+#define DAVINCI_LPSC_VPSSSLV 1
+#define DAVINCI_LPSC_TPCC 2
+#define DAVINCI_LPSC_TPTC0 3
+#define DAVINCI_LPSC_TPTC1 4
+#define DAVINCI_LPSC_EMAC 5
+#define DAVINCI_LPSC_EMAC_WRAPPER 6
+#define DAVINCI_LPSC_MDIO 7
+#define DAVINCI_LPSC_IEEE1394 8
+#define DAVINCI_LPSC_USB 9
+#define DAVINCI_LPSC_ATA 10
+#define DAVINCI_LPSC_VLYNQ 11
+#define DAVINCI_LPSC_UHPI 12
+#define DAVINCI_LPSC_DDR_EMIF 13
+#define DAVINCI_LPSC_AEMIF 14
+#define DAVINCI_LPSC_MMC_SD 15
+#define DAVINCI_LPSC_MEMSTICK 16
+#define DAVINCI_LPSC_McBSP 17
+#define DAVINCI_LPSC_I2C 18
+#define DAVINCI_LPSC_UART0 19
+#define DAVINCI_LPSC_UART1 20
+#define DAVINCI_LPSC_UART2 21
+#define DAVINCI_LPSC_SPI 22
+#define DAVINCI_LPSC_PWM0 23
+#define DAVINCI_LPSC_PWM1 24
+#define DAVINCI_LPSC_PWM2 25
+#define DAVINCI_LPSC_GPIO 26
+#define DAVINCI_LPSC_TIMER0 27
+#define DAVINCI_LPSC_TIMER1 28
+#define DAVINCI_LPSC_TIMER2 29
+#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
+#define DAVINCI_LPSC_ARM 31
+#define DAVINCI_LPSC_SCR2 32
+#define DAVINCI_LPSC_SCR3 33
+#define DAVINCI_LPSC_SCR4 34
+#define DAVINCI_LPSC_CROSSBAR 35
+#define DAVINCI_LPSC_CFG27 36
+#define DAVINCI_LPSC_CFG3 37
+#define DAVINCI_LPSC_CFG5 38
+#define DAVINCI_LPSC_GEM 39
+#define DAVINCI_LPSC_IMCOP 40
+
+/* Some PSC defines */
+#define PSC_CHP_SHRTSW (0x01c40038)
+#define PSC_GBLCTL (0x01c41010)
+#define PSC_EPCPR (0x01c41070)
+#define PSC_EPCCR (0x01c41078)
+#define PSC_PTCMD (0x01c41120)
+#define PSC_PTSTAT (0x01c41128)
+#define PSC_PDSTAT (0x01c41200)
+#define PSC_PDSTAT1 (0x01c41204)
+#define PSC_PDCTL (0x01c41300)
+#define PSC_PDCTL1 (0x01c41304)
+
+#define PSC_MDCTL_BASE (0x01c41a00)
+#define PSC_MDSTAT_BASE (0x01c41800)
+
+#define VDD3P3V_PWDN (0x01c40048)
+#define UART0_PWREMU_MGMT (0x01c20030)
+
+#define PSC_SILVER_BULLET (0x01c41a20)
+
+/* Some PLL defines */
+#define PLL1_PLLM (0x01c40910)
+#define PLL2_PLLM (0x01c40d10)
+#define PLL2_DIV2 (0x01c40d1c)
+
+/* Miscellania... */
+#define VBPR (0x20000020)
+#define PINMUX0 (0x01c40000)
+#define PINMUX1 (0x01c40004)
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-davinci/i2c_defs.h b/include/asm-arm/arch-davinci/i2c_defs.h
new file mode 100644
index 0000000..2e902e1
--- /dev/null
+++ b/include/asm-arm/arch-davinci/i2c_defs.h
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ *
+ * Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _DAVINCI_I2C_H_
+#define _DAVINCI_I2C_H_
+
+#define I2C_WRITE 0
+#define I2C_READ 1
+
+#define I2C_BASE 0x01c21000
+
+#define I2C_OA (I2C_BASE + 0x00)
+#define I2C_IE (I2C_BASE + 0x04)
+#define I2C_STAT (I2C_BASE + 0x08)
+#define I2C_SCLL (I2C_BASE + 0x0c)
+#define I2C_SCLH (I2C_BASE + 0x10)
+#define I2C_CNT (I2C_BASE + 0x14)
+#define I2C_DRR (I2C_BASE + 0x18)
+#define I2C_SA (I2C_BASE + 0x1c)
+#define I2C_DXR (I2C_BASE + 0x20)
+#define I2C_CON (I2C_BASE + 0x24)
+#define I2C_IV (I2C_BASE + 0x28)
+#define I2C_PSC (I2C_BASE + 0x30)
+
+/* I2C masks */
+
+/* I2C Interrupt Enable Register (I2C_IE): */
+#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */
+#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
+#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
+#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
+#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
+#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C Status Register (I2C_STAT): */
+
+#define I2C_STAT_BB (1 << 12) /* Bus busy */
+#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
+#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
+#define I2C_STAT_AAS (1 << 9) /* Address as slave */
+#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */
+#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
+#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
+#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
+#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
+#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
+
+
+/* I2C Interrupt Code Register (I2C_INTCODE): */
+
+#define I2C_INTCODE_MASK 7
+#define I2C_INTCODE_NONE 0
+#define I2C_INTCODE_AL 1 /* Arbitration lost */
+#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
+#define I2C_INTCODE_ARDY 3 /* Register access ready */
+#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
+#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
+#define I2C_INTCODE_SCD 6 /* Stop condition detect */
+
+
+/* I2C Configuration Register (I2C_CON): */
+
+#define I2C_CON_EN (1 << 5) /* I2C module enable */
+#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */
+#define I2C_CON_MST (1 << 10) /* Master/slave mode */
+#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */
+#define I2C_CON_XA (1 << 8) /* Expand address */
+#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */
+#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */
+
+#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */
+
+#endif
diff --git a/include/asm-arm/arch-davinci/nand_defs.h b/include/asm-arm/arch-davinci/nand_defs.h
new file mode 100644
index 0000000..619bd47
--- /dev/null
+++ b/include/asm-arm/arch-davinci/nand_defs.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts shamelesly stolen from Linux Kernel source tree.
+ *
+ * ------------------------------------------------------------
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _NAND_DEFS_H_
+#define _NAND_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+#define MASK_CLE 0x10
+#define MASK_ALE 0x0a
+
+#define NAND_CE0CLE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x10))
+#define NAND_CE0ALE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x0a))
+#define NAND_CE0DATA ((volatile u_int8_t *)CFG_NAND_BASE)
+
+typedef struct {
+ u_int32_t NRCSR;
+ u_int32_t AWCCR;
+ u_int8_t RSVD0[8];
+ u_int32_t AB1CR;
+ u_int32_t AB2CR;
+ u_int32_t AB3CR;
+ u_int32_t AB4CR;
+ u_int8_t RSVD1[32];
+ u_int32_t NIRR;
+ u_int32_t NIMR;
+ u_int32_t NIMSR;
+ u_int32_t NIMCR;
+ u_int8_t RSVD2[16];
+ u_int32_t NANDFCR;
+ u_int32_t NANDFSR;
+ u_int8_t RSVD3[8];
+ u_int32_t NANDF1ECC;
+ u_int32_t NANDF2ECC;
+ u_int32_t NANDF3ECC;
+ u_int32_t NANDF4ECC;
+ u_int8_t RSVD4[4];
+ u_int32_t IODFTECR;
+ u_int32_t IODFTGCR;
+ u_int8_t RSVD5[4];
+ u_int32_t IODFTMRLR;
+ u_int32_t IODFTMRMR;
+ u_int32_t IODFTMRMSBR;
+ u_int8_t RSVD6[20];
+ u_int32_t MODRNR;
+ u_int8_t RSVD7[76];
+ u_int32_t CE0DATA;
+ u_int32_t CE0ALE;
+ u_int32_t CE0CLE;
+ u_int8_t RSVD8[4];
+ u_int32_t CE1DATA;
+ u_int32_t CE1ALE;
+ u_int32_t CE1CLE;
+ u_int8_t RSVD9[4];
+ u_int32_t CE2DATA;
+ u_int32_t CE2ALE;
+ u_int32_t CE2CLE;
+ u_int8_t RSVD10[4];
+ u_int32_t CE3DATA;
+ u_int32_t CE3ALE;
+ u_int32_t CE3CLE;
+} nand_registers;
+
+typedef volatile nand_registers *nandregs;
+
+#define NAND_READ_START 0x00
+#define NAND_READ_END 0x30
+#define NAND_STATUS 0x70
+
+#ifdef CFG_NAND_HW_ECC
+#define NAND_Ecc_P1e (1 << 0)
+#define NAND_Ecc_P2e (1 << 1)
+#define NAND_Ecc_P4e (1 << 2)
+#define NAND_Ecc_P8e (1 << 3)
+#define NAND_Ecc_P16e (1 << 4)
+#define NAND_Ecc_P32e (1 << 5)
+#define NAND_Ecc_P64e (1 << 6)
+#define NAND_Ecc_P128e (1 << 7)
+#define NAND_Ecc_P256e (1 << 8)
+#define NAND_Ecc_P512e (1 << 9)
+#define NAND_Ecc_P1024e (1 << 10)
+#define NAND_Ecc_P2048e (1 << 11)
+
+#define NAND_Ecc_P1o (1 << 16)
+#define NAND_Ecc_P2o (1 << 17)
+#define NAND_Ecc_P4o (1 << 18)
+#define NAND_Ecc_P8o (1 << 19)
+#define NAND_Ecc_P16o (1 << 20)
+#define NAND_Ecc_P32o (1 << 21)
+#define NAND_Ecc_P64o (1 << 22)
+#define NAND_Ecc_P128o (1 << 23)
+#define NAND_Ecc_P256o (1 << 24)
+#define NAND_Ecc_P512o (1 << 25)
+#define NAND_Ecc_P1024o (1 << 26)
+#define NAND_Ecc_P2048o (1 << 27)
+
+#define TF(v) (v ? 1 : 0)
+
+#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
+#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
+#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
+#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
+#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
+#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
+#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
+#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
+
+#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
+#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
+#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
+#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
+#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
+#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
+#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
+#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
+
+#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
+#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
+#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
+#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
+#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
+#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
+#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
+#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
+
+#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
+#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
+#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
+#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
+#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
+#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
+#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
+#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
+
+#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
+#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-lpc2292/hardware.h b/include/asm-arm/arch-lpc2292/hardware.h
new file mode 100644
index 0000000..fd2b464
--- /dev/null
+++ b/include/asm-arm/arch-lpc2292/hardware.h
@@ -0,0 +1,33 @@
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/*
+ * Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if defined(CONFIG_LPC2292)
+#include <asm-arm/arch-lpc2292/lpc2292_registers.h>
+#else
+#error No hardware file defined for this configuration
+#endif
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-arm720t/lpc2292_registers.h b/include/asm-arm/arch-lpc2292/lpc2292_registers.h
index 5715f3e..5715f3e 100644
--- a/include/asm-arm/arch-arm720t/lpc2292_registers.h
+++ b/include/asm-arm/arch-lpc2292/lpc2292_registers.h
diff --git a/include/asm-arm/arch-arm720t/mmc.h b/include/asm-arm/arch-lpc2292/mmc.h
index e664a5f..e664a5f 100644
--- a/include/asm-arm/arch-arm720t/mmc.h
+++ b/include/asm-arm/arch-lpc2292/mmc.h
diff --git a/include/asm-arm/arch-lpc2292/spi.h b/include/asm-arm/arch-lpc2292/spi.h
new file mode 100644
index 0000000..6ae66e8
--- /dev/null
+++ b/include/asm-arm/arch-lpc2292/spi.h
@@ -0,0 +1,82 @@
+/*
+ This file defines the interface to the lpc22xx SPI module.
+ Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com)
+
+ This file may be included in software not adhering to the GPL.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*/
+
+#ifndef SPI_H
+#define SPI_H
+
+#include <config.h>
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/hardware.h>
+
+#define SPIF 0x80
+
+#define spi_lock() disable_interrupts();
+#define spi_unlock() enable_interrupts();
+
+extern unsigned long spi_flags;
+extern unsigned char spi_idle;
+
+int spi_init(void);
+
+static inline unsigned char spi_read(void)
+{
+ unsigned char b;
+
+ PUT8(S0SPDR, spi_idle);
+ while (!(GET8(S0SPSR) & SPIF));
+ b = GET8(S0SPDR);
+
+ return b;
+}
+
+static inline void spi_write(unsigned char b)
+{
+ PUT8(S0SPDR, b);
+ while (!(GET8(S0SPSR) & SPIF));
+ GET8(S0SPDR); /* this will clear the SPIF bit */
+}
+
+static inline void spi_set_clock(unsigned char clk_value)
+{
+ PUT8(S0SPCCR, clk_value);
+}
+
+static inline void spi_set_cfg(unsigned char phase,
+ unsigned char polarity,
+ unsigned char lsbf)
+{
+ unsigned char v = 0x20; /* master bit set */
+
+ if (phase)
+ v |= 0x08; /* set phase bit */
+ if (polarity) {
+ v |= 0x10; /* set polarity bit */
+ spi_idle = 0xFF;
+ } else {
+ spi_idle = 0x00;
+ }
+ if (lsbf)
+ v |= 0x40; /* set lsbf bit */
+
+ PUT8(S0SPCR, v);
+}
+#endif /* SPI_H */
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index ebda719..9b4da3a 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -592,9 +592,11 @@ typedef void (*ExcpHndlr) (void) ;
#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
+
/*
* USB Device Controller
*/
+#ifndef CONFIG_CPU_MONAHANS
#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
@@ -749,11 +751,28 @@ typedef void (*ExcpHndlr) (void) ;
#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
+#endif /* ! CONFIG_CPU_MONAHANS */
+
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+
+/*
+ * USB Client Controller (incomplete)
+ */
+#define UDCCR __REG(0x40600000)
+#define UDCICR0 __REG(0x40600004)
+#define UDCCIR0 __REG(0x40600008)
+#define UDCISR0 __REG(0x4060000c)
+#define UDCSIR1 __REG(0x40600010)
+#define UDCFNR __REG(0x40600014)
+#define UDCOTGICR __REG(0x40600018)
+#define UDCOTGISR __REG(0x4060001c)
+#define UP2OCR __REG(0x40600020)
+#define UP3OCR __REG(0x40600024)
-#if defined(CONFIG_PXA27X)
/*
* USB Host Controller
*/
+#define OHCI_REGS_BASE 0x4C000000 /* required for ohci driver */
#define UHCREV __REG(0x4C000000)
#define UHCHCON __REG(0x4C000004)
#define UHCCOMS __REG(0x4C000008)
@@ -1269,15 +1288,15 @@ typedef void (*ExcpHndlr) (void) ;
#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
-#define GPLR(x) ((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)
-#define GPDR(x) ((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)
-#define GPSR(x) ((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)
-#define GPCR(x) ((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)
-#define GRER(x) ((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)
-#define GFER(x) ((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)
-#define GEDR(x) ((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)
-#define GAFR(x) ((((x) & 0x7f) < 96) ? _GAFR(x) : \
- ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))
+#define GPLR(x) __REG2(0x40E00000 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GPDR(x) __REG2(0x40E0000C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GPSR(x) __REG2(0x40E00018 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GPCR(x) __REG2(0x40E00024 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GRER(x) __REG2(0x40E00030 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GFER(x) __REG2(0x40E0003C + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GEDR(x) __REG2(0x40E00048 + (((x) & 0x7f) < 96) ? 0:0x100, ((x) & 0x60) >> 3)
+#define GAFR(x) __REG2((((x) & 0x7f) < 96) ? 0x40E00054 : \
+ ((((x) & 0x7f) < 112) ? 0x40E0006C : 0x40E00070),((x) & 0x60) >> 3)
#else
#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
index 7d7888e..f6a5b4f 100644
--- a/include/asm-arm/mach-types.h
+++ b/include/asm-arm/mach-types.h
@@ -736,7 +736,11 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_LN2410SBC 725
#define MACH_TYPE_CB3RUFC 726
#define MACH_TYPE_MP2USB 727
+#define MACH_TYPE_AT91SAM9261EK 848
#define MACH_TYPE_PDNB3 1002
+#define MACH_TYPE_AT91SAM9260EK 1099
+#define MACH_TYPE_AT91RM9200DF 1119
+#define MACH_TYPE_AT91SAM9263EK 1202
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
@@ -9402,6 +9406,71 @@ extern unsigned int __machine_arch_type;
# define machine_is_mp2usb() (0)
#endif
+#ifdef CONFIG_MACH_AT91SAM9261EK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9261EK
+# endif
+# define machine_is_at91sam9261ek() \
+ (machine_arch_type == MACH_TYPE_AT91SAM9261EK)
+#else
+# define machine_is_at91sam9261ek() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9260EK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9260EK
+# endif
+# define machine_is_at91sam9260ek() \
+ (machine_arch_type == MACH_TYPE_AT91SAM9260EK)
+#else
+# define machine_is_at91sam9260ek() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9263EK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9263EK
+# endif
+# define machine_is_at91sam9263ek() \
+ (machine_arch_type == MACH_TYPE_AT91SAM9263EK)
+#else
+# define machine_is_at91sam9263ek() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91RM9200DF
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91RM9200DF
+# endif
+# define machine_is_at91rm9200df() \
+ (machine_arch_type == MACH_TYPE_AT91RM9200DF)
+#else
+# define machine_is_at91rm9200df() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9263EK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9263EK
+# endif
+# define machine_is_at91sam9263ek() \
+ (machine_arch_type == MACH_TYPE_AT91SAM9263EK)
+#else
+# define machine_is_at91sam9263ek() (0)
+#endif
+
/*
* These have not yet been registered
*/
diff --git a/include/asm-m68k/bitops.h b/include/asm-m68k/bitops.h
index 3283714..0f9e8ab 100644
--- a/include/asm-m68k/bitops.h
+++ b/include/asm-m68k/bitops.h
@@ -15,4 +15,43 @@ extern int test_and_set_bit(int nr, volatile void *addr);
extern int test_and_clear_bit(int nr, volatile void *addr);
extern int test_and_change_bit(int nr, volatile void *addr);
+#ifdef __KERNEL__
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+extern __inline__ int ffs(int x)
+{
+ int r = 1;
+
+ if (!x)
+ return 0;
+ if (!(x & 0xffff)) {
+ x >>= 16;
+ r += 16;
+ }
+ if (!(x & 0xff)) {
+ x >>= 8;
+ r += 8;
+ }
+ if (!(x & 0xf)) {
+ x >>= 4;
+ r += 4;
+ }
+ if (!(x & 3)) {
+ x >>= 2;
+ r += 2;
+ }
+ if (!(x & 1)) {
+ x >>= 1;
+ r += 1;
+ }
+ return r;
+}
+#define __ffs(x) (ffs(x) - 1)
+
+#endif /* __KERNEL__ */
+
#endif /* _M68K_BITOPS_H */
diff --git a/include/asm-m68k/byteorder.h b/include/asm-m68k/byteorder.h
index ce613ac..0e2a0ed 100644
--- a/include/asm-m68k/byteorder.h
+++ b/include/asm-m68k/byteorder.h
@@ -1,7 +1,107 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
#ifndef _M68K_BYTEORDER_H
#define _M68K_BYTEORDER_H
#include <asm/types.h>
+
+#ifdef __GNUC__
+#define __sw16(x) \
+ ((__u16)( \
+ (((__u16)(x) & (__u16)0x00ffU) << 8) | \
+ (((__u16)(x) & (__u16)0xff00U) >> 8) ))
+#define __sw32(x) \
+ ((__u32)( \
+ (((__u32)(x)) << 24) | \
+ (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \
+ (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \
+ (((__u32)(x)) >> 24) ))
+
+extern __inline__ unsigned ld_le16(const volatile unsigned short *addr)
+{
+ unsigned result = *addr;
+ return __sw16(result);
+}
+
+extern __inline__ void st_le16(volatile unsigned short *addr,
+ const unsigned val)
+{
+ *addr = __sw16(val);
+}
+
+extern __inline__ unsigned ld_le32(const volatile unsigned *addr)
+{
+ unsigned result = *addr;
+ return __sw32(result);
+}
+
+extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
+{
+ *addr = __sw32(val);
+}
+
+#if 0
+/* alas, egcs sounds like it has a bug in this code that doesn't use the
+ inline asm correctly, and can cause file corruption. Until I hear that
+ it's fixed, I can live without the extra speed. I hope. */
+#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90)
+#if 0
+# define __arch_swab16(x) ld_le16(&x)
+# define __arch_swab32(x) ld_le32(&x)
+#else
+static __inline__ __attribute__ ((const))
+__u16 ___arch__swab16(__u16 value)
+{
+ return __sw16(value);
+}
+
+static __inline__ __attribute__ ((const))
+__u32 ___arch__swab32(__u32 value)
+{
+ return __sw32(value);
+}
+
+#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch__swab16(x) ___arch__swab16(x)
+#endif /* 0 */
+
+#endif
+
+/* The same, but returns converted value from the location pointer by addr. */
+#define __arch__swab16p(addr) ld_le16(addr)
+#define __arch__swab32p(addr) ld_le32(addr)
+
+/* The same, but do the conversion in situ, ie. put the value back to addr. */
+#define __arch__swab16s(addr) st_le16(addr,*addr)
+#define __arch__swab32s(addr) st_le32(addr,*addr)
+#endif
+
+#endif /* __GNUC__ */
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+#define __BYTEORDER_HAS_U64__
+#endif
#include <linux/byteorder/big_endian.h>
-#endif /* _M68K_BYTEORDER_H */
+#endif /* _M68K_BYTEORDER_H */
diff --git a/include/asm-m68k/errno.h b/include/asm-m68k/errno.h
new file mode 100644
index 0000000..ff364b8
--- /dev/null
+++ b/include/asm-m68k/errno.h
@@ -0,0 +1,138 @@
+#ifndef _PPC_ERRNO_H
+#define _PPC_ERRNO_H
+
+#define EPERM 1 /* Operation not permitted */
+#define ENOENT 2 /* No such file or directory */
+#define ESRCH 3 /* No such process */
+#define EINTR 4 /* Interrupted system call */
+#define EIO 5 /* I/O error */
+#define ENXIO 6 /* No such device or address */
+#define E2BIG 7 /* Arg list too long */
+#define ENOEXEC 8 /* Exec format error */
+#define EBADF 9 /* Bad file number */
+#define ECHILD 10 /* No child processes */
+#define EAGAIN 11 /* Try again */
+#define ENOMEM 12 /* Out of memory */
+#define EACCES 13 /* Permission denied */
+#define EFAULT 14 /* Bad address */
+#define ENOTBLK 15 /* Block device required */
+#define EBUSY 16 /* Device or resource busy */
+#define EEXIST 17 /* File exists */
+#define EXDEV 18 /* Cross-device link */
+#define ENODEV 19 /* No such device */
+#define ENOTDIR 20 /* Not a directory */
+#define EISDIR 21 /* Is a directory */
+#define EINVAL 22 /* Invalid argument */
+#define ENFILE 23 /* File table overflow */
+#define EMFILE 24 /* Too many open files */
+#define ENOTTY 25 /* Not a typewriter */
+#define ETXTBSY 26 /* Text file busy */
+#define EFBIG 27 /* File too large */
+#define ENOSPC 28 /* No space left on device */
+#define ESPIPE 29 /* Illegal seek */
+#define EROFS 30 /* Read-only file system */
+#define EMLINK 31 /* Too many links */
+#define EPIPE 32 /* Broken pipe */
+#define EDOM 33 /* Math argument out of domain of func */
+#define ERANGE 34 /* Math result not representable */
+#define EDEADLK 35 /* Resource deadlock would occur */
+#define ENAMETOOLONG 36 /* File name too long */
+#define ENOLCK 37 /* No record locks available */
+#define ENOSYS 38 /* Function not implemented */
+#define ENOTEMPTY 39 /* Directory not empty */
+#define ELOOP 40 /* Too many symbolic links encountered */
+#define EWOULDBLOCK EAGAIN /* Operation would block */
+#define ENOMSG 42 /* No message of desired type */
+#define EIDRM 43 /* Identifier removed */
+#define ECHRNG 44 /* Channel number out of range */
+#define EL2NSYNC 45 /* Level 2 not synchronized */
+#define EL3HLT 46 /* Level 3 halted */
+#define EL3RST 47 /* Level 3 reset */
+#define ELNRNG 48 /* Link number out of range */
+#define EUNATCH 49 /* Protocol driver not attached */
+#define ENOCSI 50 /* No CSI structure available */
+#define EL2HLT 51 /* Level 2 halted */
+#define EBADE 52 /* Invalid exchange */
+#define EBADR 53 /* Invalid request descriptor */
+#define EXFULL 54 /* Exchange full */
+#define ENOANO 55 /* No anode */
+#define EBADRQC 56 /* Invalid request code */
+#define EBADSLT 57 /* Invalid slot */
+#define EDEADLOCK 58 /* File locking deadlock error */
+#define EBFONT 59 /* Bad font file format */
+#define ENOSTR 60 /* Device not a stream */
+#define ENODATA 61 /* No data available */
+#define ETIME 62 /* Timer expired */
+#define ENOSR 63 /* Out of streams resources */
+#define ENONET 64 /* Machine is not on the network */
+#define ENOPKG 65 /* Package not installed */
+#define EREMOTE 66 /* Object is remote */
+#define ENOLINK 67 /* Link has been severed */
+#define EADV 68 /* Advertise error */
+#define ESRMNT 69 /* Srmount error */
+#define ECOMM 70 /* Communication error on send */
+#define EPROTO 71 /* Protocol error */
+#define EMULTIHOP 72 /* Multihop attempted */
+#define EDOTDOT 73 /* RFS specific error */
+#define EBADMSG 74 /* Not a data message */
+#define EOVERFLOW 75 /* Value too large for defined data type */
+#define ENOTUNIQ 76 /* Name not unique on network */
+#define EBADFD 77 /* File descriptor in bad state */
+#define EREMCHG 78 /* Remote address changed */
+#define ELIBACC 79 /* Can not access a needed shared library */
+#define ELIBBAD 80 /* Accessing a corrupted shared library */
+#define ELIBSCN 81 /* .lib section in a.out corrupted */
+#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
+#define ELIBEXEC 83 /* Cannot exec a shared library directly */
+#define EILSEQ 84 /* Illegal byte sequence */
+#define ERESTART 85 /* Interrupted system call should be restarted */
+#define ESTRPIPE 86 /* Streams pipe error */
+#define EUSERS 87 /* Too many users */
+#define ENOTSOCK 88 /* Socket operation on non-socket */
+#define EDESTADDRREQ 89 /* Destination address required */
+#define EMSGSIZE 90 /* Message too long */
+#define EPROTOTYPE 91 /* Protocol wrong type for socket */
+#define ENOPROTOOPT 92 /* Protocol not available */
+#define EPROTONOSUPPORT 93 /* Protocol not supported */
+#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
+#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
+#define EPFNOSUPPORT 96 /* Protocol family not supported */
+#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
+#define EADDRINUSE 98 /* Address already in use */
+#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
+#define ENETDOWN 100 /* Network is down */
+#define ENETUNREACH 101 /* Network is unreachable */
+#define ENETRESET 102 /* Network dropped connection because of reset */
+#define ECONNABORTED 103 /* Software caused connection abort */
+#define ECONNRESET 104 /* Connection reset by peer */
+#define ENOBUFS 105 /* No buffer space available */
+#define EISCONN 106 /* Transport endpoint is already connected */
+#define ENOTCONN 107 /* Transport endpoint is not connected */
+#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
+#define ETOOMANYREFS 109 /* Too many references: cannot splice */
+#define ETIMEDOUT 110 /* Connection timed out */
+#define ECONNREFUSED 111 /* Connection refused */
+#define EHOSTDOWN 112 /* Host is down */
+#define EHOSTUNREACH 113 /* No route to host */
+#define EALREADY 114 /* Operation already in progress */
+#define EINPROGRESS 115 /* Operation now in progress */
+#define ESTALE 116 /* Stale NFS file handle */
+#define EUCLEAN 117 /* Structure needs cleaning */
+#define ENOTNAM 118 /* Not a XENIX named type file */
+#define ENAVAIL 119 /* No XENIX semaphores available */
+#define EISNAM 120 /* Is a named type file */
+#define EREMOTEIO 121 /* Remote I/O error */
+#define EDQUOT 122 /* Quota exceeded */
+
+#define ENOMEDIUM 123 /* No medium found */
+#define EMEDIUMTYPE 124 /* Wrong medium type */
+
+/* Should never be seen by user programs */
+#define ERESTARTSYS 512
+#define ERESTARTNOINTR 513
+#define ERESTARTNOHAND 514 /* restart if no handler.. */
+#define ENOIOCTLCMD 515 /* No ioctl command */
+
+#define _LAST_ERRNO 515
+
+#endif
diff --git a/include/asm-m68k/fec.h b/include/asm-m68k/fec.h
index 5bbbfb2..344c5e1 100644
--- a/include/asm-m68k/fec.h
+++ b/include/asm-m68k/fec.h
@@ -5,6 +5,10 @@
* MPC8xx Communication Processor Module.
* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
*
+ * Add FEC Structure and definitions
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -30,9 +34,9 @@
/* Buffer descriptors used FEC.
*/
typedef struct cpm_buf_desc {
- ushort cbd_sc; /* Status and Control */
- ushort cbd_datlen; /* Data length in buffer */
- uint cbd_bufaddr; /* Buffer address in host memory */
+ ushort cbd_sc; /* Status and Control */
+ ushort cbd_datlen; /* Data length in buffer */
+ uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
@@ -53,28 +57,36 @@ typedef struct cpm_buf_desc {
/* Buffer descriptor control/status used by Ethernet receive.
*/
#define BD_ENET_RX_EMPTY ((ushort)0x8000)
+#define BD_ENET_RX_RO1 ((ushort)0x4000)
#define BD_ENET_RX_WRAP ((ushort)0x2000)
#define BD_ENET_RX_INTR ((ushort)0x1000)
+#define BD_ENET_RX_RO2 BD_ENET_RX_INTR
#define BD_ENET_RX_LAST ((ushort)0x0800)
#define BD_ENET_RX_FIRST ((ushort)0x0400)
#define BD_ENET_RX_MISS ((ushort)0x0100)
+#define BD_ENET_RX_BC ((ushort)0x0080)
+#define BD_ENET_RX_MC ((ushort)0x0040)
#define BD_ENET_RX_LG ((ushort)0x0020)
#define BD_ENET_RX_NO ((ushort)0x0010)
#define BD_ENET_RX_SH ((ushort)0x0008)
#define BD_ENET_RX_CR ((ushort)0x0004)
#define BD_ENET_RX_OV ((ushort)0x0002)
#define BD_ENET_RX_CL ((ushort)0x0001)
+#define BD_ENET_RX_TR BD_ENET_RX_CL
#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
/* Buffer descriptor control/status used by Ethernet transmit.
*/
#define BD_ENET_TX_READY ((ushort)0x8000)
#define BD_ENET_TX_PAD ((ushort)0x4000)
+#define BD_ENET_TX_TO1 BD_ENET_TX_PAD
#define BD_ENET_TX_WRAP ((ushort)0x2000)
#define BD_ENET_TX_INTR ((ushort)0x1000)
+#define BD_ENET_TX_TO2 BD_ENET_TX_INTR_
#define BD_ENET_TX_LAST ((ushort)0x0800)
#define BD_ENET_TX_TC ((ushort)0x0400)
#define BD_ENET_TX_DEF ((ushort)0x0200)
+#define BD_ENET_TX_ABC BD_ENET_TX_DEF
#define BD_ENET_TX_HB ((ushort)0x0100)
#define BD_ENET_TX_LC ((ushort)0x0080)
#define BD_ENET_TX_RL ((ushort)0x0040)
@@ -83,4 +95,261 @@ typedef struct cpm_buf_desc {
#define BD_ENET_TX_CSL ((ushort)0x0001)
#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
-#endif /* fec_h */
+#ifdef CONFIG_MCFFEC
+/*********************************************************************
+*
+* Fast Ethernet Controller (FEC)
+*
+*********************************************************************/
+/* FEC private information */
+struct fec_info_s {
+ int index;
+ u32 iobase;
+ u32 pinmux;
+ u32 miibase;
+ int phy_addr;
+ int dup_spd;
+ char *phy_name;
+ int phyname_init;
+ cbd_t *rxbd; /* Rx BD */
+ cbd_t *txbd; /* Tx BD */
+ uint rxIdx;
+ uint txIdx;
+ char *txbuf;
+ int initialized;
+};
+
+/* Register read/write struct */
+typedef struct fec {
+#ifdef CONFIG_M5272
+ u32 ecr; /* 0x00 */
+ u32 eir; /* 0x04 */
+ u32 eimr; /* 0x08 */
+ u32 ivsr; /* 0x0C */
+ u32 rdar; /* 0x10 */
+ u32 tdar; /* 0x14 */
+ u8 resv1[0x28]; /* 0x18 */
+ u32 mmfr; /* 0x40 */
+ u32 mscr; /* 0x44 */
+ u8 resv2[0x44]; /* 0x48 */
+ u32 frbr; /* 0x8C */
+ u32 frsr; /* 0x90 */
+ u8 resv3[0x10]; /* 0x94 */
+ u32 tfwr; /* 0xA4 */
+ u32 res4; /* 0xA8 */
+ u32 tfsr; /* 0xAC */
+ u8 resv4[0x50]; /* 0xB0 */
+ u32 opd; /* 0x100 - dummy */
+ u32 rcr; /* 0x104 */
+ u32 mibc; /* 0x108 */
+ u8 resv5[0x38]; /* 0x10C */
+ u32 tcr; /* 0x144 */
+ u8 resv6[0x270]; /* 0x148 */
+ u32 iaur; /* 0x3B8 - dummy */
+ u32 ialr; /* 0x3BC - dummy */
+ u32 palr; /* 0x3C0 */
+ u32 paur; /* 0x3C4 */
+ u32 gaur; /* 0x3C8 */
+ u32 galr; /* 0x3CC */
+ u32 erdsr; /* 0x3D0 */
+ u32 etdsr; /* 0x3D4 */
+ u32 emrbr; /* 0x3D8 */
+ u8 resv12[0x74]; /* 0x18C */
+#else
+ u8 resv0[0x4];
+ u32 eir;
+ u32 eimr;
+ u8 resv1[0x4];
+ u32 rdar;
+ u32 tdar;
+ u8 resv2[0xC];
+ u32 ecr;
+ u8 resv3[0x18];
+ u32 mmfr;
+ u32 mscr;
+ u8 resv4[0x1C];
+ u32 mibc;
+ u8 resv5[0x1C];
+ u32 rcr;
+ u8 resv6[0x3C];
+ u32 tcr;
+ u8 resv7[0x1C];
+ u32 palr;
+ u32 paur;
+ u32 opd;
+ u8 resv8[0x28];
+ u32 iaur;
+ u32 ialr;
+ u32 gaur;
+ u32 galr;
+ u8 resv9[0x1C];
+ u32 tfwr;
+ u8 resv10[0x4];
+ u32 frbr;
+ u32 frsr;
+ u8 resv11[0x2C];
+ u32 erdsr;
+ u32 etdsr;
+ u32 emrbr;
+ u8 resv12[0x74];
+#endif
+
+ u32 rmon_t_drop;
+ u32 rmon_t_packets;
+ u32 rmon_t_bc_pkt;
+ u32 rmon_t_mc_pkt;
+ u32 rmon_t_crc_align;
+ u32 rmon_t_undersize;
+ u32 rmon_t_oversize;
+ u32 rmon_t_frag;
+ u32 rmon_t_jab;
+ u32 rmon_t_col;
+ u32 rmon_t_p64;
+ u32 rmon_t_p65to127;
+ u32 rmon_t_p128to255;
+ u32 rmon_t_p256to511;
+ u32 rmon_t_p512to1023;
+ u32 rmon_t_p1024to2047;
+ u32 rmon_t_p_gte2048;
+ u32 rmon_t_octets;
+
+ u32 ieee_t_drop;
+ u32 ieee_t_frame_ok;
+ u32 ieee_t_1col;
+ u32 ieee_t_mcol;
+ u32 ieee_t_def;
+ u32 ieee_t_lcol;
+ u32 ieee_t_excol;
+ u32 ieee_t_macerr;
+ u32 ieee_t_cserr;
+ u32 ieee_t_sqe;
+ u32 ieee_t_fdxfc;
+ u32 ieee_t_octets_ok;
+ u8 resv13[0x8];
+
+ u32 rmon_r_drop;
+ u32 rmon_r_packets;
+ u32 rmon_r_bc_pkt;
+ u32 rmon_r_mc_pkt;
+ u32 rmon_r_crc_align;
+ u32 rmon_r_undersize;
+ u32 rmon_r_oversize;
+ u32 rmon_r_frag;
+ u32 rmon_r_jab;
+ u32 rmon_r_resvd_0;
+ u32 rmon_r_p64;
+ u32 rmon_r_p65to127;
+ u32 rmon_r_p128to255;
+ u32 rmon_r_p256to511;
+ u32 rmon_r_p512to1023;
+ u32 rmon_r_p1024to2047;
+ u32 rmon_r_p_gte2048;
+ u32 rmon_r_octets;
+
+ u32 ieee_r_drop;
+ u32 ieee_r_frame_ok;
+ u32 ieee_r_crc;
+ u32 ieee_r_align;
+ u32 ieee_r_macerr;
+ u32 ieee_r_fdxfc;
+ u32 ieee_r_octets_ok;
+} fec_t;
+
+/*********************************************************************
+* Fast Ethernet Controller (FEC)
+*********************************************************************/
+/* Bit definitions and macros for FEC_EIR */
+#define FEC_EIR_CLEAR_ALL (0xFFF80000)
+#define FEC_EIR_HBERR (0x80000000)
+#define FEC_EIR_BABR (0x40000000)
+#define FEC_EIR_BABT (0x20000000)
+#define FEC_EIR_GRA (0x10000000)
+#define FEC_EIR_TXF (0x08000000)
+#define FEC_EIR_TXB (0x04000000)
+#define FEC_EIR_RXF (0x02000000)
+#define FEC_EIR_RXB (0x01000000)
+#define FEC_EIR_MII (0x00800000)
+#define FEC_EIR_EBERR (0x00400000)
+#define FEC_EIR_LC (0x00200000)
+#define FEC_EIR_RL (0x00100000)
+#define FEC_EIR_UN (0x00080000)
+
+/* Bit definitions and macros for FEC_RDAR */
+#define FEC_RDAR_R_DES_ACTIVE (0x01000000)
+
+/* Bit definitions and macros for FEC_TDAR */
+#define FEC_TDAR_X_DES_ACTIVE (0x01000000)
+
+/* Bit definitions and macros for FEC_ECR */
+#define FEC_ECR_ETHER_EN (0x00000002)
+#define FEC_ECR_RESET (0x00000001)
+
+/* Bit definitions and macros for FEC_MMFR */
+#define FEC_MMFR_DATA(x) (((x)&0xFFFF))
+#define FEC_MMFR_ST(x) (((x)&0x03)<<30)
+#define FEC_MMFR_ST_01 (0x40000000)
+#define FEC_MMFR_OP_RD (0x20000000)
+#define FEC_MMFR_OP_WR (0x10000000)
+#define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
+#define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
+#define FEC_MMFR_TA(x) (((x)&0x03)<<16)
+#define FEC_MMFR_TA_10 (0x00020000)
+
+/* Bit definitions and macros for FEC_MSCR */
+#define FEC_MSCR_DIS_PREAMBLE (0x00000080)
+#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
+
+/* Bit definitions and macros for FEC_MIBC */
+#define FEC_MIBC_MIB_DISABLE (0x80000000)
+#define FEC_MIBC_MIB_IDLE (0x40000000)
+
+/* Bit definitions and macros for FEC_RCR */
+#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
+#define FEC_RCR_FCE (0x00000020)
+#define FEC_RCR_BC_REJ (0x00000010)
+#define FEC_RCR_PROM (0x00000008)
+#define FEC_RCR_MII_MODE (0x00000004)
+#define FEC_RCR_DRT (0x00000002)
+#define FEC_RCR_LOOP (0x00000001)
+
+/* Bit definitions and macros for FEC_TCR */
+#define FEC_TCR_RFC_PAUSE (0x00000010)
+#define FEC_TCR_TFC_PAUSE (0x00000008)
+#define FEC_TCR_FDEN (0x00000004)
+#define FEC_TCR_HBC (0x00000002)
+#define FEC_TCR_GTS (0x00000001)
+
+/* Bit definitions and macros for FEC_PAUR */
+#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
+#define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
+
+/* Bit definitions and macros for FEC_OPD */
+#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
+#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for FEC_TFWR */
+#define FEC_TFWR_X_WMRK(x) ((x)&0x03)
+#define FEC_TFWR_X_WMRK_64 (0x01)
+#define FEC_TFWR_X_WMRK_128 (0x02)
+#define FEC_TFWR_X_WMRK_192 (0x03)
+
+/* Bit definitions and macros for FEC_FRBR */
+#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
+
+/* Bit definitions and macros for FEC_FRSR */
+#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
+
+/* Bit definitions and macros for FEC_ERDSR */
+#define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for FEC_ETDSR */
+#define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for FEC_EMRBR */
+#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4)
+
+#define FEC_RESET_DELAY 100
+#define FEC_RX_TOUT 100
+
+#endif /* CONFIG_MCFFEC */
+#endif /* fec_h */
diff --git a/include/asm-m68k/fsl_i2c.h b/include/asm-m68k/fsl_i2c.h
new file mode 100644
index 0000000..4f71341
--- /dev/null
+++ b/include/asm-m68k/fsl_i2c.h
@@ -0,0 +1,86 @@
+/*
+ * Freescale I2C Controller
+ *
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ *
+ * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
+ * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
+ * and Jeff Brown.
+ * Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_FSL_I2C_H_
+#define _ASM_FSL_I2C_H_
+
+#include <asm/types.h>
+
+typedef struct fsl_i2c {
+
+ u8 adr; /* I2C slave address */
+ u8 res0[3];
+#define I2C_ADR 0xFE
+#define I2C_ADR_SHIFT 1
+#define I2C_ADR_RES ~(I2C_ADR)
+
+ u8 fdr; /* I2C frequency divider register */
+ u8 res1[3];
+#define IC2_FDR 0x3F
+#define IC2_FDR_SHIFT 0
+#define IC2_FDR_RES ~(IC2_FDR)
+
+ u8 cr; /* I2C control redister */
+ u8 res2[3];
+#define I2C_CR_MEN 0x80
+#define I2C_CR_MIEN 0x40
+#define I2C_CR_MSTA 0x20
+#define I2C_CR_MTX 0x10
+#define I2C_CR_TXAK 0x08
+#define I2C_CR_RSTA 0x04
+#define I2C_CR_BCST 0x01
+
+ u8 sr; /* I2C status register */
+ u8 res3[3];
+#define I2C_SR_MCF 0x80
+#define I2C_SR_MAAS 0x40
+#define I2C_SR_MBB 0x20
+#define I2C_SR_MAL 0x10
+#define I2C_SR_BCSTM 0x08
+#define I2C_SR_SRW 0x04
+#define I2C_SR_MIF 0x02
+#define I2C_SR_RXAK 0x01
+
+ u8 dr; /* I2C data register */
+ u8 res4[3];
+#define I2C_DR 0xFF
+#define I2C_DR_SHIFT 0
+#define I2C_DR_RES ~(I2C_DR)
+
+ u8 dfsrr; /* I2C digital filter sampling rate register */
+ u8 res5[3];
+#define I2C_DFSRR 0x3F
+#define I2C_DFSRR_SHIFT 0
+#define I2C_DFSRR_RES ~(I2C_DR)
+
+ /* Fill out the reserved block */
+ u8 res6[0xE8];
+} fsl_i2c_t;
+
+#endif /* _ASM_I2C_H_ */
diff --git a/include/asm-m68k/global_data.h b/include/asm-m68k/global_data.h
index f68352f..9d9894b 100644
--- a/include/asm-m68k/global_data.h
+++ b/include/asm-m68k/global_data.h
@@ -39,6 +39,14 @@ typedef struct global_data {
unsigned long baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
+#ifdef CONFIG_PCI
+ unsigned long pci_clk;
+#endif
+#ifdef CONFIG_EXTRA_CLOCK
+ unsigned long inp_clk;
+ unsigned long vco_clk;
+ unsigned long flb_clk;
+#endif
unsigned long ram_size; /* RAM size */
unsigned long reloc_off; /* Relocation Offset */
unsigned long reset_status; /* reset status register at boot */
diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h
new file mode 100644
index 0000000..ffb9a37
--- /dev/null
+++ b/include/asm-m68k/immap.h
@@ -0,0 +1,242 @@
+/*
+ * ColdFire Internal Memory Map and Defines
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_H
+#define __IMMAP_H
+
+#ifdef CONFIG_M5235
+#include <asm/immap_5235.h>
+#include <asm/m5235.h>
+
+#define CFG_FEC0_IOBASE (MMAP_FEC)
+#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_TMR_BASE (MMAP_DTMR3)
+#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
+#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
+#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
+#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
+#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CFG_UDELAY_BASE (MMAP_PIT0)
+#define CFG_PIT_BASE (MMAP_PIT1)
+#define CFG_PIT_PRESCALE (6)
+#endif
+
+#define CFG_INTR_BASE (MMAP_INTC0)
+#define CFG_NUM_IRQS (128)
+#endif /* CONFIG_M5235 */
+
+#ifdef CONFIG_M5249
+#include <asm/immap_5249.h>
+#include <asm/m5249.h>
+
+#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+#define CFG_INTR_BASE (MMAP_INTC)
+#define CFG_NUM_IRQS (64)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_TMR_BASE (MMAP_DTMR1)
+#define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
+#define CFG_TMRINTR_NO (31)
+#define CFG_TMRINTR_MASK (0x00000400)
+#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
+#define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
+#endif
+#endif /* CONFIG_M5249 */
+
+#ifdef CONFIG_M5253
+#include <asm/immap_5253.h>
+#include <asm/m5249.h>
+#include <asm/m5253.h>
+
+#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+#define CFG_INTR_BASE (MMAP_INTC)
+#define CFG_NUM_IRQS (64)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_TMR_BASE (MMAP_DTMR1)
+#define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
+#define CFG_TMRINTR_NO (27)
+#define CFG_TMRINTR_MASK (0x00000400)
+#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
+#define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
+#endif
+#endif /* CONFIG_M5253 */
+
+#ifdef CONFIG_M5271
+#include <asm/immap_5271.h>
+#include <asm/m5271.h>
+
+#define CFG_FEC0_IOBASE (MMAP_FEC)
+#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_TMR_BASE (MMAP_DTMR3)
+#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
+#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
+#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
+#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI (0) /* Level must include inorder to work */
+#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#define CFG_INTR_BASE (MMAP_INTC0)
+#define CFG_NUM_IRQS (128)
+#endif /* CONFIG_M5271 */
+
+#ifdef CONFIG_M5272
+#include <asm/immap_5272.h>
+#include <asm/m5272.h>
+
+#define CFG_FEC0_IOBASE (MMAP_FEC)
+#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+#define CFG_INTR_BASE (MMAP_INTC)
+#define CFG_NUM_IRQS (64)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE (MMAP_TMR0)
+#define CFG_TMR_BASE (MMAP_TMR3)
+#define CFG_TMRPND_REG (((volatile intctrl_t *)(CFG_INTR_BASE))->int_isr)
+#define CFG_TMRINTR_NO (INT_TMR3)
+#define CFG_TMRINTR_MASK (INT_ISR_INT24)
+#define CFG_TMRINTR_PEND (0)
+#define CFG_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
+#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+#endif /* CONFIG_M5272 */
+
+#ifdef CONFIG_M5282
+#include <asm/immap_5282.h>
+#include <asm/m5282.h>
+
+#define CFG_FEC0_IOBASE (MMAP_FEC)
+#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+#define CFG_INTR_BASE (MMAP_INTC0)
+#define CFG_NUM_IRQS (128)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_TMR_BASE (MMAP_DTMR3)
+#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
+#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
+#define CFG_TMRINTR_MASK (1 << INT0_LO_DTMR3)
+#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
+#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+#endif /* CONFIG_M5282 */
+
+#ifdef CONFIG_M5329
+#include <asm/immap_5329.h>
+#include <asm/m5329.h>
+
+#define CFG_FEC0_IOBASE (MMAP_FEC)
+#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
+#define CFG_MCFRTC_BASE (MMAP_RTC)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_TMR_BASE (MMAP_DTMR1)
+#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
+#define CFG_TMRINTR_NO (INT0_HI_DTMR1)
+#define CFG_TMRINTR_MASK (INTC_IPRH_INT33)
+#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI (6)
+#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CFG_UDELAY_BASE (MMAP_PIT0)
+#define CFG_PIT_BASE (MMAP_PIT1)
+#define CFG_PIT_PRESCALE (6)
+#endif
+
+#define CFG_INTR_BASE (MMAP_INTC0)
+#define CFG_NUM_IRQS (128)
+#endif /* CONFIG_M5329 */
+
+#ifdef CONFIG_M54455
+#include <asm/immap_5445x.h>
+#include <asm/m5445x.h>
+
+#define CFG_FEC0_IOBASE (MMAP_FEC0)
+#define CFG_FEC1_IOBASE (MMAP_FEC1)
+
+#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
+
+#define CFG_MCFRTC_BASE (MMAP_RTC)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_TMR_BASE (MMAP_DTMR1)
+#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
+#define CFG_TMRINTR_NO (INT0_HI_DTMR1)
+#define CFG_TMRINTR_MASK (INTC_IPRH_INT33)
+#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI (6)
+#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CFG_UDELAY_BASE (MMAP_PIT0)
+#define CFG_PIT_BASE (MMAP_PIT1)
+#define CFG_PIT_PRESCALE (6)
+#endif
+
+#define CFG_INTR_BASE (MMAP_INTC0)
+#define CFG_NUM_IRQS (128)
+
+#ifdef CONFIG_PCI
+#define CFG_PCI_BAR0 CFG_SDRAM_BASE
+#define CFG_PCI_BAR4 CFG_SDRAM_BASE
+#define CFG_PCI_TBATR0 (CFG_SDRAM_BASE)
+#define CFG_PCI_TBATR4 (CFG_SDRAM_BASE)
+#endif
+#endif /* CONFIG_M54455 */
+
+#endif /* __IMMAP_H */
diff --git a/include/asm-m68k/immap_5235.h b/include/asm-m68k/immap_5235.h
new file mode 100644
index 0000000..4a03450
--- /dev/null
+++ b/include/asm-m68k/immap_5235.h
@@ -0,0 +1,378 @@
+/*
+ * MCF5329 Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5235__
+#define __IMMAP_5235__
+
+#define MMAP_SCM (CFG_MBAR + 0x00000000)
+#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_MBAR + 0x00000080)
+#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
+#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
+#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
+#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
+#define MMAP_UART0 (CFG_MBAR + 0x00000200)
+#define MMAP_UART1 (CFG_MBAR + 0x00000240)
+#define MMAP_UART2 (CFG_MBAR + 0x00000280)
+#define MMAP_I2C (CFG_MBAR + 0x00000300)
+#define MMAP_QSPI (CFG_MBAR + 0x00000340)
+#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
+#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
+#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
+#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
+#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
+#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
+#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
+#define MMAP_FEC (CFG_MBAR + 0x00001000)
+#define MMAP_FECFIFO (CFG_MBAR + 0x00001400)
+#define MMAP_GPIO (CFG_MBAR + 0x00100000)
+#define MMAP_CCM (CFG_MBAR + 0x00110000)
+#define MMAP_PLL (CFG_MBAR + 0x00120000)
+#define MMAP_EPORT (CFG_MBAR + 0x00130000)
+#define MMAP_WDOG (CFG_MBAR + 0x00140000)
+#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
+#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
+#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
+#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
+#define MMAP_MDHA (CFG_MBAR + 0x00190000)
+#define MMAP_RNG (CFG_MBAR + 0x001A0000)
+#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
+#define MMAP_CAN1 (CFG_MBAR + 0x001C0000)
+#define MMAP_ETPU (CFG_MBAR + 0x001D0000)
+#define MMAP_CAN2 (CFG_MBAR + 0x001F0000)
+
+/* System Control Module register */
+typedef struct scm_ctrl {
+ u32 ipsbar; /* 0x00 - MBAR */
+ u32 res1; /* 0x04 */
+ u32 rambar; /* 0x08 - RAMBAR */
+ u32 res2; /* 0x0C */
+ u8 crsr; /* 0x10 Core Reset Status Register */
+ u8 cwcr; /* 0x11 Core Watchdog Control Register */
+ u8 lpicr; /* 0x12 Low-Power Interrupt Control Register */
+ u8 cwsr; /* 0x13 Core Watchdog Service Register */
+ u32 dmareqc; /* 0x14 */
+ u32 res3; /* 0x18 */
+ u32 mpark; /* 0x1C */
+ u8 mpr; /* 0x20 */
+ u8 res4[3]; /* 0x21 - 0x23 */
+ u8 pacr0; /* 0x24 */
+ u8 pacr1; /* 0x25 */
+ u8 pacr2; /* 0x26 */
+ u8 pacr3; /* 0x27 */
+ u8 pacr4; /* 0x28 */
+ u32 res5; /* 0x29 */
+ u8 pacr5; /* 0x2a */
+ u8 pacr6; /* 0x2b */
+ u8 pacr7; /* 0x2c */
+ u32 res6; /* 0x2d */
+ u8 pacr8; /* 0x2e */
+ u32 res7; /* 0x2f */
+ u8 gpacr; /* 0x30 */
+ u8 res8[3]; /* 0x31 - 0x33 */
+} scm_t;
+
+/* SDRAM controller registers */
+typedef struct sdram_ctrl {
+ u16 dcr; /* 0x00 Control register */
+ u16 res1[3]; /* 0x02 - 0x07 */
+ u32 dacr0; /* 0x08 address and control register 0 */
+ u32 dmr0; /* 0x0C mask register block 0 */
+ u32 dacr1; /* 0x10 address and control register 1 */
+ u32 dmr1; /* 0x14 mask register block 1 */
+} sdram_t;
+
+/* Flexbus module Chip select registers */
+typedef struct fbcs_ctrl {
+ u16 csar0; /* 0x00 Chip-Select Address Register 0 */
+ u16 res0;
+ u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
+ u16 res1; /* 0x08 */
+ u16 cscr0; /* 0x0A Chip-Select Control Register 0 */
+
+ u16 csar1; /* 0x0C Chip-Select Address Register 1 */
+ u16 res2;
+ u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
+ u16 res3; /* 0x14 */
+ u16 cscr1; /* 0x16 Chip-Select Control Register 1 */
+
+ u16 csar2; /* 0x18 Chip-Select Address Register 2 */
+ u16 res4;
+ u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
+ u16 res5; /* 0x20 */
+ u16 cscr2; /* 0x22 Chip-Select Control Register 2 */
+
+ u16 csar3; /* 0x24 Chip-Select Address Register 3 */
+ u16 res6;
+ u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
+ u16 res7; /* 0x2C */
+ u16 cscr3; /* 0x2E Chip-Select Control Register 3 */
+
+ u16 csar4; /* 0x30 Chip-Select Address Register 4 */
+ u16 res8;
+ u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
+ u16 res9; /* 0x38 */
+ u16 cscr4; /* 0x3A Chip-Select Control Register 4 */
+
+ u16 csar5; /* 0x3C Chip-Select Address Register 5 */
+ u16 res10;
+ u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
+ u16 res11; /* 0x44 */
+ u16 cscr5; /* 0x46 Chip-Select Control Register 5 */
+
+ u16 csar6; /* 0x48 Chip-Select Address Register 5 */
+ u16 res12;
+ u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */
+ u16 res13; /* 0x50 */
+ u16 cscr6; /* 0x52 Chip-Select Control Register 5 */
+
+ u16 csar7; /* 0x54 Chip-Select Address Register 5 */
+ u16 res14;
+ u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */
+ u16 res15; /* 0x5C */
+ u16 cscr7; /* 0x5E Chip-Select Control Register 5 */
+} fbcs_t;
+
+/* QSPI module registers */
+typedef struct qspi_ctrl {
+ u16 qmr; /* Mode register */
+ u16 res1;
+ u16 qdlyr; /* Delay register */
+ u16 res2;
+ u16 qwr; /* Wrap register */
+ u16 res3;
+ u16 qir; /* Interrupt register */
+ u16 res4;
+ u16 qar; /* Address register */
+ u16 res5;
+ u16 qdr; /* Data register */
+ u16 res6;
+} qspi_t;
+
+/* Interrupt module registers */
+typedef struct int0_ctrl {
+ /* Interrupt Controller 0 */
+ u32 iprh0; /* 0x00 Pending Register High */
+ u32 iprl0; /* 0x04 Pending Register Low */
+ u32 imrh0; /* 0x08 Mask Register High */
+ u32 imrl0; /* 0x0C Mask Register Low */
+ u32 frch0; /* 0x10 Force Register High */
+ u32 frcl0; /* 0x14 Force Register Low */
+ u8 irlr; /* 0x18 */
+ u8 iacklpr; /* 0x19 */
+ u16 res1[19]; /* 0x1a - 0x3c */
+ u8 icr0[64]; /* 0x40 - 0x7F Control registers */
+ u32 res3[24]; /* 0x80 - 0xDF */
+ u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
+ u8 res4[3]; /* 0xE1 - 0xE3 */
+ u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
+ u8 res5[3]; /* 0xE5 - 0xE7 */
+ u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
+ u8 res6[3]; /* 0xE9 - 0xEB */
+ u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
+ u8 res7[3]; /* 0xED - 0xEF */
+ u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
+ u8 res8[3]; /* 0xF1 - 0xF3 */
+ u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
+ u8 res9[3]; /* 0xF5 - 0xF7 */
+ u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
+ u8 resa[3]; /* 0xF9 - 0xFB */
+ u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
+ u8 resb[3]; /* 0xFD - 0xFF */
+} int0_t;
+
+typedef struct int1_ctrl {
+ /* Interrupt Controller 1 */
+ u32 iprh1; /* 0x00 Pending Register High */
+ u32 iprl1; /* 0x04 Pending Register Low */
+ u32 imrh1; /* 0x08 Mask Register High */
+ u32 imrl1; /* 0x0C Mask Register Low */
+ u32 frch1; /* 0x10 Force Register High */
+ u32 frcl1; /* 0x14 Force Register Low */
+ u8 irlr; /* 0x18 */
+ u8 iacklpr; /* 0x19 */
+ u16 res1[19]; /* 0x1a - 0x3c */
+ u8 icr1[64]; /* 0x40 - 0x7F */
+ u32 res4[24]; /* 0x80 - 0xDF */
+ u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
+ u8 res5[3]; /* 0xE1 - 0xE3 */
+ u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
+ u8 res6[3]; /* 0xE5 - 0xE7 */
+ u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
+ u8 res7[3]; /* 0xE9 - 0xEB */
+ u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
+ u8 res8[3]; /* 0xED - 0xEF */
+ u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
+ u8 res9[3]; /* 0xF1 - 0xF3 */
+ u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
+ u8 resa[3]; /* 0xF5 - 0xF7 */
+ u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
+ u8 resb[3]; /* 0xF9 - 0xFB */
+ u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
+ u8 resc[3]; /* 0xFD - 0xFF */
+} int1_t;
+
+typedef struct intgack_ctrl1 {
+ /* Global IACK Registers */
+ u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */
+ u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
+} intgack_t;
+
+/* GPIO port registers */
+typedef struct gpio_ctrl {
+ /* Port Output Data Registers */
+ u8 podr_addr; /* 0x00 */
+ u8 podr_datah; /* 0x01 */
+ u8 podr_datal; /* 0x02 */
+ u8 podr_busctl; /* 0x03 */
+ u8 podr_bs; /* 0x04 */
+ u8 podr_cs; /* 0x05 */
+ u8 podr_sdram; /* 0x06 */
+ u8 podr_feci2c; /* 0x07 */
+ u8 podr_uarth; /* 0x08 */
+ u8 podr_uartl; /* 0x09 */
+ u8 podr_qspi; /* 0x0A */
+ u8 podr_timer; /* 0x0B */
+ u8 podr_etpu; /* 0x0C */
+ u8 res1[3]; /* 0x0D - 0x0F */
+
+ /* Port Data Direction Registers */
+ u8 pddr_addr; /* 0x10 */
+ u8 pddr_datah; /* 0x11 */
+ u8 pddr_datal; /* 0x12 */
+ u8 pddr_busctl; /* 0x13 */
+ u8 pddr_bs; /* 0x14 */
+ u8 pddr_cs; /* 0x15 */
+ u8 pddr_sdram; /* 0x16 */
+ u8 pddr_feci2c; /* 0x17 */
+ u8 pddr_uarth; /* 0x18 */
+ u8 pddr_uartl; /* 0x19 */
+ u8 pddr_qspi; /* 0x1A */
+ u8 pddr_timer; /* 0x1B */
+ u8 pddr_etpu; /* 0x1C */
+ u8 res2[3]; /* 0x1D - 0x1F */
+
+ /* Port Data Direction Registers */
+ u8 ppdsdr_addr; /* 0x20 */
+ u8 ppdsdr_datah; /* 0x21 */
+ u8 ppdsdr_datal; /* 0x22 */
+ u8 ppdsdr_busctl; /* 0x23 */
+ u8 ppdsdr_bs; /* 0x24 */
+ u8 ppdsdr_cs; /* 0x25 */
+ u8 ppdsdr_sdram; /* 0x26 */
+ u8 ppdsdr_feci2c; /* 0x27 */
+ u8 ppdsdr_uarth; /* 0x28 */
+ u8 ppdsdr_uartl; /* 0x29 */
+ u8 ppdsdr_qspi; /* 0x2A */
+ u8 ppdsdr_timer; /* 0x2B */
+ u8 ppdsdr_etpu; /* 0x2C */
+ u8 res3[3]; /* 0x2D - 0x2F */
+
+ /* Port Clear Output Data Registers */
+ u8 pclrr_addr; /* 0x30 */
+ u8 pclrr_datah; /* 0x31 */
+ u8 pclrr_datal; /* 0x32 */
+ u8 pclrr_busctl; /* 0x33 */
+ u8 pclrr_bs; /* 0x34 */
+ u8 pclrr_cs; /* 0x35 */
+ u8 pclrr_sdram; /* 0x36 */
+ u8 pclrr_feci2c; /* 0x37 */
+ u8 pclrr_uarth; /* 0x38 */
+ u8 pclrr_uartl; /* 0x39 */
+ u8 pclrr_qspi; /* 0x3A */
+ u8 pclrr_timer; /* 0x3B */
+ u8 pclrr_etpu; /* 0x3C */
+ u8 res4[3]; /* 0x3D - 0x3F */
+
+ /* Pin Assignment Registers */
+ u8 par_ad; /* 0x40 */
+ u8 res5; /* 0x41 */
+ u16 par_busctl; /* 0x42 */
+ u8 par_bs; /* 0x44 */
+ u8 par_cs; /* 0x45 */
+ u8 par_sdram; /* 0x46 */
+ u8 par_feci2c; /* 0x47 */
+ u16 par_uart; /* 0x48 */
+ u8 par_qspi; /* 0x4A */
+ u8 res6; /* 0x4B */
+ u16 par_timer; /* 0x4C */
+ u8 par_etpu; /* 0x4E */
+ u8 res7; /* 0x4F */
+
+ /* Drive Strength Control Registers */
+ u8 dscr_eim; /* 0x50 */
+ u8 dscr_etpu; /* 0x51 */
+ u8 dscr_feci2c; /* 0x52 */
+ u8 dscr_uart; /* 0x53 */
+ u8 dscr_qspi; /* 0x54 */
+ u8 dscr_timer; /* 0x55 */
+ u16 res8; /* 0x56 */
+} gpio_t;
+
+/*Chip configuration module registers */
+typedef struct ccm_ctrl {
+ u8 rcr; /* 0x01 */
+ u8 rsr; /* 0x02 */
+ u16 res1; /* 0x03 */
+ u16 ccr; /* 0x04 Chip configuration register */
+ u16 lpcr; /* 0x06 Low-power Control register */
+ u16 rcon; /* 0x08 Rreset configuration register */
+ u16 cir; /* 0x0a Chip identification register */
+} ccm_t;
+
+/* Clock Module registers */
+typedef struct pll_ctrl {
+ u32 syncr; /* 0x00 synthesizer control register */
+ u32 synsr; /* 0x04 synthesizer status register */
+} pll_t;
+
+/* Watchdog registers */
+typedef struct wdog_ctrl {
+ u16 cr; /* 0x00 Control register */
+ u16 mr; /* 0x02 Modulus register */
+ u16 cntr; /* 0x04 Count register */
+ u16 sr; /* 0x06 Service register */
+} wdog_t;
+
+/* FlexCan module registers */
+typedef struct can_ctrl {
+ u32 mcr; /* 0x00 Module Configuration register */
+ u32 ctrl; /* 0x04 Control register */
+ u32 timer; /* 0x08 Free Running Timer */
+ u32 res1; /* 0x0C */
+ u32 rxgmask; /* 0x10 Rx Global Mask */
+ u32 rx14mask; /* 0x14 RxBuffer 14 Mask */
+ u32 rx15mask; /* 0x18 RxBuffer 15 Mask */
+ u32 errcnt; /* 0x1C Error Counter Register */
+ u32 errstat; /* 0x20 Error and status Register */
+ u32 res2; /* 0x24 */
+ u32 imask; /* 0x28 Interrupt Mask Register */
+ u32 res3; /* 0x2C */
+ u32 iflag; /* 0x30 Interrupt Flag Register */
+ u32 res4[19]; /* 0x34 - 0x7F */
+ u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */
+} can_t;
+
+#endif /* __IMMAP_5235__ */
diff --git a/include/asm-m68k/immap_5249.h b/include/asm-m68k/immap_5249.h
index a2c1271..6c6fbcc 100644
--- a/include/asm-m68k/immap_5249.h
+++ b/include/asm-m68k/immap_5249.h
@@ -25,19 +25,11 @@
#ifndef __IMMAP_5249__
#define __IMMAP_5249__
-/* Timer module registers
- */
-typedef struct timer_ctrl {
- ushort timer_tmr;
- ushort res1;
- ushort timer_trr;
- ushort res2;
- ushort timer_tcap;
- ushort res3;
- ushort timer_tcn;
- ushort res4;
- ushort timer_ter;
- uchar res5[14];
-} timer_t;
+#define MMAP_INTC (CFG_MBAR + 0x00000040)
+#define MMAP_DTMR0 (CFG_MBAR + 0x00000140)
+#define MMAP_DTMR1 (CFG_MBAR + 0x00000180)
+#define MMAP_UART0 (CFG_MBAR + 0x000001C0)
+#define MMAP_UART1 (CFG_MBAR + 0x00000200)
+#define MMAP_QSPI (CFG_MBAR + 0x00000400)
-#endif /* __IMMAP_5249__ */
+#endif /* __IMMAP_5249__ */
diff --git a/include/asm-m68k/immap_5253.h b/include/asm-m68k/immap_5253.h
new file mode 100644
index 0000000..aafbdd0
--- /dev/null
+++ b/include/asm-m68k/immap_5253.h
@@ -0,0 +1,95 @@
+/*
+ * MCF5253 Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5249__
+#define __IMMAP_5249__
+
+#define MMAP_INTC (CFG_MBAR + 0x00000040)
+#define MMAP_DTMR0 (CFG_MBAR + 0x00000140)
+#define MMAP_DTMR1 (CFG_MBAR + 0x00000180)
+#define MMAP_UART0 (CFG_MBAR + 0x000001C0)
+#define MMAP_UART1 (CFG_MBAR + 0x00000200)
+#define MMAP_I2C0 (CFG_MBAR + 0x00000280)
+#define MMAP_QSPI (CFG_MBAR + 0x00000400)
+#define MMAP_CAN0 (CFG_MBAR + 0x00010000)
+#define MMAP_CAN1 (CFG_MBAR + 0x00011000)
+
+#define MMAP_I2C1 (CFG_MBAR2 + 0x00000440)
+#define MMAP_UART2 (CFG_MBAR2 + 0x00000C00)
+
+/*********************************************************************
+* ATA Module (ATAC)
+*********************************************************************/
+
+/* Register read/write struct */
+typedef struct atac {
+ /* PIO */
+ u8 toff; /* 0x00 */
+ u8 ton; /* 0x01 */
+ u8 t1; /* 0x02 */
+ u8 t2w; /* 0x03 */
+ u8 t2r; /* 0x04 */
+ u8 ta; /* 0x05 */
+ u8 trd; /* 0x06 */
+ u8 t4; /* 0x07 */
+ u8 t9; /* 0x08 */
+
+ /* DMA */
+ u8 tm; /* 0x09 */
+ u8 tn; /* 0x0A */
+ u8 td; /* 0x0B */
+ u8 tk; /* 0x0C */
+ u8 tack; /* 0x0D */
+ u8 tenv; /* 0x0E */
+ u8 trp; /* 0x0F */
+ u8 tzah; /* 0x10 */
+ u8 tmli; /* 0x11 */
+ u8 tdvh; /* 0x12 */
+ u8 tdzfs; /* 0x13 */
+ u8 tdvs; /* 0x14 */
+ u8 tcvh; /* 0x15 */
+ u8 tss; /* 0x16 */
+ u8 tcyc; /* 0x17 */
+
+ /* FIFO */
+ u32 fifo32; /* 0x18 */
+ u16 fifo16; /* 0x1C */
+ u8 rsvd0[2];
+ u8 ffill; /* 0x20 */
+ u8 rsvd1[3];
+
+ /* ATA */
+ u8 cr; /* 0x24 */
+ u8 rsvd2[3];
+ u8 isr; /* 0x28 */
+ u8 rsvd3[3];
+ u8 ier; /* 0x2C */
+ u8 rsvd4[3];
+ u8 icr; /* 0x30 */
+ u8 rsvd5[3];
+ u8 falarm; /* 0x34 */
+} atac_t;
+
+#endif /* __IMMAP_5249__ */
diff --git a/include/asm-m68k/immap_5271.h b/include/asm-m68k/immap_5271.h
index 424dc1d..d9dc015 100644
--- a/include/asm-m68k/immap_5271.h
+++ b/include/asm-m68k/immap_5271.h
@@ -26,73 +26,73 @@
#ifndef __IMMAP_5271__
#define __IMMAP_5271__
-/* Interrupt module registers
-*/
-typedef struct int_ctrl {
- uint int_icr1;
- uint int_icr2;
- uint int_icr3;
- uint int_icr4;
- uint int_isr;
- uint int_pitr;
- uint int_piwr;
- uchar res1[3];
- uchar int_pivr;
-} intctrl_t;
+#define MMAP_SCM (CFG_MBAR + 0x00000000)
+#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_MBAR + 0x00000080)
+#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
+#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
+#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
+#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
+#define MMAP_UART0 (CFG_MBAR + 0x00000200)
+#define MMAP_UART1 (CFG_MBAR + 0x00000240)
+#define MMAP_UART2 (CFG_MBAR + 0x00000280)
+#define MMAP_I2C (CFG_MBAR + 0x00000300)
+#define MMAP_QSPI (CFG_MBAR + 0x00000340)
+#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
+#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
+#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
+#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
+#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
+#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
+#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
+#define MMAP_FEC (CFG_MBAR + 0x00001000)
+#define MMAP_FECFIFO (CFG_MBAR + 0x00001400)
+#define MMAP_GPIO (CFG_MBAR + 0x00100000)
+#define MMAP_CCM (CFG_MBAR + 0x00110000)
+#define MMAP_PLL (CFG_MBAR + 0x00120000)
+#define MMAP_EPORT (CFG_MBAR + 0x00130000)
+#define MMAP_WDOG (CFG_MBAR + 0x00140000)
+#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
+#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
+#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
+#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
+#define MMAP_MDHA (CFG_MBAR + 0x00190000)
+#define MMAP_RNG (CFG_MBAR + 0x001A0000)
+#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
+#define MMAP_CAN1 (CFG_MBAR + 0x001C0000)
+#define MMAP_ETPU (CFG_MBAR + 0x001D0000)
+#define MMAP_CAN2 (CFG_MBAR + 0x001F0000)
-/* Timer module registers
- */
-typedef struct timer_ctrl {
- ushort timer_tmr;
- ushort res1;
- ushort timer_trr;
- ushort res2;
- ushort timer_tcap;
- ushort res3;
- ushort timer_tcn;
- ushort res4;
- ushort timer_ter;
- uchar res5[14];
-} timer_t;
-
- /* Fast ethernet controller registers
- */
-typedef struct fec {
- uint res1;
- uint fec_ievent;
- uint fec_imask;
- uint res2;
- uint fec_r_des_active;
- uint fec_x_des_active;
- uint res3[3];
- uint fec_ecntrl;
- uint res4[6];
- uint fec_mii_data;
- uint fec_mii_speed;
- uint res5[7];
- uint fec_mibc;
- uint res6[7];
- uint fec_r_cntrl;
- uint res7[15];
- uint fec_x_cntrl;
- uint res8[7];
- uint fec_addr_low;
- uint fec_addr_high;
- uint fec_opd;
- uint res9[10];
- uint fec_ihash_table_high;
- uint fec_ihash_table_low;
- uint fec_ghash_table_high;
- uint fec_ghash_table_low;
- uint res10[7];
- uint fec_tfwr;
- uint res11;
- uint fec_r_bound;
- uint fec_r_fstart;
- uint res12[11];
- uint fec_r_des_start;
- uint fec_x_des_start;
- uint fec_r_buff_size;
-} fec_t;
+/* Interrupt module registers */
+typedef struct int0_ctrl {
+ /* Interrupt Controller 0 */
+ u32 iprh0; /* 0x00 Pending Register High */
+ u32 iprl0; /* 0x04 Pending Register Low */
+ u32 imrh0; /* 0x08 Mask Register High */
+ u32 imrl0; /* 0x0C Mask Register Low */
+ u32 frch0; /* 0x10 Force Register High */
+ u32 frcl0; /* 0x14 Force Register Low */
+ u8 irlr; /* 0x18 */
+ u8 iacklpr; /* 0x19 */
+ u16 res1[19]; /* 0x1a - 0x3c */
+ u8 icr0[64]; /* 0x40 - 0x7F Control registers */
+ u32 res3[24]; /* 0x80 - 0xDF */
+ u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
+ u8 res4[3]; /* 0xE1 - 0xE3 */
+ u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
+ u8 res5[3]; /* 0xE5 - 0xE7 */
+ u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
+ u8 res6[3]; /* 0xE9 - 0xEB */
+ u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
+ u8 res7[3]; /* 0xED - 0xEF */
+ u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
+ u8 res8[3]; /* 0xF1 - 0xF3 */
+ u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
+ u8 res9[3]; /* 0xF5 - 0xF7 */
+ u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
+ u8 resa[3]; /* 0xF9 - 0xFB */
+ u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
+ u8 resb[3]; /* 0xFD - 0xFF */
+} int0_t;
-#endif /* __IMMAP_5271__ */
+#endif /* __IMMAP_5271__ */
diff --git a/include/asm-m68k/immap_5272.h b/include/asm-m68k/immap_5272.h
index ecb4906..2ebb140 100644
--- a/include/asm-m68k/immap_5272.h
+++ b/include/asm-m68k/immap_5272.h
@@ -25,423 +25,326 @@
#ifndef __IMMAP_5272__
#define __IMMAP_5272__
-/* System configuration registers
-*/
-typedef struct sys_ctrl {
- uint sc_mbar;
- ushort sc_scr;
- ushort sc_spr;
- uint sc_pmr;
- char res1[2];
- ushort sc_alpr;
- uint sc_dir;
- char res2[12];
+#define MMAP_CFG (CFG_MBAR + 0x00000000)
+#define MMAP_INTC (CFG_MBAR + 0x00000020)
+#define MMAP_FBCS (CFG_MBAR + 0x00000040)
+#define MMAP_GPIO (CFG_MBAR + 0x00000080)
+#define MMAP_QSPI (CFG_MBAR + 0x000000A0)
+#define MMAP_PWM (CFG_MBAR + 0x000000C0)
+#define MMAP_DMA0 (CFG_MBAR + 0x000000E0)
+#define MMAP_UART0 (CFG_MBAR + 0x00000100)
+#define MMAP_UART1 (CFG_MBAR + 0x00000140)
+#define MMAP_SDRAM (CFG_MBAR + 0x00000180)
+#define MMAP_TMR0 (CFG_MBAR + 0x00000200)
+#define MMAP_TMR1 (CFG_MBAR + 0x00000220)
+#define MMAP_TMR2 (CFG_MBAR + 0x00000240)
+#define MMAP_TMR3 (CFG_MBAR + 0x00000260)
+#define MMAP_WDOG (CFG_MBAR + 0x00000280)
+#define MMAP_PLIC (CFG_MBAR + 0x00000300)
+#define MMAP_FEC (CFG_MBAR + 0x00000840)
+#define MMAP_USB (CFG_MBAR + 0x00001000)
+
+/* System configuration registers */
+typedef struct sys_ctrl {
+ uint sc_mbar;
+ ushort sc_scr;
+ ushort sc_spr;
+ uint sc_pmr;
+ char res1[2];
+ ushort sc_alpr;
+ uint sc_dir;
+ char res2[12];
} sysctrl_t;
-/* Interrupt module registers
-*/
+/* Interrupt module registers */
typedef struct int_ctrl {
- uint int_icr1;
- uint int_icr2;
- uint int_icr3;
- uint int_icr4;
- uint int_isr;
- uint int_pitr;
- uint int_piwr;
- uchar res1[3];
- uchar int_pivr;
+ uint int_icr1;
+ uint int_icr2;
+ uint int_icr3;
+ uint int_icr4;
+ uint int_isr;
+ uint int_pitr;
+ uint int_piwr;
+ uchar res1[3];
+ uchar int_pivr;
} intctrl_t;
-/* Chip select module registers.
-*/
-typedef struct cs_ctlr {
- uint cs_br0;
- uint cs_or0;
- uint cs_br1;
- uint cs_or1;
- uint cs_br2;
- uint cs_or2;
- uint cs_br3;
- uint cs_or3;
- uint cs_br4;
- uint cs_or4;
- uint cs_br5;
- uint cs_or5;
- uint cs_br6;
- uint cs_or6;
- uint cs_br7;
- uint cs_or7;
+/* Chip select module registers */
+typedef struct cs_ctlr {
+ uint cs_br0;
+ uint cs_or0;
+ uint cs_br1;
+ uint cs_or1;
+ uint cs_br2;
+ uint cs_or2;
+ uint cs_br3;
+ uint cs_or3;
+ uint cs_br4;
+ uint cs_or4;
+ uint cs_br5;
+ uint cs_or5;
+ uint cs_br6;
+ uint cs_or6;
+ uint cs_br7;
+ uint cs_or7;
} csctrl_t;
-/* GPIO port registers
-*/
-typedef struct gpio_ctrl {
- uint gpio_pacnt;
- ushort gpio_paddr;
- ushort gpio_padat;
- uint gpio_pbcnt;
- ushort gpio_pbddr;
- ushort gpio_pbdat;
- uchar res1[4];
- ushort gpio_pcddr;
- ushort gpio_pcdat;
- uint gpio_pdcnt;
- uchar res2[4];
+/* GPIO port registers */
+typedef struct gpio_ctrl {
+ uint gpio_pacnt;
+ ushort gpio_paddr;
+ ushort gpio_padat;
+ uint gpio_pbcnt;
+ ushort gpio_pbddr;
+ ushort gpio_pbdat;
+ uchar res1[4];
+ ushort gpio_pcddr;
+ ushort gpio_pcdat;
+ uint gpio_pdcnt;
+ uchar res2[4];
} gpio_t;
-/* QSPI module registers
- */
-typedef struct qspi_ctrl {
- ushort qspi_qmr;
- uchar res1[2];
- ushort qspi_qdlyr;
- uchar res2[2];
- ushort qspi_qwr;
- uchar res3[2];
- ushort qspi_qir;
- uchar res4[2];
- ushort qspi_qar;
- uchar res5[2];
- ushort qspi_qdr;
- uchar res6[10];
+/* QSPI module registers */
+typedef struct qspi_ctrl {
+ ushort qspi_qmr;
+ uchar res1[2];
+ ushort qspi_qdlyr;
+ uchar res2[2];
+ ushort qspi_qwr;
+ uchar res3[2];
+ ushort qspi_qir;
+ uchar res4[2];
+ ushort qspi_qar;
+ uchar res5[2];
+ ushort qspi_qdr;
+ uchar res6[10];
} qspi_t;
-/* PWM module registers
- */
-typedef struct pwm_ctrl {
- uchar pwm_pwcr0;
- uchar res1[3];
- uchar pwm_pwcr1;
- uchar res2[3];
- uchar pwm_pwcr2;
- uchar res3[7];
- uchar pwm_pwwd0;
- uchar res4[3];
- uchar pwm_pwwd1;
- uchar res5[3];
- uchar pwm_pwwd2;
- uchar res6[7];
+/* PWM module registers */
+typedef struct pwm_ctrl {
+ uchar pwm_pwcr0;
+ uchar res1[3];
+ uchar pwm_pwcr1;
+ uchar res2[3];
+ uchar pwm_pwcr2;
+ uchar res3[7];
+ uchar pwm_pwwd0;
+ uchar res4[3];
+ uchar pwm_pwwd1;
+ uchar res5[3];
+ uchar pwm_pwwd2;
+ uchar res6[7];
} pwm_t;
-/* DMA module registers
- */
-typedef struct dma_ctrl {
- ulong dma_dmr;
- uchar res1[2];
- ushort dma_dir;
- ulong dma_dbcr;
- ulong dma_dsar;
- ulong dma_ddar;
- uchar res2[12];
+/* DMA module registers */
+typedef struct dma_ctrl {
+ ulong dma_dmr;
+ uchar res1[2];
+ ushort dma_dir;
+ ulong dma_dbcr;
+ ulong dma_dsar;
+ ulong dma_ddar;
+ uchar res2[12];
} dma_t;
-/* UART module registers
- */
-typedef struct uart_ctrl {
- uchar uart_umr;
- uchar res1[3];
- uchar uart_usr_ucsr;
- uchar res2[3];
- uchar uart_ucr;
- uchar res3[3];
- uchar uart_urb_utb;
- uchar res4[3];
- uchar uart_uipcr_uacr;
- uchar res5[3];
- uchar uart_uisr_uimr;
- uchar res6[3];
- uchar uart_udu;
- uchar res7[3];
- uchar uart_udl;
- uchar res8[3];
- uchar uart_uabu;
- uchar res9[3];
- uchar uart_uabl;
- uchar res10[3];
- uchar uart_utf;
- uchar res11[3];
- uchar uart_urf;
- uchar res12[3];
- uchar uart_ufpd;
- uchar res13[3];
- uchar uart_uip;
- uchar res14[3];
- uchar uart_uop1;
- uchar res15[3];
- uchar uart_uop0;
- uchar res16[3];
-} uart_t;
-
-/* SDRAM controller registers, offset: 0x180
- */
+/* SDRAM controller registers, offset: 0x180 */
typedef struct sdram_ctrl {
- uchar res1[2];
- ushort sdram_sdcr;
- uchar res2[2];
- ushort sdram_sdtr;
- uchar res3[120];
+ uchar res1[2];
+ ushort sdram_sdcr;
+ uchar res2[2];
+ ushort sdram_sdtr;
+ uchar res3[120];
} sdramctrl_t;
-/* Timer module registers
- */
-typedef struct timer_ctrl {
- ushort timer_tmr;
- ushort res1;
- ushort timer_trr;
- ushort res2;
- ushort timer_tcap;
- ushort res3;
- ushort timer_tcn;
- ushort res4;
- ushort timer_ter;
- uchar res5[14];
-} timer_t;
-
-/* Watchdog registers
- */
+/* Watchdog registers */
typedef struct wdog_ctrl {
- ushort wdog_wrrr;
- ushort res1;
- ushort wdog_wirr;
- ushort res2;
- ushort wdog_wcr;
- ushort res3;
- ushort wdog_wer;
- uchar res4[114];
+ ushort wdog_wrrr;
+ ushort res1;
+ ushort wdog_wirr;
+ ushort res2;
+ ushort wdog_wcr;
+ ushort res3;
+ ushort wdog_wer;
+ uchar res4[114];
} wdog_t;
-/* PLIC module registers
- */
+/* PLIC module registers */
typedef struct plic_ctrl {
- ulong plic_p0b1rr;
- ulong plic_p1b1rr;
- ulong plic_p2b1rr;
- ulong plic_p3b1rr;
- ulong plic_p0b2rr;
- ulong plic_p1b2rr;
- ulong plic_p2b2rr;
- ulong plic_p3b2rr;
- uchar plic_p0drr;
- uchar plic_p1drr;
- uchar plic_p2drr;
- uchar plic_p3drr;
- uchar res1[4];
- ulong plic_p0b1tr;
- ulong plic_p1b1tr;
- ulong plic_p2b1tr;
- ulong plic_p3b1tr;
- ulong plic_p0b2tr;
- ulong plic_p1b2tr;
- ulong plic_p2b2tr;
- ulong plic_p3b2tr;
- uchar plic_p0dtr;
- uchar plic_p1dtr;
- uchar plic_p2dtr;
- uchar plic_p3dtr;
- uchar res2[4];
- ushort plic_p0cr;
- ushort plic_p1cr;
- ushort plic_p2cr;
- ushort plic_p3cr;
- ushort plic_p0icr;
- ushort plic_p1icr;
- ushort plic_p2icr;
- ushort plic_p3icr;
- ushort plic_p0gmr;
- ushort plic_p1gmr;
- ushort plic_p2gmr;
- ushort plic_p3gmr;
- ushort plic_p0gmt;
- ushort plic_p1gmt;
- ushort plic_p2gmt;
- ushort plic_p3gmt;
- uchar res3;
- uchar plic_pgmts;
- uchar plic_pgmta;
- uchar res4;
- uchar plic_p0gcir;
- uchar plic_p1gcir;
- uchar plic_p2gcir;
- uchar plic_p3gcir;
- uchar plic_p0gcit;
- uchar plic_p1gcit;
- uchar plic_p2gcit;
- uchar plic_p3gcit;
- uchar res5[3];
- uchar plic_pgcitsr;
- uchar res6[3];
- uchar plic_pdcsr;
- ushort plic_p0psr;
- ushort plic_p1psr;
- ushort plic_p2psr;
- ushort plic_p3psr;
- ushort plic_pasr;
- uchar res7;
- uchar plic_plcr;
- ushort res8;
- ushort plic_pdrqr;
- ushort plic_p0sdr;
- ushort plic_p1sdr;
- ushort plic_p2sdr;
- ushort plic_p3sdr;
- ushort res9;
- ushort plic_pcsr;
- uchar res10[1184];
+ ulong plic_p0b1rr;
+ ulong plic_p1b1rr;
+ ulong plic_p2b1rr;
+ ulong plic_p3b1rr;
+ ulong plic_p0b2rr;
+ ulong plic_p1b2rr;
+ ulong plic_p2b2rr;
+ ulong plic_p3b2rr;
+ uchar plic_p0drr;
+ uchar plic_p1drr;
+ uchar plic_p2drr;
+ uchar plic_p3drr;
+ uchar res1[4];
+ ulong plic_p0b1tr;
+ ulong plic_p1b1tr;
+ ulong plic_p2b1tr;
+ ulong plic_p3b1tr;
+ ulong plic_p0b2tr;
+ ulong plic_p1b2tr;
+ ulong plic_p2b2tr;
+ ulong plic_p3b2tr;
+ uchar plic_p0dtr;
+ uchar plic_p1dtr;
+ uchar plic_p2dtr;
+ uchar plic_p3dtr;
+ uchar res2[4];
+ ushort plic_p0cr;
+ ushort plic_p1cr;
+ ushort plic_p2cr;
+ ushort plic_p3cr;
+ ushort plic_p0icr;
+ ushort plic_p1icr;
+ ushort plic_p2icr;
+ ushort plic_p3icr;
+ ushort plic_p0gmr;
+ ushort plic_p1gmr;
+ ushort plic_p2gmr;
+ ushort plic_p3gmr;
+ ushort plic_p0gmt;
+ ushort plic_p1gmt;
+ ushort plic_p2gmt;
+ ushort plic_p3gmt;
+ uchar res3;
+ uchar plic_pgmts;
+ uchar plic_pgmta;
+ uchar res4;
+ uchar plic_p0gcir;
+ uchar plic_p1gcir;
+ uchar plic_p2gcir;
+ uchar plic_p3gcir;
+ uchar plic_p0gcit;
+ uchar plic_p1gcit;
+ uchar plic_p2gcit;
+ uchar plic_p3gcit;
+ uchar res5[3];
+ uchar plic_pgcitsr;
+ uchar res6[3];
+ uchar plic_pdcsr;
+ ushort plic_p0psr;
+ ushort plic_p1psr;
+ ushort plic_p2psr;
+ ushort plic_p3psr;
+ ushort plic_pasr;
+ uchar res7;
+ uchar plic_plcr;
+ ushort res8;
+ ushort plic_pdrqr;
+ ushort plic_p0sdr;
+ ushort plic_p1sdr;
+ ushort plic_p2sdr;
+ ushort plic_p3sdr;
+ ushort res9;
+ ushort plic_pcsr;
+ uchar res10[1184];
} plic_t;
-/* Fast ethernet controller registers
- */
-typedef struct fec {
- uint fec_ecntrl; /* ethernet control register */
- uint fec_ievent; /* interrupt event register */
- uint fec_imask; /* interrupt mask register */
- uint fec_ivec; /* interrupt level and vector status */
- uint fec_r_des_active; /* Rx ring updated flag */
- uint fec_x_des_active; /* Tx ring updated flag */
- uint res3[10]; /* reserved */
- uint fec_mii_data; /* MII data register */
- uint fec_mii_speed; /* MII speed control register */
- uint res4[17]; /* reserved */
- uint fec_r_bound; /* end of RAM (read-only) */
- uint fec_r_fstart; /* Rx FIFO start address */
- uint res5[6]; /* reserved */
- uint fec_x_fstart; /* Tx FIFO start address */
- uint res7[21]; /* reserved */
- uint fec_r_cntrl; /* Rx control register */
- uint fec_r_hash; /* Rx hash register */
- uint res8[14]; /* reserved */
- uint fec_x_cntrl; /* Tx control register */
- uint res9[0x9e]; /* reserved */
- uint fec_addr_low; /* lower 32 bits of station address */
- uint fec_addr_high; /* upper 16 bits of station address */
- uint fec_hash_table_high; /* upper 32-bits of hash table */
- uint fec_hash_table_low; /* lower 32-bits of hash table */
- uint fec_r_des_start; /* beginning of Rx descriptor ring */
- uint fec_x_des_start; /* beginning of Tx descriptor ring */
- uint fec_r_buff_size; /* Rx buffer size */
- uint res2[9]; /* reserved */
- uchar fec_fifo[960]; /* fifo RAM */
-} fec_t;
-
-/* USB module registers
-*/
+/* USB module registers */
typedef struct usb {
- ushort res1;
- ushort usb_fnr;
- ushort res2;
- ushort usb_fnmr;
- ushort res3;
- ushort usb_rfmr;
- ushort res4;
- ushort usb_rfmmr;
- uchar res5[3];
- uchar usb_far;
- ulong usb_asr;
- ulong usb_drr1;
- ulong usb_drr2;
- ushort res6;
- ushort usb_specr;
- ushort res7;
- ushort usb_ep0sr;
- ulong usb_iep0cfg;
- ulong usb_oep0cfg;
- ulong usb_ep1cfg;
- ulong usb_ep2cfg;
- ulong usb_ep3cfg;
- ulong usb_ep4cfg;
- ulong usb_ep5cfg;
- ulong usb_ep6cfg;
- ulong usb_ep7cfg;
- ulong usb_ep0ctl;
- ushort res8;
- ushort usb_ep1ctl;
- ushort res9;
- ushort usb_ep2ctl;
- ushort res10;
- ushort usb_ep3ctl;
- ushort res11;
- ushort usb_ep4ctl;
- ushort res12;
- ushort usb_ep5ctl;
- ushort res13;
- ushort usb_ep6ctl;
- ushort res14;
- ushort usb_ep7ctl;
- ulong usb_ep0isr;
- ushort res15;
- ushort usb_ep1isr;
- ushort res16;
- ushort usb_ep2isr;
- ushort res17;
- ushort usb_ep3isr;
- ushort res18;
- ushort usb_ep4isr;
- ushort res19;
- ushort usb_ep5isr;
- ushort res20;
- ushort usb_ep6isr;
- ushort res21;
- ushort usb_ep7isr;
- ulong usb_ep0imr;
- ushort res22;
- ushort usb_ep1imr;
- ushort res23;
- ushort usb_ep2imr;
- ushort res24;
- ushort usb_ep3imr;
- ushort res25;
- ushort usb_ep4imr;
- ushort res26;
- ushort usb_ep5imr;
- ushort res27;
- ushort usb_ep6imr;
- ushort res28;
- ushort usb_ep7imr;
- ulong usb_ep0dr;
- ulong usb_ep1dr;
- ulong usb_ep2dr;
- ulong usb_ep3dr;
- ulong usb_ep4dr;
- ulong usb_ep5dr;
- ulong usb_ep6dr;
- ulong usb_ep7dr;
- ushort res29;
- ushort usb_ep0dpr;
- ushort res30;
- ushort usb_ep1dpr;
- ushort res31;
- ushort usb_ep2dpr;
- ushort res32;
- ushort usb_ep3dpr;
- ushort res33;
- ushort usb_ep4dpr;
- ushort res34;
- ushort usb_ep5dpr;
- ushort res35;
- ushort usb_ep6dpr;
- ushort res36;
- ushort usb_ep7dpr;
- uchar res37[788];
- uchar usb_cfgram[1024];
+ ushort res1;
+ ushort usb_fnr;
+ ushort res2;
+ ushort usb_fnmr;
+ ushort res3;
+ ushort usb_rfmr;
+ ushort res4;
+ ushort usb_rfmmr;
+ uchar res5[3];
+ uchar usb_far;
+ ulong usb_asr;
+ ulong usb_drr1;
+ ulong usb_drr2;
+ ushort res6;
+ ushort usb_specr;
+ ushort res7;
+ ushort usb_ep0sr;
+ ulong usb_iep0cfg;
+ ulong usb_oep0cfg;
+ ulong usb_ep1cfg;
+ ulong usb_ep2cfg;
+ ulong usb_ep3cfg;
+ ulong usb_ep4cfg;
+ ulong usb_ep5cfg;
+ ulong usb_ep6cfg;
+ ulong usb_ep7cfg;
+ ulong usb_ep0ctl;
+ ushort res8;
+ ushort usb_ep1ctl;
+ ushort res9;
+ ushort usb_ep2ctl;
+ ushort res10;
+ ushort usb_ep3ctl;
+ ushort res11;
+ ushort usb_ep4ctl;
+ ushort res12;
+ ushort usb_ep5ctl;
+ ushort res13;
+ ushort usb_ep6ctl;
+ ushort res14;
+ ushort usb_ep7ctl;
+ ulong usb_ep0isr;
+ ushort res15;
+ ushort usb_ep1isr;
+ ushort res16;
+ ushort usb_ep2isr;
+ ushort res17;
+ ushort usb_ep3isr;
+ ushort res18;
+ ushort usb_ep4isr;
+ ushort res19;
+ ushort usb_ep5isr;
+ ushort res20;
+ ushort usb_ep6isr;
+ ushort res21;
+ ushort usb_ep7isr;
+ ulong usb_ep0imr;
+ ushort res22;
+ ushort usb_ep1imr;
+ ushort res23;
+ ushort usb_ep2imr;
+ ushort res24;
+ ushort usb_ep3imr;
+ ushort res25;
+ ushort usb_ep4imr;
+ ushort res26;
+ ushort usb_ep5imr;
+ ushort res27;
+ ushort usb_ep6imr;
+ ushort res28;
+ ushort usb_ep7imr;
+ ulong usb_ep0dr;
+ ulong usb_ep1dr;
+ ulong usb_ep2dr;
+ ulong usb_ep3dr;
+ ulong usb_ep4dr;
+ ulong usb_ep5dr;
+ ulong usb_ep6dr;
+ ulong usb_ep7dr;
+ ushort res29;
+ ushort usb_ep0dpr;
+ ushort res30;
+ ushort usb_ep1dpr;
+ ushort res31;
+ ushort usb_ep2dpr;
+ ushort res32;
+ ushort usb_ep3dpr;
+ ushort res33;
+ ushort usb_ep4dpr;
+ ushort res34;
+ ushort usb_ep5dpr;
+ ushort res35;
+ ushort usb_ep6dpr;
+ ushort res36;
+ ushort usb_ep7dpr;
+ uchar res37[788];
+ uchar usb_cfgram[1024];
} usb_t;
-/* Internal memory map.
-*/
-typedef struct immap {
- sysctrl_t sysctrl_reg; /* System configuration registers */
- intctrl_t intctrl_reg; /* Interrupt controller registers */
- csctrl_t csctrl_reg; /* Chip select controller registers */
- gpio_t gpio_reg; /* GPIO controller registers */
- qspi_t qspi_reg; /* QSPI controller registers */
- pwm_t pwm_reg; /* Pulse width modulation registers */
- dma_t dma_reg; /* DMA registers */
- uart_t uart_reg[2]; /* UART registers */
- sdramctrl_t sdram_reg; /* SDRAM controller registers */
- timer_t timer_reg[4]; /* Timer registers */
- wdog_t wdog_reg; /* Watchdog registers */
- plic_t plic_reg; /* Physical layer interface registers */
- fec_t fec_reg; /* Fast ethernet controller registers */
- usb_t usb_reg; /* USB controller registers */
-} immap_t;
-
-#endif /* __IMMAP_5272__ */
+#endif /* __IMMAP_5272__ */
diff --git a/include/asm-m68k/immap_5282.h b/include/asm-m68k/immap_5282.h
index 6553b08..e82960a 100644
--- a/include/asm-m68k/immap_5282.h
+++ b/include/asm-m68k/immap_5282.h
@@ -25,61 +25,168 @@
#ifndef __IMMAP_5282__
#define __IMMAP_5282__
-struct sys_ctrl {
- uint ipsbar;
- char res1[4];
- uint rambar;
- char res2[4];
- uchar crsr;
- uchar cwcr;
- uchar lpicr;
- uchar cwsr;
- uint dmareqc;
- char res3[4];
- uint mpark;
+#define MMAP_SCM (CFG_MBAR + 0x00000000)
+#define MMAP_SDRAMC (CFG_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_MBAR + 0x00000080)
+#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
+#define MMAP_DMA1 (CFG_MBAR + 0x00000140)
+#define MMAP_DMA2 (CFG_MBAR + 0x00000180)
+#define MMAP_DMA3 (CFG_MBAR + 0x000001C0)
+#define MMAP_UART0 (CFG_MBAR + 0x00000200)
+#define MMAP_UART1 (CFG_MBAR + 0x00000240)
+#define MMAP_UART2 (CFG_MBAR + 0x00000280)
+#define MMAP_I2C (CFG_MBAR + 0x00000300)
+#define MMAP_QSPI (CFG_MBAR + 0x00000340)
+#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
+#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
+#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
+#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
+#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
+#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
+#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
+#define MMAP_FEC (CFG_MBAR + 0x00001000)
+#define MMAP_FECFIFO (CFG_MBAR + 0x00001400)
+#define MMAP_GPIO (CFG_MBAR + 0x00100000)
+#define MMAP_CCM (CFG_MBAR + 0x00110000)
+#define MMAP_PLL (CFG_MBAR + 0x00120000)
+#define MMAP_EPORT (CFG_MBAR + 0x00130000)
+#define MMAP_WDOG (CFG_MBAR + 0x00140000)
+#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
+#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
+#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
+#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
+#define MMAP_QADC (CFG_MBAR + 0x00190000)
+#define MMAP_GPTMRA (CFG_MBAR + 0x001A0000)
+#define MMAP_GPTMRB (CFG_MBAR + 0x001B0000)
+#define MMAP_CAN (CFG_MBAR + 0x001C0000)
+#define MMAP_CFMC (CFG_MBAR + 0x001D0000)
+#define MMAP_CFMMEM (CFG_MBAR + 0x04000000)
- /* TODO: finish these */
-};
+/* System Control Module */
+typedef struct scm_ctrl {
+ u32 ipsbar;
+ u32 res1;
+ u32 rambar;
+ u32 res2;
+ u8 crsr;
+ u8 cwcr;
+ u8 lpicr;
+ u8 cwsr;
+ u32 res3;
+ u8 mpark;
+ u8 res4[3];
+ u8 pacr0;
+ u8 pacr1;
+ u8 pacr2;
+ u8 pacr3;
+ u8 pacr4;
+ u8 res5;
+ u8 pacr5;
+ u8 pacr6;
+ u8 pacr7;
+ u8 res6;
+ u8 pacr8;
+ u8 res7;
+ u8 gpacr0;
+ u8 gpacr1;
+ u16 res8;
+} scm_t;
-/* Fast ethernet controller registers
- */
-typedef struct fec {
- uint res1; /* reserved 1000*/
- uint fec_ievent; /* interrupt event register 1004*/ /* EIR */
- uint fec_imask; /* interrupt mask register 1008*/ /* EIMR */
- uint res2; /* reserved 100c*/
- uint fec_r_des_active; /* Rx ring updated flag 1010*/ /* RDAR */
- uint fec_x_des_active; /* Tx ring updated flag 1014*/ /* XDAR */
- uint res3[3]; /* reserved 1018*/
- uint fec_ecntrl; /* ethernet control register 1024*/ /* ECR */
- uint res4[6]; /* reserved 1028*/
- uint fec_mii_data; /* MII data register 1040*/ /* MDATA */
- uint fec_mii_speed; /* MII speed control register 1044*/ /* MSCR */
- /*1044*/
- uint res5[7]; /* reserved 1048*/
- uint fec_mibc; /* MIB Control/Status register 1064*/ /* MIBC */
- uint res6[7]; /* reserved 1068*/
- uint fec_r_cntrl; /* Rx control register 1084*/ /* RCR */
- uint res7[15]; /* reserved 1088*/
- uint fec_x_cntrl; /* Tx control register 10C4*/ /* TCR */
- uint res8[7]; /* reserved 10C8*/
- uint fec_addr_low; /* lower 32 bits of station address */ /* PALR */
- uint fec_addr_high; /* upper 16 bits of station address */ /* PAUR */
- uint fec_opd; /* opcode + pause duration 10EC*/ /* OPD */
- uint res9[10]; /* reserved 10F0*/
- uint fec_ihash_table_high; /* upper 32-bits of individual hash */ /* IAUR */
- uint fec_ihash_table_low; /* lower 32-bits of individual hash */ /* IALR */
- uint fec_ghash_table_high; /* upper 32-bits of group hash */ /* GAUR */
- uint fec_ghash_table_low; /* lower 32-bits of group hash */ /* GALR */
- uint res10[7]; /* reserved 1128*/
- uint fec_tfwr; /* Transmit FIFO watermark 1144*/ /* TFWR */
- uint res11; /* reserved 1148*/
- uint fec_r_bound; /* FIFO Receive Bound Register = end of */ /* FRBR */
- uint fec_r_fstart; /* FIFO Receive FIfo Start Registers = */ /* FRSR */
- uint res12[11]; /* reserved 1154*/
- uint fec_r_des_start;/* beginning of Rx descriptor ring 1180*/ /* ERDSR */
- uint fec_x_des_start;/* beginning of Tx descriptor ring 1184*/ /* ETDSR */
- uint fec_r_buff_size;/* Rx buffer size 1188*/ /* EMRBR */
-} fec_t;
+/* Flexbus module Chip select registers */
+typedef struct fbcs_ctrl {
+ u16 csar0; /* 0x00 Chip-Select Address Register 0 */
+ u16 res0;
+ u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
+ u16 res1; /* 0x08 */
+ u16 cscr0; /* 0x0A Chip-Select Control Register 0 */
+
+ u16 csar1; /* 0x0C Chip-Select Address Register 1 */
+ u16 res2;
+ u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
+ u16 res3; /* 0x14 */
+ u16 cscr1; /* 0x16 Chip-Select Control Register 1 */
+
+ u16 csar2; /* 0x18 Chip-Select Address Register 2 */
+ u16 res4;
+ u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
+ u16 res5; /* 0x20 */
+ u16 cscr2; /* 0x22 Chip-Select Control Register 2 */
+
+ u16 csar3; /* 0x24 Chip-Select Address Register 3 */
+ u16 res6;
+ u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
+ u16 res7; /* 0x2C */
+ u16 cscr3; /* 0x2E Chip-Select Control Register 3 */
+
+ u16 csar4; /* 0x30 Chip-Select Address Register 4 */
+ u16 res8;
+ u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
+ u16 res9; /* 0x38 */
+ u16 cscr4; /* 0x3A Chip-Select Control Register 4 */
+
+ u16 csar5; /* 0x3C Chip-Select Address Register 5 */
+ u16 res10;
+ u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
+ u16 res11; /* 0x44 */
+ u16 cscr5; /* 0x46 Chip-Select Control Register 5 */
+
+ u16 csar6; /* 0x48 Chip-Select Address Register 5 */
+ u16 res12;
+ u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */
+ u16 res13; /* 0x50 */
+ u16 cscr6; /* 0x52 Chip-Select Control Register 5 */
+
+ u16 csar7; /* 0x54 Chip-Select Address Register 5 */
+ u16 res14;
+ u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */
+ u16 res15; /* 0x5C */
+ u16 cscr7; /* 0x5E Chip-Select Control Register 5 */
+} fbcs_t;
+
+/* Interrupt module registers */
+typedef struct int0_ctrl {
+ /* Interrupt Controller 0 */
+ u32 iprh0; /* 0x00 Pending Register High */
+ u32 iprl0; /* 0x04 Pending Register Low */
+ u32 imrh0; /* 0x08 Mask Register High */
+ u32 imrl0; /* 0x0C Mask Register Low */
+ u32 frch0; /* 0x10 Force Register High */
+ u32 frcl0; /* 0x14 Force Register Low */
+ u8 irlr; /* 0x18 */
+ u8 iacklpr; /* 0x19 */
+ u16 res1[19]; /* 0x1a - 0x3c */
+ u8 icr0[64]; /* 0x40 - 0x7F Control registers */
+ u32 res3[24]; /* 0x80 - 0xDF */
+ u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
+ u8 res4[3]; /* 0xE1 - 0xE3 */
+ u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
+ u8 res5[3]; /* 0xE5 - 0xE7 */
+ u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
+ u8 res6[3]; /* 0xE9 - 0xEB */
+ u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
+ u8 res7[3]; /* 0xED - 0xEF */
+ u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
+ u8 res8[3]; /* 0xF1 - 0xF3 */
+ u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
+ u8 res9[3]; /* 0xF5 - 0xF7 */
+ u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
+ u8 resa[3]; /* 0xF9 - 0xFB */
+ u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
+ u8 resb[3]; /* 0xFD - 0xFF */
+} int0_t;
+
+/* Clock Module registers */
+typedef struct pll_ctrl {
+ u16 syncr; /* 0x00 synthesizer control register */
+ u16 synsr; /* 0x02 synthesizer status register */
+} pll_t;
+
+/* Watchdog registers */
+typedef struct wdog_ctrl {
+ ushort wcr;
+ ushort wmr;
+ ushort wcntr;
+ ushort wsr;
+} wdog_t;
-#endif /* __IMMAP_5282__ */
+#endif /* __IMMAP_5282__ */
diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h
new file mode 100644
index 0000000..2a3980c
--- /dev/null
+++ b/include/asm-m68k/immap_5329.h
@@ -0,0 +1,793 @@
+/*
+ * MCF5329 Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5329__
+#define __IMMAP_5329__
+
+#define MMAP_SCM1 0xEC000000
+#define MMAP_MDHA 0xEC080000
+#define MMAP_SKHA 0xEC084000
+#define MMAP_RNG 0xEC088000
+#define MMAP_SCM2 0xFC000000
+#define MMAP_XBS 0xFC004000
+#define MMAP_FBCS 0xFC008000
+#define MMAP_CAN 0xFC020000
+#define MMAP_FEC 0xFC030000
+#define MMAP_SCM3 0xFC040000
+#define MMAP_EDMA 0xFC044000
+#define MMAP_TCD 0xFC045000
+#define MMAP_INTC0 0xFC048000
+#define MMAP_INTC1 0xFC04C000
+#define MMAP_INTCACK 0xFC054000
+#define MMAP_I2C 0xFC058000
+#define MMAP_QSPI 0xFC05C000
+#define MMAP_UART0 0xFC060000
+#define MMAP_UART1 0xFC064000
+#define MMAP_UART2 0xFC068000
+#define MMAP_DTMR0 0xFC070000
+#define MMAP_DTMR1 0xFC074000
+#define MMAP_DTMR2 0xFC078000
+#define MMAP_DTMR3 0xFC07C000
+#define MMAP_PIT0 0xFC080000
+#define MMAP_PIT1 0xFC084000
+#define MMAP_PIT2 0xFC088000
+#define MMAP_PIT3 0xFC08C000
+#define MMAP_PWM 0xFC090000
+#define MMAP_EPORT 0xFC094000
+#define MMAP_WDOG 0xFC098000
+#define MMAP_CCM 0xFC0A0000
+#define MMAP_GPIO 0xFC0A4000
+#define MMAP_RTC 0xFC0A8000
+#define MMAP_LCDC 0xFC0AC000
+#define MMAP_USBOTG 0xFC0B0000
+#define MMAP_USBH 0xFC0B4000
+#define MMAP_SDRAM 0xFC0B8000
+#define MMAP_SSI 0xFC0BC000
+#define MMAP_PLL 0xFC0C0000
+
+/* System control module registers */
+typedef struct scm1_ctrl {
+ u32 mpr0; /* 0x00 Master Privilege Register 0 */
+ u32 res1[15]; /* 0x04 - 0x3F */
+ u32 pacrh; /* 0x40 Peripheral Access Control Register H */
+ u32 res2[3]; /* 0x44 - 0x53 */
+ u32 bmt0; /*0x54 Bus Monitor Timeout 0 */
+} scm1_t;
+
+/* Message Digest Hardware Accelerator */
+typedef struct mdha_ctrl {
+ u32 mdmr; /* 0x00 MDHA Mode Register */
+ u32 mdcr; /* 0x04 Control register */
+ u32 mdcmr; /* 0x08 Command Register */
+ u32 mdsr; /* 0x0C Status Register */
+ u32 mdisr; /* 0x10 Interrupt Status Register */
+ u32 mdimr; /* 0x14 Interrupt Mask Register */
+ u32 mddsr; /* 0x1C Data Size Register */
+ u32 mdin; /* 0x20 Input FIFO */
+ u32 res1[3]; /* 0x24 - 0x2F */
+ u32 mdao; /* 0x30 Message Digest AO Register */
+ u32 mdbo; /* 0x34 Message Digest BO Register */
+ u32 mdco; /* 0x38 Message Digest CO Register */
+ u32 mddo; /* 0x3C Message Digest DO Register */
+ u32 mdeo; /* 0x40 Message Digest EO Register */
+ u32 mdmds; /* 0x44 Message Data Size Register */
+ u32 res[10]; /* 0x48 - 0x6F */
+ u32 mda1; /* 0x70 Message Digest A1 Register */
+ u32 mdb1; /* 0x74 Message Digest B1 Register */
+ u32 mdc1; /* 0x78 Message Digest C1 Register */
+ u32 mdd1; /* 0x7C Message Digest D1 Register */
+ u32 mde1; /* 0x80 Message Digest E1 Register */
+} mdha_t;
+
+/* Symmetric Key Hardware Accelerator */
+typedef struct skha_ctrl {
+ u32 mr; /* 0x00 Mode Register */
+ u32 cr; /* 0x04 Control Register */
+ u32 cmr; /* 0x08 Command Register */
+ u32 sr; /* 0x0C Status Register */
+ u32 esr; /* 0x10 Error Status Register */
+ u32 emr; /* 0x14 Error Status Mask Register) */
+ u32 ksr; /* 0x18 Key Size Register */
+ u32 dsr; /* 0x1C Data Size Register */
+ u32 in; /* 0x20 Input FIFO */
+ u32 out; /* 0x24 Output FIFO */
+ u32 res1[2]; /* 0x28 - 0x2F */
+ u32 kdr1; /* 0x30 Key Data Register 1 */
+ u32 kdr2; /* 0x34 Key Data Register 2 */
+ u32 kdr3; /* 0x38 Key Data Register 3 */
+ u32 kdr4; /* 0x3C Key Data Register 4 */
+ u32 kdr5; /* 0x40 Key Data Register 5 */
+ u32 kdr6; /* 0x44 Key Data Register 6 */
+ u32 res2[10]; /* 0x48 - 0x6F */
+ u32 c1; /* 0x70 Context 1 */
+ u32 c2; /* 0x74 Context 2 */
+ u32 c3; /* 0x78 Context 3 */
+ u32 c4; /* 0x7C Context 4 */
+ u32 c5; /* 0x80 Context 5 */
+ u32 c6; /* 0x84 Context 6 */
+ u32 c7; /* 0x88 Context 7 */
+ u32 c8; /* 0x8C Context 8 */
+ u32 c9; /* 0x90 Context 9 */
+ u32 c10; /* 0x94 Context 10 */
+ u32 c11; /* 0x98 Context 11 */
+} skha_t;
+
+/* Random Number Generator */
+typedef struct rng_ctrl {
+ u32 rngcr; /* 0x00 RNG Control Register */
+ u32 rngsr; /* 0x04 RNG Status Register */
+ u32 rnger; /* 0x08 RNG Entropy Register */
+ u32 rngout; /* 0x0C RNG Output FIFO */
+} rng_t;
+
+/* System control module registers 2 */
+typedef struct scm2_ctrl {
+ u32 mpr1; /* 0x00 Master Privilege Register */
+ u32 res1[7]; /* 0x04 - 0x1F */
+ u32 pacra; /* 0x20 Peripheral Access Control Register A */
+ u32 pacrb; /* 0x24 Peripheral Access Control Register B */
+ u32 pacrc; /* 0x28 Peripheral Access Control Register C */
+ u32 pacrd; /* 0x2C Peripheral Access Control Register D */
+ u32 res2[4]; /* 0x30 - 0x3F */
+ u32 pacre; /* 0x40 Peripheral Access Control Register E */
+ u32 pacrf; /* 0x44 Peripheral Access Control Register F */
+ u32 pacrg; /* 0x48 Peripheral Access Control Register G */
+ u32 res3[2]; /* 0x4C - 0x53 */
+ u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */
+} scm2_t;
+
+/* Cross-Bar Switch Module */
+typedef struct xbs_ctrl {
+ u32 prs1; /* 0x100 Priority Register Slave 1 */
+ u32 res1[3]; /* 0x104 - 0F */
+ u32 crs1; /* 0x110 Control Register Slave 1 */
+ u32 res2[187]; /* 0x114 - 0x3FF */
+
+ u32 prs4; /* 0x400 Priority Register Slave 4 */
+ u32 res3[3]; /* 0x404 - 0F */
+ u32 crs4; /* 0x410 Control Register Slave 4 */
+ u32 res4[123]; /* 0x414 - 0x5FF */
+
+ u32 prs6; /* 0x600 Priority Register Slave 6 */
+ u32 res5[3]; /* 0x604 - 0F */
+ u32 crs6; /* 0x610 Control Register Slave 6 */
+ u32 res6[59]; /* 0x614 - 0x6FF */
+
+ u32 prs7; /* 0x700 Priority Register Slave 7 */
+ u32 res7[3]; /* 0x704 - 0F */
+ u32 crs7; /* 0x710 Control Register Slave 7 */
+} xbs_t;
+
+/* Flexbus module Chip select registers */
+typedef struct fbcs_ctrl {
+ u16 csar0; /* 0x00 Chip-Select Address Register 0 */
+ u16 res0;
+ u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
+ u32 cscr0; /* 0x08 Chip-Select Control Register 0 */
+
+ u16 csar1; /* 0x0C Chip-Select Address Register 1 */
+ u16 res1;
+ u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
+ u32 cscr1; /* 0x14 Chip-Select Control Register 1 */
+
+ u16 csar2; /* 0x18 Chip-Select Address Register 2 */
+ u16 res2;
+ u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
+ u32 cscr2; /* 0x20 Chip-Select Control Register 2 */
+
+ u16 csar3; /* 0x24 Chip-Select Address Register 3 */
+ u16 res3;
+ u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
+ u32 cscr3; /* 0x2C Chip-Select Control Register 3 */
+
+ u16 csar4; /* 0x30 Chip-Select Address Register 4 */
+ u16 res4;
+ u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
+ u32 cscr4; /* 0x38 Chip-Select Control Register 4 */
+
+ u16 csar5; /* 0x3C Chip-Select Address Register 5 */
+ u16 res5;
+ u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
+ u32 cscr5; /* 0x44 Chip-Select Control Register 5 */
+} fbcs_t;
+
+/* FlexCan module registers */
+typedef struct can_ctrl {
+ u32 mcr; /* 0x00 Module Configuration register */
+ u32 ctrl; /* 0x04 Control register */
+ u32 timer; /* 0x08 Free Running Timer */
+ u32 res1; /* 0x0C */
+ u32 rxgmask; /* 0x10 Rx Global Mask */
+ u32 rx14mask; /* 0x14 RxBuffer 14 Mask */
+ u32 rx15mask; /* 0x18 RxBuffer 15 Mask */
+ u32 errcnt; /* 0x1C Error Counter Register */
+ u32 errstat; /* 0x20 Error and status Register */
+ u32 res2; /* 0x24 */
+ u32 imask; /* 0x28 Interrupt Mask Register */
+ u32 res3; /* 0x2C */
+ u32 iflag; /* 0x30 Interrupt Flag Register */
+ u32 res4[19]; /* 0x34 - 0x7F */
+ u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */
+} can_t;
+
+/* System Control Module register 3 */
+typedef struct scm3_ctrl {
+ u8 res1[19]; /* 0x00 - 0x12 */
+ u8 wcr; /* 0x13 wakeup control register */
+ u16 res2; /* 0x14 - 0x15 */
+ u16 cwcr; /* 0x16 Core Watchdog Control Register */
+ u8 res3[3]; /* 0x18 - 0x1A */
+ u8 cwsr; /* 0x1B Core Watchdog Service Register */
+ u8 res4[2]; /* 0x1C - 0x1D */
+ u8 scmisr; /* 0x1F Interrupt Status Register */
+ u32 res5; /* 0x20 */
+ u32 bcr; /* 0x24 Burst Configuration Register */
+ u32 res6[18]; /* 0x28 - 0x6F */
+ u32 cfadr; /* 0x70 Core Fault Address Register */
+ u8 res7[4]; /* 0x71 - 0x74 */
+ u8 cfier; /* 0x75 Core Fault Interrupt Enable Register */
+ u8 cfloc; /* 0x76 Core Fault Location Register */
+ u8 cfatr; /* 0x77 Core Fault Attributes Register */
+ u32 res8; /* 0x78 */
+ u32 cfdtr; /* 0x7C Core Fault Data Register */
+} scm3_t;
+
+/* eDMA module registers */
+typedef struct edma_ctrl {
+ u32 cr; /* 0x00 Control Register */
+ u32 es; /* 0x04 Error Status Register */
+ u16 res1[3]; /* 0x08 - 0x0D */
+ u16 erq; /* 0x0E Enable Request Register */
+ u16 res2[3]; /* 0x10 - 0x15 */
+ u16 eei; /* 0x16 Enable Error Interrupt Request */
+ u8 serq; /* 0x18 Set Enable Request */
+ u8 cerq; /* 0x19 Clear Enable Request */
+ u8 seei; /* 0x1A Set Enable Error Interrupt Request */
+ u8 ceei; /* 0x1B Clear Enable Error Interrupt Request */
+ u8 cint; /* 0x1C Clear Interrupt Enable Register */
+ u8 cerr; /* 0x1D Clear Error Register */
+ u8 ssrt; /* 0x1E Set START Bit Register */
+ u8 cdne; /* 0x1F Clear DONE Status Bit Register */
+ u16 res3[3]; /* 0x20 - 0x25 */
+ u16 intr; /* 0x26 Interrupt Request Register */
+ u16 res4[3]; /* 0x28 - 0x2D */
+ u16 err; /* 0x2E Error Register */
+ u32 res5[52]; /* 0x30 - 0xFF */
+ u8 dchpri0; /* 0x100 Channel 0 Priority Register */
+ u8 dchpri1; /* 0x101 Channel 1 Priority Register */
+ u8 dchpri2; /* 0x102 Channel 2 Priority Register */
+ u8 dchpri3; /* 0x103 Channel 3 Priority Register */
+ u8 dchpri4; /* 0x104 Channel 4 Priority Register */
+ u8 dchpri5; /* 0x105 Channel 5 Priority Register */
+ u8 dchpri6; /* 0x106 Channel 6 Priority Register */
+ u8 dchpri7; /* 0x107 Channel 7 Priority Register */
+ u8 dchpri8; /* 0x108 Channel 8 Priority Register */
+ u8 dchpri9; /* 0x109 Channel 9 Priority Register */
+ u8 dchpri10; /* 0x110 Channel 10 Priority Register */
+ u8 dchpri11; /* 0x111 Channel 11 Priority Register */
+ u8 dchpri12; /* 0x112 Channel 12 Priority Register */
+ u8 dchpri13; /* 0x113 Channel 13 Priority Register */
+ u8 dchpri14; /* 0x114 Channel 14 Priority Register */
+ u8 dchpri15; /* 0x115 Channel 15 Priority Register */
+} edma_t;
+
+/* TCD - eDMA*/
+typedef struct tcd_ctrl {
+ u32 saddr; /* 0x00 Source Address */
+ u16 attr; /* 0x04 Transfer Attributes */
+ u16 soff; /* 0x06 Signed Source Address Offset */
+ u32 nbytes; /* 0x08 Minor Byte Count */
+ u32 slast; /* 0x0C Last Source Address Adjustment */
+ u32 daddr; /* 0x10 Destination address */
+ u16 citer; /* 0x14 Current Minor Loop Link, Major Loop Count */
+ u16 doff; /* 0x16 Signed Destination Address Offset */
+ u32 dlast_sga; /* 0x18 Last Destination Address Adjustment/Scatter Gather Address */
+ u16 biter; /* 0x1C Beginning Minor Loop Link, Major Loop Count */
+ u16 csr; /* 0x1E Control and Status */
+} tcd_st;
+
+typedef struct tcd_multiple {
+ tcd_st tcd[16];
+} tcd_t;
+
+/* Interrupt module registers */
+typedef struct int0_ctrl {
+ /* Interrupt Controller 0 */
+ u32 iprh0; /* 0x00 Pending Register High */
+ u32 iprl0; /* 0x04 Pending Register Low */
+ u32 imrh0; /* 0x08 Mask Register High */
+ u32 imrl0; /* 0x0C Mask Register Low */
+ u32 frch0; /* 0x10 Force Register High */
+ u32 frcl0; /* 0x14 Force Register Low */
+ u16 res1; /* 0x18 - 0x19 */
+ u16 icfg0; /* 0x1A Configuration Register */
+ u8 simr0; /* 0x1C Set Interrupt Mask */
+ u8 cimr0; /* 0x1D Clear Interrupt Mask */
+ u8 clmask0; /* 0x1E Current Level Mask */
+ u8 slmask; /* 0x1F Saved Level Mask */
+ u32 res2[8]; /* 0x20 - 0x3F */
+ u8 icr0[64]; /* 0x40 - 0x7F Control registers */
+ u32 res3[24]; /* 0x80 - 0xDF */
+ u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
+ u8 res4[3]; /* 0xE1 - 0xE3 */
+ u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
+ u8 res5[3]; /* 0xE5 - 0xE7 */
+ u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
+ u8 res6[3]; /* 0xE9 - 0xEB */
+ u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
+ u8 res7[3]; /* 0xED - 0xEF */
+ u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
+ u8 res8[3]; /* 0xF1 - 0xF3 */
+ u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
+ u8 res9[3]; /* 0xF5 - 0xF7 */
+ u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
+ u8 resa[3]; /* 0xF9 - 0xFB */
+ u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
+ u8 resb[3]; /* 0xFD - 0xFF */
+} int0_t;
+
+typedef struct int1_ctrl {
+ /* Interrupt Controller 1 */
+ u32 iprh1; /* 0x00 Pending Register High */
+ u32 iprl1; /* 0x04 Pending Register Low */
+ u32 imrh1; /* 0x08 Mask Register High */
+ u32 imrl1; /* 0x0C Mask Register Low */
+ u32 frch1; /* 0x10 Force Register High */
+ u32 frcl1; /* 0x14 Force Register Low */
+ u16 res1; /* 0x18 */
+ u16 icfg1; /* 0x1A Configuration Register */
+ u8 simr1; /* 0x1C Set Interrupt Mask */
+ u8 cimr1; /* 0x1D Clear Interrupt Mask */
+ u16 res2; /* 0x1E - 0x1F */
+ u32 res3[8]; /* 0x20 - 0x3F */
+ u8 icr1[64]; /* 0x40 - 0x7F */
+ u32 res4[24]; /* 0x80 - 0xDF */
+ u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
+ u8 res5[3]; /* 0xE1 - 0xE3 */
+ u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
+ u8 res6[3]; /* 0xE5 - 0xE7 */
+ u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
+ u8 res7[3]; /* 0xE9 - 0xEB */
+ u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
+ u8 res8[3]; /* 0xED - 0xEF */
+ u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
+ u8 res9[3]; /* 0xF1 - 0xF3 */
+ u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
+ u8 resa[3]; /* 0xF5 - 0xF7 */
+ u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
+ u8 resb[3]; /* 0xF9 - 0xFB */
+ u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
+ u8 resc[3]; /* 0xFD - 0xFF */
+} int1_t;
+
+typedef struct intgack_ctrl1 {
+ /* Global IACK Registers */
+ u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */
+ u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
+} intgack_t;
+
+/*I2C module registers */
+typedef struct i2c_ctrl {
+ u8 adr; /* 0x00 address register */
+ u8 res1[3]; /* 0x01 - 0x03 */
+ u8 fdr; /* 0x04 frequency divider register */
+ u8 res2[3]; /* 0x05 - 0x07 */
+ u8 cr; /* 0x08 control register */
+ u8 res3[3]; /* 0x09 - 0x0B */
+ u8 sr; /* 0x0C status register */
+ u8 res4[3]; /* 0x0D - 0x0F */
+ u8 dr; /* 0x10 data register */
+ u8 res5[3]; /* 0x11 - 0x13 */
+} i2c_t;
+
+/* QSPI module registers */
+typedef struct qspi_ctrl {
+ u16 qmr; /* Mode register */
+ u16 res1;
+ u16 qdlyr; /* Delay register */
+ u16 res2;
+ u16 qwr; /* Wrap register */
+ u16 res3;
+ u16 qir; /* Interrupt register */
+ u16 res4;
+ u16 qar; /* Address register */
+ u16 res5;
+ u16 qdr; /* Data register */
+ u16 res6;
+} qspi_t;
+
+/* PWM module registers */
+typedef struct pwm_ctrl {
+ u8 en; /* 0x00 PWM Enable Register */
+ u8 pol; /* 0x01 Polarity Register */
+ u8 clk; /* 0x02 Clock Select Register */
+ u8 prclk; /* 0x03 Prescale Clock Select Register */
+ u8 cae; /* 0x04 Center Align Enable Register */
+ u8 ctl; /* 0x05 Control Register */
+ u8 res1[2]; /* 0x06 - 0x07 */
+ u8 scla; /* 0x08 Scale A register */
+ u8 sclb; /* 0x09 Scale B register */
+ u8 res2[2]; /* 0x0A - 0x0B */
+ u8 cnt0; /* 0x0C Channel 0 Counter register */
+ u8 cnt1; /* 0x0D Channel 1 Counter register */
+ u8 cnt2; /* 0x0E Channel 2 Counter register */
+ u8 cnt3; /* 0x0F Channel 3 Counter register */
+ u8 cnt4; /* 0x10 Channel 4 Counter register */
+ u8 cnt5; /* 0x11 Channel 5 Counter register */
+ u8 cnt6; /* 0x12 Channel 6 Counter register */
+ u8 cnt7; /* 0x13 Channel 7 Counter register */
+ u8 per0; /* 0x14 Channel 0 Period register */
+ u8 per1; /* 0x15 Channel 1 Period register */
+ u8 per2; /* 0x16 Channel 2 Period register */
+ u8 per3; /* 0x17 Channel 3 Period register */
+ u8 per4; /* 0x18 Channel 4 Period register */
+ u8 per5; /* 0x19 Channel 5 Period register */
+ u8 per6; /* 0x1A Channel 6 Period register */
+ u8 per7; /* 0x1B Channel 7 Period register */
+ u8 dty0; /* 0x1C Channel 0 Duty register */
+ u8 dty1; /* 0x1D Channel 1 Duty register */
+ u8 dty2; /* 0x1E Channel 2 Duty register */
+ u8 dty3; /* 0x1F Channel 3 Duty register */
+ u8 dty4; /* 0x20 Channel 4 Duty register */
+ u8 dty5; /* 0x21 Channel 5 Duty register */
+ u8 dty6; /* 0x22 Channel 6 Duty register */
+ u8 dty7; /* 0x23 Channel 7 Duty register */
+ u8 sdn; /* 0x24 Shutdown register */
+ u8 res3[3]; /* 0x25 - 0x27 */
+} pwm_t;
+
+/* Edge Port module registers */
+typedef struct eport_ctrl {
+ u16 par; /* 0x00 Pin Assignment Register */
+ u8 ddar; /* 0x02 Data Direction Register */
+ u8 ier; /* 0x03 Interrupt Enable Register */
+ u8 dr; /* 0x04 Data Register */
+ u8 pdr; /* 0x05 Pin Data Register */
+ u8 fr; /* 0x06 Flag_Register */
+ u8 res1;
+} eport_t;
+
+/* Watchdog registers */
+typedef struct wdog_ctrl {
+ u16 cr; /* 0x00 Control register */
+ u16 mr; /* 0x02 Modulus register */
+ u16 cntr; /* 0x04 Count register */
+ u16 sr; /* 0x06 Service register */
+} wdog_t;
+
+/*Chip configuration module registers */
+typedef struct ccm_ctrl {
+ u8 rstctrl; /* 0x00 Reset Controller register */
+ u8 rststat; /* 0x01 Reset Status register */
+ u16 res1; /* 0x02 - 0x03 */
+ u16 ccr; /* 0x04 Chip configuration register */
+ u16 res2; /* 0x06 */
+ u16 rcon; /* 0x08 Rreset configuration register */
+ u16 cir; /* 0x0A Chip identification register */
+ u32 res3; /* 0x0C */
+ u16 misccr; /* 0x10 Miscellaneous control register */
+ u16 cdr; /* 0x12 Clock divider register */
+ u16 uhcsr; /* 0x14 USB Host controller status register */
+ u16 uocsr; /* 0x16 USB On-the-Go Controller Status Register */
+} ccm_t;
+
+/* GPIO port registers */
+typedef struct gpio_ctrl {
+ /* Port Output Data Registers */
+ u8 podr_fech; /* 0x00 */
+ u8 podr_fecl; /* 0x01 */
+ u8 podr_ssi; /* 0x02 */
+ u8 podr_busctl; /* 0x03 */
+ u8 podr_be; /* 0x04 */
+ u8 podr_cs; /* 0x05 */
+ u8 podr_pwm; /* 0x06 */
+ u8 podr_feci2c; /* 0x07 */
+ u8 res1; /* 0x08 */
+ u8 podr_uart; /* 0x09 */
+ u8 podr_qspi; /* 0x0A */
+ u8 podr_timer; /* 0x0B */
+ u8 res2; /* 0x0C */
+ u8 podr_lcddatah; /* 0x0D */
+ u8 podr_lcddatam; /* 0x0E */
+ u8 podr_lcddatal; /* 0x0F */
+ u8 podr_lcdctlh; /* 0x10 */
+ u8 podr_lcdctll; /* 0x11 */
+
+ /* Port Data Direction Registers */
+ u16 res3; /* 0x12 - 0x13 */
+ u8 pddr_fech; /* 0x14 */
+ u8 pddr_fecl; /* 0x15 */
+ u8 pddr_ssi; /* 0x16 */
+ u8 pddr_busctl; /* 0x17 */
+ u8 pddr_be; /* 0x18 */
+ u8 pddr_cs; /* 0x19 */
+ u8 pddr_pwm; /* 0x1A */
+ u8 pddr_feci2c; /* 0x1B */
+ u8 res4; /* 0x1C */
+ u8 pddr_uart; /* 0x1D */
+ u8 pddr_qspi; /* 0x1E */
+ u8 pddr_timer; /* 0x1F */
+ u8 res5; /* 0x20 */
+ u8 pddr_lcddatah; /* 0x21 */
+ u8 pddr_lcddatam; /* 0x22 */
+ u8 pddr_lcddatal; /* 0x23 */
+ u8 pddr_lcdctlh; /* 0x24 */
+ u8 pddr_lcdctll; /* 0x25 */
+ u16 res6; /* 0x26 - 0x27 */
+
+ /* Port Data Direction Registers */
+ u8 ppd_fech; /* 0x28 */
+ u8 ppd_fecl; /* 0x29 */
+ u8 ppd_ssi; /* 0x2A */
+ u8 ppd_busctl; /* 0x2B */
+ u8 ppd_be; /* 0x2C */
+ u8 ppd_cs; /* 0x2D */
+ u8 ppd_pwm; /* 0x2E */
+ u8 ppd_feci2c; /* 0x2F */
+ u8 res7; /* 0x30 */
+ u8 ppd_uart; /* 0x31 */
+ u8 ppd_qspi; /* 0x32 */
+ u8 ppd_timer; /* 0x33 */
+ u8 res8; /* 0x34 */
+ u8 ppd_lcddatah; /* 0x35 */
+ u8 ppd_lcddatam; /* 0x36 */
+ u8 ppd_lcddatal; /* 0x37 */
+ u8 ppd_lcdctlh; /* 0x38 */
+ u8 ppd_lcdctll; /* 0x39 */
+ u16 res9; /* 0x3A - 0x3B */
+
+ /* Port Clear Output Data Registers */
+ u8 pclrr_fech; /* 0x3C */
+ u8 pclrr_fecl; /* 0x3D */
+ u8 pclrr_ssi; /* 0x3E */
+ u8 pclrr_busctl; /* 0x3F */
+ u8 pclrr_be; /* 0x40 */
+ u8 pclrr_cs; /* 0x41 */
+ u8 pclrr_pwm; /* 0x42 */
+ u8 pclrr_feci2c; /* 0x43 */
+ u8 res10; /* 0x44 */
+ u8 pclrr_uart; /* 0x45 */
+ u8 pclrr_qspi; /* 0x46 */
+ u8 pclrr_timer; /* 0x47 */
+ u8 res11; /* 0x48 */
+ u8 pclrr_lcddatah; /* 0x49 */
+ u8 pclrr_lcddatam; /* 0x4A */
+ u8 pclrr_lcddatal; /* 0x4B */
+ u8 pclrr_lcdctlh; /* 0x4C */
+ u8 pclrr_lcdctll; /* 0x4D */
+ u16 res12; /* 0x4E - 0x4F */
+
+ /* Pin Assignment Registers */
+ u8 par_fec; /* 0x50 */
+ u8 par_pwm; /* 0x51 */
+ u8 par_busctl; /* 0x52 */
+ u8 par_feci2c; /* 0x53 */
+ u8 par_be; /* 0x54 */
+ u8 par_cs; /* 0x55 */
+ u16 par_ssi; /* 0x56 */
+ u16 par_uart; /* 0x58 */
+ u16 par_qspi; /* 0x5A */
+ u8 par_timer; /* 0x5C */
+ u8 par_lcddata; /* 0x5D */
+ u16 par_lcdctl; /* 0x5E */
+ u16 par_irq; /* 0x60 */
+ u16 res16; /* 0x62 - 0x63 */
+
+ /* Mode Select Control Registers */
+ u8 mscr_flexbus; /* 0x64 */
+ u8 mscr_sdram; /* 0x65 */
+ u16 res17; /* 0x66 - 0x67 */
+
+ /* Drive Strength Control Registers */
+ u8 dscr_i2c; /* 0x68 */
+ u8 dscr_pwm; /* 0x69 */
+ u8 dscr_fec; /* 0x6A */
+ u8 dscr_uart; /* 0x6B */
+ u8 dscr_qspi; /* 0x6C */
+ u8 dscr_timer; /* 0x6D */
+ u8 dscr_ssi; /* 0x6E */
+ u8 dscr_lcd; /* 0x6F */
+ u8 dscr_debug; /* 0x70 */
+ u8 dscr_clkrst; /* 0x71 */
+ u8 dscr_irq; /* 0x72 */
+} gpio_t;
+
+/* LCD module registers */
+typedef struct lcd_ctrl {
+ u32 ssar; /* 0x00 Screen Start Address Register */
+ u32 sr; /* 0x04 LCD Size Register */
+ u32 vpw; /* 0x08 Virtual Page Width Register */
+ u32 cpr; /* 0x0C Cursor Position Register */
+ u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */
+ u32 ccmr; /* 0x14 Color Cursor Mapping Register */
+ u32 pcr; /* 0x18 Panel Configuration Register */
+ u32 hcr; /* 0x1C Horizontal Configuration Register */
+ u32 vcr; /* 0x20 Vertical Configuration Register */
+ u32 por; /* 0x24 Panning Offset Register */
+ u32 scr; /* 0x28 Sharp Configuration Register */
+ u32 pccr; /* 0x2C PWM Contrast Control Register */
+ u32 dcr; /* 0x30 DMA Control Register */
+ u32 rmcr; /* 0x34 Refresh Mode Control Register */
+ u32 icr; /* 0x38 Refresh Mode Control Register */
+ u32 ier; /* 0x3C Interrupt Enable Register */
+ u32 isr; /* 0x40 Interrupt Status Register */
+ u32 res[4];
+ u32 gwsar; /* 0x50 Graphic Window Start Address Register */
+ u32 gwsr; /* 0x54 Graphic Window Size Register */
+ u32 gwvpw; /* 0x58 Graphic Window Virtual Page Width Register */
+ u32 gwpor; /* 0x5C Graphic Window Panning Offset Register */
+ u32 gwpr; /* 0x60 Graphic Window Position Register */
+ u32 gwcr; /* 0x64 Graphic Window Control Register */
+ u32 gwdcr; /* 0x68 Graphic Window DMA Control Register */
+} lcd_t;
+
+typedef struct lcdbg_ctrl {
+ u32 bglut[255];
+} lcdbg_t;
+
+typedef struct lcdgw_ctrl {
+ u32 gwlut[255];
+} lcdgw_t;
+
+/* USB OTG module registers */
+typedef struct usb_otg {
+ u32 id; /* 0x000 Identification Register */
+ u32 hwgeneral; /* 0x004 General HW Parameters */
+ u32 hwhost; /* 0x008 Host HW Parameters */
+ u32 hwdev; /* 0x00C Device HW parameters */
+ u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */
+ u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */
+ u32 res1[58]; /* 0x18 - 0xFF */
+ u8 caplength; /* 0x100 Capability Register Length */
+ u8 res2; /* 0x101 */
+ u16 hciver; /* 0x102 Host Interface Version Number */
+ u32 hcsparams; /* 0x104 Host Structural Parameters */
+ u32 hccparams; /* 0x108 Host Capability Parameters */
+ u32 res3[5]; /* 0x10C - 0x11F */
+ u16 dciver; /* 0x120 Device Interface Version Number */
+ u16 res4; /* 0x122 */
+ u32 dccparams; /* 0x124 Device Capability Parameters */
+ u32 res5[6]; /* 0x128 - 0x13F */
+ u32 cmd; /* 0x140 USB Command */
+ u32 sts; /* 0x144 USB Status */
+ u32 intr; /* 0x148 USB Interrupt Enable */
+ u32 frindex; /* 0x14C USB Frame Index */
+ u32 res6; /* 0x150 */
+ u32 prd_dev; /* 0x154 Periodic Frame List Base or Device Address */
+ u32 aync_ep; /* 0x158 Current Asynchronous List or Address at Endpoint List Address */
+ u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control */
+ u32 burstsize; /* 0x160 Master Interface Data Burst Size */
+ u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control */
+ u32 res7[6]; /* 0x168 - 0x17F */
+ u32 cfgflag; /* 0x180 Configure Flag Register */
+ u32 portsc1; /* 0x184 Port Status/Control */
+ u32 res8[7]; /* 0x188 - 0x1A3 */
+ u32 otgsc; /* 0x1A4 On The Go Status and Control */
+ u32 mode; /* 0x1A8 USB mode register */
+ u32 eptsetstat; /* 0x1AC Endpoint Setup status */
+ u32 eptprime; /* 0x1B0 Endpoint initialization */
+ u32 eptflush; /* 0x1B4 Endpoint de-initialize */
+ u32 eptstat; /* 0x1B8 Endpoint status */
+ u32 eptcomplete; /* 0x1BC Endpoint Complete */
+ u32 eptctrl0; /* 0x1C0 Endpoint control 0 */
+ u32 eptctrl1; /* 0x1C4 Endpoint control 1 */
+ u32 eptctrl2; /* 0x1C8 Endpoint control 2 */
+ u32 eptctrl3; /* 0x1CC Endpoint control 3 */
+} usbotg_t;
+
+/* USB Host module registers */
+typedef struct usb_host {
+ u32 id; /* 0x000 Identification Register */
+ u32 hwgeneral; /* 0x004 General HW Parameters */
+ u32 hwhost; /* 0x008 Host HW Parameters */
+ u32 res1; /* 0x0C */
+ u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */
+ u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */
+ u32 res2[58]; /* 0x18 - 0xFF */
+
+ /* Host Controller Capability Register */
+ u8 caplength; /* 0x100 Capability Register Length */
+ u8 res3; /* 0x101 */
+ u16 hciver; /* 0x102 Host Interface Version Number */
+ u32 hcsparams; /* 0x104 Host Structural Parameters */
+ u32 hccparams; /* 0x108 Host Capability Parameters */
+ u32 res4[13]; /* 0x10C - 0x13F */
+
+ /* Host Controller Operational Register */
+ u32 cmd; /* 0x140 USB Command */
+ u32 sts; /* 0x144 USB Status */
+ u32 intr; /* 0x148 USB Interrupt Enable */
+ u32 frindex; /* 0x14C USB Frame Index */
+ u32 res5; /* 0x150 (ctrl segment register in EHCI spec) */
+ u32 prdlst; /* 0x154 Periodic Frame List Base Address */
+ u32 aynclst; /* 0x158 Current Asynchronous List Address */
+ u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control (non-ehci) */
+ u32 burstsize; /* 0x160 Master Interface Data Burst Size (non-ehci) */
+ u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control (non-ehci) */
+ u32 res6[6]; /* 0x168 - 0x17F */
+ u32 cfgflag; /* 0x180 Configure Flag Register */
+ u32 portsc1; /* 0x184 Port Status/Control */
+ u32 res7[8]; /* 0x188 - 0x1A7 */
+
+ /* non-ehci registers */
+ u32 mode; /* 0x1A8 USB mode register */
+ u32 eptsetstat; /* 0x1AC Endpoint Setup status */
+ u32 eptprime; /* 0x1B0 Endpoint initialization */
+ u32 eptflush; /* 0x1B4 Endpoint de-initialize */
+ u32 eptstat; /* 0x1B8 Endpoint status */
+ u32 eptcomplete; /* 0x1BC Endpoint Complete */
+ u32 eptctrl0; /* 0x1C0 Endpoint control 0 */
+ u32 eptctrl1; /* 0x1C4 Endpoint control 1 */
+ u32 eptctrl2; /* 0x1C8 Endpoint control 2 */
+ u32 eptctrl3; /* 0x1CC Endpoint control 3 */
+} usbhost_t;
+
+/* SDRAM controller registers */
+typedef struct sdram_ctrl {
+ u32 mode; /* 0x00 Mode/Extended Mode register */
+ u32 ctrl; /* 0x04 Control register */
+ u32 cfg1; /* 0x08 Configuration register 1 */
+ u32 cfg2; /* 0x0C Configuration register 2 */
+ u32 res1[64]; /* 0x10 - 0x10F */
+ u32 cs0; /* 0x110 Chip Select 0 Configuration */
+ u32 cs1; /* 0x114 Chip Select 1 Configuration */
+} sdram_t;
+
+/* Synchronous serial interface */
+typedef struct ssi_ctrl {
+ u32 tx0; /* 0x00 Transmit Data Register 0 */
+ u32 tx1; /* 0x04 Transmit Data Register 1 */
+ u32 rx0; /* 0x08 Receive Data Register 0 */
+ u32 rx1; /* 0x0C Receive Data Register 1 */
+ u32 cr; /* 0x10 Control Register */
+ u32 isr; /* 0x14 Interrupt Status Register */
+ u32 ier; /* 0x18 Interrupt Enable Register */
+ u32 tcr; /* 0x1C Transmit Configuration Register */
+ u32 rcr; /* 0x20 Receive Configuration Register */
+ u32 ccr; /* 0x24 Clock Control Register */
+ u32 res1; /* 0x28 */
+ u32 fcsr; /* 0x2C FIFO Control/Status Register */
+ u32 res2[2]; /* 0x30 - 0x37 */
+ u32 acr; /* 0x38 AC97 Control Register */
+ u32 acadd; /* 0x3C AC97 Command Address Register */
+ u32 acdat; /* 0x40 AC97 Command Data Register */
+ u32 atag; /* 0x44 AC97 Tag Register */
+ u32 tmask; /* 0x48 Transmit Time Slot Mask Register */
+ u32 rmask; /* 0x4C Receive Time Slot Mask Register */
+} ssi_t;
+
+/* Clock Module registers */
+typedef struct pll_ctrl {
+ u8 podr; /* 0x00 Output Divider Register */
+ u8 res1[3];
+ u8 pcr; /* 0x04 Control Register */
+ u8 res2[3];
+ u8 pmdr; /* 0x08 Modulation Divider Register */
+ u8 res3[3];
+ u8 pfdr; /* 0x0C Feedback Divider Register */
+ u8 res4[3];
+} pll_t;
+
+#endif /* __IMMAP_5329__ */
diff --git a/include/asm-m68k/immap_5445x.h b/include/asm-m68k/immap_5445x.h
new file mode 100644
index 0000000..d091d7b
--- /dev/null
+++ b/include/asm-m68k/immap_5445x.h
@@ -0,0 +1,937 @@
+/*
+ * MCF5445x Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5445X__
+#define __IMMAP_5445X__
+
+/* Module Base Addresses */
+#define MMAP_SCM1 0xFC000000
+#define MMAP_XBS 0xFC004000
+#define MMAP_FBCS 0xFC008000
+#define MMAP_FEC0 0xFC030000
+#define MMAP_FEC1 0xFC034000
+#define MMAP_RTC 0xFC03C000
+#define MMAP_EDMA 0xFC044000
+#define MMAP_INTC0 0xFC048000
+#define MMAP_INTC1 0xFC04C000
+#define MMAP_IACK 0xFC054000
+#define MMAP_I2C 0xFC058000
+#define MMAP_DSPI 0xFC05C000
+#define MMAP_UART0 0xFC060000
+#define MMAP_UART1 0xFC064000
+#define MMAP_UART2 0xFC068000
+#define MMAP_DTMR0 0xFC070000
+#define MMAP_DTMR1 0xFC074000
+#define MMAP_DTMR2 0xFC078000
+#define MMAP_DTMR3 0xFC07C000
+#define MMAP_PIT0 0xFC080000
+#define MMAP_PIT1 0xFC084000
+#define MMAP_PIT2 0xFC088000
+#define MMAP_PIT3 0xFC08C000
+#define MMAP_EPORT 0xFC094000
+#define MMAP_WTM 0xFC098000
+#define MMAP_SBF 0xFC0A0000
+#define MMAP_RCM 0xFC0A0000
+#define MMAP_CCM 0xFC0A0000
+#define MMAP_GPIO 0xFC0A4000
+#define MMAP_PCI 0xFC0A8000
+#define MMAP_PCIARB 0xFC0AC000
+#define MMAP_RNG 0xFC0B4000
+#define MMAP_SDRAM 0xFC0B8000
+#define MMAP_SSI 0xFC0BC000
+#define MMAP_PLL 0xFC0C4000
+#define MMAP_ATA 0x90000000
+
+/*********************************************************************
+* ATA
+*********************************************************************/
+
+typedef struct atac {
+ /* PIO */
+ u8 toff; /* 0x00 */
+ u8 ton; /* 0x01 */
+ u8 t1; /* 0x02 */
+ u8 t2w; /* 0x03 */
+ u8 t2r; /* 0x04 */
+ u8 ta; /* 0x05 */
+ u8 trd; /* 0x06 */
+ u8 t4; /* 0x07 */
+ u8 t9; /* 0x08 */
+
+ /* DMA */
+ u8 tm; /* 0x09 */
+ u8 tn; /* 0x0A */
+ u8 td; /* 0x0B */
+ u8 tk; /* 0x0C */
+ u8 tack; /* 0x0D */
+ u8 tenv; /* 0x0E */
+ u8 trp; /* 0x0F */
+ u8 tzah; /* 0x10 */
+ u8 tmli; /* 0x11 */
+ u8 tdvh; /* 0x12 */
+ u8 tdzfs; /* 0x13 */
+ u8 tdvs; /* 0x14 */
+ u8 tcvh; /* 0x15 */
+ u8 tss; /* 0x16 */
+ u8 tcyc; /* 0x17 */
+
+ /* FIFO */
+ u32 fifo32; /* 0x18 */
+ u16 fifo16; /* 0x1C */
+ u8 rsvd0[2];
+ u8 ffill; /* 0x20 */
+ u8 rsvd1[3];
+
+ /* ATA */
+ u8 cr; /* 0x24 */
+ u8 rsvd2[3];
+ u8 isr; /* 0x28 */
+ u8 rsvd3[3];
+ u8 ier; /* 0x2C */
+ u8 rsvd4[3];
+ u8 icr; /* 0x30 */
+ u8 rsvd5[3];
+ u8 falarm; /* 0x34 */
+ u8 rsvd6[106];
+} atac_t;
+
+/*********************************************************************
+* Cross-bar switch (XBS)
+*********************************************************************/
+
+typedef struct xbs {
+ u8 resv0[0x100];
+ u32 prs1; /* XBS Priority Register */
+ u8 resv1[0xC];
+ u32 crs1; /* XBS Control Register */
+ u8 resv2[0xEC];
+ u32 prs2; /* XBS Priority Register */
+ u8 resv3[0xC];
+ u32 crs2; /* XBS Control Register */
+ u8 resv4[0xEC];
+ u32 prs3; /* XBS Priority Register */
+ u8 resv5[0xC];
+ u32 crs3; /* XBS Control Register */
+ u8 resv6[0xEC];
+ u32 prs4; /* XBS Priority Register */
+ u8 resv7[0xC];
+ u32 crs4; /* XBS Control Register */
+ u8 resv8[0xEC];
+ u32 prs5; /* XBS Priority Register */
+ u8 resv9[0xC];
+ u32 crs5; /* XBS Control Register */
+ u8 resv10[0xEC];
+ u32 prs6; /* XBS Priority Register */
+ u8 resv11[0xC];
+ u32 crs6; /* XBS Control Register */
+ u8 resv12[0xEC];
+ u32 prs7; /* XBS Priority Register */
+ u8 resv13[0xC];
+ u32 crs7; /* XBS Control Register */
+} xbs_t;
+
+/*********************************************************************
+* FlexBus Chip Selects (FBCS)
+*********************************************************************/
+
+typedef struct fbcs {
+ u32 csar0; /* Chip-select Address Register */
+ u32 csmr0; /* Chip-select Mask Register */
+ u32 cscr0; /* Chip-select Control Register */
+ u32 csar1; /* Chip-select Address Register */
+ u32 csmr1; /* Chip-select Mask Register */
+ u32 cscr1; /* Chip-select Control Register */
+ u32 csar2; /* Chip-select Address Register */
+ u32 csmr2; /* Chip-select Mask Register */
+ u32 cscr2; /* Chip-select Control Register */
+ u32 csar3; /* Chip-select Address Register */
+ u32 csmr3; /* Chip-select Mask Register */
+ u32 cscr3; /* Chip-select Control Register */
+} fbcs_t;
+
+/*********************************************************************
+* Enhanced DMA (EDMA)
+*********************************************************************/
+
+typedef struct edma {
+ u32 cr;
+ u32 es;
+ u8 resv0[0x6];
+ u16 erq;
+ u8 resv1[0x6];
+ u16 eei;
+ u8 serq;
+ u8 cerq;
+ u8 seei;
+ u8 ceei;
+ u8 cint;
+ u8 cerr;
+ u8 ssrt;
+ u8 cdne;
+ u8 resv2[0x6];
+ u16 intr;
+ u8 resv3[0x6];
+ u16 err;
+ u8 resv4[0xD0];
+ u8 dchpri0;
+ u8 dchpri1;
+ u8 dchpri2;
+ u8 dchpri3;
+ u8 dchpri4;
+ u8 dchpri5;
+ u8 dchpri6;
+ u8 dchpri7;
+ u8 dchpri8;
+ u8 dchpri9;
+ u8 dchpri10;
+ u8 dchpri11;
+ u8 dchpri12;
+ u8 dchpri13;
+ u8 dchpri14;
+ u8 dchpri15;
+ u8 resv5[0xEF0];
+ u32 tcd0_saddr;
+ u16 tcd0_attr;
+ u16 tcd0_soff;
+ u32 tcd0_nbytes;
+ u32 tcd0_slast;
+ u32 tcd0_daddr;
+ union {
+ u16 tcd0_citer_elink;
+ u16 tcd0_citer;
+ };
+ u16 tcd0_doff;
+ u32 tcd0_dlast_sga;
+ union {
+ u16 tcd0_biter_elink;
+ u16 tcd0_biter;
+ };
+ u16 tcd0_csr;
+ u32 tcd1_saddr;
+ u16 tcd1_attr;
+ u16 tcd1_soff;
+ u32 tcd1_nbytes;
+ u32 tcd1_slast;
+ u32 tcd1_daddr;
+ union {
+ u16 tcd1_citer_elink;
+ u16 tcd1_citer;
+ };
+ u16 tcd1_doff;
+ u32 tcd1_dlast_sga;
+ union {
+ u16 tcd1_biter;
+ u16 tcd1_biter_elink;
+ };
+ u16 tcd1_csr;
+ u32 tcd2_saddr;
+ u16 tcd2_attr;
+ u16 tcd2_soff;
+ u32 tcd2_nbytes;
+ u32 tcd2_slast;
+ u32 tcd2_daddr;
+ union {
+ u16 tcd2_citer;
+ u16 tcd2_citer_elink;
+ };
+ u16 tcd2_doff;
+ u32 tcd2_dlast_sga;
+ union {
+ u16 tcd2_biter_elink;
+ u16 tcd2_biter;
+ };
+ u16 tcd2_csr;
+ u32 tcd3_saddr;
+ u16 tcd3_attr;
+ u16 tcd3_soff;
+ u32 tcd3_nbytes;
+ u32 tcd3_slast;
+ u32 tcd3_daddr;
+ union {
+ u16 tcd3_citer;
+ u16 tcd3_citer_elink;
+ };
+ u16 tcd3_doff;
+ u32 tcd3_dlast_sga;
+ union {
+ u16 tcd3_biter_elink;
+ u16 tcd3_biter;
+ };
+ u16 tcd3_csr;
+ u32 tcd4_saddr;
+ u16 tcd4_attr;
+ u16 tcd4_soff;
+ u32 tcd4_nbytes;
+ u32 tcd4_slast;
+ u32 tcd4_daddr;
+ union {
+ u16 tcd4_citer;
+ u16 tcd4_citer_elink;
+ };
+ u16 tcd4_doff;
+ u32 tcd4_dlast_sga;
+ union {
+ u16 tcd4_biter;
+ u16 tcd4_biter_elink;
+ };
+ u16 tcd4_csr;
+ u32 tcd5_saddr;
+ u16 tcd5_attr;
+ u16 tcd5_soff;
+ u32 tcd5_nbytes;
+ u32 tcd5_slast;
+ u32 tcd5_daddr;
+ union {
+ u16 tcd5_citer;
+ u16 tcd5_citer_elink;
+ };
+ u16 tcd5_doff;
+ u32 tcd5_dlast_sga;
+ union {
+ u16 tcd5_biter_elink;
+ u16 tcd5_biter;
+ };
+ u16 tcd5_csr;
+ u32 tcd6_saddr;
+ u16 tcd6_attr;
+ u16 tcd6_soff;
+ u32 tcd6_nbytes;
+ u32 tcd6_slast;
+ u32 tcd6_daddr;
+ union {
+ u16 tcd6_citer;
+ u16 tcd6_citer_elink;
+ };
+ u16 tcd6_doff;
+ u32 tcd6_dlast_sga;
+ union {
+ u16 tcd6_biter_elink;
+ u16 tcd6_biter;
+ };
+ u16 tcd6_csr;
+ u32 tcd7_saddr;
+ u16 tcd7_attr;
+ u16 tcd7_soff;
+ u32 tcd7_nbytes;
+ u32 tcd7_slast;
+ u32 tcd7_daddr;
+ union {
+ u16 tcd7_citer;
+ u16 tcd7_citer_elink;
+ };
+ u16 tcd7_doff;
+ u32 tcd7_dlast_sga;
+ union {
+ u16 tcd7_biter_elink;
+ u16 tcd7_biter;
+ };
+ u16 tcd7_csr;
+ u32 tcd8_saddr;
+ u16 tcd8_attr;
+ u16 tcd8_soff;
+ u32 tcd8_nbytes;
+ u32 tcd8_slast;
+ u32 tcd8_daddr;
+ union {
+ u16 tcd8_citer;
+ u16 tcd8_citer_elink;
+ };
+ u16 tcd8_doff;
+ u32 tcd8_dlast_sga;
+ union {
+ u16 tcd8_biter_elink;
+ u16 tcd8_biter;
+ };
+ u16 tcd8_csr;
+ u32 tcd9_saddr;
+ u16 tcd9_attr;
+ u16 tcd9_soff;
+ u32 tcd9_nbytes;
+ u32 tcd9_slast;
+ u32 tcd9_daddr;
+ union {
+ u16 tcd9_citer_elink;
+ u16 tcd9_citer;
+ };
+ u16 tcd9_doff;
+ u32 tcd9_dlast_sga;
+ union {
+ u16 tcd9_biter_elink;
+ u16 tcd9_biter;
+ };
+ u16 tcd9_csr;
+ u32 tcd10_saddr;
+ u16 tcd10_attr;
+ u16 tcd10_soff;
+ u32 tcd10_nbytes;
+ u32 tcd10_slast;
+ u32 tcd10_daddr;
+ union {
+ u16 tcd10_citer_elink;
+ u16 tcd10_citer;
+ };
+ u16 tcd10_doff;
+ u32 tcd10_dlast_sga;
+ union {
+ u16 tcd10_biter;
+ u16 tcd10_biter_elink;
+ };
+ u16 tcd10_csr;
+ u32 tcd11_saddr;
+ u16 tcd11_attr;
+ u16 tcd11_soff;
+ u32 tcd11_nbytes;
+ u32 tcd11_slast;
+ u32 tcd11_daddr;
+ union {
+ u16 tcd11_citer;
+ u16 tcd11_citer_elink;
+ };
+ u16 tcd11_doff;
+ u32 tcd11_dlast_sga;
+ union {
+ u16 tcd11_biter;
+ u16 tcd11_biter_elink;
+ };
+ u16 tcd11_csr;
+ u32 tcd12_saddr;
+ u16 tcd12_attr;
+ u16 tcd12_soff;
+ u32 tcd12_nbytes;
+ u32 tcd12_slast;
+ u32 tcd12_daddr;
+ union {
+ u16 tcd12_citer;
+ u16 tcd12_citer_elink;
+ };
+ u16 tcd12_doff;
+ u32 tcd12_dlast_sga;
+ union {
+ u16 tcd12_biter;
+ u16 tcd12_biter_elink;
+ };
+ u16 tcd12_csr;
+ u32 tcd13_saddr;
+ u16 tcd13_attr;
+ u16 tcd13_soff;
+ u32 tcd13_nbytes;
+ u32 tcd13_slast;
+ u32 tcd13_daddr;
+ union {
+ u16 tcd13_citer_elink;
+ u16 tcd13_citer;
+ };
+ u16 tcd13_doff;
+ u32 tcd13_dlast_sga;
+ union {
+ u16 tcd13_biter_elink;
+ u16 tcd13_biter;
+ };
+ u16 tcd13_csr;
+ u32 tcd14_saddr;
+ u16 tcd14_attr;
+ u16 tcd14_soff;
+ u32 tcd14_nbytes;
+ u32 tcd14_slast;
+ u32 tcd14_daddr;
+ union {
+ u16 tcd14_citer;
+ u16 tcd14_citer_elink;
+ };
+ u16 tcd14_doff;
+ u32 tcd14_dlast_sga;
+ union {
+ u16 tcd14_biter_elink;
+ u16 tcd14_biter;
+ };
+ u16 tcd14_csr;
+ u32 tcd15_saddr;
+ u16 tcd15_attr;
+ u16 tcd15_soff;
+ u32 tcd15_nbytes;
+ u32 tcd15_slast;
+ u32 tcd15_daddr;
+ union {
+ u16 tcd15_citer_elink;
+ u16 tcd15_citer;
+ };
+ u16 tcd15_doff;
+ u32 tcd15_dlast_sga;
+ union {
+ u16 tcd15_biter;
+ u16 tcd15_biter_elink;
+ };
+ u16 tcd15_csr;
+} edma_t;
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+
+typedef struct int0_ctrl {
+ u32 iprh0; /* 0x00 Pending Register High */
+ u32 iprl0; /* 0x04 Pending Register Low */
+ u32 imrh0; /* 0x08 Mask Register High */
+ u32 imrl0; /* 0x0C Mask Register Low */
+ u32 frch0; /* 0x10 Force Register High */
+ u32 frcl0; /* 0x14 Force Register Low */
+ u16 res1; /* 0x18 - 0x19 */
+ u16 icfg0; /* 0x1A Configuration Register */
+ u8 simr0; /* 0x1C Set Interrupt Mask */
+ u8 cimr0; /* 0x1D Clear Interrupt Mask */
+ u8 clmask0; /* 0x1E Current Level Mask */
+ u8 slmask; /* 0x1F Saved Level Mask */
+ u32 res2[8]; /* 0x20 - 0x3F */
+ u8 icr0[64]; /* 0x40 - 0x7F Control registers */
+ u32 res3[24]; /* 0x80 - 0xDF */
+ u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
+ u8 res4[3]; /* 0xE1 - 0xE3 */
+ u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
+ u8 res5[3]; /* 0xE5 - 0xE7 */
+ u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
+ u8 res6[3]; /* 0xE9 - 0xEB */
+ u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
+ u8 res7[3]; /* 0xED - 0xEF */
+ u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
+ u8 res8[3]; /* 0xF1 - 0xF3 */
+ u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
+ u8 res9[3]; /* 0xF5 - 0xF7 */
+ u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
+ u8 resa[3]; /* 0xF9 - 0xFB */
+ u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
+ u8 resb[3]; /* 0xFD - 0xFF */
+} int0_t;
+
+typedef struct int1_ctrl {
+ /* Interrupt Controller 1 */
+ u32 iprh1; /* 0x00 Pending Register High */
+ u32 iprl1; /* 0x04 Pending Register Low */
+ u32 imrh1; /* 0x08 Mask Register High */
+ u32 imrl1; /* 0x0C Mask Register Low */
+ u32 frch1; /* 0x10 Force Register High */
+ u32 frcl1; /* 0x14 Force Register Low */
+ u16 res1; /* 0x18 */
+ u16 icfg1; /* 0x1A Configuration Register */
+ u8 simr1; /* 0x1C Set Interrupt Mask */
+ u8 cimr1; /* 0x1D Clear Interrupt Mask */
+ u16 res2; /* 0x1E - 0x1F */
+ u32 res3[8]; /* 0x20 - 0x3F */
+ u8 icr1[64]; /* 0x40 - 0x7F */
+ u32 res4[24]; /* 0x80 - 0xDF */
+ u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
+ u8 res5[3]; /* 0xE1 - 0xE3 */
+ u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
+ u8 res6[3]; /* 0xE5 - 0xE7 */
+ u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
+ u8 res7[3]; /* 0xE9 - 0xEB */
+ u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
+ u8 res8[3]; /* 0xED - 0xEF */
+ u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
+ u8 res9[3]; /* 0xF1 - 0xF3 */
+ u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
+ u8 resa[3]; /* 0xF5 - 0xF7 */
+ u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
+ u8 resb[3]; /* 0xF9 - 0xFB */
+ u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
+ u8 resc[3]; /* 0xFD - 0xFF */
+} int1_t;
+
+/*********************************************************************
+* Global Interrupt Acknowledge (IACK)
+*********************************************************************/
+
+typedef struct iack {
+ u8 resv0[0xE0];
+ u8 gswiack;
+ u8 resv1[0x3];
+ u8 gl1iack;
+ u8 resv2[0x3];
+ u8 gl2iack;
+ u8 resv3[0x3];
+ u8 gl3iack;
+ u8 resv4[0x3];
+ u8 gl4iack;
+ u8 resv5[0x3];
+ u8 gl5iack;
+ u8 resv6[0x3];
+ u8 gl6iack;
+ u8 resv7[0x3];
+ u8 gl7iack;
+} iack_t;
+
+/*********************************************************************
+* DMA Serial Peripheral Interface (DSPI)
+*********************************************************************/
+
+typedef struct dspi {
+ u32 dmcr;
+ u8 resv0[0x4];
+ u32 dtcr;
+ u32 dctar0;
+ u32 dctar1;
+ u32 dctar2;
+ u32 dctar3;
+ u32 dctar4;
+ u32 dctar5;
+ u32 dctar6;
+ u32 dctar7;
+ u32 dsr;
+ u32 dirsr;
+ u32 dtfr;
+ u32 drfr;
+ u32 dtfdr0;
+ u32 dtfdr1;
+ u32 dtfdr2;
+ u32 dtfdr3;
+ u8 resv1[0x30];
+ u32 drfdr0;
+ u32 drfdr1;
+ u32 drfdr2;
+ u32 drfdr3;
+} dspi_t;
+
+/*********************************************************************
+* Edge Port Module (EPORT)
+*********************************************************************/
+
+typedef struct eport {
+ u16 eppar;
+ u8 epddr;
+ u8 epier;
+ u8 epdr;
+ u8 eppdr;
+ u8 epfr;
+} eport_t;
+
+/*********************************************************************
+* Watchdog Timer Modules (WTM)
+*********************************************************************/
+
+typedef struct wtm {
+ u16 wcr;
+ u16 wmr;
+ u16 wcntr;
+ u16 wsr;
+} wtm_t;
+
+/*********************************************************************
+* Serial Boot Facility (SBF)
+*********************************************************************/
+
+typedef struct sbf {
+ u8 resv0[0x18];
+ u16 sbfsr; /* Serial Boot Facility Status Register */
+ u8 resv1[0x6];
+ u16 sbfcr; /* Serial Boot Facility Control Register */
+} sbf_t;
+
+/*********************************************************************
+* Reset Controller Module (RCM)
+*********************************************************************/
+
+typedef struct rcm {
+ u8 rcr;
+ u8 rsr;
+} rcm_t;
+
+/*********************************************************************
+* Chip Configuration Module (CCM)
+*********************************************************************/
+
+typedef struct ccm {
+ u8 ccm_resv0[0x4];
+ u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */
+ u8 resv1[0x2];
+ u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */
+ u16 cir; /* Chip Identification Register (Read-only) */
+ u8 resv2[0x4];
+ u16 misccr; /* Miscellaneous Control Register */
+ u16 cdr; /* Clock Divider Register */
+ u16 uocsr; /* USB On-the-Go Controller Status Register */
+} ccm_t;
+
+/*********************************************************************
+* General Purpose I/O Module (GPIO)
+*********************************************************************/
+
+typedef struct gpio {
+ u8 podr_fec0h; /* FEC0 High Port Output Data Register */
+ u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
+ u8 podr_ssi; /* SSI Port Output Data Register */
+ u8 podr_fbctl; /* Flexbus Control Port Output Data Register */
+ u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */
+ u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */
+ u8 podr_dma; /* DMA Port Output Data Register */
+ u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */
+ u8 resv0[0x1];
+ u8 podr_uart; /* UART Port Output Data Register */
+ u8 podr_dspi; /* DSPI Port Output Data Register */
+ u8 podr_timer; /* Timer Port Output Data Register */
+ u8 podr_pci; /* PCI Port Output Data Register */
+ u8 podr_usb; /* USB Port Output Data Register */
+ u8 podr_atah; /* ATA High Port Output Data Register */
+ u8 podr_atal; /* ATA Low Port Output Data Register */
+ u8 podr_fec1h; /* FEC1 High Port Output Data Register */
+ u8 podr_fec1l; /* FEC1 Low Port Output Data Register */
+ u8 resv1[0x2];
+ u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */
+ u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */
+ u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */
+ u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */
+ u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */
+ u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */
+ u8 pddr_ssi; /* SSI Port Data Direction Register */
+ u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */
+ u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */
+ u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */
+ u8 pddr_dma; /* DMA Port Data Direction Register */
+ u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */
+ u8 resv2[0x1];
+ u8 pddr_uart; /* UART Port Data Direction Register */
+ u8 pddr_dspi; /* DSPI Port Data Direction Register */
+ u8 pddr_timer; /* Timer Port Data Direction Register */
+ u8 pddr_pci; /* PCI Port Data Direction Register */
+ u8 pddr_usb; /* USB Port Data Direction Register */
+ u8 pddr_atah; /* ATA High Port Data Direction Register */
+ u8 pddr_atal; /* ATA Low Port Data Direction Register */
+ u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */
+ u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */
+ u8 resv3[0x2];
+ u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */
+ u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */
+ u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */
+ u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */
+ u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */
+ u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */
+ u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */
+ u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */
+ u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */
+ u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */
+ u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */
+ u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */
+ u8 resv4[0x1];
+ u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */
+ u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */
+ u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */
+ u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */
+ u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */
+ u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */
+ u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */
+ u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */
+ u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */
+ u8 resv5[0x2];
+ u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */
+ u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */
+ u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */
+ u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */
+ u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */
+ u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */
+ u8 pclrr_ssi; /* SSI Port Clear Output Data Register */
+ u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */
+ u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */
+ u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */
+ u8 pclrr_dma; /* DMA Port Clear Output Data Register */
+ u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */
+ u8 resv6[0x1];
+ u8 pclrr_uart; /* UART Port Clear Output Data Register */
+ u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */
+ u8 pclrr_timer; /* Timer Port Clear Output Data Register */
+ u8 pclrr_pci; /* PCI Port Clear Output Data Register */
+ u8 pclrr_usb; /* USB Port Clear Output Data Register */
+ u8 pclrr_atah; /* ATA High Port Clear Output Data Register */
+ u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */
+ u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */
+ u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */
+ u8 resv7[0x2];
+ u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */
+ u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */
+ u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */
+ u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */
+ u8 par_fec; /* FEC Pin Assignment Register */
+ u8 par_dma; /* DMA Pin Assignment Register */
+ u8 par_fbctl; /* Flexbus Control Pin Assignment Register */
+ u8 par_dspi; /* DSPI Pin Assignment Register */
+ u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */
+ u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */
+ u8 par_timer; /* Time Pin Assignment Register */
+ u8 par_usb; /* USB Pin Assignment Register */
+ u8 resv8[0x1];
+ u8 par_uart; /* UART Pin Assignment Register */
+ u16 par_feci2c; /* FEC / I2C Pin Assignment Register */
+ u16 par_ssi; /* SSI Pin Assignment Register */
+ u16 par_ata; /* ATA Pin Assignment Register */
+ u8 par_irq; /* IRQ Pin Assignment Register */
+ u8 resv9[0x1];
+ u16 par_pci; /* PCI Pin Assignment Register */
+ u8 mscr_sdram; /* SDRAM Mode Select Control Register */
+ u8 mscr_pci; /* PCI Mode Select Control Register */
+ u8 resv10[0x2];
+ u8 dscr_i2c; /* I2C Drive Strength Control Register */
+ u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */
+ u8 dscr_fec; /* FEC Drive Strength Control Register */
+ u8 dscr_uart; /* UART Drive Strength Control Register */
+ u8 dscr_dspi; /* DSPI Drive Strength Control Register */
+ u8 dscr_timer; /* TIMER Drive Strength Control Register */
+ u8 dscr_ssi; /* SSI Drive Strength Control Register */
+ u8 dscr_dma; /* DMA Drive Strength Control Register */
+ u8 dscr_debug; /* DEBUG Drive Strength Control Register */
+ u8 dscr_reset; /* RESET Drive Strength Control Register */
+ u8 dscr_irq; /* IRQ Drive Strength Control Register */
+ u8 dscr_usb; /* USB Drive Strength Control Register */
+ u8 dscr_ata; /* ATA Drive Strength Control Register */
+} gpio_t;
+
+/*********************************************************************
+* Random Number Generator (RNG)
+*********************************************************************/
+
+typedef struct rng {
+ u32 rngcr;
+ u32 rngsr;
+ u32 rnger;
+ u32 rngout;
+} rng_t;
+
+/*********************************************************************
+* SDRAM Controller (SDRAMC)
+*********************************************************************/
+
+typedef struct sdramc {
+ u32 sdmr; /* SDRAM Mode/Extended Mode Register */
+ u32 sdcr; /* SDRAM Control Register */
+ u32 sdcfg1; /* SDRAM Configuration Register 1 */
+ u32 sdcfg2; /* SDRAM Chip Select Register */
+ u8 resv0[0x100];
+ u32 sdcs0; /* SDRAM Mode/Extended Mode Register */
+ u32 sdcs1; /* SDRAM Mode/Extended Mode Register */
+} sdramc_t;
+
+/*********************************************************************
+* Synchronous Serial Interface (SSI)
+*********************************************************************/
+
+typedef struct ssi {
+ u32 tx0;
+ u32 tx1;
+ u32 rx0;
+ u32 rx1;
+ u32 cr;
+ u32 isr;
+ u32 ier;
+ u32 tcr;
+ u32 rcr;
+ u32 ccr;
+ u8 resv0[0x4];
+ u32 fcsr;
+ u8 resv1[0x8];
+ u32 acr;
+ u32 acadd;
+ u32 acdat;
+ u32 atag;
+ u32 tmask;
+ u32 rmask;
+} ssi_t;
+
+/*********************************************************************
+* Phase Locked Loop (PLL)
+*********************************************************************/
+
+typedef struct pll {
+ u32 pcr; /* PLL Control Register */
+ u32 psr; /* PLL Status Register */
+} pll_t;
+
+typedef struct pci {
+ u32 idr; /* 0x00 Device Id / Vendor Id Register */
+ u32 scr; /* 0x04 Status / command Register */
+ u32 ccrir; /* 0x08 Class Code / Revision Id Register */
+ u32 cr1; /* 0x0c Configuration 1 Register */
+ u32 bar0; /* 0x10 Base address register 0 Register */
+ u32 bar1; /* 0x14 Base address register 1 Register */
+ u32 bar2; /* 0x18 Base address register 2 Register */
+ u32 bar3; /* 0x1c Base address register 3 Register */
+ u32 bar4; /* 0x20 Base address register 4 Register */
+ u32 bar5; /* 0x24 Base address register 5 Register */
+ u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */
+ u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */
+ u32 erbar; /* 0x30 Expansion ROM Base Address Register */
+ u32 cpr; /* 0x34 Capabilities Pointer Register */
+ u32 rsvd1; /* 0x38 */
+ u32 cr2; /* 0x3c Configuration Register 2 */
+ u32 rsvd2[8]; /* 0x40 - 0x5f */
+
+ /* General control / status registers */
+ u32 gscr; /* 0x60 Global Status / Control Register */
+ u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */
+ u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */
+ u32 tcr1; /* 0x6c Target Control 1 Register */
+ u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */
+ u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */
+ u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */
+ u32 rsvd3; /* 0x7c */
+ u32 iwcr; /* 0x80 Initiator Window Configuration Register */
+ u32 icr; /* 0x84 Initiator Control Register */
+ u32 isr; /* 0x88 Initiator Status Register */
+ u32 tcr2; /* 0x8c Target Control 2 Register */
+ u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */
+ u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */
+ u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */
+ u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */
+ u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */
+ u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */
+ u32 intr; /* 0xa8 Interrupt Register */
+ u32 rsvd4[19]; /* 0xac - 0xf7 */
+ u32 car; /* 0xf8 Configuration Address Register */
+} pci_t;
+
+typedef struct pci_arbiter {
+ /* Pci Arbiter Registers */
+ union {
+ u32 acr; /* Arbiter Control Register */
+ u32 asr; /* Arbiter Status Register */
+ };
+} pciarb_t;
+
+/* Register read/write struct */
+typedef struct scm1 {
+ u32 mpr; /* 0x00 Master Privilege Register */
+ u32 rsvd1[7];
+ u32 pacra; /* 0x20 Peripheral Access Control Register A */
+ u32 pacrb; /* 0x24 Peripheral Access Control Register B */
+ u32 pacrc; /* 0x28 Peripheral Access Control Register C */
+ u32 pacrd; /* 0x2C Peripheral Access Control Register D */
+ u32 rsvd2[4];
+ u32 pacre; /* 0x40 Peripheral Access Control Register E */
+ u32 pacrf; /* 0x44 Peripheral Access Control Register F */
+ u32 pacrg; /* 0x48 Peripheral Access Control Register G */
+} scm1_t;
+/********************************************************************/
+
+typedef struct rtcex {
+ u32 rsvd1[3];
+ u32 gocu;
+ u32 gocl;
+} rtcex_t;
+#endif /* __IMMAP_5445X__ */
diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h
index 7bbdefb..e14a581 100644
--- a/include/asm-m68k/io.h
+++ b/include/asm-m68k/io.h
@@ -1,8 +1,221 @@
-#ifndef __ASM_M68K_IO_H_
-#define __ASM_M68K_IO_H_
+/*
+ * IO header file
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
-static inline void sync(void)
+#ifndef __ASM_M68K_IO_H__
+#define __ASM_M68K_IO_H__
+
+#include <asm/byteorder.h>
+
+#define readb(addr) in_8((volatile u8 *)(addr))
+#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
+#if !defined(__BIG_ENDIAN)
+#define readw(addr) (*(volatile u16 *) (addr))
+#define readl(addr) (*(volatile u32 *) (addr))
+#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
+#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
+#else
+#define readw(addr) in_le16((volatile u16 *)(addr))
+#define readl(addr) in_le32((volatile u32 *)(addr))
+#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
+#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
+#endif
+
+/*
+ * The insw/outsw/insl/outsl macros don't do byte-swapping.
+ * They are only used in practice for transferring buffers which
+ * are arrays of bytes, and byte-swapping is not appropriate in
+ * that case. - paulus
+ */
+#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+#define inb(port) in_8((u8 *)((port)+_IO_BASE))
+#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
+#if !defined(__BIG_ENDIAN)
+#define inw(port) in_be16((u16 *)((port)+_IO_BASE))
+#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val))
+#define inl(port) in_be32((u32 *)((port)+_IO_BASE))
+#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val))
+#else
+#define inw(port) in_le16((u16 *)((port)+_IO_BASE))
+#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
+#define inl(port) in_le32((u32 *)((port)+_IO_BASE))
+#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
+#endif
+
+extern inline void _insb(volatile u8 * port, void *buf, int ns)
+{
+ u8 *data = (u8 *) buf;
+ while (ns--)
+ *data++ = *port;
+}
+
+extern inline void _outsb(volatile u8 * port, const void *buf, int ns)
+{
+ u8 *data = (u8 *) buf;
+ while (ns--)
+ *port = *data++;
+}
+
+extern inline void _insw(volatile u16 * port, void *buf, int ns)
+{
+ u16 *data = (u16 *) buf;
+ while (ns--)
+ *data++ = __sw16(*port);
+}
+
+extern inline void _outsw(volatile u16 * port, const void *buf, int ns)
+{
+ u16 *data = (u16 *) buf;
+ while (ns--) {
+ *port = __sw16(*data);
+ data++;
+ }
+}
+
+extern inline void _insl(volatile u32 * port, void *buf, int nl)
+{
+ u32 *data = (u32 *) buf;
+ while (nl--)
+ *data++ = __sw32(*port);
+}
+
+extern inline void _outsl(volatile u32 * port, const void *buf, int nl)
+{
+ u32 *data = (u32 *) buf;
+ while (nl--) {
+ *port = __sw32(*data);
+ data++;
+ }
+}
+
+extern inline void _insw_ns(volatile u16 * port, void *buf, int ns)
+{
+ u16 *data = (u16 *) buf;
+ while (ns--)
+ *data++ = *port;
+}
+
+extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns)
+{
+ u16 *data = (u16 *) buf;
+ while (ns--) {
+ *port = *data++;
+ }
+}
+
+extern inline void _insl_ns(volatile u32 * port, void *buf, int nl)
+{
+ u32 *data = (u32 *) buf;
+ while (nl--)
+ *data++ = *port;
+}
+
+extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl)
+{
+ u32 *data = (u32 *) buf;
+ while (nl--) {
+ *port = *data;
+ data++;
+ }
+}
+
+/*
+ * The *_ns versions below don't do byte-swapping.
+ * Neither do the standard versions now, these are just here
+ * for older code.
+ */
+#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+#define IO_SPACE_LIMIT ~0
+
+/*
+ * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
+ */
+extern inline int in_8(volatile u8 * addr)
+{
+ return (int)*addr;
+}
+
+extern inline void out_8(volatile u8 * addr, int val)
+{
+ *addr = (u8) val;
+}
+
+extern inline int in_le16(volatile u16 * addr)
+{
+ return __sw16(*addr);
+}
+
+extern inline int in_be16(volatile u16 * addr)
+{
+ return (*addr & 0xFFFF);
+}
+
+extern inline void out_le16(volatile u16 * addr, int val)
+{
+ *addr = __sw16(val);
+}
+
+extern inline void out_be16(volatile u16 * addr, int val)
+{
+ *addr = (u16) val;
+}
+
+extern inline unsigned in_le32(volatile u32 * addr)
{
+ return __sw32(*addr);
}
-#endif /* __ASM_M68K_IO_H_ */
+extern inline unsigned in_be32(volatile u32 * addr)
+{
+ return (*addr);
+}
+
+extern inline void out_le32(volatile unsigned *addr, int val)
+{
+ *addr = __sw32(val);
+}
+
+extern inline void out_be32(volatile unsigned *addr, int val)
+{
+ *addr = val;
+}
+
+static inline void sync(void)
+{
+ /* This sync function is for PowerPC or other architecture instruction
+ * ColdFire does not have this instruction. Dummy function, added for
+ * compatibility (CFI driver)
+ */
+}
+#endif /* __ASM_M68K_IO_H__ */
diff --git a/include/asm-m68k/m5235.h b/include/asm-m68k/m5235.h
new file mode 100644
index 0000000..b98b452
--- /dev/null
+++ b/include/asm-m68k/m5235.h
@@ -0,0 +1,905 @@
+/*
+ * mcf5329.h -- Definitions for Freescale Coldfire 5329
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef mcf5235_h
+#define mcf5235_h
+/****************************************************************************/
+
+/*********************************************************************
+* System Control Module (SCM)
+*********************************************************************/
+
+/* Bit definition and macros for SCM_IPSBAR */
+#define SCM_IPSBAR_BA(x) (((x)&0x03)<<30)
+#define SCM_IPSBAR_V (0x00000001)
+
+/* Bit definition and macros for SCM_RAMBAR */
+#define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16)
+#define SCM_RAMBAR_BDE (0x00000200)
+
+/* Bit definition and macros for SCM_CRSR */
+#define SCM_CRSR_EXT (0x80)
+
+/* Bit definitions and macros for SCM_CWCR */
+#define SCM_CWCR_CWE (0x80)
+#define SCM_CWCR_CWRI (0x40)
+#define SCM_CWCR_CWT(x) (((x)&0x07)<<3)
+#define SCM_CWCR_CWTA (0x04)
+#define SCM_CWCR_CWTAVAL (0x02)
+#define SCM_CWCR_CWTIC (0x01)
+
+/* Bit definitions and macros for SCM_LPICR */
+#define SCM_LPICR_ENBSTOP (0x80)
+#define SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4)
+#define SCM_LPICR_XLPM_IPL_ANY (0x00)
+#define SCM_LPICR_XLPM_IPL_L2_7 (0x10)
+#define SCM_LPICR_XLPM_IPL_L3_7 (0x20)
+#define SCM_LPICR_XLPM_IPL_L4_7 (0x30)
+#define SCM_LPICR_XLPM_IPL_L5_7 (0x40)
+#define SCM_LPICR_XLPM_IPL_L6_7 (0x50)
+#define SCM_LPICR_XLPM_IPL_L7 (0x70)
+
+/* Bit definitions and macros for SCM_DMAREQC */
+#define SCM_DMAREQC_EXT(x) (((x)&0x0F)<<16)
+#define SCM_DMAREQC_EXT_ETPU (0x00080000)
+#define SCM_DMAREQC_EXT_EXTDREQ2 (0x00040000)
+#define SCM_DMAREQC_EXT_EXTDREQ1 (0x00020000)
+#define SCM_DMAREQC_EXT_EXTDREQ0 (0x00010000)
+#define SCM_DMAREQC_DMAC3(x) (((x)&0x0F)<<12)
+#define SCM_DMAREQC_DMAC2(x) (((x)&0x0F)<<8)
+#define SCM_DMAREQC_DMAC1(x) (((x)&0x0F)<<4)
+#define SCM_DMAREQC_DMAC0(x) (((x)&0x0F))
+#define SCM_DMAREQC_DMACn_DTMR0 (0x04)
+#define SCM_DMAREQC_DMACn_DTMR1 (0x05)
+#define SCM_DMAREQC_DMACn_DTMR2 (0x06)
+#define SCM_DMAREQC_DMACn_DTMR3 (0x07)
+#define SCM_DMAREQC_DMACn_UART0RX (0x08)
+#define SCM_DMAREQC_DMACn_UART1RX (0x09)
+#define SCM_DMAREQC_DMACn_UART2RX (0x0A)
+#define SCM_DMAREQC_DMACn_UART0TX (0x0C)
+#define SCM_DMAREQC_DMACn_UART1TX (0x0D)
+#define SCM_DMAREQC_DMACn_UART3TX (0x0E)
+
+/* Bit definitions and macros for SCM_MPARK */
+#define SCM_MPARK_M2_P_EN (0x02000000)
+#define SCM_MPARK_M3_PRTY_MSK (0x00C00000)
+#define SCM_MPARK_M3_PRTY_4TH (0x00000000)
+#define SCM_MPARK_M3_PRTY_3RD (0x00400000)
+#define SCM_MPARK_M3_PRTY_2ND (0x00800000)
+#define SCM_MPARK_M3_PRTY_1ST (0x00C00000)
+#define SCM_MPARK_M2_PRTY_MSK (0x00300000)
+#define SCM_MPARK_M2_PRTY_4TH (0x00000000)
+#define SCM_MPARK_M2_PRTY_3RD (0x00100000)
+#define SCM_MPARK_M2_PRTY_2ND (0x00200000)
+#define SCM_MPARK_M2_PRTY_1ST (0x00300000)
+#define SCM_MPARK_M0_PRTY_MSK (0x000C0000)
+#define SCM_MPARK_M0_PRTY_4TH (0x00000000)
+#define SCM_MPARK_M0_PRTY_3RD (0x00040000)
+#define SCM_MPARK_M0_PRTY_2ND (0x00080000)
+#define SCM_MPARK_M0_PRTY_1ST (0x000C0000)
+#define SCM_MPARK_FIXED (0x00004000)
+#define SCM_MPARK_TIMEOUT (0x00002000)
+#define SCM_MPARK_PRKLAST (0x00001000)
+#define SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0F)<<8)
+
+/* Bit definitions and macros for SCM_MPR */
+#define SCM_MPR_MPR3 (0x08)
+#define SCM_MPR_MPR2 (0x04)
+#define SCM_MPR_MPR1 (0x02)
+#define SCM_MPR_MPR0 (0x01)
+
+/* Bit definitions and macros for SCM_PACRn */
+#define SCM_PACRn_LOCK1 (0x80)
+#define SCM_PACRn_ACCESSCTRL1(x) (((x)&0x07)<<4)
+#define SCM_PACRn_LOCK0 (0x08)
+#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07))
+
+/* Bit definitions and macros for SCM_GPACR */
+#define SCM_PACRn_LOCK (0x80)
+#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07))
+
+/*********************************************************************
+* SDRAM Controller (SDRAMC)
+*********************************************************************/
+/* Bit definitions and macros for SDRAMC_DCR */
+#define SDRAMC_DCR_NAM (0x2000)
+#define SDRAMC_DCR_COC (0x1000)
+#define SDRAMC_DCR_IS (0x0800)
+#define SDRAMC_DCR_RTIM_MASK (0x0C00)
+#define SDRAMC_DCR_RTIM_3CLKS (0x0000)
+#define SDRAMC_DCR_RTIM_6CLKS (0x0200)
+#define SDRAMC_DCR_RTIM_9CLKS (0x0400)
+#define SDRAMC_DCR_RC(x) (((x)&0xFF)<<8)
+
+/* Bit definitions and macros for SDRAMC_DARCn */
+#define SDRAMC_DARCn_BA(x) (((x)&0xFFFC)<<18)
+#define SDRAMC_DARCn_RE (0x00008000)
+#define SDRAMC_DARCn_CASL_MASK (0x00003000)
+#define SDRAMC_DARCn_CASL_C0 (0x00000000)
+#define SDRAMC_DARCn_CASL_C1 (0x00001000)
+#define SDRAMC_DARCn_CASL_C2 (0x00002000)
+#define SDRAMC_DARCn_CASL_C3 (0x00003000)
+#define SDRAMC_DARCn_CBM_MASK (0x00000700)
+#define SDRAMC_DARCn_CBM_CMD17 (0x00000000)
+#define SDRAMC_DARCn_CBM_CMD18 (0x00000100)
+#define SDRAMC_DARCn_CBM_CMD19 (0x00000200)
+#define SDRAMC_DARCn_CBM_CMD20 (0x00000300)
+#define SDRAMC_DARCn_CBM_CMD21 (0x00000400)
+#define SDRAMC_DARCn_CBM_CMD22 (0x00000500)
+#define SDRAMC_DARCn_CBM_CMD23 (0x00000600)
+#define SDRAMC_DARCn_CBM_CMD24 (0x00000700)
+#define SDRAMC_DARCn_IMRS (0x00000040)
+#define SDRAMC_DARCn_PS_MASK (0x00000030)
+#define SDRAMC_DARCn_PS_32 (0x00000000)
+#define SDRAMC_DARCn_PS_16 (0x00000010)
+#define SDRAMC_DARCn_PS_8 (0x00000020)
+#define SDRAMC_DARCn_IP (0x00000008)
+
+/* Bit definitions and macros for SDRAMC_DMRn */
+#define SDRAMC_DMRn_BAM(x) (((x)&0x3FFF)<<18)
+#define SDRAMC_DMRn_WP (0x00000100)
+#define SDRAMC_DMRn_V (0x00000001)
+
+/*********************************************************************
+* FlexBus Chip Selects (FBCS)
+*********************************************************************/
+/* Bit definitions and macros for FBCS_CSMR */
+#define FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<16)
+#define FBCS_CSMR_BAM_4G (0xFFFF0000)
+#define FBCS_CSMR_BAM_2G (0x7FFF0000)
+#define FBCS_CSMR_BAM_1G (0x3FFF0000)
+#define FBCS_CSMR_BAM_1024M (0x3FFF0000)
+#define FBCS_CSMR_BAM_512M (0x1FFF0000)
+#define FBCS_CSMR_BAM_256M (0x0FFF0000)
+#define FBCS_CSMR_BAM_128M (0x07FF0000)
+#define FBCS_CSMR_BAM_64M (0x03FF0000)
+#define FBCS_CSMR_BAM_32M (0x01FF0000)
+#define FBCS_CSMR_BAM_16M (0x00FF0000)
+#define FBCS_CSMR_BAM_8M (0x007F0000)
+#define FBCS_CSMR_BAM_4M (0x003F0000)
+#define FBCS_CSMR_BAM_2M (0x001F0000)
+#define FBCS_CSMR_BAM_1M (0x000F0000)
+#define FBCS_CSMR_BAM_1024K (0x000F0000)
+#define FBCS_CSMR_BAM_512K (0x00070000)
+#define FBCS_CSMR_BAM_256K (0x00030000)
+#define FBCS_CSMR_BAM_128K (0x00010000)
+#define FBCS_CSMR_BAM_64K (0x00000000)
+#define FBCS_CSMR_WP (0x00000100)
+#define FBCS_CSMR_V (0x00000001)
+
+/* Bit definitions and macros for FBCS_CSCR */
+#define FBCS_CSCR_SRWS(x) (((x)&0x03)<<14)
+#define FBCS_CSCR_IWS(x) (((x)&0x0F)<<10)
+#define FBCS_CSCR_AA (0x0100)
+#define FBCS_CSCR_PS_MASK (0x00C0)
+#define FBCS_CSCR_PS_32 (0x0000)
+#define FBCS_CSCR_PS_16 (0x0080)
+#define FBCS_CSCR_PS_8 (0x0040)
+#define FBCS_CSCR_BEM (0x0020)
+#define FBCS_CSCR_BSTR (0x0010)
+#define FBCS_CSCR_BSTW (0x0008)
+#define FBCS_CSCR_SWWS(x) ((x)&0x07)
+
+/*********************************************************************
+* Queued Serial Peripheral Interface (QSPI)
+*********************************************************************/
+/* Bit definitions and macros for QSPI_QMR */
+#define QSPI_QMR_MSTR (0x8000)
+#define QSPI_QMR_DOHIE (0x4000)
+#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
+#define QSPI_QMR_CPOL (0x0200)
+#define QSPI_QMR_CPHA (0x0100)
+#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
+
+/* Bit definitions and macros for QSPI_QDLYR */
+#define QSPI_QDLYR_SPE (0x8000)
+#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
+#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
+
+/* Bit definitions and macros for QSPI_QWR */
+#define QSPI_QWR_HALT (0x8000)
+#define QSPI_QWR_WREN (0x4000)
+#define QSPI_QWR_WRTO (0x2000)
+#define QSPI_QWR_CSIV (0x1000)
+#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
+#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
+
+/* Bit definitions and macros for QSPI_QIR */
+#define QSPI_QIR_WCEFB (0x8000)
+#define QSPI_QIR_ABRTB (0x4000)
+#define QSPI_QIR_ABRTL (0x1000)
+#define QSPI_QIR_WCEFE (0x0800)
+#define QSPI_QIR_ABRTE (0x0400)
+#define QSPI_QIR_SPIFE (0x0100)
+#define QSPI_QIR_WCEF (0x0008)
+#define QSPI_QIR_ABRT (0x0004)
+#define QSPI_QIR_SPIF (0x0001)
+
+/* Bit definitions and macros for QSPI_QAR */
+#define QSPI_QAR_ADDR(x) ((x)&0x003F)
+
+/* Bit definitions and macros for QSPI_QDR */
+#define QSPI_QDR_CONT (0x8000)
+#define QSPI_QDR_BITSE (0x4000)
+#define QSPI_QDR_DT (0x2000)
+#define QSPI_QDR_DSCK (0x1000)
+#define QSPI_QDR_QSPI_CS3 (0x0800)
+#define QSPI_QDR_QSPI_CS2 (0x0400)
+#define QSPI_QDR_QSPI_CS1 (0x0200)
+#define QSPI_QDR_QSPI_CS0 (0x0100)
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INT0_LO_RSVD0 (0)
+#define INT0_LO_EPORT1 (1)
+#define INT0_LO_EPORT2 (2)
+#define INT0_LO_EPORT3 (3)
+#define INT0_LO_EPORT4 (4)
+#define INT0_LO_EPORT5 (5)
+#define INT0_LO_EPORT6 (6)
+#define INT0_LO_EPORT7 (7)
+#define INT0_LO_SCM (8)
+#define INT0_LO_DMA0 (9)
+#define INT0_LO_DMA1 (10)
+#define INT0_LO_DMA2 (11)
+#define INT0_LO_DMA3 (12)
+#define INT0_LO_UART0 (13)
+#define INT0_LO_UART1 (14)
+#define INT0_LO_UART2 (15)
+#define INT0_LO_RSVD1 (16)
+#define INT0_LO_I2C (17)
+#define INT0_LO_QSPI (18)
+#define INT0_LO_DTMR0 (19)
+#define INT0_LO_DTMR1 (20)
+#define INT0_LO_DTMR2 (21)
+#define INT0_LO_DTMR3 (22)
+#define INT0_LO_FEC_TXF (23)
+#define INT0_LO_FEC_TXB (24)
+#define INT0_LO_FEC_UN (25)
+#define INT0_LO_FEC_RL (26)
+#define INT0_LO_FEC_RXF (27)
+#define INT0_LO_FEC_RXB (28)
+#define INT0_LO_FEC_MII (29)
+#define INT0_LO_FEC_LC (30)
+#define INT0_LO_FEC_HBERR (31)
+#define INT0_HI_FEC_GRA (32)
+#define INT0_HI_FEC_EBERR (33)
+#define INT0_HI_FEC_BABT (34)
+#define INT0_HI_FEC_BABR (35)
+#define INT0_HI_PIT0 (36)
+#define INT0_HI_PIT1 (37)
+#define INT0_HI_PIT2 (38)
+#define INT0_HI_PIT3 (39)
+#define INT0_HI_RNG (40)
+#define INT0_HI_SKHA (41)
+#define INT0_HI_MDHA (42)
+#define INT0_HI_CAN1_BUF0I (43)
+#define INT0_HI_CAN1_BUF1I (44)
+#define INT0_HI_CAN1_BUF2I (45)
+#define INT0_HI_CAN1_BUF3I (46)
+#define INT0_HI_CAN1_BUF4I (47)
+#define INT0_HI_CAN1_BUF5I (48)
+#define INT0_HI_CAN1_BUF6I (49)
+#define INT0_HI_CAN1_BUF7I (50)
+#define INT0_HI_CAN1_BUF8I (51)
+#define INT0_HI_CAN1_BUF9I (52)
+#define INT0_HI_CAN1_BUF10I (53)
+#define INT0_HI_CAN1_BUF11I (54)
+#define INT0_HI_CAN1_BUF12I (55)
+#define INT0_HI_CAN1_BUF13I (56)
+#define INT0_HI_CAN1_BUF14I (57)
+#define INT0_HI_CAN1_BUF15I (58)
+#define INT0_HI_CAN1_ERRINT (59)
+#define INT0_HI_CAN1_BOFFINT (60)
+/* 60-63 Reserved */
+
+/* 0 - 7 Reserved */
+#define INT1_LO_CAN1_BUF0I (8)
+#define INT1_LO_CAN1_BUF1I (9)
+#define INT1_LO_CAN1_BUF2I (10)
+#define INT1_LO_CAN1_BUF3I (11)
+#define INT1_LO_CAN1_BUF4I (12)
+#define INT1_LO_CAN1_BUF5I (13)
+#define INT1_LO_CAN1_BUF6I (14)
+#define INT1_LO_CAN1_BUF7I (15)
+#define INT1_LO_CAN1_BUF8I (16)
+#define INT1_LO_CAN1_BUF9I (17)
+#define INT1_LO_CAN1_BUF10I (18)
+#define INT1_LO_CAN1_BUF11I (19)
+#define INT1_LO_CAN1_BUF12I (20)
+#define INT1_LO_CAN1_BUF13I (21)
+#define INT1_LO_CAN1_BUF14I (22)
+#define INT1_LO_CAN1_BUF15I (23)
+#define INT1_LO_CAN1_ERRINT (24)
+#define INT1_LO_CAN1_BOFFINT (25)
+/* 26 Reserved */
+#define INT1_LO_ETPU_TC0F (27)
+#define INT1_LO_ETPU_TC1F (28)
+#define INT1_LO_ETPU_TC2F (29)
+#define INT1_LO_ETPU_TC3F (30)
+#define INT1_LO_ETPU_TC4F (31)
+#define INT1_HI_ETPU_TC5F (32)
+#define INT1_HI_ETPU_TC6F (33)
+#define INT1_HI_ETPU_TC7F (34)
+#define INT1_HI_ETPU_TC8F (35)
+#define INT1_HI_ETPU_TC9F (36)
+#define INT1_HI_ETPU_TC10F (37)
+#define INT1_HI_ETPU_TC11F (38)
+#define INT1_HI_ETPU_TC12F (39)
+#define INT1_HI_ETPU_TC13F (40)
+#define INT1_HI_ETPU_TC14F (41)
+#define INT1_HI_ETPU_TC15F (42)
+#define INT1_HI_ETPU_TC16F (43)
+#define INT1_HI_ETPU_TC17F (44)
+#define INT1_HI_ETPU_TC18F (45)
+#define INT1_HI_ETPU_TC19F (46)
+#define INT1_HI_ETPU_TC20F (47)
+#define INT1_HI_ETPU_TC21F (48)
+#define INT1_HI_ETPU_TC22F (49)
+#define INT1_HI_ETPU_TC23F (50)
+#define INT1_HI_ETPU_TC24F (51)
+#define INT1_HI_ETPU_TC25F (52)
+#define INT1_HI_ETPU_TC26F (53)
+#define INT1_HI_ETPU_TC27F (54)
+#define INT1_HI_ETPU_TC28F (55)
+#define INT1_HI_ETPU_TC29F (56)
+#define INT1_HI_ETPU_TC30F (57)
+#define INT1_HI_ETPU_TC31F (58)
+#define INT1_HI_ETPU_TGIF (59)
+
+/* Bit definitions and macros for INTC_IPRH */
+#define INTC_IPRH_INT63 (0x80000000)
+#define INTC_IPRH_INT62 (0x40000000)
+#define INTC_IPRH_INT61 (0x20000000)
+#define INTC_IPRH_INT60 (0x10000000)
+#define INTC_IPRH_INT59 (0x08000000)
+#define INTC_IPRH_INT58 (0x04000000)
+#define INTC_IPRH_INT57 (0x02000000)
+#define INTC_IPRH_INT56 (0x01000000)
+#define INTC_IPRH_INT55 (0x00800000)
+#define INTC_IPRH_INT54 (0x00400000)
+#define INTC_IPRH_INT53 (0x00200000)
+#define INTC_IPRH_INT52 (0x00100000)
+#define INTC_IPRH_INT51 (0x00080000)
+#define INTC_IPRH_INT50 (0x00040000)
+#define INTC_IPRH_INT49 (0x00020000)
+#define INTC_IPRH_INT48 (0x00010000)
+#define INTC_IPRH_INT47 (0x00008000)
+#define INTC_IPRH_INT46 (0x00004000)
+#define INTC_IPRH_INT45 (0x00002000)
+#define INTC_IPRH_INT44 (0x00001000)
+#define INTC_IPRH_INT43 (0x00000800)
+#define INTC_IPRH_INT42 (0x00000400)
+#define INTC_IPRH_INT41 (0x00000200)
+#define INTC_IPRH_INT40 (0x00000100)
+#define INTC_IPRH_INT39 (0x00000080)
+#define INTC_IPRH_INT38 (0x00000040)
+#define INTC_IPRH_INT37 (0x00000020)
+#define INTC_IPRH_INT36 (0x00000010)
+#define INTC_IPRH_INT35 (0x00000008)
+#define INTC_IPRH_INT34 (0x00000004)
+#define INTC_IPRH_INT33 (0x00000002)
+#define INTC_IPRH_INT32 (0x00000001)
+
+/* Bit definitions and macros for INTC_IPRL */
+#define INTC_IPRL_INT31 (0x80000000)
+#define INTC_IPRL_INT30 (0x40000000)
+#define INTC_IPRL_INT29 (0x20000000)
+#define INTC_IPRL_INT28 (0x10000000)
+#define INTC_IPRL_INT27 (0x08000000)
+#define INTC_IPRL_INT26 (0x04000000)
+#define INTC_IPRL_INT25 (0x02000000)
+#define INTC_IPRL_INT24 (0x01000000)
+#define INTC_IPRL_INT23 (0x00800000)
+#define INTC_IPRL_INT22 (0x00400000)
+#define INTC_IPRL_INT21 (0x00200000)
+#define INTC_IPRL_INT20 (0x00100000)
+#define INTC_IPRL_INT19 (0x00080000)
+#define INTC_IPRL_INT18 (0x00040000)
+#define INTC_IPRL_INT17 (0x00020000)
+#define INTC_IPRL_INT16 (0x00010000)
+#define INTC_IPRL_INT15 (0x00008000)
+#define INTC_IPRL_INT14 (0x00004000)
+#define INTC_IPRL_INT13 (0x00002000)
+#define INTC_IPRL_INT12 (0x00001000)
+#define INTC_IPRL_INT11 (0x00000800)
+#define INTC_IPRL_INT10 (0x00000400)
+#define INTC_IPRL_INT9 (0x00000200)
+#define INTC_IPRL_INT8 (0x00000100)
+#define INTC_IPRL_INT7 (0x00000080)
+#define INTC_IPRL_INT6 (0x00000040)
+#define INTC_IPRL_INT5 (0x00000020)
+#define INTC_IPRL_INT4 (0x00000010)
+#define INTC_IPRL_INT3 (0x00000008)
+#define INTC_IPRL_INT2 (0x00000004)
+#define INTC_IPRL_INT1 (0x00000002)
+#define INTC_IPRL_INT0 (0x00000001)
+
+/* Bit definitions and macros for INTC_IRLR */
+#define INTC_IRLRn(x) (((x)&0x7F)<<1)
+
+/* Bit definitions and macros for INTC_IACKLPRn */
+#define INTC_IACKLPRn_LEVEL(x) (((x)&0x07)<<4)
+#define INTC_IACKLPRn_PRI(x) ((x)&0x0F)
+
+/* Bit definitions and macros for INTC_ICRnx */
+#define INTC_ICRnx_IL(x) (((x)&0x07)<<3)
+#define INTC_ICRnx_IP(x) ((x)&0x07)
+
+/*********************************************************************
+* General Purpose I/O (GPIO)
+*********************************************************************/
+/* Bit definitions and macros for GPIO_PODR */
+#define GPIO_PODR_ADDR(x) (((x)&0x07)<<5)
+#define GPIO_PODR_ADDR_MASK (0xE0)
+#define GPIO_PODR_BS(x) ((x)&0x0F)
+#define GPIO_PODR_BS_MASK (0x0F)
+#define GPIO_PODR_CS(x) (((x)&0x7F)<<1)
+#define GPIO_PODR_CS_MASK (0xFE)
+#define GPIO_PODR_SDRAM(X) ((x)&0x3F)
+#define GPIO_PODR_SDRAM_MASK (0x3F)
+#define GPIO_PODR_FECI2C(x) GPIO_PODR_BS(x)
+#define GPIO_PODR_FECI2C_MASK GPIO_PODR_BS_MASK
+#define GPIO_PODR_UARTH(x) ((x)&0x03)
+#define GPIO_PODR_UARTH_MASK (0x03)
+#define GPIO_PODR_QSPI(x) ((x)&0x1F)
+#define GPIO_PODR_QSPI_MASK (0x1F)
+#define GPIO_PODR_ETPU(x) ((x)&0x07)
+#define GPIO_PODR_ETPU_MASK (0x07)
+
+/* Bit definitions and macros for GPIO_PDDR */
+#define GPIO_PDDR_ADDR(x) GPIO_PODR_ADDR(x)
+#define GPIO_PDDR_ADDR_MASK GPIO_PODR_ADDR_MASK
+#define GPIO_PDDR_BS(x) GPIO_PODR_BS(x)
+#define GPIO_PDDR_BS_MASK GPIO_PODR_BS_MASK
+#define GPIO_PDDR_CS(x) GPIO_PODR_CS(x)
+#define GPIO_PDDR_CS_MASK GPIO_PODR_CS_MASK
+#define GPIO_PDDR_SDRAM(X) GPIO_PODR_SDRAM(X)
+#define GPIO_PDDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
+#define GPIO_PDDR_FECI2C(x) GPIO_PDDR_BS(x)
+#define GPIO_PDDR_FECI2C_MASK GPIO_PDDR_BS_MASK
+#define GPIO_PDDR_UARTH(x) GPIO_PODR_UARTH(x)
+#define GPIO_PDDR_UARTH_MASK GPIO_PODR_UARTH_MASK
+#define GPIO_PDDR_QSPI(x) GPIO_PODR_QSPI(x)
+#define GPIO_PDDR_QSPI_MASK GPIO_PODR_QSPI_MASK
+#define GPIO_PDDR_ETPU(x) GPIO_PODR_ETPU(x)
+#define GPIO_PDDR_ETPU_MASK GPIO_PODR_ETPU_MASK
+
+/* Bit definitions and macros for GPIO_PPDSDR */
+#define GPIO_PPDSDR_ADDR(x) GPIO_PODR_ADDR(x)
+#define GPIO_PPDSDR_ADDR_MASK GPIO_PODR_ADDR_MASK
+#define GPIO_PPDSDR_BS(x) GPIO_PODR_BS(x)
+#define GPIO_PPDSDR_BS_MASK GPIO_PODR_BS_MASK
+#define GPIO_PPDSDR_CS(x) GPIO_PODR_CS(x)
+#define GPIO_PPDSDR_CS_MASK GPIO_PODR_CS_MASK
+#define GPIO_PPDSDR_SDRAM(X) GPIO_PODR_SDRAM(X)
+#define GPIO_PPDSDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
+#define GPIO_PPDSDR_FECI2C(x) GPIO_PPDSDR_BS(x)
+#define GPIO_PPDSDR_FECI2C_MASK GPIO_PPDSDR_BS_MASK
+#define GPIO_PPDSDR_UARTH(x) GPIO_PODR_UARTH(x)
+#define GPIO_PPDSDR_UARTH_MASK GPIO_PODR_UARTH_MASK
+#define GPIO_PPDSDR_QSPI(x) GPIO_PODR_QSPI(x)
+#define GPIO_PPDSDR_QSPI_MASK GPIO_PODR_QSPI_MASK
+#define GPIO_PPDSDR_ETPU(x) GPIO_PODR_ETPU(x)
+#define GPIO_PPDSDR_ETPU_MASK GPIO_PODR_ETPU_MASK
+
+/* Bit definitions and macros for GPIO_PCLRR */
+#define GPIO_PCLRR_ADDR(x) GPIO_PODR_ADDR(x)
+#define GPIO_PCLRR_ADDR_MASK GPIO_PODR_ADDR_MASK
+#define GPIO_PCLRR_BS(x) GPIO_PODR_BS(x)
+#define GPIO_PCLRR_BS_MASK GPIO_PODR_BS_MASK
+#define GPIO_PCLRR_CS(x) GPIO_PODR_CS(x)
+#define GPIO_PCLRR_CS_MASK GPIO_PODR_CS_MASK
+#define GPIO_PCLRR_SDRAM(X) GPIO_PODR_SDRAM(X)
+#define GPIO_PCLRR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
+#define GPIO_PCLRR_FECI2C(x) GPIO_PCLRR_BS(x)
+#define GPIO_PCLRR_FECI2C_MASK GPIO_PCLRR_BS_MASK
+#define GPIO_PCLRR_UARTH(x) GPIO_PODR_UARTH(x)
+#define GPIO_PCLRR_UARTH_MASK GPIO_PODR_UARTH_MASK
+#define GPIO_PCLRR_QSPI(x) GPIO_PODR_QSPI(x)
+#define GPIO_PCLRR_QSPI_MASK GPIO_PODR_QSPI_MASK
+#define GPIO_PCLRR_ETPU(x) GPIO_PODR_ETPU(x)
+#define GPIO_PCLRR_ETPU_MASK GPIO_PODR_ETPU_MASK
+
+/* Bit definitions and macros for GPIO_PAR */
+#define GPIO_PAR_AD_ADDR23 (0x80)
+#define GPIO_PAR_AD_ADDR22 (0x40)
+#define GPIO_PAR_AD_ADDR21 (0x20)
+#define GPIO_PAR_AD_DATAL (0x01)
+#define GPIO_PAR_BUSCTL_OE (0x4000)
+#define GPIO_PAR_BUSCTL_TA (0x1000)
+#define GPIO_PAR_BUSCTL_TEA(x) (((x)&0x03)<<10)
+#define GPIO_PAR_BUSCTL_TEA_MASK (0x0C00)
+#define GPIO_PAR_BUSCTL_TEA_GPIO (0x0400)
+#define GPIO_PAR_BUSCTL_TEA_DREQ1 (0x0800)
+#define GPIO_PAR_BUSCTL_TEA_EXTBUS (0x0C00)
+#define GPIO_PAR_BUSCTL_RWB (0x0100)
+#define GPIO_PAR_BUSCTL_TSIZ1 (0x0040)
+#define GPIO_PAR_BUSCTL_TSIZ0 (0x0010)
+#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<2)
+#define GPIO_PAR_BUSCTL_TS_MASK (0x0C)
+#define GPIO_PAR_BUSCTL_TS_GPIO (0x04)
+#define GPIO_PAR_BUSCTL_TS_DACK2 (0x08)
+#define GPIO_PAR_BUSCTL_TS_EXTBUS (0x0C)
+#define GPIO_PAR_BUSCTL_TIP(x) ((x)&0x03)
+#define GPIO_PAR_BUSCTL_TIP_MASK (0x03)
+#define GPIO_PAR_BUSCTL_TIP_GPIO (0x01)
+#define GPIO_PAR_BUSCTL_TIP_DREQ0 (0x02)
+#define GPIO_PAR_BUSCTL_TIP_EXTBUS (0x03)
+#define GPIO_PAR_BS(x) ((x)&0x0F)
+#define GPIO_PAR_BS_MASK (0x0F)
+#define GPIO_PAR_CS(x) (((x)&0x7F)<<1)
+#define GPIO_PAR_CS_MASK (0xFE)
+#define GPIO_PAR_CS_CS7 (0x80)
+#define GPIO_PAR_CS_CS6 (0x40)
+#define GPIO_PAR_CS_CS5 (0x20)
+#define GPIO_PAR_CS_CS4 (0x10)
+#define GPIO_PAR_CS_CS3 (0x08)
+#define GPIO_PAR_CS_CS2 (0x04)
+#define GPIO_PAR_CS_CS1 (0x02)
+#define GPIO_PAR_CS_SD3 GPIO_PAR_CS_CS3
+#define GPIO_PAR_CS_SD2 GPIO_PAR_CS_CS2
+#define GPIO_PAR_SDRAM_CSSDCS(x) (((x)&0x03)<<6)
+#define GPIO_PAR_SDRAM_CSSDCS_MASK (0xC0)
+#define GPIO_PAR_SDRAM_SDWE (0x20)
+#define GPIO_PAR_SDRAM_SCAS (0x10)
+#define GPIO_PAR_SDRAM_SRAS (0x08)
+#define GPIO_PAR_SDRAM_SCKE (0x04)
+#define GPIO_PAR_SDRAM_SDCS(x) ((x)&0x03)
+#define GPIO_PAR_SDRAM_SDCS_MASK (0x03)
+#define GPIO_PAR_FECI2C_EMDC(x) (((x)&0x03)<<6)
+#define GPIO_PAR_FECI2C_EMDC_MASK (0xC0)
+#define GPIO_PAR_FECI2C_EMDC_U2TXD (0x40)
+#define GPIO_PAR_FECI2C_EMDC_I2CSCL (0x80)
+#define GPIO_PAR_FECI2C_EMDC_FECEMDC (0xC0)
+#define GPIO_PAR_FECI2C_EMDIO(x) (((x)&0x03)<<4)
+#define GPIO_PAR_FECI2C_EMDIO_MASK (0x30)
+#define GPIO_PAR_FECI2C_EMDIO_U2RXD (0x10)
+#define GPIO_PAR_FECI2C_EMDIO_I2CSDA (0x20)
+#define GPIO_PAR_FECI2C_EMDIO_FECEMDIO (0x30)
+#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2)
+#define GPIO_PAR_FECI2C_SCL_MASK (0x0C)
+#define GPIO_PAR_FECI2C_SCL_CAN0RX (0x08)
+#define GPIO_PAR_FECI2C_SCL_I2CSCL (0x0C)
+#define GPIO_PAR_FECI2C_SDA(x) ((x)&0x03)
+#define GPIO_PAR_FECI2C_SDA_MASK (0x03)
+#define GPIO_PAR_FECI2C_SDA_CAN0TX (0x02)
+#define GPIO_PAR_FECI2C_SDA_I2CSDA (0x03)
+#define GPIO_PAR_UART_DREQ2 (0x8000)
+#define GPIO_PAR_UART_CAN1EN (0x4000)
+#define GPIO_PAR_UART_U2RXD (0x2000)
+#define GPIO_PAR_UART_U2TXD (0x1000)
+#define GPIO_PAR_UART_U1RXD(x) (((x)&0x03)<<10)
+#define GPIO_PAR_UART_U1RXD_MASK (0x0C00)
+#define GPIO_PAR_UART_U1RXD_CAN0RX (0x0800)
+#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00)
+#define GPIO_PAR_UART_U1TXD(x) (((x)&0x03)<<8)
+#define GPIO_PAR_UART_U1TXD_MASK (0x0300)
+#define GPIO_PAR_UART_U1TXD_CAN0TX (0x0200)
+#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300)
+#define GPIO_PAR_UART_U1CTS(x) (((x)&0x03)<<6)
+#define GPIO_PAR_UART_U1CTS_MASK (0x00C0)
+#define GPIO_PAR_UART_U1CTS_U2CTS (0x0080)
+#define GPIO_PAR_UART_U1CTS_U1CTS (0x00C0)
+#define GPIO_PAR_UART_U1RTS(x) (((x)&0x03)<<4)
+#define GPIO_PAR_UART_U1RTS_MASK (0x0030)
+#define GPIO_PAR_UART_U1RTS_U2RTS (0x0020)
+#define GPIO_PAR_UART_U1RTS_U1RTS (0x0030)
+#define GPIO_PAR_UART_U0RXD (0x0008)
+#define GPIO_PAR_UART_U0TXD (0x0004)
+#define GPIO_PAR_UART_U0CTS (0x0002)
+#define GPIO_PAR_UART_U0RTS (0x0001)
+#define GPIO_PAR_QSPI_CS1(x) (((x)&0x03)<<6)
+#define GPIO_PAR_QSPI_CS1_MASK (0xC0)
+#define GPIO_PAR_QSPI_CS1_SDRAMSCKE (0x80)
+#define GPIO_PAR_QSPI_CS1_QSPICS1 (0xC0)
+#define GPIO_PAR_QSPI_CS0 (0x20)
+#define GPIO_PAR_QSPI_DIN(x) (((x)&0x03)<<3)
+#define GPIO_PAR_QSPI_DIN_MASK (0x18)
+#define GPIO_PAR_QSPI_DIN_I2CSDA (0x10)
+#define GPIO_PAR_QSPI_DIN_QSPIDIN (0x18)
+#define GPIO_PAR_QSPI_DOUT (0x04)
+#define GPIO_PAR_QSPI_SCK(x) ((x)&0x03)
+#define GPIO_PAR_QSPI_SCK_MASK (0x03)
+#define GPIO_PAR_QSPI_SCK_I2CSCL (0x02)
+#define GPIO_PAR_QSPI_SCK_QSPISCK (0x03)
+#define GPIO_PAR_DT3IN(x) (((x)&0x03)<<14)
+#define GPIO_PAR_DT3IN_MASK (0xC000)
+#define GPIO_PAR_DT3IN_QSPICS2 (0x4000)
+#define GPIO_PAR_DT3IN_U2CTS (0x8000)
+#define GPIO_PAR_DT3IN_DT3IN (0xC000)
+#define GPIO_PAR_DT2IN(x) (((x)&0x03)<<12)
+#define GPIO_PAR_DT2IN_MASK (0x3000)
+#define GPIO_PAR_DT2IN_DT2OUT (0x1000)
+#define GPIO_PAR_DT2IN_DREQ2 (0x2000)
+#define GPIO_PAR_DT2IN_DT2IN (0x3000)
+#define GPIO_PAR_DT1IN(x) (((x)&0x03)<<10)
+#define GPIO_PAR_DT1IN_MASK (0x0C00)
+#define GPIO_PAR_DT1IN_DT1OUT (0x0400)
+#define GPIO_PAR_DT1IN_DREQ1 (0x0800)
+#define GPIO_PAR_DT1IN_DT1IN (0x0C00)
+#define GPIO_PAR_DT0IN(x) (((x)&0x03)<<8)
+#define GPIO_PAR_DT0IN_MASK (0x0300)
+#define GPIO_PAR_DT0IN_DREQ0 (0x0200)
+#define GPIO_PAR_DT0IN_DT0IN (0x0300)
+#define GPIO_PAR_DT3OUT(x) (((x)&0x03)<<6)
+#define GPIO_PAR_DT3OUT_MASK (0x00C0)
+#define GPIO_PAR_DT3OUT_QSPICS3 (0x0040)
+#define GPIO_PAR_DT3OUT_U2RTS (0x0080)
+#define GPIO_PAR_DT3OUT_DT3OUT (0x00C0)
+#define GPIO_PAR_DT2OUT(x) (((x)&0x03)<<4)
+#define GPIO_PAR_DT2OUT_MASK (0x0030)
+#define GPIO_PAR_DT2OUT_DACK2 (0x0020)
+#define GPIO_PAR_DT2OUT_DT2OUT (0x0030)
+#define GPIO_PAR_DT1OUT(x) (((x)&0x03)<<2)
+#define GPIO_PAR_DT1OUT_MASK (0x000C)
+#define GPIO_PAR_DT1OUT_DACK1 (0x0008)
+#define GPIO_PAR_DT1OUT_DT1OUT (0x000C)
+#define GPIO_PAR_DT0OUT(x) ((x)&0x03)
+#define GPIO_PAR_DT0OUT_MASK (0x0003)
+#define GPIO_PAR_DT0OUT_DACK0 (0x0002)
+#define GPIO_PAR_DT0OUT_DT0OUT (0x0003)
+#define GPIO_PAR_ETPU_TCRCLK (0x04)
+#define GPIO_PAR_ETPU_UTPU_ODIS (0x02)
+#define GPIO_PAR_ETPU_LTPU_ODIS (0x01)
+
+/* Bit definitions and macros for GPIO_DSCR */
+#define GPIO_DSCR_EIM_EIM1 (0x10)
+#define GPIO_DSCR_EIM_EIM0 (0x01)
+#define GPIO_DSCR_ETPU_ETPU31_24 (0x40)
+#define GPIO_DSCR_ETPU_ETPU23_16 (0x10)
+#define GPIO_DSCR_ETPU_ETPU15_8 (0x04)
+#define GPIO_DSCR_ETPU_ETPU7_0 (0x01)
+#define GPIO_DSCR_FECI2C_FEC (0x10)
+#define GPIO_DSCR_FECI2C_I2C (0x01)
+#define GPIO_DSCR_UART_IRQ (0x40)
+#define GPIO_DSCR_UART_UART2 (0x10)
+#define GPIO_DSCR_UART_UART1 (0x04)
+#define GPIO_DSCR_UART_UART0 (0x01)
+#define GPIO_DSCR_QSPI_QSPI (0x01)
+#define GPIO_DSCR_TIMER (0x01)
+
+/*********************************************************************
+* Chip Configuration Module (CCM)
+*********************************************************************/
+/* Bit definitions and macros for CCM_RCR */
+#define CCM_RCR_SOFTRST (0x80)
+#define CCM_RCR_FRCRSTOUT (0x40)
+
+/* Bit definitions and macros for CCM_RSR */
+#define CCM_RSR_SOFT (0x20)
+#define CCM_RSR_WDR (0x10)
+#define CCM_RSR_POR (0x08)
+#define CCM_RSR_EXT (0x04)
+#define CCM_RSR_LOC (0x02)
+#define CCM_RSR_LOL (0x01)
+
+/* Bit definitions and macros for CCM_CCR */
+#define CCM_CCR_LOAD (0x8000)
+#define CCM_CCR_SZEN (0x0040)
+#define CCM_CCR_PSTEN (0x0020)
+#define CCM_CCR_BME (0x0008)
+#define CCM_CCR_BMT(x) ((x)&0x07)
+#define CCM_CCR_BMT_MASK (0x0007)
+#define CCM_CCR_BMT_64K (0x0000)
+#define CCM_CCR_BMT_32K (0x0001)
+#define CCM_CCR_BMT_16K (0x0002)
+#define CCM_CCR_BMT_8K (0x0003)
+#define CCM_CCR_BMT_4K (0x0004)
+#define CCM_CCR_BMT_2K (0x0005)
+#define CCM_CCR_BMT_1K (0x0006)
+#define CCM_CCR_BMT_512 (0x0007)
+
+/* Bit definitions and macros for CCM_RCON */
+#define CCM_RCON_RCSC(x) (((x)&0x0003)<<8)
+#define CCM_RCON_RLOAD (0x0020)
+#define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3)
+#define CCM_RCON_BOOTPS_MASK (0x0018)
+#define CCM_RCON_BOOTPS_32 (0x0018)
+#define CCM_RCON_BOOTPS_16 (0x0008)
+#define CCM_RCON_BOOTPS_8 (0x0010)
+#define CCM_RCON_MODE (0x0001)
+
+/* Bit definitions and macros for CCM_CIR */
+#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
+#define CCM_CIR_PRN(x) ((x)&0x003F)
+
+/*********************************************************************
+* PLL Clock Module
+*********************************************************************/
+/* Bit definitions and macros for PLL_SYNCR */
+#define PLL_SYNCR_MFD(x) (((x)&0x07)<<24)
+#define PLL_SYNCR_MFD_MASK (0x07000000)
+#define PLL_SYNCR_RFC(x) (((x)&0x07)<<19)
+#define PLL_SYNCR_RFC_MASK (0x00380000)
+#define PLL_SYNCR_LOCEN (0x00040000)
+#define PLL_SYNCR_LOLRE (0x00020000)
+#define PLL_SYNCR_LOCRE (0x00010000)
+#define PLL_SYNCR_DISCLK (0x00008000)
+#define PLL_SYNCR_LOLIRQ (0x00004000)
+#define PLL_SYNCR_LOCIRQ (0x00002000)
+#define PLL_SYNCR_RATE (0x00001000)
+#define PLL_SYNCR_DEPTH(x) (((x)&0x03)<<10)
+#define PLL_SYNCR_EXP(x) ((x)&0x03FF)
+
+/* Bit definitions and macros for PLL_SYNSR */
+#define PLL_SYNSR_LOLF (0x00000200)
+#define PLL_SYNSR_LOC (0x00000100)
+#define PLL_SYNSR_MODE (0x00000080)
+#define PLL_SYNSR_PLLSEL (0x00000040)
+#define PLL_SYNSR_PLLREF (0x00000020)
+#define PLL_SYNSR_LOCKS (0x00000010)
+#define PLL_SYNSR_LOCK (0x00000008)
+#define PLL_SYNSR_LOCF (0x00000004)
+#define PLL_SYNSR_CALDONE (0x00000002)
+#define PLL_SYNSR_CALPASS (0x00000001)
+
+/*********************************************************************
+ * Edge Port
+*********************************************************************/
+#define EPORT_EPPAR_EPPA7(x) (((x)&0x03)<<14)
+#define EPORT_EPPAR_EPPA6(x) (((x)&0x03)<<12)
+#define EPORT_EPPAR_EPPA5(x) (((x)&0x03)<<10)
+#define EPORT_EPPAR_EPPA4(x) (((x)&0x03)<<8)
+#define EPORT_EPPAR_EPPA3(x) (((x)&0x03)<<6)
+#define EPORT_EPPAR_EPPA2(x) (((x)&0x03)<<4)
+#define EPORT_EPPAR_EPPA1(x) (((x)&0x03)<<2)
+
+#define EPORT_EPDDR_EPDD7(x) EPORT_EPPAR_EPPA7(x)
+#define EPORT_EPDDR_EPDD6(x) EPORT_EPPAR_EPPA6(x)
+#define EPORT_EPDDR_EPDD5(x) EPORT_EPPAR_EPPA5(x)
+#define EPORT_EPDDR_EPDD4(x) EPORT_EPPAR_EPPA4(x)
+#define EPORT_EPDDR_EPDD3(x) EPORT_EPPAR_EPPA3(x)
+#define EPORT_EPDDR_EPDD2(x) EPORT_EPPAR_EPPA2(x)
+#define EPORT_EPDDR_EPDD1(x) EPORT_EPPAR_EPPA1(x)
+
+#define EPORT_EPIER_EPIE7 (0x80)
+#define EPORT_EPIER_EPIE6 (0x40)
+#define EPORT_EPIER_EPIE5 (0x20)
+#define EPORT_EPIER_EPIE4 (0x10)
+#define EPORT_EPIER_EPIE3 (0x08)
+#define EPORT_EPIER_EPIE2 (0x04)
+#define EPORT_EPIER_EPIE1 (0x02)
+
+#define EPORT_EPDR_EPDR7 EPORT_EPIER_EPIE7
+#define EPORT_EPDR_EPDR6 EPORT_EPIER_EPIE6
+#define EPORT_EPDR_EPDR5 EPORT_EPIER_EPIE5
+#define EPORT_EPDR_EPDR4 EPORT_EPIER_EPIE4
+#define EPORT_EPDR_EPDR3 EPORT_EPIER_EPIE3
+#define EPORT_EPDR_EPDR2 EPORT_EPIER_EPIE2
+#define EPORT_EPDR_EPDR1 EPORT_EPIER_EPIE1
+
+#define EPORT_EPPDR_EPPDR7 EPORT_EPIER_EPIE7
+#define EPORT_EPPDR_EPPDR6 EPORT_EPIER_EPIE6
+#define EPORT_EPPDR_EPPDR5 EPORT_EPIER_EPIE5
+#define EPORT_EPPDR_EPPDR4 EPORT_EPIER_EPIE4
+#define EPORT_EPPDR_EPPDR3 EPORT_EPIER_EPIE3
+#define EPORT_EPPDR_EPPDR2 EPORT_EPIER_EPIE2
+#define EPORT_EPPDR_EPPDR1 EPORT_EPIER_EPIE1
+
+/*********************************************************************
+* Watchdog Timer Modules (WTM)
+*********************************************************************/
+/* Bit definitions and macros for WTM_WCR */
+#define WTM_WCR_WAIT (0x0008)
+#define WTM_WCR_DOZE (0x0004)
+#define WTM_WCR_HALTED (0x0002)
+#define WTM_WCR_EN (0x0001)
+
+/*********************************************************************
+* FlexCAN Module (CAN)
+*********************************************************************/
+/* Bit definitions and macros for CAN_CANMCR */
+#define CANMCR_MDIS (0x80000000)
+#define CANMCR_FRZ (0x40000000)
+#define CANMCR_HALT (0x10000000)
+#define CANMCR_NORDY (0x08000000)
+#define CANMCR_SOFTRST (0x02000000)
+#define CANMCR_FRZACK (0x01000000)
+#define CANMCR_SUPV (0x00800000)
+#define CANMCR_LPMACK (0x00100000)
+#define CANMCR_MAXMB(x) (((x)&0x0F))
+
+/* Bit definitions and macros for CAN_CANCTRL */
+#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
+#define CANCTRL_RJW(x) (((x)&0x03)<<22)
+#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
+#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
+#define CANCTRL_BOFFMSK (0x00008000)
+#define CANCTRL_ERRMSK (0x00004000)
+#define CANCTRL_CLKSRC (0x00002000)
+#define CANCTRL_LPB (0x00001000)
+#define CANCTRL_SMP (0x00000080)
+#define CANCTRL_BOFFREC (0x00000040)
+#define CANCTRL_TSYNC (0x00000020)
+#define CANCTRL_LBUF (0x00000010)
+#define CANCTRL_LOM (0x00000008)
+#define CANCTRL_PROPSEG(x) (((x)&0x07))
+
+/* Bit definitions and macros for CAN_TIMER */
+#define TIMER_TIMER(x) ((x)&0xFFFF)
+
+/* Bit definitions and macros for CAN_RXGMASK */
+#define RXGMASK_MI(x) ((x)&0x1FFFFFFF)
+
+/* Bit definitions and macros for CAN_ERRCNT */
+#define ERRCNT_TXECTR(x) (((x)&0xFF))
+#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
+
+/* Bit definitions and macros for CAN_ERRSTAT */
+#define ERRSTAT_BITERR1 (0x00008000)
+#define ERRSTAT_BITERR0 (0x00004000)
+#define ERRSTAT_ACKERR (0x00002000)
+#define ERRSTAT_CRCERR (0x00001000)
+#define ERRSTAT_FRMERR (0x00000800)
+#define ERRSTAT_STFERR (0x00000400)
+#define ERRSTAT_TXWRN (0x00000200)
+#define ERRSTAT_RXWRN (0x00000100)
+#define ERRSTAT_IDLE (0x00000080)
+#define ERRSTAT_TXRX (0x00000040)
+#define ERRSTAT_FLT_BUSOFF (0x00000020)
+#define ERRSTAT_FLT_PASSIVE (0x00000010)
+#define ERRSTAT_FLT_ACTIVE (0x00000000)
+#define ERRSTAT_BOFFINT (0x00000004)
+#define ERRSTAT_ERRINT (0x00000002)
+
+/* Bit definitions and macros for CAN_IMASK */
+#define IMASK_BUF15M (0x00008000)
+#define IMASK_BUF14M (0x00004000)
+#define IMASK_BUF13M (0x00002000)
+#define IMASK_BUF12M (0x00001000)
+#define IMASK_BUF11M (0x00000800)
+#define IMASK_BUF10M (0x00000400)
+#define IMASK_BUF9M (0x00000200)
+#define IMASK_BUF8M (0x00000100)
+#define IMASK_BUF7M (0x00000080)
+#define IMASK_BUF6M (0x00000040)
+#define IMASK_BUF5M (0x00000020)
+#define IMASK_BUF4M (0x00000010)
+#define IMASK_BUF3M (0x00000008)
+#define IMASK_BUF2M (0x00000004)
+#define IMASK_BUF1M (0x00000002)
+#define IMASK_BUF0M (0x00000001)
+
+/* Bit definitions and macros for CAN_IFLAG */
+#define IFLAG_BUF15I (0x00008000)
+#define IFLAG_BUF14I (0x00004000)
+#define IFLAG_BUF13I (0x00002000)
+#define IFLAG_BUF12I (0x00001000)
+#define IFLAG_BUF11I (0x00000800)
+#define IFLAG_BUF10I (0x00000400)
+#define IFLAG_BUF9I (0x00000200)
+#define IFLAG_BUF8I (0x00000100)
+#define IFLAG_BUF7I (0x00000080)
+#define IFLAG_BUF6I (0x00000040)
+#define IFLAG_BUF5I (0x00000020)
+#define IFLAG_BUF4I (0x00000010)
+#define IFLAG_BUF3I (0x00000008)
+#define IFLAG_BUF2I (0x00000004)
+#define IFLAG_BUF1I (0x00000002)
+#define IFLAG_BUF0I (0x00000001)
+
+#endif /* mcf5235_h */
diff --git a/include/asm-m68k/m5249.h b/include/asm-m68k/m5249.h
index 8c1b077..5ed3cbc 100644
--- a/include/asm-m68k/m5249.h
+++ b/include/asm-m68k/m5249.h
@@ -24,7 +24,6 @@
* MA 02111-1307 USA
*/
-
#ifndef mcf5249_h
#define mcf5249_h
/****************************************************************************/
@@ -32,22 +31,21 @@
/*
* useful definitions for reading/writing MBAR offset memory
*/
-#define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x))
-#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y
-#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y
-#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y
-#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_MBAR2 + x))
-#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR2 + x)) = y
-#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR2 + x)) = y
-#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR2 + x)) = y
-
+#define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x))
+#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y
+#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y
+#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y
+#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_MBAR2 + x))
+#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR2 + x)) = y
+#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR2 + x)) = y
+#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR2 + x)) = y
/*
* Size of internal RAM
*/
-#define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */
-#define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */
+#define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */
+#define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */
/*
* Define the 5249 SIM register set addresses.
@@ -56,51 +54,47 @@
/*****************
***** MBAR1 *****
*****************/
-#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
-#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
-#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */
-
-#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */
-#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
-#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
-
-#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
-#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
-
-#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
-#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
-
-#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
-#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
-
-/** UART Bases **/
-#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
-#define MCFUART_BASE2 0x200 /* Base address of UART2 */
+#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
+#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w) */
+#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
+#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
+#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */
+
+#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */
+#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
+#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
+#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
+#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
+#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
+#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
+#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
+#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
+#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
+#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
+#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
+#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
+
+#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
+#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
+
+#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
+#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
+#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
+#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
+#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
+#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
+#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
+#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
+#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
+#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
+#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
+#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
+
+#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
+#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
+#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
+#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
+#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
/*****************
***** MBAR2 *****
@@ -109,39 +103,39 @@
/* GPIO Addresses
* Note: These are offset from MBAR2!
*/
-#define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */
-#define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w)*/
-#define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w)*/
-#define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */
-#define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */
-#define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */
-#define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */
-#define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */
-
-#define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */
-#define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */
-#define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */
-
-#define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */
-#define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */
-#define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */
-
-#define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */
-#define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */
-#define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */
-#define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */
-#define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */
-#define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */
-#define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */
-#define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */
-
-#define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */
-#define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */
-
-#define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */
-#define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */
-
-#define MCFSIM_PLLCR 0x180 /* PLL Control register */
+#define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */
+#define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w) */
+#define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w) */
+#define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */
+#define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */
+#define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */
+#define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */
+#define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */
+
+#define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */
+#define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */
+#define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */
+
+#define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */
+#define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */
+#define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */
+
+#define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */
+#define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */
+#define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */
+#define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */
+#define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */
+#define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */
+#define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */
+#define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */
+
+#define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */
+#define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */
+
+#define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */
+#define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */
+
+#define MCFSIM_PLLCR 0x180 /* PLL Control register */
/*
* Some symbol defines for the above...
@@ -158,21 +152,20 @@
/*
* Bit definitions for the ICR family of registers.
*/
-#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
-#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
-#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
-#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
-#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
-#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
-#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
-#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
-#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
-
-#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
-#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
-#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
-#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
-
+#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
+#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
+#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
+#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
+#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
+#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
+#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
+#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
+#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
+
+#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
+#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
+#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
+#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
/*
* Macros to read/set IMR register. It is 32 bits on the 5249.
@@ -184,4 +177,4 @@
#define mcf_setimr(imr) \
*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
-#endif /* mcf5249_h */
+#endif /* mcf5249_h */
diff --git a/include/asm-m68k/m5253.h b/include/asm-m68k/m5253.h
new file mode 100644
index 0000000..eda3472
--- /dev/null
+++ b/include/asm-m68k/m5253.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef m5253_h
+#define m5253_h
+/****************************************************************************/
+
+/*
+* PLL Module (PLL)
+*/
+
+/* Register read/write macros */
+#define PLL_PLLCR (0x000180)
+
+#define SIM_RSR (0x000000)
+#define SIM_SYPCR (0x000001)
+#define SIM_SWIVR (0x000002)
+#define SIM_SWSR (0x000003)
+#define SIM_MPARK (0x00000C)
+
+/* Bit definitions and macros for RSR */
+#define SIM_RSR_SWTR (0x20)
+#define SIM_RSR_HRST (0x80)
+
+/* Register read/write macros */
+#define CIM_MISCCR (0x000500)
+#define CIM_ATA_DADDR (0x000504)
+#define CIM_ATA_DCOUNT (0x000508)
+#define CIM_RTC_TIME (0x00050C)
+#define CIM_USB_CANCLK (0x000510)
+
+/* Bit definitions and macros for MISCCR */
+#define CIM_MISCCR_ADTA (0x00000001)
+#define CIM_MISCCR_ADTD (0x00000002)
+#define CIM_MISCCR_ADIE (0x00000004)
+#define CIM_MISCCR_ADIC (0x00000008)
+#define CIM_MISCCR_ADIP (0x00000010)
+#define CIM_MISCCR_CPUEND (0x00000020)
+#define CIM_MISCCR_DMAEND (0x00000040)
+#define CIM_MISCCR_RTCCLR (0x00000080)
+#define CIM_MISCCR_RTCPL (0x00000100)
+#define CIM_MISCCR_URIE (0x00000800)
+#define CIM_MISCCR_URIC (0x00001000)
+#define CIM_MISCCR_URIP (0x00002000)
+
+/* Bit definitions and macros for ATA_DADDR */
+#define CIM_ATA_DADDR_ATAADDR(x) (((x)&0x00003FFF)<<2)
+#define CIM_ATA_DADDR_RAMADDR(x) (((x)&0x00003FFF)<<18)
+
+/* Bit definitions and macros for ATA_DCOUNT */
+#define CIM_ATA_DCOUNT_COUNT(x) (((x)&0x0000FFFF))
+
+#endif /* m5253_h */
diff --git a/include/asm-m68k/m5271.h b/include/asm-m68k/m5271.h
index e0f02cf..be34398 100644
--- a/include/asm-m68k/m5271.h
+++ b/include/asm-m68k/m5271.h
@@ -25,7 +25,6 @@
* MA 02111-1307 USA
*/
-
#ifndef _MCF5271_H_
#define _MCF5271_H_
@@ -91,7 +90,7 @@
#define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00
#define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300
-#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
#define MCF_SDRAMC_DCR 0x000040
#define MCF_SDRAMC_DACR0 0x000048
@@ -117,4 +116,104 @@
#define MCFSIM_ICR1 0x000C41
-#endif /* _MCF5271_H_ */
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INT0_LO_RSVD0 (0)
+#define INT0_LO_EPORT1 (1)
+#define INT0_LO_EPORT2 (2)
+#define INT0_LO_EPORT3 (3)
+#define INT0_LO_EPORT4 (4)
+#define INT0_LO_EPORT5 (5)
+#define INT0_LO_EPORT6 (6)
+#define INT0_LO_EPORT7 (7)
+#define INT0_LO_SCM (8)
+#define INT0_LO_DMA0 (9)
+#define INT0_LO_DMA1 (10)
+#define INT0_LO_DMA2 (11)
+#define INT0_LO_DMA3 (12)
+#define INT0_LO_UART0 (13)
+#define INT0_LO_UART1 (14)
+#define INT0_LO_UART2 (15)
+#define INT0_LO_RSVD1 (16)
+#define INT0_LO_I2C (17)
+#define INT0_LO_QSPI (18)
+#define INT0_LO_DTMR0 (19)
+#define INT0_LO_DTMR1 (20)
+#define INT0_LO_DTMR2 (21)
+#define INT0_LO_DTMR3 (22)
+#define INT0_LO_FEC_TXF (23)
+#define INT0_LO_FEC_TXB (24)
+#define INT0_LO_FEC_UN (25)
+#define INT0_LO_FEC_RL (26)
+#define INT0_LO_FEC_RXF (27)
+#define INT0_LO_FEC_RXB (28)
+#define INT0_LO_FEC_MII (29)
+#define INT0_LO_FEC_LC (30)
+#define INT0_LO_FEC_HBERR (31)
+#define INT0_HI_FEC_GRA (32)
+#define INT0_HI_FEC_EBERR (33)
+#define INT0_HI_FEC_BABT (34)
+#define INT0_HI_FEC_BABR (35)
+#define INT0_HI_PIT0 (36)
+#define INT0_HI_PIT1 (37)
+#define INT0_HI_PIT2 (38)
+#define INT0_HI_PIT3 (39)
+#define INT0_HI_RNG (40)
+#define INT0_HI_SKHA (41)
+#define INT0_HI_MDHA (42)
+#define INT0_HI_CAN1_BUF0I (43)
+#define INT0_HI_CAN1_BUF1I (44)
+#define INT0_HI_CAN1_BUF2I (45)
+#define INT0_HI_CAN1_BUF3I (46)
+#define INT0_HI_CAN1_BUF4I (47)
+#define INT0_HI_CAN1_BUF5I (48)
+#define INT0_HI_CAN1_BUF6I (49)
+#define INT0_HI_CAN1_BUF7I (50)
+#define INT0_HI_CAN1_BUF8I (51)
+#define INT0_HI_CAN1_BUF9I (52)
+#define INT0_HI_CAN1_BUF10I (53)
+#define INT0_HI_CAN1_BUF11I (54)
+#define INT0_HI_CAN1_BUF12I (55)
+#define INT0_HI_CAN1_BUF13I (56)
+#define INT0_HI_CAN1_BUF14I (57)
+#define INT0_HI_CAN1_BUF15I (58)
+#define INT0_HI_CAN1_ERRINT (59)
+#define INT0_HI_CAN1_BOFFINT (60)
+/* 60-63 Reserved */
+
+/* Bit definitions and macros for INTC_IPRL */
+#define INTC_IPRL_INT31 (0x80000000)
+#define INTC_IPRL_INT30 (0x40000000)
+#define INTC_IPRL_INT29 (0x20000000)
+#define INTC_IPRL_INT28 (0x10000000)
+#define INTC_IPRL_INT27 (0x08000000)
+#define INTC_IPRL_INT26 (0x04000000)
+#define INTC_IPRL_INT25 (0x02000000)
+#define INTC_IPRL_INT24 (0x01000000)
+#define INTC_IPRL_INT23 (0x00800000)
+#define INTC_IPRL_INT22 (0x00400000)
+#define INTC_IPRL_INT21 (0x00200000)
+#define INTC_IPRL_INT20 (0x00100000)
+#define INTC_IPRL_INT19 (0x00080000)
+#define INTC_IPRL_INT18 (0x00040000)
+#define INTC_IPRL_INT17 (0x00020000)
+#define INTC_IPRL_INT16 (0x00010000)
+#define INTC_IPRL_INT15 (0x00008000)
+#define INTC_IPRL_INT14 (0x00004000)
+#define INTC_IPRL_INT13 (0x00002000)
+#define INTC_IPRL_INT12 (0x00001000)
+#define INTC_IPRL_INT11 (0x00000800)
+#define INTC_IPRL_INT10 (0x00000400)
+#define INTC_IPRL_INT9 (0x00000200)
+#define INTC_IPRL_INT8 (0x00000100)
+#define INTC_IPRL_INT7 (0x00000080)
+#define INTC_IPRL_INT6 (0x00000040)
+#define INTC_IPRL_INT5 (0x00000020)
+#define INTC_IPRL_INT4 (0x00000010)
+#define INTC_IPRL_INT3 (0x00000008)
+#define INTC_IPRL_INT2 (0x00000004)
+#define INTC_IPRL_INT1 (0x00000002)
+#define INTC_IPRL_INT0 (0x00000001)
+
+#endif /* _MCF5271_H_ */
diff --git a/include/asm-m68k/m5272.h b/include/asm-m68k/m5272.h
index 54d4a32..895f89d 100644
--- a/include/asm-m68k/m5272.h
+++ b/include/asm-m68k/m5272.h
@@ -24,7 +24,6 @@
* MA 02111-1307 USA
*/
-
#ifndef mcf5272_h
#define mcf5272_h
/****************************************************************************/
@@ -35,65 +34,173 @@
#define INT_RAM_SIZE 4096
+#define GPIO_PACNT_PA15MSK (0xC0000000)
+#define GPIO_PACNT_DGNT1 (0x40000000)
+#define GPIO_PACNT_PA14MSK (0x30000000)
+#define GPIO_PACNT_DREQ1 (0x10000000)
+#define GPIO_PACNT_PA13MSK (0x0C000000)
+#define GPIO_PACNT_DFSC3 (0x04000000)
+#define GPIO_PACNT_PA12MSK (0x03000000)
+#define GPIO_PACNT_DFSC2 (0x01000000)
+#define GPIO_PACNT_PA11MSK (0x00C00000)
+#define GPIO_PACNT_QSPI_CS1 (0x00800000)
+#define GPIO_PACNT_PA10MSK (0x00300000)
+#define GPIO_PACNT_DREQ0 (0x00100000)
+#define GPIO_PACNT_PA9MSK (0x000C0000)
+#define GPIO_PACNT_DGNT0 (0x00040000)
+#define GPIO_PACNT_PA8MSK (0x00030000)
+#define GPIO_PACNT_FSC0 (0x00010000)
+#define GPIO_PACNT_FSR0 (0x00010000)
+#define GPIO_PACNT_PA7MSK (0x0000C000)
+#define GPIO_PACNT_DOUT3 (0x00008000)
+#define GPIO_PACNT_QSPI_CS3 (0x00004000)
+#define GPIO_PACNT_PA6MSK (0x00003000)
+#define GPIO_PACNT_USB_RXD (0x00001000)
+#define GPIO_PACNT_PA5MSK (0x00000C00)
+#define GPIO_PACNT_USB_TXEN (0x00000400)
+#define GPIO_PACNT_PA4MSK (0x00000300)
+#define GPIO_PACNT_USB_SUSP (0x00000100)
+#define GPIO_PACNT_PA3MSK (0x000000C0)
+#define GPIO_PACNT_USB_TN (0x00000040)
+#define GPIO_PACNT_PA2MSK (0x00000030)
+#define GPIO_PACNT_USB_RN (0x00000010)
+#define GPIO_PACNT_PA1MSK (0x0000000C)
+#define GPIO_PACNT_USB_RP (0x00000004)
+#define GPIO_PACNT_PA0MSK (0x00000003)
+#define GPIO_PACNT_USB_TP (0x00000001)
-/*
- * Define the 5272 SIM register set addresses.
- */
-#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */
-#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/
-#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */
-#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */
-#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */
-
-#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */
-
-#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */
-#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */
-#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */
-#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */
+#define GPIO_PBCNT_PB15MSK (0xC0000000)
+#define GPIO_PBCNT_E_MDC (0x40000000)
+#define GPIO_PBCNT_PB14MSK (0x30000000)
+#define GPIO_PBCNT_E_RXER (0x10000000)
+#define GPIO_PBCNT_PB13MSK (0x0C000000)
+#define GPIO_PBCNT_E_RXD1 (0x04000000)
+#define GPIO_PBCNT_PB12MSK (0x03000000)
+#define GPIO_PBCNT_E_RXD2 (0x01000000)
+#define GPIO_PBCNT_PB11MSK (0x00C00000)
+#define GPIO_PBCNT_E_RXD3 (0x00400000)
+#define GPIO_PBCNT_PB10MSK (0x00300000)
+#define GPIO_PBCNT_E_TXD1 (0x00100000)
+#define GPIO_PBCNT_PB9MSK (0x000C0000)
+#define GPIO_PBCNT_E_TXD2 (0x00040000)
+#define GPIO_PBCNT_PB8MSK (0x00030000)
+#define GPIO_PBCNT_E_TXD3 (0x00010000)
+#define GPIO_PBCNT_PB7MSK (0x0000C000)
+#define GPIO_PBCNT_TOUT0 (0x00004000)
+#define GPIO_PBCNT_PB6MSK (0x00003000)
+#define GPIO_PBCNT_TA (0x00001000)
+#define GPIO_PBCNT_PB4MSK (0x00000300)
+#define GPIO_PBCNT_URT0_CLK (0x00000100)
+#define GPIO_PBCNT_PB3MSK (0x000000C0)
+#define GPIO_PBCNT_URT0_RTS (0x00000040)
+#define GPIO_PBCNT_PB2MSK (0x00000030)
+#define GPIO_PBCNT_URT0_CTS (0x00000010)
+#define GPIO_PBCNT_PB1MSK (0x0000000C)
+#define GPIO_PBCNT_URT0_RXD (0x00000004)
+#define GPIO_PBCNT_URT0_TIN2 (0x00000004)
+#define GPIO_PBCNT_PB0MSK (0x00000003)
+#define GPIO_PBCNT_URT0_TXD (0x00000001)
-#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */
-#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */
-#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */
-#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */
+#define GPIO_PDCNT_PD7MSK (0x0000C000)
+#define GPIO_PDCNT_TIN1 (0x00008000)
+#define GPIO_PDCNT_PWM_OUT2 (0x00004000)
+#define GPIO_PDCNT_PD6MSK (0x00003000)
+#define GPIO_PDCNT_TOUT1 (0x00002000)
+#define GPIO_PDCNT_PWM_OUT1 (0x00001000)
+#define GPIO_PDCNT_PD5MSK (0x00000C00)
+#define GPIO_PDCNT_INT4 (0x00000C00)
+#define GPIO_PDCNT_DIN3 (0x00000800)
+#define GPIO_PDCNT_PD4MSK (0x00000300)
+#define GPIO_PDCNT_URT1_TXD (0x00000200)
+#define GPIO_PDCNT_DOUT0 (0x00000100)
+#define GPIO_PDCNT_PD3MSK (0x000000C0)
+#define GPIO_PDCNT_INT5 (0x000000C0)
+#define GPIO_PDCNT_URT1_RTS (0x00000080)
+#define GPIO_PDCNT_PD2MSK (0x00000030)
+#define GPIO_PDCNT_QSPI_CS2 (0x00000030)
+#define GPIO_PDCNT_URT1_CTS (0x00000020)
+#define GPIO_PDCNT_PD1MSK (0x0000000C)
+#define GPIO_PDCNT_URT1_RXD (0x00000008)
+#define GPIO_PDCNT_URT1_TIN3 (0x00000008)
+#define GPIO_PDCNT_DIN0 (0x00000004)
+#define GPIO_PDCNT_PD0MSK (0x00000003)
+#define GPIO_PDCNT_URT1_CLK (0x00000002)
+#define GPIO_PDCNT_DCL0 (0x00000001)
-#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */
-#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */
-#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */
-#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */
-#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */
-#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */
-#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */
-#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */
-#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */
-#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */
-#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */
-#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */
-#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */
-#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */
-#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */
-#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */
+#define INT_RSVD0 (0)
+#define INT_INT1 (1)
+#define INT_INT2 (2)
+#define INT_INT3 (3)
+#define INT_INT4 (4)
+#define INT_TMR0 (5)
+#define INT_TMR1 (6)
+#define INT_TMR2 (7)
+#define INT_TMR3 (8)
+#define INT_UART1 (9)
+#define INT_UART2 (10)
+#define INT_PLIP (11)
+#define INT_PLIA (12)
+#define INT_USB0 (13)
+#define INT_USB1 (14)
+#define INT_USB2 (15)
+#define INT_USB3 (16)
+#define INT_USB4 (17)
+#define INT_USB5 (18)
+#define INT_USB6 (19)
+#define INT_USB7 (20)
+#define INT_DMA (21)
+#define INT_ERX (22)
+#define INT_ETX (23)
+#define INT_ENTC (24)
+#define INT_QSPI (25)
+#define INT_INT5 (26)
+#define INT_INT6 (27)
+#define INT_SWTO (28)
-#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */
-#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */
-#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */
-#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */
-#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */
-#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
-#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
+#define INT_ICR1_TMR0MASK (0x000F000)
+#define INT_ICR1_TMR0PI (0x0008000)
+#define INT_ICR1_TMR0IPL(x) (((x)&0x7)<<12)
+#define INT_ICR1_TMR1MASK (0x0000F00)
+#define INT_ICR1_TMR1PI (0x0000800)
+#define INT_ICR1_TMR1IPL(x) (((x)&0x7)<<8)
+#define INT_ICR1_TMR2MASK (0x00000F0)
+#define INT_ICR1_TMR2PI (0x0000080)
+#define INT_ICR1_TMR2IPL(x) (((x)&0x7)<<4)
+#define INT_ICR1_TMR3MASK (0x000000F)
+#define INT_ICR1_TMR3PI (0x0000008)
+#define INT_ICR1_TMR3IPL(x) (((x)&0x7))
-#define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */
-#define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */
-#define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */
-#define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */
-#define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */
-#define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */
-#define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */
-#define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */
-#define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */
+#define INT_ISR_INT31 (0x80000000)
+#define INT_ISR_INT30 (0x40000000)
+#define INT_ISR_INT29 (0x20000000)
+#define INT_ISR_INT28 (0x10000000)
+#define INT_ISR_INT27 (0x08000000)
+#define INT_ISR_INT26 (0x04000000)
+#define INT_ISR_INT25 (0x02000000)
+#define INT_ISR_INT24 (0x01000000)
+#define INT_ISR_INT23 (0x00800000)
+#define INT_ISR_INT22 (0x00400000)
+#define INT_ISR_INT21 (0x00200000)
+#define INT_ISR_INT20 (0x00100000)
+#define INT_ISR_INT19 (0x00080000)
+#define INT_ISR_INT18 (0x00040000)
+#define INT_ISR_INT17 (0x00020000)
+#define INT_ISR_INT16 (0x00010000)
+#define INT_ISR_INT15 (0x00008000)
+#define INT_ISR_INT14 (0x00004000)
+#define INT_ISR_INT13 (0x00002000)
+#define INT_ISR_INT12 (0x00001000)
+#define INT_ISR_INT11 (0x00000800)
+#define INT_ISR_INT10 (0x00000400)
+#define INT_ISR_INT9 (0x00000200)
+#define INT_ISR_INT8 (0x00000100)
+#define INT_ISR_INT7 (0x00000080)
+#define INT_ISR_INT6 (0x00000040)
+#define INT_ISR_INT5 (0x00000020)
+#define INT_ISR_INT4 (0x00000010)
+#define INT_ISR_INT3 (0x00000008)
+#define INT_ISR_INT2 (0x00000004)
+#define INT_ISR_INT1 (0x00000002)
+#define INT_ISR_INT0 (0x00000001)
-#endif /* mcf5272_h */
+#endif /* mcf5272_h */
diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h
index e5058a4..7473bb9 100644
--- a/include/asm-m68k/m5282.h
+++ b/include/asm-m68k/m5282.h
@@ -23,7 +23,99 @@
/****************************************************************************/
#ifndef m5282_h
#define m5282_h
-/****************************************************************************/
+
+/*********************************************************************
+* PLL Clock Module
+*********************************************************************/
+/* Bit definitions and macros for PLL_SYNCR */
+#define PLL_SYNCR_LOLRE (0x8000)
+#define PLL_SYNCR_MFD2 (0x4000)
+#define PLL_SYNCR_MFD1 (0x2000)
+#define PLL_SYNCR_MFD0 (0x1000)
+#define PLL_SYNCR_LOCRE (0x0800)
+#define PLL_SYNCR_RFC2 (0x0400)
+#define PLL_SYNCR_RFC1 (0x0200)
+#define PLL_SYNCR_RFC0 (0x0100)
+#define PLL_SYNCR_LOCEN (0x0080)
+#define PLL_SYNCR_DISCLK (0x0040)
+#define PLL_SYNCR_FWKUP (0x0020)
+#define PLL_SYNCR_STPMD1 (0x0008)
+#define PLL_SYNCR_STPMD0 (0x0004)
+
+/* Bit definitions and macros for PLL_SYNSR */
+#define PLL_SYNSR_MODE (0x0080)
+#define PLL_SYNSR_PLLSEL (0x0040)
+#define PLL_SYNSR_PLLREF (0x0020)
+#define PLL_SYNSR_LOCKS (0x0010)
+#define PLL_SYNSR_LOCK (0x0008)
+#define PLL_SYNSR_LOCS (0x0004)
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INT0_LO_RSVD0 (0)
+#define INT0_LO_EPORT1 (1)
+#define INT0_LO_EPORT2 (2)
+#define INT0_LO_EPORT3 (3)
+#define INT0_LO_EPORT4 (4)
+#define INT0_LO_EPORT5 (5)
+#define INT0_LO_EPORT6 (6)
+#define INT0_LO_EPORT7 (7)
+#define INT0_LO_SCM_SWT1 (8)
+#define INT0_LO_DMA_00 (9)
+#define INT0_LO_DMA_01 (10)
+#define INT0_LO_DMA_02 (11)
+#define INT0_LO_DMA_03 (12)
+#define INT0_LO_UART0 (13)
+#define INT0_LO_UART1 (14)
+#define INT0_LO_UART2 (15)
+#define INT0_LO_RSVD1 (16)
+#define INT0_LO_I2C (17)
+#define INT0_LO_QSPI (18)
+#define INT0_LO_DTMR0 (19)
+#define INT0_LO_DTMR1 (20)
+#define INT0_LO_DTMR2 (21)
+#define INT0_LO_DTMR3 (22)
+#define INT0_LO_FEC_TXF (23)
+#define INT0_LO_FEC_TXB (24)
+#define INT0_LO_FEC_UN (25)
+#define INT0_LO_FEC_RL (26)
+#define INT0_LO_FEC_RXF (27)
+#define INT0_LO_FEC_RXB (28)
+#define INT0_LO_FEC_MII (29)
+#define INT0_LO_FEC_LC (30)
+#define INT0_LO_FEC_HBERR (31)
+#define INT0_HI_FEC_GRA (32)
+#define INT0_HI_FEC_EBERR (33)
+#define INT0_HI_FEC_BABT (34)
+#define INT0_HI_FEC_BABR (35)
+#define INT0_HI_PMM_LVDF (36)
+#define INT0_HI_QADC_CF1 (37)
+#define INT0_HI_QADC_CF2 (38)
+#define INT0_HI_QADC_PF1 (39)
+#define INT0_HI_QADC_PF2 (40)
+#define INT0_HI_GPTA_TOF (41)
+#define INT0_HI_GPTA_PAIF (42)
+#define INT0_HI_GPTA_PAOVF (43)
+#define INT0_HI_GPTA_C0F (44)
+#define INT0_HI_GPTA_C1F (45)
+#define INT0_HI_GPTA_C2F (46)
+#define INT0_HI_GPTA_C3F (47)
+#define INT0_HI_GPTB_TOF (48)
+#define INT0_HI_GPTB_PAIF (49)
+#define INT0_HI_GPTB_PAOVF (50)
+#define INT0_HI_GPTB_C0F (51)
+#define INT0_HI_GPTB_C1F (52)
+#define INT0_HI_GPTB_C2F (53)
+#define INT0_HI_GPTB_C3F (54)
+#define INT0_HI_PIT0 (55)
+#define INT0_HI_PIT1 (56)
+#define INT0_HI_PIT2 (57)
+#define INT0_HI_PIT3 (58)
+#define INT0_HI_CFM_CBEIF (59)
+#define INT0_HI_CFM_CCIF (60)
+#define INT0_HI_CFM_PVIF (61)
+#define INT0_HI_CFM_AEIF (62)
/*
* Size of internal RAM
@@ -96,49 +188,49 @@
#define MCFGPIO_SETD (*(vu_char *) (CFG_MBAR+0x10002B))
#define MCFGPIO_SETE (*(vu_char *) (CFG_MBAR+0x10002C))
#define MCFGPIO_SETF (*(vu_char *) (CFG_MBAR+0x10002D))
-#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E))
-#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F))
-#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030))
-#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031))
-#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032))
-#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033))
-#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034))
-#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035))
-#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036))
-#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037))
-#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038))
-#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039))
-
-#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C))
-#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D))
-#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E))
-#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F))
-#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040))
-#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041))
-#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042))
-#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043))
-#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044))
-#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045))
-#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046))
-#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047))
-#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048))
-#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049))
-#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A))
-#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B))
-#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C))
-#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D))
-
-#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050))
-#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051))
-#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052))
-#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054))
-#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055))
-#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056))
-#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058))
-#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059))
-#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A))
-#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B))
-#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C))
+#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E))
+#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F))
+#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030))
+#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031))
+#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032))
+#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033))
+#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034))
+#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035))
+#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036))
+#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037))
+#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038))
+#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039))
+
+#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C))
+#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D))
+#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E))
+#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F))
+#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040))
+#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041))
+#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042))
+#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043))
+#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044))
+#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045))
+#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046))
+#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047))
+#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048))
+#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049))
+#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A))
+#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B))
+#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C))
+#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D))
+
+#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050))
+#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051))
+#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052))
+#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054))
+#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055))
+#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056))
+#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058))
+#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059))
+#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A))
+#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B))
+#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C))
/* Bit level definitions and macros */
#define MCFGPIO_PORT7 (0x80)
@@ -171,7 +263,6 @@
#define MCFGPIO_Px0 (0x01)
#define MCFGPIO_Px(x) (0x01<<x)
-
#define MCFGPIO_PBCDPAR_PBPA (0x80)
#define MCFGPIO_PBCDPAR_PCDPA (0x40)
@@ -236,7 +327,7 @@
/* System Conrol Module SCM */
-#define MCFSCM_RAMBAR (*(vu_long *) (CFG_MBAR+0x00000008))
+#define MCFSCM_RAMBAR (*(vu_long *) (CFG_MBAR+0x00000008))
#define MCFSCM_CRSR (*(vu_char *) (CFG_MBAR+0x00000010))
#define MCFSCM_CWCR (*(vu_char *) (CFG_MBAR+0x00000011))
#define MCFSCM_LPICR (*(vu_char *) (CFG_MBAR+0x00000012))
@@ -256,34 +347,33 @@
#define MCFSCM_GPACR0 (*(vu_char *) (CFG_MBAR+0x00000030))
#define MCFSCM_GPACR1 (*(vu_char *) (CFG_MBAR+0x00000031))
-
#define MCFSCM_CRSR_EXT (0x80)
#define MCFSCM_CRSR_CWDR (0x20)
-#define MCFSCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
-#define MCFSCM_RAMBAR_BDE (0x00000200)
+#define MCFSCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
+#define MCFSCM_RAMBAR_BDE (0x00000200)
/* Reset Controller Module RCM */
#define MCFRESET_RCR (*(vu_char *) (CFG_MBAR+0x00110000))
#define MCFRESET_RSR (*(vu_char *) (CFG_MBAR+0x00110001))
-#define MCFRESET_RCR_SOFTRST (0x80)
-#define MCFRESET_RCR_FRCRSTOUT (0x40)
-#define MCFRESET_RCR_LVDF (0x10)
-#define MCFRESET_RCR_LVDIE (0x08)
-#define MCFRESET_RCR_LVDRE (0x04)
-#define MCFRESET_RCR_LVDE (0x01)
-
-#define MCFRESET_RSR_LVD (0x40)
-#define MCFRESET_RSR_SOFT (0x20)
-#define MCFRESET_RSR_WDR (0x10)
-#define MCFRESET_RSR_POR (0x08)
-#define MCFRESET_RSR_EXT (0x04)
-#define MCFRESET_RSR_LOC (0x02)
-#define MCFRESET_RSR_LOL (0x01)
-#define MCFRESET_RSR_ALL (0x7F)
-#define MCFRESET_RCR_SOFTRST (0x80)
-#define MCFRESET_RCR_FRCRSTOUT (0x40)
+#define MCFRESET_RCR_SOFTRST (0x80)
+#define MCFRESET_RCR_FRCRSTOUT (0x40)
+#define MCFRESET_RCR_LVDF (0x10)
+#define MCFRESET_RCR_LVDIE (0x08)
+#define MCFRESET_RCR_LVDRE (0x04)
+#define MCFRESET_RCR_LVDE (0x01)
+
+#define MCFRESET_RSR_LVD (0x40)
+#define MCFRESET_RSR_SOFT (0x20)
+#define MCFRESET_RSR_WDR (0x10)
+#define MCFRESET_RSR_POR (0x08)
+#define MCFRESET_RSR_EXT (0x04)
+#define MCFRESET_RSR_LOC (0x02)
+#define MCFRESET_RSR_LOL (0x01)
+#define MCFRESET_RSR_ALL (0x7F)
+#define MCFRESET_RCR_SOFTRST (0x80)
+#define MCFRESET_RCR_FRCRSTOUT (0x40)
/* Chip Configuration Module CCM */
@@ -291,26 +381,25 @@
#define MCFCCM_RCON (*(vu_short *)(CFG_MBAR+0x00110008))
#define MCFCCM_CIR (*(vu_short *)(CFG_MBAR+0x0011000A))
-
/* Bit level definitions and macros */
#define MCFCCM_CCR_LOAD (0x8000)
#define MCFCCM_CCR_MODE(x) (((x)&0x0007)<<8)
-#define MCFCCM_CCR_SZEN (0x0040)
-#define MCFCCM_CCR_PSTEN (0x0020)
+#define MCFCCM_CCR_SZEN (0x0040)
+#define MCFCCM_CCR_PSTEN (0x0020)
#define MCFCCM_CCR_BME (0x0008)
-#define MCFCCM_CCR_BMT(x) (((x)&0x0007))
+#define MCFCCM_CCR_BMT(x) (((x)&0x0007))
#define MCFCCM_CIR_PIN_MASK (0xFF00)
#define MCFCCM_CIR_PRN_MASK (0x00FF)
/* Clock Module */
-#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_MBAR+0x120000))
-#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_MBAR+0x120002))
+#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_MBAR+0x120000))
+#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_MBAR+0x120002))
-#define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12)
-#define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8)
-#define MCFCLOCK_SYNSR_LOCK 0x08
+#define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12)
+#define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8)
+#define MCFCLOCK_SYNSR_LOCK 0x08
#define MCFSDRAMC_DCR (*(vu_short *)(CFG_MBAR+0x00000040))
#define MCFSDRAMC_DACR0 (*(vu_long *) (CFG_MBAR+0x00000048))
@@ -337,19 +426,19 @@
#define MCFSDRAMC_DACR_IMRS (0x00000040)
#define MCFSDRAMC_DMR_BAM_16M (0x00FC0000)
-#define MCFSDRAMC_DMR_WP (0x00000100)
-#define MCFSDRAMC_DMR_CI (0x00000040)
-#define MCFSDRAMC_DMR_AM (0x00000020)
-#define MCFSDRAMC_DMR_SC (0x00000010)
-#define MCFSDRAMC_DMR_SD (0x00000008)
-#define MCFSDRAMC_DMR_UC (0x00000004)
-#define MCFSDRAMC_DMR_UD (0x00000002)
-#define MCFSDRAMC_DMR_V (0x00000001)
-
-#define MCFWTM_WCR (*(vu_short *)(CFG_MBAR+0x00140000))
-#define MCFWTM_WMR (*(vu_short *)(CFG_MBAR+0x00140002))
-#define MCFWTM_WCNTR (*(vu_short *)(CFG_MBAR+0x00140004))
-#define MCFWTM_WSR (*(vu_short *)(CFG_MBAR+0x00140006))
+#define MCFSDRAMC_DMR_WP (0x00000100)
+#define MCFSDRAMC_DMR_CI (0x00000040)
+#define MCFSDRAMC_DMR_AM (0x00000020)
+#define MCFSDRAMC_DMR_SC (0x00000010)
+#define MCFSDRAMC_DMR_SD (0x00000008)
+#define MCFSDRAMC_DMR_UC (0x00000004)
+#define MCFSDRAMC_DMR_UD (0x00000002)
+#define MCFSDRAMC_DMR_V (0x00000001)
+
+#define MCFWTM_WCR (*(vu_short *)(CFG_MBAR+0x00140000))
+#define MCFWTM_WMR (*(vu_short *)(CFG_MBAR+0x00140002))
+#define MCFWTM_WCNTR (*(vu_short *)(CFG_MBAR+0x00140004))
+#define MCFWTM_WSR (*(vu_short *)(CFG_MBAR+0x00140006))
/* Chip SELECT Module CSM */
#define MCFCSM_CSAR0 (*(vu_short *)(CFG_MBAR+0x00000080))
@@ -375,9 +464,7 @@
#define MCFCSM_CSCR_PS_16 (0x0080)
/*********************************************************************
-*
* General Purpose Timer (GPT) Module
-*
*********************************************************************/
#define MCFGPTA_GPTIOS (*(vu_char *)(CFG_MBAR+0x1A0000))
@@ -403,7 +490,6 @@
#define MCFGPTA_GPTPORT (*(vu_char *)(CFG_MBAR+0x1A001D))
#define MCFGPTA_GPTDDR (*(vu_char *)(CFG_MBAR+0x1A001E))
-
#define MCFGPTB_GPTIOS (*(vu_char *)(CFG_MBAR+0x1B0000))
#define MCFGPTB_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1B0001))
#define MCFGPTB_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1B0002))
@@ -542,4 +628,4 @@
#define MCFCFM_CMD_MASERS 0x41
/****************************************************************************/
-#endif /* m5282_h */
+#endif /* m5282_h */
diff --git a/include/asm-m68k/m5329.h b/include/asm-m68k/m5329.h
new file mode 100644
index 0000000..cd69fb0
--- /dev/null
+++ b/include/asm-m68k/m5329.h
@@ -0,0 +1,1658 @@
+/*
+ * mcf5329.h -- Definitions for Freescale Coldfire 5329
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef mcf5329_h
+#define mcf5329_h
+/****************************************************************************/
+
+/*********************************************************************
+* System Control Module (SCM)
+*********************************************************************/
+/* Bit definitions and macros for SCM_MPR */
+#define SCM_MPR_MPROT0(x) (((x)&0x0F)<<28)
+#define SCM_MPR_MPROT1(x) (((x)&0x0F)<<24)
+#define SCM_MPR_MPROT2(x) (((x)&0x0F)<<20)
+#define SCM_MPR_MPROT4(x) (((x)&0x0F)<<12)
+#define SCM_MPR_MPROT5(x) (((x)&0x0F)<<8)
+#define SCM_MPR_MPROT6(x) (((x)&0x0F)<<4)
+#define MPROT_MTR 4
+#define MPROT_MTW 2
+#define MPROT_MPL 1
+
+/* Bit definitions and macros for SCM_BMT */
+#define BMT_BME (0x08)
+#define BMT_8 (0x07)
+#define BMT_16 (0x06)
+#define BMT_32 (0x05)
+#define BMT_64 (0x04)
+#define BMT_128 (0x03)
+#define BMT_256 (0x02)
+#define BMT_512 (0x01)
+#define BMT_1024 (0x00)
+
+/* Bit definitions and macros for SCM_PACRA */
+#define SCM_PACRA_PACR0(x) (((x)&0x0F)<<28)
+#define SCM_PACRA_PACR1(x) (((x)&0x0F)<<24)
+#define SCM_PACRA_PACR2(x) (((x)&0x0F)<<20)
+#define PACR_SP 4
+#define PACR_WP 2
+#define PACR_TP 1
+
+/* Bit definitions and macros for SCM_PACRB */
+#define SCM_PACRB_PACR8(x) (((x)&0x0F)<<28)
+#define SCM_PACRB_PACR12(x) (((x)&0x0F)<<12)
+
+/* Bit definitions and macros for SCM_PACRC */
+#define SCM_PACRC_PACR16(x) (((x)&0x0F)<<28)
+#define SCM_PACRC_PACR17(x) (((x)&0x0F)<<24)
+#define SCM_PACRC_PACR18(x) (((x)&0x0F)<<20)
+#define SCM_PACRC_PACR19(x) (((x)&0x0F)<<16)
+#define SCM_PACRC_PACR21(x) (((x)&0x0F)<<8)
+#define SCM_PACRC_PACR22(x) (((x)&0x0F)<<4)
+#define SCM_PACRC_PACR23(x) (((x)&0x0F)<<0)
+
+/* Bit definitions and macros for SCM_PACRD */
+#define SCM_PACRD_PACR24(x) (((x)&0x0F)<<28)
+#define SCM_PACRD_PACR25(x) (((x)&0x0F)<<24)
+#define SCM_PACRD_PACR26(x) (((x)&0x0F)<<20)
+#define SCM_PACRD_PACR28(x) (((x)&0x0F)<<12)
+#define SCM_PACRD_PACR29(x) (((x)&0x0F)<<8)
+#define SCM_PACRD_PACR30(x) (((x)&0x0F)<<4)
+#define SCM_PACRD_PACR31(x) (((x)&0x0F)<<0)
+
+/* Bit definitions and macros for SCM_PACRE */
+#define SCM_PACRE_PACR32(x) (((x)&0x0F)<<28)
+#define SCM_PACRE_PACR33(x) (((x)&0x0F)<<24)
+#define SCM_PACRE_PACR34(x) (((x)&0x0F)<<20)
+#define SCM_PACRE_PACR35(x) (((x)&0x0F)<<16)
+#define SCM_PACRE_PACR36(x) (((x)&0x0F)<<12)
+#define SCM_PACRE_PACR37(x) (((x)&0x0F)<<8)
+#define SCM_PACRE_PACR38(x) (((x)&0x0F)<<4)
+
+/* Bit definitions and macros for SCM_PACRF */
+#define SCM_PACRF_PACR40(x) (((x)&0x0F)<<28)
+#define SCM_PACRF_PACR41(x) (((x)&0x0F)<<24)
+#define SCM_PACRF_PACR42(x) (((x)&0x0F)<<20)
+#define SCM_PACRF_PACR43(x) (((x)&0x0F)<<16)
+#define SCM_PACRF_PACR44(x) (((x)&0x0F)<<12)
+#define SCM_PACRF_PACR45(x) (((x)&0x0F)<<8)
+#define SCM_PACRF_PACR46(x) (((x)&0x0F)<<4)
+#define SCM_PACRF_PACR47(x) (((x)&0x0F)<<0)
+
+/* Bit definitions and macros for SCM_PACRG */
+#define SCM_PACRG_PACR48(x) (((x)&0x0F)<<28)
+
+/* Bit definitions and macros for SCM_PACRH */
+#define SCM_PACRH_PACR56(x) (((x)&0x0F)<<28)
+#define SCM_PACRH_PACR57(x) (((x)&0x0F)<<24)
+#define SCM_PACRH_PACR58(x) (((x)&0x0F)<<20)
+
+/* PACRn Assignments */
+#define PACR0(x) SCM_PACRA_PACR0(x)
+#define PACR1(x) SCM_PACRA_PACR1(x)
+#define PACR2(x) SCM_PACRA_PACR2(x)
+#define PACR8(x) SCM_PACRB_PACR8(x)
+#define PACR12(x) SCM_PACRB_PACR12(x)
+#define PACR16(x) SCM_PACRC_PACR16(x)
+#define PACR17(x) SCM_PACRC_PACR17(x)
+#define PACR18(x) SCM_PACRC_PACR18(x)
+#define PACR19(x) SCM_PACRC_PACR19(x)
+#define PACR21(x) SCM_PACRC_PACR21(x)
+#define PACR22(x) SCM_PACRC_PACR22(x)
+#define PACR23(x) SCM_PACRC_PACR23(x)
+#define PACR24(x) SCM_PACRD_PACR24(x)
+#define PACR25(x) SCM_PACRD_PACR25(x)
+#define PACR26(x) SCM_PACRD_PACR26(x)
+#define PACR28(x) SCM_PACRD_PACR28(x)
+#define PACR29(x) SCM_PACRD_PACR29(x)
+#define PACR30(x) SCM_PACRD_PACR30(x)
+#define PACR31(x) SCM_PACRD_PACR31(x)
+#define PACR32(x) SCM_PACRE_PACR32(x)
+#define PACR33(x) SCM_PACRE_PACR33(x)
+#define PACR34(x) SCM_PACRE_PACR34(x)
+#define PACR35(x) SCM_PACRE_PACR35(x)
+#define PACR36(x) SCM_PACRE_PACR36(x)
+#define PACR37(x) SCM_PACRE_PACR37(x)
+#define PACR38(x) SCM_PACRE_PACR38(x)
+#define PACR40(x) SCM_PACRF_PACR40(x)
+#define PACR41(x) SCM_PACRF_PACR41(x)
+#define PACR42(x) SCM_PACRF_PACR42(x)
+#define PACR43(x) SCM_PACRF_PACR43(x)
+#define PACR44(x) SCM_PACRF_PACR44(x)
+#define PACR45(x) SCM_PACRF_PACR45(x)
+#define PACR46(x) SCM_PACRF_PACR46(x)
+#define PACR47(x) SCM_PACRF_PACR47(x)
+#define PACR48(x) SCM_PACRG_PACR48(x)
+#define PACR56(x) SCM_PACRH_PACR56(x)
+#define PACR57(x) SCM_PACRH_PACR57(x)
+#define PACR58(x) SCM_PACRH_PACR58(x)
+
+/* Bit definitions and macros for SCM_CWCR */
+#define CWCR_RO (0x8000)
+#define CWCR_CWR_WH (0x0100)
+#define CWCR_CWE (0x0080)
+#define CWRI_WINDOW (0x0060)
+#define CWRI_RESET (0x0040)
+#define CWRI_INT_RESET (0x0020)
+#define CWRI_INT (0x0000)
+#define CWCR_CWT(x) (((x)&0x001F))
+
+/* Bit definitions and macros for SCM_ISR */
+#define SCMISR_CFEI (0x02)
+#define SCMISR_CWIC (0x01)
+
+/* Bit definitions and macros for SCM_BCR */
+#define BCR_GBR (0x00000200)
+#define BCR_GBW (0x00000100)
+#define BCR_S7 (0x00000080)
+#define BCR_S6 (0x00000040)
+#define BCR_S4 (0x00000010)
+#define BCR_S1 (0x00000002)
+
+/* Bit definitions and macros for SCM_CFIER */
+#define CFIER_ECFEI (0x01)
+
+/* Bit definitions and macros for SCM_CFLOC */
+#define CFLOC_LOC (0x80)
+
+/* Bit definitions and macros for SCM_CFATR */
+#define CFATR_WRITE (0x80)
+#define CFATR_SZ32 (0x20)
+#define CFATR_SZ16 (0x10)
+#define CFATR_SZ08 (0x00)
+#define CFATR_CACHE (0x08)
+#define CFATR_MODE (0x02)
+#define CFATR_TYPE (0x01)
+
+/*********************************************************************
+* FlexBus Chip Selects (FBCS)
+*********************************************************************/
+/* Bit definitions and macros for FBCS_CSAR */
+#define CSAR_BA(x) (((x)&0xFFFF)<<16)
+
+/* Bit definitions and macros for FBCS_CSMR */
+#define CSMR_BAM(x) (((x)&0xFFFF)<<16)
+#define CSMR_BAM_4G (0xFFFF0000)
+#define CSMR_BAM_2G (0x7FFF0000)
+#define CSMR_BAM_1G (0x3FFF0000)
+#define CSMR_BAM_1024M (0x3FFF0000)
+#define CSMR_BAM_512M (0x1FFF0000)
+#define CSMR_BAM_256M (0x0FFF0000)
+#define CSMR_BAM_128M (0x07FF0000)
+#define CSMR_BAM_64M (0x03FF0000)
+#define CSMR_BAM_32M (0x01FF0000)
+#define CSMR_BAM_16M (0x00FF0000)
+#define CSMR_BAM_8M (0x007F0000)
+#define CSMR_BAM_4M (0x003F0000)
+#define CSMR_BAM_2M (0x001F0000)
+#define CSMR_BAM_1M (0x000F0000)
+#define CSMR_BAM_1024K (0x000F0000)
+#define CSMR_BAM_512K (0x00070000)
+#define CSMR_BAM_256K (0x00030000)
+#define CSMR_BAM_128K (0x00010000)
+#define CSMR_BAM_64K (0x00000000)
+#define CSMR_WP (0x00000100)
+#define CSMR_V (0x00000001)
+
+/* Bit definitions and macros for FBCS_CSCR */
+#define CSCR_SWS(x) (((x)&0x3F)<<26)
+#define CSCR_ASET(x) (((x)&0x03)<<20)
+#define CSCR_SWSEN (0x00800000)
+#define CSCR_ASET_4CLK (0x00300000)
+#define CSCR_ASET_3CLK (0x00200000)
+#define CSCR_ASET_2CLK (0x00100000)
+#define CSCR_ASET_1CLK (0x00000000)
+#define CSCR_RDAH(x) (((x)&0x03)<<18)
+#define CSCR_RDAH_4CYC (0x000C0000)
+#define CSCR_RDAH_3CYC (0x00080000)
+#define CSCR_RDAH_2CYC (0x00040000)
+#define CSCR_RDAH_1CYC (0x00000000)
+#define CSCR_WRAH(x) (((x)&0x03)<<16)
+#define CSCR_WDAH_4CYC (0x00003000)
+#define CSCR_WDAH_3CYC (0x00002000)
+#define CSCR_WDAH_2CYC (0x00001000)
+#define CSCR_WDAH_1CYC (0x00000000)
+#define CSCR_WS(x) (((x)&0x3F)<<10)
+#define CSCR_SBM (0x00000200)
+#define CSCR_AA (0x00000100)
+#define CSCR_PS_MASK (0x000000C0)
+#define CSCR_PS_32 (0x00000000)
+#define CSCR_PS_16 (0x00000080)
+#define CSCR_PS_8 (0x00000040)
+#define CSCR_BEM (0x00000020)
+#define CSCR_BSTR (0x00000010)
+#define CSCR_BSTW (0x00000008)
+
+/*********************************************************************
+* FlexCAN Module (CAN)
+*********************************************************************/
+/* Bit definitions and macros for CAN_CANMCR */
+#define CANMCR_MDIS (0x80000000)
+#define CANMCR_FRZ (0x40000000)
+#define CANMCR_HALT (0x10000000)
+#define CANMCR_NORDY (0x08000000)
+#define CANMCR_SOFTRST (0x02000000)
+#define CANMCR_FRZACK (0x01000000)
+#define CANMCR_SUPV (0x00800000)
+#define CANMCR_LPMACK (0x00100000)
+#define CANMCR_MAXMB(x) (((x)&0x0F))
+
+/* Bit definitions and macros for CAN_CANCTRL */
+#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
+#define CANCTRL_RJW(x) (((x)&0x03)<<22)
+#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
+#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
+#define CANCTRL_BOFFMSK (0x00008000)
+#define CANCTRL_ERRMSK (0x00004000)
+#define CANCTRL_CLKSRC (0x00002000)
+#define CANCTRL_LPB (0x00001000)
+#define CANCTRL_SMP (0x00000080)
+#define CANCTRL_BOFFREC (0x00000040)
+#define CANCTRL_TSYNC (0x00000020)
+#define CANCTRL_LBUF (0x00000010)
+#define CANCTRL_LOM (0x00000008)
+#define CANCTRL_PROPSEG(x) (((x)&0x07))
+
+/* Bit definitions and macros for CAN_TIMER */
+#define TIMER_TIMER(x) ((x)&0xFFFF)
+
+/* Bit definitions and macros for CAN_RXGMASK */
+#define RXGMASK_MI(x) ((x)&0x1FFFFFFF)
+
+/* Bit definitions and macros for CAN_ERRCNT */
+#define ERRCNT_TXECTR(x) (((x)&0xFF))
+#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
+
+/* Bit definitions and macros for CAN_ERRSTAT */
+#define ERRSTAT_BITERR1 (0x00008000)
+#define ERRSTAT_BITERR0 (0x00004000)
+#define ERRSTAT_ACKERR (0x00002000)
+#define ERRSTAT_CRCERR (0x00001000)
+#define ERRSTAT_FRMERR (0x00000800)
+#define ERRSTAT_STFERR (0x00000400)
+#define ERRSTAT_TXWRN (0x00000200)
+#define ERRSTAT_RXWRN (0x00000100)
+#define ERRSTAT_IDLE (0x00000080)
+#define ERRSTAT_TXRX (0x00000040)
+#define ERRSTAT_FLT_BUSOFF (0x00000020)
+#define ERRSTAT_FLT_PASSIVE (0x00000010)
+#define ERRSTAT_FLT_ACTIVE (0x00000000)
+#define ERRSTAT_BOFFINT (0x00000004)
+#define ERRSTAT_ERRINT (0x00000002)
+#define ERRSTAT_WAKINT (0x00000001)
+
+/* Bit definitions and macros for CAN_IMASK */
+#define IMASK_BUF15M (0x00008000)
+#define IMASK_BUF14M (0x00004000)
+#define IMASK_BUF13M (0x00002000)
+#define IMASK_BUF12M (0x00001000)
+#define IMASK_BUF11M (0x00000800)
+#define IMASK_BUF10M (0x00000400)
+#define IMASK_BUF9M (0x00000200)
+#define IMASK_BUF8M (0x00000100)
+#define IMASK_BUF7M (0x00000080)
+#define IMASK_BUF6M (0x00000040)
+#define IMASK_BUF5M (0x00000020)
+#define IMASK_BUF4M (0x00000010)
+#define IMASK_BUF3M (0x00000008)
+#define IMASK_BUF2M (0x00000004)
+#define IMASK_BUF1M (0x00000002)
+#define IMASK_BUF0M (0x00000001)
+
+/* Bit definitions and macros for CAN_IFLAG */
+#define IFLAG_BUF15I (0x00008000)
+#define IFLAG_BUF14I (0x00004000)
+#define IFLAG_BUF13I (0x00002000)
+#define IFLAG_BUF12I (0x00001000)
+#define IFLAG_BUF11I (0x00000800)
+#define IFLAG_BUF10I (0x00000400)
+#define IFLAG_BUF9I (0x00000200)
+#define IFLAG_BUF8I (0x00000100)
+#define IFLAG_BUF7I (0x00000080)
+#define IFLAG_BUF6I (0x00000040)
+#define IFLAG_BUF5I (0x00000020)
+#define IFLAG_BUF4I (0x00000010)
+#define IFLAG_BUF3I (0x00000008)
+#define IFLAG_BUF2I (0x00000004)
+#define IFLAG_BUF1I (0x00000002)
+#define IFLAG_BUF0I (0x00000001)
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INTC0_EPORT INTC_IPRL_INT1
+
+#define INT0_LO_RSVD0 (0)
+#define INT0_LO_EPORT1 (1)
+#define INT0_LO_EPORT2 (2)
+#define INT0_LO_EPORT3 (3)
+#define INT0_LO_EPORT4 (4)
+#define INT0_LO_EPORT5 (5)
+#define INT0_LO_EPORT6 (6)
+#define INT0_LO_EPORT7 (7)
+#define INT0_LO_EDMA_00 (8)
+#define INT0_LO_EDMA_01 (9)
+#define INT0_LO_EDMA_02 (10)
+#define INT0_LO_EDMA_03 (11)
+#define INT0_LO_EDMA_04 (12)
+#define INT0_LO_EDMA_05 (13)
+#define INT0_LO_EDMA_06 (14)
+#define INT0_LO_EDMA_07 (15)
+#define INT0_LO_EDMA_08 (16)
+#define INT0_LO_EDMA_09 (17)
+#define INT0_LO_EDMA_10 (18)
+#define INT0_LO_EDMA_11 (19)
+#define INT0_LO_EDMA_12 (20)
+#define INT0_LO_EDMA_13 (21)
+#define INT0_LO_EDMA_14 (22)
+#define INT0_LO_EDMA_15 (23)
+#define INT0_LO_EDMA_ERR (24)
+#define INT0_LO_SCM (25)
+#define INT0_LO_UART0 (26)
+#define INT0_LO_UART1 (27)
+#define INT0_LO_UART2 (28)
+#define INT0_LO_RSVD1 (29)
+#define INT0_LO_I2C (30)
+#define INT0_LO_QSPI (31)
+#define INT0_HI_DTMR0 (32)
+#define INT0_HI_DTMR1 (33)
+#define INT0_HI_DTMR2 (34)
+#define INT0_HI_DTMR3 (35)
+#define INT0_HI_FEC_TXF (36)
+#define INT0_HI_FEC_TXB (37)
+#define INT0_HI_FEC_UN (38)
+#define INT0_HI_FEC_RL (39)
+#define INT0_HI_FEC_RXF (40)
+#define INT0_HI_FEC_RXB (41)
+#define INT0_HI_FEC_MII (42)
+#define INT0_HI_FEC_LC (43)
+#define INT0_HI_FEC_HBERR (44)
+#define INT0_HI_FEC_GRA (45)
+#define INT0_HI_FEC_EBERR (46)
+#define INT0_HI_FEC_BABT (47)
+#define INT0_HI_FEC_BABR (48)
+/* 49 - 61 Reserved */
+#define INT0_HI_SCM (62)
+
+/* Bit definitions and macros for INTC_IPRH */
+#define INTC_IPRH_INT63 (0x80000000)
+#define INTC_IPRH_INT62 (0x40000000)
+#define INTC_IPRH_INT61 (0x20000000)
+#define INTC_IPRH_INT60 (0x10000000)
+#define INTC_IPRH_INT59 (0x08000000)
+#define INTC_IPRH_INT58 (0x04000000)
+#define INTC_IPRH_INT57 (0x02000000)
+#define INTC_IPRH_INT56 (0x01000000)
+#define INTC_IPRH_INT55 (0x00800000)
+#define INTC_IPRH_INT54 (0x00400000)
+#define INTC_IPRH_INT53 (0x00200000)
+#define INTC_IPRH_INT52 (0x00100000)
+#define INTC_IPRH_INT51 (0x00080000)
+#define INTC_IPRH_INT50 (0x00040000)
+#define INTC_IPRH_INT49 (0x00020000)
+#define INTC_IPRH_INT48 (0x00010000)
+#define INTC_IPRH_INT47 (0x00008000)
+#define INTC_IPRH_INT46 (0x00004000)
+#define INTC_IPRH_INT45 (0x00002000)
+#define INTC_IPRH_INT44 (0x00001000)
+#define INTC_IPRH_INT43 (0x00000800)
+#define INTC_IPRH_INT42 (0x00000400)
+#define INTC_IPRH_INT41 (0x00000200)
+#define INTC_IPRH_INT40 (0x00000100)
+#define INTC_IPRH_INT39 (0x00000080)
+#define INTC_IPRH_INT38 (0x00000040)
+#define INTC_IPRH_INT37 (0x00000020)
+#define INTC_IPRH_INT36 (0x00000010)
+#define INTC_IPRH_INT35 (0x00000008)
+#define INTC_IPRH_INT34 (0x00000004)
+#define INTC_IPRH_INT33 (0x00000002)
+#define INTC_IPRH_INT32 (0x00000001)
+
+/* Bit definitions and macros for INTC_IPRL */
+#define INTC_IPRL_INT31 (0x80000000)
+#define INTC_IPRL_INT30 (0x40000000)
+#define INTC_IPRL_INT29 (0x20000000)
+#define INTC_IPRL_INT28 (0x10000000)
+#define INTC_IPRL_INT27 (0x08000000)
+#define INTC_IPRL_INT26 (0x04000000)
+#define INTC_IPRL_INT25 (0x02000000)
+#define INTC_IPRL_INT24 (0x01000000)
+#define INTC_IPRL_INT23 (0x00800000)
+#define INTC_IPRL_INT22 (0x00400000)
+#define INTC_IPRL_INT21 (0x00200000)
+#define INTC_IPRL_INT20 (0x00100000)
+#define INTC_IPRL_INT19 (0x00080000)
+#define INTC_IPRL_INT18 (0x00040000)
+#define INTC_IPRL_INT17 (0x00020000)
+#define INTC_IPRL_INT16 (0x00010000)
+#define INTC_IPRL_INT15 (0x00008000)
+#define INTC_IPRL_INT14 (0x00004000)
+#define INTC_IPRL_INT13 (0x00002000)
+#define INTC_IPRL_INT12 (0x00001000)
+#define INTC_IPRL_INT11 (0x00000800)
+#define INTC_IPRL_INT10 (0x00000400)
+#define INTC_IPRL_INT9 (0x00000200)
+#define INTC_IPRL_INT8 (0x00000100)
+#define INTC_IPRL_INT7 (0x00000080)
+#define INTC_IPRL_INT6 (0x00000040)
+#define INTC_IPRL_INT5 (0x00000020)
+#define INTC_IPRL_INT4 (0x00000010)
+#define INTC_IPRL_INT3 (0x00000008)
+#define INTC_IPRL_INT2 (0x00000004)
+#define INTC_IPRL_INT1 (0x00000002)
+#define INTC_IPRL_INT0 (0x00000001)
+
+/* Bit definitions and macros for INTC_ICONFIG */
+#define INTC_ICFG_ELVLPRI7 (0x8000)
+#define INTC_ICFG_ELVLPRI6 (0x4000)
+#define INTC_ICFG_ELVLPRI5 (0x2000)
+#define INTC_ICFG_ELVLPRI4 (0x1000)
+#define INTC_ICFG_ELVLPRI3 (0x0800)
+#define INTC_ICFG_ELVLPRI2 (0x0400)
+#define INTC_ICFG_ELVLPRI1 (0x0200)
+#define INTC_ICFG_EMASK (0x0020)
+
+/* Bit definitions and macros for INTC_SIMR */
+#define INTC_SIMR_SALL (0x40)
+#define INTC_SIMR_SIMR(x) ((x)&0x3F)
+
+/* Bit definitions and macros for INTC_CIMR */
+#define INTC_CIMR_CALL (0x40)
+#define INTC_CIMR_CIMR(x) ((x)&0x3F)
+
+/* Bit definitions and macros for INTC_CLMASK */
+#define INTC_CLMASK_CLMASK(x) ((x)&0x0F)
+
+/* Bit definitions and macros for INTC_SLMASK */
+#define INTC_SLMASK_SLMASK(x) ((x)&0x0F)
+
+/* Bit definitions and macros for INTC_ICR */
+#define INTC_ICR_IL(x) ((x)&0x07)
+
+/*********************************************************************
+* Queued Serial Peripheral Interface (QSPI)
+*********************************************************************/
+/* Bit definitions and macros for QSPI_QMR */
+#define QSPI_QMR_MSTR (0x8000)
+#define QSPI_QMR_DOHIE (0x4000)
+#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
+#define QSPI_QMR_CPOL (0x0200)
+#define QSPI_QMR_CPHA (0x0100)
+#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
+
+/* Bit definitions and macros for QSPI_QDLYR */
+#define QSPI_QDLYR_SPE (0x8000)
+#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
+#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
+
+/* Bit definitions and macros for QSPI_QWR */
+#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
+#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
+#define QSPI_QWR_CSIV (0x1000)
+#define QSPI_QWR_WRTO (0x2000)
+#define QSPI_QWR_WREN (0x4000)
+#define QSPI_QWR_HALT (0x8000)
+
+/* Bit definitions and macros for QSPI_QIR */
+#define QSPI_QIR_WCEFB (0x8000)
+#define QSPI_QIR_ABRTB (0x4000)
+#define QSPI_QIR_ABRTL (0x1000)
+#define QSPI_QIR_WCEFE (0x0800)
+#define QSPI_QIR_ABRTE (0x0400)
+#define QSPI_QIR_SPIFE (0x0100)
+#define QSPI_QIR_WCEF (0x0008)
+#define QSPI_QIR_ABRT (0x0004)
+#define QSPI_QIR_SPIF (0x0001)
+
+/* Bit definitions and macros for QSPI_QAR */
+#define QSPI_QAR_ADDR(x) ((x)&0x003F)
+#define QSPI_QAR_TRANS (0x0000)
+#define QSPI_QAR_RECV (0x0010)
+#define QSPI_QAR_CMD (0x0020)
+
+/* Bit definitions and macros for QSPI_QDR */
+#define QSPI_QDR_CONT (0x8000)
+#define QSPI_QDR_BITSE (0x4000)
+#define QSPI_QDR_DT (0x2000)
+#define QSPI_QDR_DSCK (0x1000)
+#define QSPI_QDR_QSPI_CS3 (0x0800)
+#define QSPI_QDR_QSPI_CS2 (0x0400)
+#define QSPI_QDR_QSPI_CS1 (0x0200)
+#define QSPI_QDR_QSPI_CS0 (0x0100)
+
+/*********************************************************************
+* Pulse Width Modulation (PWM)
+*********************************************************************/
+/* Bit definitions and macros for PWM_E */
+#define PWM_EN_PWME7 (0x80)
+#define PWM_EN_PWME5 (0x20)
+#define PWM_EN_PWME3 (0x08)
+#define PWM_EN_PWME1 (0x02)
+
+/* Bit definitions and macros for PWM_POL */
+#define PWM_POL_PPOL7 (0x80)
+#define PWM_POL_PPOL5 (0x20)
+#define PWM_POL_PPOL3 (0x08)
+#define PWM_POL_PPOL1 (0x02)
+
+/* Bit definitions and macros for PWM_CLK */
+#define PWM_CLK_PCLK7 (0x80)
+#define PWM_CLK_PCLK5 (0x20)
+#define PWM_CLK_PCLK3 (0x08)
+#define PWM_CLK_PCLK1 (0x02)
+
+/* Bit definitions and macros for PWM_PRCLK */
+#define PWM_PRCLK_PCKB(x) (((x)&0x07)<<4)
+#define PWM_PRCLK_PCKA(x) ((x)&0x07)
+
+/* Bit definitions and macros for PWM_CAE */
+#define PWM_CAE_CAE7 (0x80)
+#define PWM_CAE_CAE5 (0x20)
+#define PWM_CAE_CAE3 (0x08)
+#define PWM_CAE_CAE1 (0x02)
+
+/* Bit definitions and macros for PWM_CTL */
+#define PWM_CTL_CON67 (0x80)
+#define PWM_CTL_CON45 (0x40)
+#define PWM_CTL_CON23 (0x20)
+#define PWM_CTL_CON01 (0x10)
+#define PWM_CTL_PSWAR (0x08)
+#define PWM_CTL_PFRZ (0x04)
+
+/* Bit definitions and macros for PWM_SDN */
+#define PWM_SDN_IF (0x80)
+#define PWM_SDN_IE (0x40)
+#define PWM_SDN_RESTART (0x20)
+#define PWM_SDN_LVL (0x10)
+#define PWM_SDN_PWM7IN (0x04)
+#define PWM_SDN_PWM7IL (0x02)
+#define PWM_SDN_SDNEN (0x01)
+
+/*********************************************************************
+* Watchdog Timer Modules (WTM)
+*********************************************************************/
+/* Bit definitions and macros for WTM_WCR */
+#define WTM_WCR_WAIT (0x0008)
+#define WTM_WCR_DOZE (0x0004)
+#define WTM_WCR_HALTED (0x0002)
+#define WTM_WCR_EN (0x0001)
+
+/*********************************************************************
+* Chip Configuration Module (CCM)
+*********************************************************************/
+/* Bit definitions and macros for CCM_CCR */
+#define CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001)
+#define CCM_CCR_LIMP (0x0041)
+#define CCM_CCR_LOAD (0x0021)
+#define CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
+#define CCM_CCR_OSC_MODE (0x0005)
+#define CCM_CCR_PLL_MODE (0x0003)
+#define CCM_CCR_RESERVED (0x0001)
+
+/* Bit definitions and macros for CCM_RCON */
+#define CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001)
+#define CCM_RCON_LIMP (0x0041)
+#define CCM_RCON_LOAD (0x0021)
+#define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
+#define CCM_RCON_OSC_MODE (0x0005)
+#define CCM_RCON_PLL_MODE (0x0003)
+#define CCM_RCON_RESERVED (0x0001)
+
+/* Bit definitions and macros for CCM_CIR */
+#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
+#define CCM_CIR_PRN(x) ((x)&0x003F)
+
+/* Bit definitions and macros for CCM_MISCCR */
+#define CCM_MISCCR_PLL_LOCK (0x2000)
+#define CCM_MISCCR_LIMP (0x1000)
+#define CCM_MISCCR_LCD_CHEN (0x0100)
+#define CCM_MISCCR_SSI_PUE (0x0080)
+#define CCM_MISCCR_SSI_PUS (0x0040)
+#define CCM_MISCCR_TIM_DMA (0x0020)
+#define CCM_MISCCR_SSI_SRC (0x0010)
+#define CCM_MISCCR_USBDIV (0x0002)
+#define CCM_MISCCR_USBSRC (0x0001)
+
+/* Bit definitions and macros for CCM_CDR */
+#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8)
+#define CCM_CDR_SSIDIV(x) ((x)&0x000F)
+
+/* Bit definitions and macros for CCM_UHCSR */
+#define CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14)
+#define CCM_UHCSR_WKUP (0x0004)
+#define CCM_UHCSR_UHMIE (0x0002)
+#define CCM_UHCSR_XPDE (0x0001)
+
+/* Bit definitions and macros for CCM_UOCSR */
+#define CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14)
+#define CCM_UOCSR_DPPD (0x2000)
+#define CCM_UOCSR_DMPD (0x1000)
+#define CCM_UOCSR_DRV_VBUS (0x0800)
+#define CCM_UOCSR_CRG_VBUS (0x0400)
+#define CCM_UOCSR_DCR_VBUS (0x0200)
+#define CCM_UOCSR_DPPU (0x0100)
+#define CCM_UOCSR_AVLD (0x0080)
+#define CCM_UOCSR_BVLD (0x0040)
+#define CCM_UOCSR_VVLD (0x0020)
+#define CCM_UOCSR_SEND (0x0010)
+#define CCM_UOCSR_PWRFLT (0x0008)
+#define CCM_UOCSR_WKUP (0x0004)
+#define CCM_UOCSR_UOMIE (0x0002)
+#define CCM_UOCSR_XPDE (0x0001)
+
+/* not done yet */
+/*********************************************************************
+* General Purpose I/O (GPIO)
+*********************************************************************/
+/* Bit definitions and macros for GPIO_PODR_FECH_L */
+#define GPIO_PODR_FECH_L7 (0x80)
+#define GPIO_PODR_FECH_L6 (0x40)
+#define GPIO_PODR_FECH_L5 (0x20)
+#define GPIO_PODR_FECH_L4 (0x10)
+#define GPIO_PODR_FECH_L3 (0x08)
+#define GPIO_PODR_FECH_L2 (0x04)
+#define GPIO_PODR_FECH_L1 (0x02)
+#define GPIO_PODR_FECH_L0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_SSI */
+#define GPIO_PODR_SSI_4 (0x10)
+#define GPIO_PODR_SSI_3 (0x08)
+#define GPIO_PODR_SSI_2 (0x04)
+#define GPIO_PODR_SSI_1 (0x02)
+#define GPIO_PODR_SSI_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_BUSCTL */
+#define GPIO_PODR_BUSCTL_3 (0x08)
+#define GPIO_PODR_BUSCTL_2 (0x04)
+#define GPIO_PODR_BUSCTL_1 (0x02)
+#define GPIO_PODR_BUSCTL_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_BE */
+#define GPIO_PODR_BE_3 (0x08)
+#define GPIO_PODR_BE_2 (0x04)
+#define GPIO_PODR_BE_1 (0x02)
+#define GPIO_PODR_BE_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_CS */
+#define GPIO_PODR_CS_5 (0x20)
+#define GPIO_PODR_CS_4 (0x10)
+#define GPIO_PODR_CS_3 (0x08)
+#define GPIO_PODR_CS_2 (0x04)
+#define GPIO_PODR_CS_1 (0x02)
+
+/* Bit definitions and macros for GPIO_PODR_PWM */
+#define GPIO_PODR_PWM_5 (0x20)
+#define GPIO_PODR_PWM_4 (0x10)
+#define GPIO_PODR_PWM_3 (0x08)
+#define GPIO_PODR_PWM_2 (0x04)
+
+/* Bit definitions and macros for GPIO_PODR_FECI2C */
+#define GPIO_PODR_FECI2C_3 (0x08)
+#define GPIO_PODR_FECI2C_2 (0x04)
+#define GPIO_PODR_FECI2C_1 (0x02)
+#define GPIO_PODR_FECI2C_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_UART */
+#define GPIO_PODR_UART_7 (0x80)
+#define GPIO_PODR_UART_6 (0x40)
+#define GPIO_PODR_UART_5 (0x20)
+#define GPIO_PODR_UART_4 (0x10)
+#define GPIO_PODR_UART_3 (0x08)
+#define GPIO_PODR_UART_2 (0x04)
+#define GPIO_PODR_UART_1 (0x02)
+#define GPIO_PODR_UART_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_QSPI */
+#define GPIO_PODR_QSPI_5 (0x20)
+#define GPIO_PODR_QSPI_4 (0x10)
+#define GPIO_PODR_QSPI_3 (0x08)
+#define GPIO_PODR_QSPI_2 (0x04)
+#define GPIO_PODR_QSPI_1 (0x02)
+#define GPIO_PODR_QSPI_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_TIMER */
+#define GPIO_PODR_TIMER_3 (0x08)
+#define GPIO_PODR_TIMER_2 (0x04)
+#define GPIO_PODR_TIMER_1 (0x02)
+#define GPIO_PODR_TIMER_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDDATAH */
+#define GPIO_PODR_LCDDATAH_1 (0x02)
+#define GPIO_PODR_LCDDATAH_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDDATAM */
+#define GPIO_PODR_LCDDATAM_7 (0x80)
+#define GPIO_PODR_LCDDATAM_6 (0x40)
+#define GPIO_PODR_LCDDATAM_5 (0x20)
+#define GPIO_PODR_LCDDATAM_4 (0x10)
+#define GPIO_PODR_LCDDATAM_3 (0x08)
+#define GPIO_PODR_LCDDATAM_2 (0x04)
+#define GPIO_PODR_LCDDATAM_1 (0x02)
+#define GPIO_PODR_LCDDATAM_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDDATAL */
+#define GPIO_PODR_LCDDATAL_7 (0x80)
+#define GPIO_PODR_LCDDATAL_6 (0x40)
+#define GPIO_PODR_LCDDATAL_5 (0x20)
+#define GPIO_PODR_LCDDATAL_4 (0x10)
+#define GPIO_PODR_LCDDATAL_3 (0x08)
+#define GPIO_PODR_LCDDATAL_2 (0x04)
+#define GPIO_PODR_LCDDATAL_1 (0x02)
+#define GPIO_PODR_LCDDATAL_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDCTLH */
+#define GPIO_PODR_LCDCTLH_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDCTLL */
+#define GPIO_PODR_LCDCTLL_7 (0x80)
+#define GPIO_PODR_LCDCTLL_6 (0x40)
+#define GPIO_PODR_LCDCTLL_5 (0x20)
+#define GPIO_PODR_LCDCTLL_4 (0x10)
+#define GPIO_PODR_LCDCTLL_3 (0x08)
+#define GPIO_PODR_LCDCTLL_2 (0x04)
+#define GPIO_PODR_LCDCTLL_1 (0x02)
+#define GPIO_PODR_LCDCTLL_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_FECH */
+#define GPIO_PDDR_FECH_L7 (0x80)
+#define GPIO_PDDR_FECH_L6 (0x40)
+#define GPIO_PDDR_FECH_L5 (0x20)
+#define GPIO_PDDR_FECH_L4 (0x10)
+#define GPIO_PDDR_FECH_L3 (0x08)
+#define GPIO_PDDR_FECH_L2 (0x04)
+#define GPIO_PDDR_FECH_L1 (0x02)
+#define GPIO_PDDR_FECH_L0 (0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_SSI */
+#define GPIO_PDDR_SSI_4 (0x10)
+#define GPIO_PDDR_SSI_3 (0x08)
+#define GPIO_PDDR_SSI_2 (0x04)
+#define GPIO_PDDR_SSI_1 (0x02)
+#define GPIO_PDDR_SSI_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_BUSCTL */
+#define GPIO_PDDR_BUSCTL_3 (0x08)
+#define GPIO_PDDR_BUSCTL_2 (0x04)
+#define GPIO_PDDR_BUSCTL_1 (0x02)
+#define GPIO_PDDR_BUSCTL_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_BE */
+#define GPIO_PDDR_BE_3 (0x08)
+#define GPIO_PDDR_BE_2 (0x04)
+#define GPIO_PDDR_BE_1 (0x02)
+#define GPIO_PDDR_BE_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_CS */
+#define GPIO_PDDR_CS_1 (0x02)
+#define GPIO_PDDR_CS_2 (0x04)
+#define GPIO_PDDR_CS_3 (0x08)
+#define GPIO_PDDR_CS_4 (0x10)
+#define GPIO_PDDR_CS_5 (0x20)
+
+/* Bit definitions and macros for GPIO_PDDR_PWM */
+#define GPIO_PDDR_PWM_2 (0x04)
+#define GPIO_PDDR_PWM_3 (0x08)
+#define GPIO_PDDR_PWM_4 (0x10)
+#define GPIO_PDDR_PWM_5 (0x20)
+
+/* Bit definitions and macros for GPIO_PDDR_FECI2C */
+#define GPIO_PDDR_FECI2C_0 (0x01)
+#define GPIO_PDDR_FECI2C_1 (0x02)
+#define GPIO_PDDR_FECI2C_2 (0x04)
+#define GPIO_PDDR_FECI2C_3 (0x08)
+
+/* Bit definitions and macros for GPIO_PDDR_UART */
+#define GPIO_PDDR_UART_0 (0x01)
+#define GPIO_PDDR_UART_1 (0x02)
+#define GPIO_PDDR_UART_2 (0x04)
+#define GPIO_PDDR_UART_3 (0x08)
+#define GPIO_PDDR_UART_4 (0x10)
+#define GPIO_PDDR_UART_5 (0x20)
+#define GPIO_PDDR_UART_6 (0x40)
+#define GPIO_PDDR_UART_7 (0x80)
+
+/* Bit definitions and macros for GPIO_PDDR_QSPI */
+#define GPIO_PDDR_QSPI_0 (0x01)
+#define GPIO_PDDR_QSPI_1 (0x02)
+#define GPIO_PDDR_QSPI_2 (0x04)
+#define GPIO_PDDR_QSPI_3 (0x08)
+#define GPIO_PDDR_QSPI_4 (0x10)
+#define GPIO_PDDR_QSPI_5 (0x20)
+
+/* Bit definitions and macros for GPIO_PDDR_TIMER */
+#define GPIO_PDDR_TIMER_0 (0x01)
+#define GPIO_PDDR_TIMER_1 (0x02)
+#define GPIO_PDDR_TIMER_2 (0x04)
+#define GPIO_PDDR_TIMER_3 (0x08)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDDATAH */
+#define GPIO_PDDR_LCDDATAH_0 (0x01)
+#define GPIO_PDDR_LCDDATAH_1 (0x02)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDDATAM */
+#define GPIO_PDDR_LCDDATAM_0 (0x01)
+#define GPIO_PDDR_LCDDATAM_1 (0x02)
+#define GPIO_PDDR_LCDDATAM_2 (0x04)
+#define GPIO_PDDR_LCDDATAM_3 (0x08)
+#define GPIO_PDDR_LCDDATAM_4 (0x10)
+#define GPIO_PDDR_LCDDATAM_5 (0x20)
+#define GPIO_PDDR_LCDDATAM_6 (0x40)
+#define GPIO_PDDR_LCDDATAM_7 (0x80)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDDATAL */
+#define GPIO_PDDR_LCDDATAL_0 (0x01)
+#define GPIO_PDDR_LCDDATAL_1 (0x02)
+#define GPIO_PDDR_LCDDATAL_2 (0x04)
+#define GPIO_PDDR_LCDDATAL_3 (0x08)
+#define GPIO_PDDR_LCDDATAL_4 (0x10)
+#define GPIO_PDDR_LCDDATAL_5 (0x20)
+#define GPIO_PDDR_LCDDATAL_6 (0x40)
+#define GPIO_PDDR_LCDDATAL_7 (0x80)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDCTLH */
+#define GPIO_PDDR_LCDCTLH_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDCTLL */
+#define GPIO_PDDR_LCDCTLL_0 (0x01)
+#define GPIO_PDDR_LCDCTLL_1 (0x02)
+#define GPIO_PDDR_LCDCTLL_2 (0x04)
+#define GPIO_PDDR_LCDCTLL_3 (0x08)
+#define GPIO_PDDR_LCDCTLL_4 (0x10)
+#define GPIO_PDDR_LCDCTLL_5 (0x20)
+#define GPIO_PDDR_LCDCTLL_6 (0x40)
+#define GPIO_PDDR_LCDCTLL_7 (0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_FECH */
+#define GPIO_PPDSDR_FECH_L0 (0x01)
+#define GPIO_PPDSDR_FECH_L1 (0x02)
+#define GPIO_PPDSDR_FECH_L2 (0x04)
+#define GPIO_PPDSDR_FECH_L3 (0x08)
+#define GPIO_PPDSDR_FECH_L4 (0x10)
+#define GPIO_PPDSDR_FECH_L5 (0x20)
+#define GPIO_PPDSDR_FECH_L6 (0x40)
+#define GPIO_PPDSDR_FECH_L7 (0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_SSI */
+#define GPIO_PPDSDR_SSI_0 (0x01)
+#define GPIO_PPDSDR_SSI_1 (0x02)
+#define GPIO_PPDSDR_SSI_2 (0x04)
+#define GPIO_PPDSDR_SSI_3 (0x08)
+#define GPIO_PPDSDR_SSI_4 (0x10)
+
+/* Bit definitions and macros for GPIO_PPDSDR_BUSCTL */
+#define GPIO_PPDSDR_BUSCTL_0 (0x01)
+#define GPIO_PPDSDR_BUSCTL_1 (0x02)
+#define GPIO_PPDSDR_BUSCTL_2 (0x04)
+#define GPIO_PPDSDR_BUSCTL_3 (0x08)
+
+/* Bit definitions and macros for GPIO_PPDSDR_BE */
+#define GPIO_PPDSDR_BE_0 (0x01)
+#define GPIO_PPDSDR_BE_1 (0x02)
+#define GPIO_PPDSDR_BE_2 (0x04)
+#define GPIO_PPDSDR_BE_3 (0x08)
+
+/* Bit definitions and macros for GPIO_PPDSDR_CS */
+#define GPIO_PPDSDR_CS_1 (0x02)
+#define GPIO_PPDSDR_CS_2 (0x04)
+#define GPIO_PPDSDR_CS_3 (0x08)
+#define GPIO_PPDSDR_CS_4 (0x10)
+#define GPIO_PPDSDR_CS_5 (0x20)
+
+/* Bit definitions and macros for GPIO_PPDSDR_PWM */
+#define GPIO_PPDSDR_PWM_2 (0x04)
+#define GPIO_PPDSDR_PWM_3 (0x08)
+#define GPIO_PPDSDR_PWM_4 (0x10)
+#define GPIO_PPDSDR_PWM_5 (0x20)
+
+/* Bit definitions and macros for GPIO_PPDSDR_FECI2C */
+#define GPIO_PPDSDR_FECI2C_0 (0x01)
+#define GPIO_PPDSDR_FECI2C_1 (0x02)
+#define GPIO_PPDSDR_FECI2C_2 (0x04)
+#define GPIO_PPDSDR_FECI2C_3 (0x08)
+
+/* Bit definitions and macros for GPIO_PPDSDR_UART */
+#define GPIO_PPDSDR_UART_0 (0x01)
+#define GPIO_PPDSDR_UART_1 (0x02)
+#define GPIO_PPDSDR_UART_2 (0x04)
+#define GPIO_PPDSDR_UART_3 (0x08)
+#define GPIO_PPDSDR_UART_4 (0x10)
+#define GPIO_PPDSDR_UART_5 (0x20)
+#define GPIO_PPDSDR_UART_6 (0x40)
+#define GPIO_PPDSDR_UART_7 (0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_QSPI */
+#define GPIO_PPDSDR_QSPI_0 (0x01)
+#define GPIO_PPDSDR_QSPI_1 (0x02)
+#define GPIO_PPDSDR_QSPI_2 (0x04)
+#define GPIO_PPDSDR_QSPI_3 (0x08)
+#define GPIO_PPDSDR_QSPI_4 (0x10)
+#define GPIO_PPDSDR_QSPI_5 (0x20)
+
+/* Bit definitions and macros for GPIO_PPDSDR_TIMER */
+#define GPIO_PPDSDR_TIMER_0 (0x01)
+#define GPIO_PPDSDR_TIMER_1 (0x02)
+#define GPIO_PPDSDR_TIMER_2 (0x04)
+#define GPIO_PPDSDR_TIMER_3 (0x08)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAH */
+#define GPIO_PPDSDR_LCDDATAH_0 (0x01)
+#define GPIO_PPDSDR_LCDDATAH_1 (0x02)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAM */
+#define GPIO_PPDSDR_LCDDATAM_0 (0x01)
+#define GPIO_PPDSDR_LCDDATAM_1 (0x02)
+#define GPIO_PPDSDR_LCDDATAM_2 (0x04)
+#define GPIO_PPDSDR_LCDDATAM_3 (0x08)
+#define GPIO_PPDSDR_LCDDATAM_4 (0x10)
+#define GPIO_PPDSDR_LCDDATAM_5 (0x20)
+#define GPIO_PPDSDR_LCDDATAM_6 (0x40)
+#define GPIO_PPDSDR_LCDDATAM_7 (0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAL */
+#define GPIO_PPDSDR_LCDDATAL_0 (0x01)
+#define GPIO_PPDSDR_LCDDATAL_1 (0x02)
+#define GPIO_PPDSDR_LCDDATAL_2 (0x04)
+#define GPIO_PPDSDR_LCDDATAL_3 (0x08)
+#define GPIO_PPDSDR_LCDDATAL_4 (0x10)
+#define GPIO_PPDSDR_LCDDATAL_5 (0x20)
+#define GPIO_PPDSDR_LCDDATAL_6 (0x40)
+#define GPIO_PPDSDR_LCDDATAL_7 (0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDCTLH */
+#define GPIO_PPDSDR_LCDCTLH_0 (0x01)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDCTLL */
+#define GPIO_PPDSDR_LCDCTLL_0 (0x01)
+#define GPIO_PPDSDR_LCDCTLL_1 (0x02)
+#define GPIO_PPDSDR_LCDCTLL_2 (0x04)
+#define GPIO_PPDSDR_LCDCTLL_3 (0x08)
+#define GPIO_PPDSDR_LCDCTLL_4 (0x10)
+#define GPIO_PPDSDR_LCDCTLL_5 (0x20)
+#define GPIO_PPDSDR_LCDCTLL_6 (0x40)
+#define GPIO_PPDSDR_LCDCTLL_7 (0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_FECH */
+#define GPIO_PCLRR_FECH_L0 (0x01)
+#define GPIO_PCLRR_FECH_L1 (0x02)
+#define GPIO_PCLRR_FECH_L2 (0x04)
+#define GPIO_PCLRR_FECH_L3 (0x08)
+#define GPIO_PCLRR_FECH_L4 (0x10)
+#define GPIO_PCLRR_FECH_L5 (0x20)
+#define GPIO_PCLRR_FECH_L6 (0x40)
+#define GPIO_PCLRR_FECH_L7 (0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_SSI */
+#define GPIO_PCLRR_SSI_0 (0x01)
+#define GPIO_PCLRR_SSI_1 (0x02)
+#define GPIO_PCLRR_SSI_2 (0x04)
+#define GPIO_PCLRR_SSI_3 (0x08)
+#define GPIO_PCLRR_SSI_4 (0x10)
+
+/* Bit definitions and macros for GPIO_PCLRR_BUSCTL */
+#define GPIO_PCLRR_BUSCTL_L0 (0x01)
+#define GPIO_PCLRR_BUSCTL_L1 (0x02)
+#define GPIO_PCLRR_BUSCTL_L2 (0x04)
+#define GPIO_PCLRR_BUSCTL_L3 (0x08)
+
+/* Bit definitions and macros for GPIO_PCLRR_BE */
+#define GPIO_PCLRR_BE_0 (0x01)
+#define GPIO_PCLRR_BE_1 (0x02)
+#define GPIO_PCLRR_BE_2 (0x04)
+#define GPIO_PCLRR_BE_3 (0x08)
+
+/* Bit definitions and macros for GPIO_PCLRR_CS */
+#define GPIO_PCLRR_CS_1 (0x02)
+#define GPIO_PCLRR_CS_2 (0x04)
+#define GPIO_PCLRR_CS_3 (0x08)
+#define GPIO_PCLRR_CS_4 (0x10)
+#define GPIO_PCLRR_CS_5 (0x20)
+
+/* Bit definitions and macros for GPIO_PCLRR_PWM */
+#define GPIO_PCLRR_PWM_2 (0x04)
+#define GPIO_PCLRR_PWM_3 (0x08)
+#define GPIO_PCLRR_PWM_4 (0x10)
+#define GPIO_PCLRR_PWM_5 (0x20)
+
+/* Bit definitions and macros for GPIO_PCLRR_FECI2C */
+#define GPIO_PCLRR_FECI2C_0 (0x01)
+#define GPIO_PCLRR_FECI2C_1 (0x02)
+#define GPIO_PCLRR_FECI2C_2 (0x04)
+#define GPIO_PCLRR_FECI2C_3 (0x08)
+
+/* Bit definitions and macros for GPIO_PCLRR_UART */
+#define GPIO_PCLRR_UART0 (0x01)
+#define GPIO_PCLRR_UART1 (0x02)
+#define GPIO_PCLRR_UART2 (0x04)
+#define GPIO_PCLRR_UART3 (0x08)
+#define GPIO_PCLRR_UART4 (0x10)
+#define GPIO_PCLRR_UART5 (0x20)
+#define GPIO_PCLRR_UART6 (0x40)
+#define GPIO_PCLRR_UART7 (0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_QSPI */
+#define GPIO_PCLRR_QSPI0 (0x01)
+#define GPIO_PCLRR_QSPI1 (0x02)
+#define GPIO_PCLRR_QSPI2 (0x04)
+#define GPIO_PCLRR_QSPI3 (0x08)
+#define GPIO_PCLRR_QSPI4 (0x10)
+#define GPIO_PCLRR_QSPI5 (0x20)
+
+/* Bit definitions and macros for GPIO_PCLRR_TIMER */
+#define GPIO_PCLRR_TIMER0 (0x01)
+#define GPIO_PCLRR_TIMER1 (0x02)
+#define GPIO_PCLRR_TIMER2 (0x04)
+#define GPIO_PCLRR_TIMER3 (0x08)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDDATAH */
+#define GPIO_PCLRR_LCDDATAH0 (0x01)
+#define GPIO_PCLRR_LCDDATAH1 (0x02)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDDATAM */
+#define GPIO_PCLRR_LCDDATAM0 (0x01)
+#define GPIO_PCLRR_LCDDATAM1 (0x02)
+#define GPIO_PCLRR_LCDDATAM2 (0x04)
+#define GPIO_PCLRR_LCDDATAM3 (0x08)
+#define GPIO_PCLRR_LCDDATAM4 (0x10)
+#define GPIO_PCLRR_LCDDATAM5 (0x20)
+#define GPIO_PCLRR_LCDDATAM6 (0x40)
+#define GPIO_PCLRR_LCDDATAM7 (0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDDATAL */
+#define GPIO_PCLRR_LCDDATAL0 (0x01)
+#define GPIO_PCLRR_LCDDATAL1 (0x02)
+#define GPIO_PCLRR_LCDDATAL2 (0x04)
+#define GPIO_PCLRR_LCDDATAL3 (0x08)
+#define GPIO_PCLRR_LCDDATAL4 (0x10)
+#define GPIO_PCLRR_LCDDATAL5 (0x20)
+#define GPIO_PCLRR_LCDDATAL6 (0x40)
+#define GPIO_PCLRR_LCDDATAL7 (0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDCTLH */
+#define GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDCTLL */
+#define GPIO_PCLRR_LCDCTLL0 (0x01)
+#define GPIO_PCLRR_LCDCTLL1 (0x02)
+#define GPIO_PCLRR_LCDCTLL2 (0x04)
+#define GPIO_PCLRR_LCDCTLL3 (0x08)
+#define GPIO_PCLRR_LCDCTLL4 (0x10)
+#define GPIO_PCLRR_LCDCTLL5 (0x20)
+#define GPIO_PCLRR_LCDCTLL6 (0x40)
+#define GPIO_PCLRR_LCDCTLL7 (0x80)
+
+/* Bit definitions and macros for GPIO_PAR_FEC */
+#define GPIO_PAR_FEC_MII(x) (((x)&0x03)<<0)
+#define GPIO_PAR_FEC_7W(x) (((x)&0x03)<<2)
+#define GPIO_PAR_FEC_7W_GPIO (0x00)
+#define GPIO_PAR_FEC_7W_URTS1 (0x04)
+#define GPIO_PAR_FEC_7W_FEC (0x0C)
+#define GPIO_PAR_FEC_MII_GPIO (0x00)
+#define GPIO_PAR_FEC_MII_UART (0x01)
+#define GPIO_PAR_FEC_MII_FEC (0x03)
+
+/* Bit definitions and macros for GPIO_PAR_PWM */
+#define GPIO_PAR_PWM1(x) (((x)&0x03)<<0)
+#define GPIO_PAR_PWM3(x) (((x)&0x03)<<2)
+#define GPIO_PAR_PWM5 (0x10)
+#define GPIO_PAR_PWM7 (0x20)
+
+/* Bit definitions and macros for GPIO_PAR_BUSCTL */
+#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<3)
+#define GPIO_PAR_BUSCTL_RWB (0x20)
+#define GPIO_PAR_BUSCTL_TA (0x40)
+#define GPIO_PAR_BUSCTL_OE (0x80)
+#define GPIO_PAR_BUSCTL_OE_GPIO (0x00)
+#define GPIO_PAR_BUSCTL_OE_OE (0x80)
+#define GPIO_PAR_BUSCTL_TA_GPIO (0x00)
+#define GPIO_PAR_BUSCTL_TA_TA (0x40)
+#define GPIO_PAR_BUSCTL_RWB_GPIO (0x00)
+#define GPIO_PAR_BUSCTL_RWB_RWB (0x20)
+#define GPIO_PAR_BUSCTL_TS_GPIO (0x00)
+#define GPIO_PAR_BUSCTL_TS_DACK0 (0x10)
+#define GPIO_PAR_BUSCTL_TS_TS (0x18)
+
+/* Bit definitions and macros for GPIO_PAR_FECI2C */
+#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x03)<<0)
+#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2)
+#define GPIO_PAR_FECI2C_MDIO(x) (((x)&0x03)<<4)
+#define GPIO_PAR_FECI2C_MDC(x) (((x)&0x03)<<6)
+#define GPIO_PAR_FECI2C_MDC_GPIO (0x00)
+#define GPIO_PAR_FECI2C_MDC_UTXD2 (0x40)
+#define GPIO_PAR_FECI2C_MDC_SCL (0x80)
+#define GPIO_PAR_FECI2C_MDC_EMDC (0xC0)
+#define GPIO_PAR_FECI2C_MDIO_GPIO (0x00)
+#define GPIO_PAR_FECI2C_MDIO_URXD2 (0x10)
+#define GPIO_PAR_FECI2C_MDIO_SDA (0x20)
+#define GPIO_PAR_FECI2C_MDIO_EMDIO (0x30)
+#define GPIO_PAR_FECI2C_SCL_GPIO (0x00)
+#define GPIO_PAR_FECI2C_SCL_UTXD2 (0x04)
+#define GPIO_PAR_FECI2C_SCL_SCL (0x0C)
+#define GPIO_PAR_FECI2C_SDA_GPIO (0x00)
+#define GPIO_PAR_FECI2C_SDA_URXD2 (0x02)
+#define GPIO_PAR_FECI2C_SDA_SDA (0x03)
+
+/* Bit definitions and macros for GPIO_PAR_BE */
+#define GPIO_PAR_BE0 (0x01)
+#define GPIO_PAR_BE1 (0x02)
+#define GPIO_PAR_BE2 (0x04)
+#define GPIO_PAR_BE3 (0x08)
+
+/* Bit definitions and macros for GPIO_PAR_CS */
+#define GPIO_PAR_CS1 (0x02)
+#define GPIO_PAR_CS2 (0x04)
+#define GPIO_PAR_CS3 (0x08)
+#define GPIO_PAR_CS4 (0x10)
+#define GPIO_PAR_CS5 (0x20)
+#define GPIO_PAR_CS1_GPIO (0x00)
+#define GPIO_PAR_CS1_SDCS1 (0x01)
+#define GPIO_PAR_CS1_CS1 (0x03)
+
+/* Bit definitions and macros for GPIO_PAR_SSI */
+#define GPIO_PAR_SSI_MCLK (0x0080)
+#define GPIO_PAR_SSI_TXD(x) (((x)&0x0003)<<8)
+#define GPIO_PAR_SSI_RXD(x) (((x)&0x0003)<<10)
+#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<12)
+#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for GPIO_PAR_UART */
+#define GPIO_PAR_UART_TXD0 (0x0001)
+#define GPIO_PAR_UART_RXD0 (0x0002)
+#define GPIO_PAR_UART_RTS0 (0x0004)
+#define GPIO_PAR_UART_CTS0 (0x0008)
+#define GPIO_PAR_UART_TXD1(x) (((x)&0x0003)<<4)
+#define GPIO_PAR_UART_RXD1(x) (((x)&0x0003)<<6)
+#define GPIO_PAR_UART_RTS1(x) (((x)&0x0003)<<8)
+#define GPIO_PAR_UART_CTS1(x) (((x)&0x0003)<<10)
+#define GPIO_PAR_UART_CTS1_GPIO (0x0000)
+#define GPIO_PAR_UART_CTS1_SSI_BCLK (0x0800)
+#define GPIO_PAR_UART_CTS1_ULPI_D7 (0x0400)
+#define GPIO_PAR_UART_CTS1_UCTS1 (0x0C00)
+#define GPIO_PAR_UART_RTS1_GPIO (0x0000)
+#define GPIO_PAR_UART_RTS1_SSI_FS (0x0200)
+#define GPIO_PAR_UART_RTS1_ULPI_D6 (0x0100)
+#define GPIO_PAR_UART_RTS1_URTS1 (0x0300)
+#define GPIO_PAR_UART_RXD1_GPIO (0x0000)
+#define GPIO_PAR_UART_RXD1_SSI_RXD (0x0080)
+#define GPIO_PAR_UART_RXD1_ULPI_D5 (0x0040)
+#define GPIO_PAR_UART_RXD1_URXD1 (0x00C0)
+#define GPIO_PAR_UART_TXD1_GPIO (0x0000)
+#define GPIO_PAR_UART_TXD1_SSI_TXD (0x0020)
+#define GPIO_PAR_UART_TXD1_ULPI_D4 (0x0010)
+#define GPIO_PAR_UART_TXD1_UTXD1 (0x0030)
+
+/* Bit definitions and macros for GPIO_PAR_QSPI */
+#define GPIO_PAR_QSPI_SCK(x) (((x)&0x0003)<<4)
+#define GPIO_PAR_QSPI_DOUT(x) (((x)&0x0003)<<6)
+#define GPIO_PAR_QSPI_DIN(x) (((x)&0x0003)<<8)
+#define GPIO_PAR_QSPI_PCS0(x) (((x)&0x0003)<<10)
+#define GPIO_PAR_QSPI_PCS1(x) (((x)&0x0003)<<12)
+#define GPIO_PAR_QSPI_PCS2(x) (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for GPIO_PAR_TIMER */
+#define GPIO_PAR_TIN0(x) (((x)&0x03)<<0)
+#define GPIO_PAR_TIN1(x) (((x)&0x03)<<2)
+#define GPIO_PAR_TIN2(x) (((x)&0x03)<<4)
+#define GPIO_PAR_TIN3(x) (((x)&0x03)<<6)
+#define GPIO_PAR_TIN3_GPIO (0x00)
+#define GPIO_PAR_TIN3_TOUT3 (0x80)
+#define GPIO_PAR_TIN3_URXD2 (0x40)
+#define GPIO_PAR_TIN3_TIN3 (0xC0)
+#define GPIO_PAR_TIN2_GPIO (0x00)
+#define GPIO_PAR_TIN2_TOUT2 (0x20)
+#define GPIO_PAR_TIN2_UTXD2 (0x10)
+#define GPIO_PAR_TIN2_TIN2 (0x30)
+#define GPIO_PAR_TIN1_GPIO (0x00)
+#define GPIO_PAR_TIN1_TOUT1 (0x08)
+#define GPIO_PAR_TIN1_DACK1 (0x04)
+#define GPIO_PAR_TIN1_TIN1 (0x0C)
+#define GPIO_PAR_TIN0_GPIO (0x00)
+#define GPIO_PAR_TIN0_TOUT0 (0x02)
+#define GPIO_PAR_TIN0_DREQ0 (0x01)
+#define GPIO_PAR_TIN0_TIN0 (0x03)
+
+/* Bit definitions and macros for GPIO_PAR_LCDDATA */
+#define GPIO_PAR_LCDDATA_LD7_0(x) ((x)&0x03)
+#define GPIO_PAR_LCDDATA_LD15_8(x) (((x)&0x03)<<2)
+#define GPIO_PAR_LCDDATA_LD16(x) (((x)&0x03)<<4)
+#define GPIO_PAR_LCDDATA_LD17(x) (((x)&0x03)<<6)
+
+/* Bit definitions and macros for GPIO_PAR_LCDCTL */
+#define GPIO_PAR_LCDCTL_CLS (0x0001)
+#define GPIO_PAR_LCDCTL_PS (0x0002)
+#define GPIO_PAR_LCDCTL_REV (0x0004)
+#define GPIO_PAR_LCDCTL_SPL_SPR (0x0008)
+#define GPIO_PAR_LCDCTL_CONTRAST (0x0010)
+#define GPIO_PAR_LCDCTL_LSCLK (0x0020)
+#define GPIO_PAR_LCDCTL_LP_HSYNC (0x0040)
+#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x0080)
+#define GPIO_PAR_LCDCTL_ACD_OE (0x0100)
+
+/* Bit definitions and macros for GPIO_PAR_IRQ */
+#define GPIO_PAR_IRQ1(x) (((x)&0x0003)<<4)
+#define GPIO_PAR_IRQ2(x) (((x)&0x0003)<<6)
+#define GPIO_PAR_IRQ4(x) (((x)&0x0003)<<8)
+#define GPIO_PAR_IRQ5(x) (((x)&0x0003)<<10)
+#define GPIO_PAR_IRQ6(x) (((x)&0x0003)<<12)
+
+/* Bit definitions and macros for GPIO_MSCR_FLEXBUS */
+#define GPIO_MSCR_FLEXBUS_ADDRCTL(x) ((x)&0x03)
+#define GPIO_MSCR_FLEXBUS_DLOWER(x) (((x)&0x03)<<2)
+#define GPIO_MSCR_FLEXBUS_DUPPER(x) (((x)&0x03)<<4)
+
+/* Bit definitions and macros for GPIO_MSCR_SDRAM */
+#define GPIO_MSCR_SDRAM_SDRAM(x) ((x)&0x03)
+#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2)
+#define GPIO_MSCR_SDRAM_SDCLKB(x) (((x)&0x03)<<4)
+
+/* Bit definitions and macros for GPIO_DSCR_I2C */
+#define GPIO_DSCR_I2C_DSE(x) ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_PWM */
+#define GPIO_DSCR_PWM_DSE(x) ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_FEC */
+#define GPIO_DSCR_FEC_DSE(x) ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_UART */
+#define GPIO_DSCR_UART0_DSE(x) ((x)&0x03)
+#define GPIO_DSCR_UART1_DSE(x) (((x)&0x03)<<2)
+
+/* Bit definitions and macros for GPIO_DSCR_QSPI */
+#define GPIO_DSCR_QSPI_DSE(x) ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_TIMER */
+#define GPIO_DSCR_TIMER_DSE(x) ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_SSI */
+#define GPIO_DSCR_SSI_DSE(x) ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_LCD */
+#define GPIO_DSCR_LCD_DSE(x) ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_DEBUG */
+#define GPIO_DSCR_DEBUG_DSE(x) ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_CLKRST */
+#define GPIO_DSCR_CLKRST_DSE(x) ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_IRQ */
+#define GPIO_DSCR_IRQ_DSE(x) ((x)&0x03)
+
+/* not done yet */
+/*********************************************************************
+* LCD Controller (LCDC)
+*********************************************************************/
+/* Bit definitions and macros for LCDC_LSSAR */
+#define LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for LCDC_LSR */
+#define LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0)
+#define LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20)
+
+/* Bit definitions and macros for LCDC_LVPWR */
+#define LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0)
+
+/* Bit definitions and macros for LCDC_LCPR */
+#define LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0)
+#define LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16)
+#define LCDC_LCPR_OP (0x10000000)
+#define LCDC_LCPR_CC(x) (((x)&0x00000003)<<30)
+#define LCDC_LCPR_CC_TRANSPARENT (0x00000000)
+#define LCDC_LCPR_CC_OR (0x40000000)
+#define LCDC_LCPR_CC_XOR (0x80000000)
+#define LCDC_LCPR_CC_AND (0xC0000000)
+#define LCDC_LCPR_OP_ON (0x10000000)
+#define LCDC_LCPR_OP_OFF (0x00000000)
+
+/* Bit definitions and macros for LCDC_LCWHBR */
+#define LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0)
+#define LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16)
+#define LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24)
+#define LCDC_LCWHBR_BK_EN (0x80000000)
+#define LCDC_LCWHBR_BK_EN_ON (0x80000000)
+#define LCDC_LCWHBR_BK_EN_OFF (0x00000000)
+
+/* Bit definitions and macros for LCDC_LCCMR */
+#define LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0)
+#define LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6)
+#define LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12)
+
+/* Bit definitions and macros for LCDC_LPCR */
+#define LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0)
+#define LCDC_LPCR_SHARP (0x00000040)
+#define LCDC_LPCR_SCLKSEL (0x00000080)
+#define LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8)
+#define LCDC_LPCR_ACDSEL (0x00008000)
+#define LCDC_LPCR_REV_VS (0x00010000)
+#define LCDC_LPCR_SWAP_SEL (0x00020000)
+#define LCDC_LPCR_ENDSEL (0x00040000)
+#define LCDC_LPCR_SCLKIDLE (0x00080000)
+#define LCDC_LPCR_OEPOL (0x00100000)
+#define LCDC_LPCR_CLKPOL (0x00200000)
+#define LCDC_LPCR_LPPOL (0x00400000)
+#define LCDC_LPCR_FLM (0x00800000)
+#define LCDC_LPCR_PIXPOL (0x01000000)
+#define LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25)
+#define LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28)
+#define LCDC_LPCR_COLOR (0x40000000)
+#define LCDC_LPCR_TFT (0x80000000)
+#define LCDC_LPCR_MODE_MONOCHROME (0x00000000)
+#define LCDC_LPCR_MODE_CSTN (0x40000000)
+#define LCDC_LPCR_MODE_TFT (0xC0000000)
+#define LCDC_LPCR_PBSIZ_1 (0x00000000)
+#define LCDC_LPCR_PBSIZ_2 (0x10000000)
+#define LCDC_LPCR_PBSIZ_4 (0x20000000)
+#define LCDC_LPCR_PBSIZ_8 (0x30000000)
+#define LCDC_LPCR_BPIX_1bpp (0x00000000)
+#define LCDC_LPCR_BPIX_2bpp (0x02000000)
+#define LCDC_LPCR_BPIX_4bpp (0x04000000)
+#define LCDC_LPCR_BPIX_8bpp (0x06000000)
+#define LCDC_LPCR_BPIX_12bpp (0x08000000)
+#define LCDC_LPCR_BPIX_16bpp (0x0A000000)
+#define LCDC_LPCR_BPIX_18bpp (0x0C000000)
+
+#define LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30)
+
+/* Bit definitions and macros for LCDC_LHCR */
+#define LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0)
+#define LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8)
+#define LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26)
+
+/* Bit definitions and macros for LCDC_LVCR */
+#define LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0)
+#define LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8)
+#define LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26)
+
+/* Bit definitions and macros for LCDC_LPOR */
+#define LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0)
+
+/* Bit definitions and macros for LCDC_LPCCR */
+#define LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0)
+#define LCDC_LPCCR_CC_EN (0x00000100)
+#define LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9)
+#define LCDC_LPCCR_LDMSK (0x00008000)
+#define LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16)
+#define LCDC_LPCCR_SCR_LINEPULSE (0x00000000)
+#define LCDC_LPCCR_SCR_PIXELCLK (0x00002000)
+#define LCDC_LPCCR_SCR_LCDCLOCK (0x00004000)
+
+/* Bit definitions and macros for LCDC_LDCR */
+#define LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0)
+#define LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16)
+#define LCDC_LDCR_BURST (0x80000000)
+
+/* Bit definitions and macros for LCDC_LRMCR */
+#define LCDC_LRMCR_SEL_REF (0x00000001)
+
+/* Bit definitions and macros for LCDC_LICR */
+#define LCDC_LICR_INTCON (0x00000001)
+#define LCDC_LICR_INTSYN (0x00000004)
+#define LCDC_LICR_GW_INT_CON (0x00000010)
+
+/* Bit definitions and macros for LCDC_LIER */
+#define LCDC_LIER_BOF_EN (0x00000001)
+#define LCDC_LIER_EOF_EN (0x00000002)
+#define LCDC_LIER_ERR_RES_EN (0x00000004)
+#define LCDC_LIER_UDR_ERR_EN (0x00000008)
+#define LCDC_LIER_GW_BOF_EN (0x00000010)
+#define LCDC_LIER_GW_EOF_EN (0x00000020)
+#define LCDC_LIER_GW_ERR_RES_EN (0x00000040)
+#define LCDC_LIER_GW_UDR_ERR_EN (0x00000080)
+
+/* Bit definitions and macros for LCDC_LISR */
+#define LCDC_LISR_BOF (0x00000001)
+#define LCDC_LISR_EOF (0x00000002)
+#define LCDC_LISR_ERR_RES (0x00000004)
+#define LCDC_LISR_UDR_ERR (0x00000008)
+#define LCDC_LISR_GW_BOF (0x00000010)
+#define LCDC_LISR_GW_EOF (0x00000020)
+#define LCDC_LISR_GW_ERR_RES (0x00000040)
+#define LCDC_LISR_GW_UDR_ERR (0x00000080)
+
+/* Bit definitions and macros for LCDC_LGWSAR */
+#define LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for LCDC_LGWSR */
+#define LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0)
+#define LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20)
+
+/* Bit definitions and macros for LCDC_LGWVPWR */
+#define LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0)
+
+/* Bit definitions and macros for LCDC_LGWPOR */
+#define LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0)
+
+/* Bit definitions and macros for LCDC_LGWPR */
+#define LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0)
+#define LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16)
+
+/* Bit definitions and macros for LCDC_LGWCR */
+#define LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0)
+#define LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6)
+#define LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12)
+#define LCDC_LGWCR_GW_RVS (0x00200000)
+#define LCDC_LGWCR_GWE (0x00400000)
+#define LCDC_LGWCR_GWCKE (0x00800000)
+#define LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24)
+
+/* Bit definitions and macros for LCDC_LGWDCR */
+#define LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0)
+#define LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16)
+#define LCDC_LGWDCR_GWBT (0x80000000)
+
+/*********************************************************************
+* SDRAM Controller (SDRAMC)
+*********************************************************************/
+/* Bit definitions and macros for SDRAMC_SDMR */
+#define SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
+#define SDRAMC_SDMR_BNKAD_LMR (0x00000000)
+#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
+#define SDRAMC_SDMR_CMD (0x00010000)
+
+/* Bit definitions and macros for SDRAMC_SDCR */
+#define SDRAMC_SDCR_MODE_EN (0x80000000)
+#define SDRAMC_SDCR_CKE (0x40000000)
+#define SDRAMC_SDCR_DDR (0x20000000)
+#define SDRAMC_SDCR_REF (0x10000000)
+#define SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
+#define SDRAMC_SDCR_OE_RULE (0x00400000)
+#define SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
+#define SDRAMC_SDCR_PS_32 (0x00000000)
+#define SDRAMC_SDCR_PS_16 (0x00002000)
+#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8)
+#define SDRAMC_SDCR_IREF (0x00000004)
+#define SDRAMC_SDCR_IPALL (0x00000002)
+
+/* Bit definitions and macros for SDRAMC_SDCFG1 */
+#define SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
+#define SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
+#define SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
+#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
+#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
+#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
+#define SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
+
+/* Bit definitions and macros for SDRAMC_SDCFG2 */
+#define SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
+#define SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
+#define SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
+#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
+
+/* Bit definitions and macros for SDRAMC_SDDS */
+#define SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8)
+#define SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6)
+#define SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4)
+#define SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2)
+#define SDRAMC_SDDS_SB_D(x) ((x)&0x00000003)
+
+/* Bit definitions and macros for SDRAMC_SDCS */
+#define SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20)
+#define SDRAMC_SDCS_CSSZ(x) ((x)&0x0000001F)
+#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
+#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
+#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
+#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
+#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
+#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
+#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
+#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
+#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
+#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
+#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
+#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
+#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
+#define SDRAMC_SDCS_CSSZ_DIABLE (0x00000000)
+
+/*********************************************************************
+* Synchronous Serial Interface (SSI)
+*********************************************************************/
+/* Bit definitions and macros for SSI_CR */
+#define SSI_CR_CIS (0x00000200)
+#define SSI_CR_TCH (0x00000100)
+#define SSI_CR_MCE (0x00000080)
+#define SSI_CR_I2S_SLAVE (0x00000040)
+#define SSI_CR_I2S_MASTER (0x00000020)
+#define SSI_CR_I2S_NORMAL (0x00000000)
+#define SSI_CR_SYN (0x00000010)
+#define SSI_CR_NET (0x00000008)
+#define SSI_CR_RE (0x00000004)
+#define SSI_CR_TE (0x00000002)
+#define SSI_CR_SSI_EN (0x00000001)
+
+/* Bit definitions and macros for SSI_ISR */
+#define SSI_ISR_CMDAU (0x00040000)
+#define SSI_ISR_CMDDU (0x00020000)
+#define SSI_ISR_RXT (0x00010000)
+#define SSI_ISR_RDR1 (0x00008000)
+#define SSI_ISR_RDR0 (0x00004000)
+#define SSI_ISR_TDE1 (0x00002000)
+#define SSI_ISR_TDE0 (0x00001000)
+#define SSI_ISR_ROE1 (0x00000800)
+#define SSI_ISR_ROE0 (0x00000400)
+#define SSI_ISR_TUE1 (0x00000200)
+#define SSI_ISR_TUE0 (0x00000100)
+#define SSI_ISR_TFS (0x00000080)
+#define SSI_ISR_RFS (0x00000040)
+#define SSI_ISR_TLS (0x00000020)
+#define SSI_ISR_RLS (0x00000010)
+#define SSI_ISR_RFF1 (0x00000008)
+#define SSI_ISR_RFF0 (0x00000004)
+#define SSI_ISR_TFE1 (0x00000002)
+#define SSI_ISR_TFE0 (0x00000001)
+
+/* Bit definitions and macros for SSI_IER */
+#define SSI_IER_RDMAE (0x00400000)
+#define SSI_IER_RIE (0x00200000)
+#define SSI_IER_TDMAE (0x00100000)
+#define SSI_IER_TIE (0x00080000)
+#define SSI_IER_CMDAU (0x00040000)
+#define SSI_IER_CMDU (0x00020000)
+#define SSI_IER_RXT (0x00010000)
+#define SSI_IER_RDR1 (0x00008000)
+#define SSI_IER_RDR0 (0x00004000)
+#define SSI_IER_TDE1 (0x00002000)
+#define SSI_IER_TDE0 (0x00001000)
+#define SSI_IER_ROE1 (0x00000800)
+#define SSI_IER_ROE0 (0x00000400)
+#define SSI_IER_TUE1 (0x00000200)
+#define SSI_IER_TUE0 (0x00000100)
+#define SSI_IER_TFS (0x00000080)
+#define SSI_IER_RFS (0x00000040)
+#define SSI_IER_TLS (0x00000020)
+#define SSI_IER_RLS (0x00000010)
+#define SSI_IER_RFF1 (0x00000008)
+#define SSI_IER_RFF0 (0x00000004)
+#define SSI_IER_TFE1 (0x00000002)
+#define SSI_IER_TFE0 (0x00000001)
+
+/* Bit definitions and macros for SSI_TCR */
+#define SSI_TCR_TXBIT0 (0x00000200)
+#define SSI_TCR_TFEN1 (0x00000100)
+#define SSI_TCR_TFEN0 (0x00000080)
+#define SSI_TCR_TFDIR (0x00000040)
+#define SSI_TCR_TXDIR (0x00000020)
+#define SSI_TCR_TSHFD (0x00000010)
+#define SSI_TCR_TSCKP (0x00000008)
+#define SSI_TCR_TFSI (0x00000004)
+#define SSI_TCR_TFSL (0x00000002)
+#define SSI_TCR_TEFS (0x00000001)
+
+/* Bit definitions and macros for SSI_RCR */
+#define SSI_RCR_RXEXT (0x00000400)
+#define SSI_RCR_RXBIT0 (0x00000200)
+#define SSI_RCR_RFEN1 (0x00000100)
+#define SSI_RCR_RFEN0 (0x00000080)
+#define SSI_RCR_RSHFD (0x00000010)
+#define SSI_RCR_RSCKP (0x00000008)
+#define SSI_RCR_RFSI (0x00000004)
+#define SSI_RCR_RFSL (0x00000002)
+#define SSI_RCR_REFS (0x00000001)
+
+/* Bit definitions and macros for SSI_CCR */
+#define SSI_CCR_DIV2 (0x00040000)
+#define SSI_CCR_PSR (0x00020000)
+#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
+#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
+#define SSI_CCR_PM(x) ((x)&0x000000FF)
+
+/* Bit definitions and macros for SSI_FCSR */
+#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
+#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
+#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
+#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
+#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
+#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
+#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
+#define SSI_FCSR_TFWM0(x) ((x)&0x0000000F)
+
+/* Bit definitions and macros for SSI_ACR */
+#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
+#define SSI_ACR_WR (0x00000010)
+#define SSI_ACR_RD (0x00000008)
+#define SSI_ACR_TIF (0x00000004)
+#define SSI_ACR_FV (0x00000002)
+#define SSI_ACR_AC97EN (0x00000001)
+
+/* Bit definitions and macros for SSI_ACADD */
+#define SSI_ACADD_SSI_ACADD(x) ((x)&0x0007FFFF)
+
+/* Bit definitions and macros for SSI_ACDAT */
+#define SSI_ACDAT_SSI_ACDAT(x) ((x)&0x0007FFFF)
+
+/* Bit definitions and macros for SSI_ATAG */
+#define SSI_ATAG_DDI_ATAG(x) ((x)&0x0000FFFF)
+
+/*********************************************************************
+* Phase Locked Loop (PLL)
+*********************************************************************/
+/* Bit definitions and macros for PLL_PODR */
+#define PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4)
+#define PLL_PODR_BUSDIV(x) ((x)&0x0F)
+
+/* Bit definitions and macros for PLL_PLLCR */
+#define PLL_PLLCR_DITHEN (0x80)
+#define PLL_PLLCR_DITHDEV(x) ((x)&0x07)
+
+#endif /* mcf5329_h */
diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h
new file mode 100644
index 0000000..8b886b0
--- /dev/null
+++ b/include/asm-m68k/m5445x.h
@@ -0,0 +1,1541 @@
+/*
+ * MCF5445x Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MCF5445X__
+#define __MCF5445X__
+
+/*********************************************************************
+* Cross-bar switch (XBS)
+*********************************************************************/
+
+/* Bit definitions and macros for PRS group */
+#define XBS_PRS_M0(x) (((x)&0x00000007)) /* Core */
+#define XBS_PRS_M1(x) (((x)&0x00000007)<<4) /* eDMA */
+#define XBS_PRS_M2(x) (((x)&0x00000007)<<8) /* FEC0 */
+#define XBS_PRS_M3(x) (((x)&0x00000007)<<12) /* FEC1 */
+#define XBS_PRS_M5(x) (((x)&0x00000007)<<20) /* PCI controller */
+#define XBS_PRS_M6(x) (((x)&0x00000007)<<24) /* USB OTG */
+#define XBS_PRS_M7(x) (((x)&0x00000007)<<28) /* Serial Boot */
+
+/* Bit definitions and macros for CRS group */
+#define XBS_CRS_PARK(x) (((x)&0x00000007)) /* Master parking ctrl */
+#define XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) /* Parking mode ctrl */
+#define XBS_CRS_ARB (0x00000100) /* Arbitration Mode */
+#define XBS_CRS_RO (0x80000000) /* Read Only */
+
+#define XBS_CRS_PCTL_PARK_FIELD (0)
+#define XBS_CRS_PCTL_PARK_ON_LAST (1)
+#define XBS_CRS_PCTL_PARK_NONE (2)
+#define XBS_CRS_PCTL_PARK_CORE (0)
+#define XBS_CRS_PCTL_PARK_EDMA (1)
+#define XBS_CRS_PCTL_PARK_FEC0 (2)
+#define XBS_CRS_PCTL_PARK_FEC1 (3)
+#define XBS_CRS_PCTL_PARK_PCI (5)
+#define XBS_CRS_PCTL_PARK_USB (6)
+#define XBS_CRS_PCTL_PARK_SBF (7)
+
+/*********************************************************************
+* FlexBus Chip Selects (FBCS)
+*********************************************************************/
+
+/* Bit definitions and macros for CSAR group */
+#define FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for CSMR group */
+#define FBCS_CSMR_V (0x00000001) /* Valid bit */
+#define FBCS_CSMR_WP (0x00000100) /* Write protect */
+#define FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
+#define FBCS_CSMR_BAM_4G (0xFFFF0000)
+#define FBCS_CSMR_BAM_2G (0x7FFF0000)
+#define FBCS_CSMR_BAM_1G (0x3FFF0000)
+#define FBCS_CSMR_BAM_1024M (0x3FFF0000)
+#define FBCS_CSMR_BAM_512M (0x1FFF0000)
+#define FBCS_CSMR_BAM_256M (0x0FFF0000)
+#define FBCS_CSMR_BAM_128M (0x07FF0000)
+#define FBCS_CSMR_BAM_64M (0x03FF0000)
+#define FBCS_CSMR_BAM_32M (0x01FF0000)
+#define FBCS_CSMR_BAM_16M (0x00FF0000)
+#define FBCS_CSMR_BAM_8M (0x007F0000)
+#define FBCS_CSMR_BAM_4M (0x003F0000)
+#define FBCS_CSMR_BAM_2M (0x001F0000)
+#define FBCS_CSMR_BAM_1M (0x000F0000)
+#define FBCS_CSMR_BAM_1024K (0x000F0000)
+#define FBCS_CSMR_BAM_512K (0x00070000)
+#define FBCS_CSMR_BAM_256K (0x00030000)
+#define FBCS_CSMR_BAM_128K (0x00010000)
+#define FBCS_CSMR_BAM_64K (0x00000000)
+
+/* Bit definitions and macros for CSCR group */
+#define FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */
+#define FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */
+#define FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */
+#define FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */
+#define FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */
+#define FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
+#define FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
+#define FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
+#define FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
+#define FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */
+#define FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
+
+#define FBCS_CSCR_PS_8 (0x00000040)
+#define FBCS_CSCR_PS_16 (0x00000080)
+#define FBCS_CSCR_PS_32 (0x00000000)
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INT0_LO_RSVD0 (0)
+#define INT0_LO_EPORT1 (1)
+#define INT0_LO_EPORT2 (2)
+#define INT0_LO_EPORT3 (3)
+#define INT0_LO_EPORT4 (4)
+#define INT0_LO_EPORT5 (5)
+#define INT0_LO_EPORT6 (6)
+#define INT0_LO_EPORT7 (7)
+#define INT0_LO_EDMA_00 (8)
+#define INT0_LO_EDMA_01 (9)
+#define INT0_LO_EDMA_02 (10)
+#define INT0_LO_EDMA_03 (11)
+#define INT0_LO_EDMA_04 (12)
+#define INT0_LO_EDMA_05 (13)
+#define INT0_LO_EDMA_06 (14)
+#define INT0_LO_EDMA_07 (15)
+#define INT0_LO_EDMA_08 (16)
+#define INT0_LO_EDMA_09 (17)
+#define INT0_LO_EDMA_10 (18)
+#define INT0_LO_EDMA_11 (19)
+#define INT0_LO_EDMA_12 (20)
+#define INT0_LO_EDMA_13 (21)
+#define INT0_LO_EDMA_14 (22)
+#define INT0_LO_EDMA_15 (23)
+#define INT0_LO_EDMA_ERR (24)
+#define INT0_LO_SCM (25)
+#define INT0_LO_UART0 (26)
+#define INT0_LO_UART1 (27)
+#define INT0_LO_UART2 (28)
+#define INT0_LO_RSVD1 (29)
+#define INT0_LO_I2C (30)
+#define INT0_LO_QSPI (31)
+#define INT0_HI_DTMR0 (32)
+#define INT0_HI_DTMR1 (33)
+#define INT0_HI_DTMR2 (34)
+#define INT0_HI_DTMR3 (35)
+#define INT0_HI_FEC0_TXF (36)
+#define INT0_HI_FEC0_TXB (37)
+#define INT0_HI_FEC0_UN (38)
+#define INT0_HI_FEC0_RL (39)
+#define INT0_HI_FEC0_RXF (40)
+#define INT0_HI_FEC0_RXB (41)
+#define INT0_HI_FEC0_MII (42)
+#define INT0_HI_FEC0_LC (43)
+#define INT0_HI_FEC0_HBERR (44)
+#define INT0_HI_FEC0_GRA (45)
+#define INT0_HI_FEC0_EBERR (46)
+#define INT0_HI_FEC0_BABT (47)
+#define INT0_HI_FEC0_BABR (48)
+#define INT0_HI_FEC1_TXF (49)
+#define INT0_HI_FEC1_TXB (50)
+#define INT0_HI_FEC1_UN (51)
+#define INT0_HI_FEC1_RL (52)
+#define INT0_HI_FEC1_RXF (53)
+#define INT0_HI_FEC1_RXB (54)
+#define INT0_HI_FEC1_MII (55)
+#define INT0_HI_FEC1_LC (56)
+#define INT0_HI_FEC1_HBERR (57)
+#define INT0_HI_FEC1_GRA (58)
+#define INT0_HI_FEC1_EBERR (59)
+#define INT0_HI_FEC1_BABT (60)
+#define INT0_HI_FEC1_BABR (61)
+#define INT0_HI_SCMIR (62)
+#define INT0_HI_RTC_ISR (63)
+
+#define INT1_HI_DSPI_EOQF (33)
+#define INT1_HI_DSPI_TFFF (34)
+#define INT1_HI_DSPI_TCF (35)
+#define INT1_HI_DSPI_TFUF (36)
+#define INT1_HI_DSPI_RFDF (37)
+#define INT1_HI_DSPI_RFOF (38)
+#define INT1_HI_DSPI_RFOF_TFUF (39)
+#define INT1_HI_RNG_EI (40)
+#define INT1_HI_PIT0_PIF (43)
+#define INT1_HI_PIT1_PIF (44)
+#define INT1_HI_PIT2_PIF (45)
+#define INT1_HI_PIT3_PIF (46)
+#define INT1_HI_USBOTG_USBSTS (47)
+#define INT1_HI_SSI_ISR (49)
+#define INT1_HI_CCM_UOCSR (53)
+#define INT1_HI_ATA_ISR (54)
+#define INT1_HI_PCI_SCR (55)
+#define INT1_HI_PCI_ASR (56)
+#define INT1_HI_PLL_LOCKS (57)
+
+/* Bit definitions and macros for IPRH */
+#define INTC_IPRH_INT32 (0x00000001)
+#define INTC_IPRH_INT33 (0x00000002)
+#define INTC_IPRH_INT34 (0x00000004)
+#define INTC_IPRH_INT35 (0x00000008)
+#define INTC_IPRH_INT36 (0x00000010)
+#define INTC_IPRH_INT37 (0x00000020)
+#define INTC_IPRH_INT38 (0x00000040)
+#define INTC_IPRH_INT39 (0x00000080)
+#define INTC_IPRH_INT40 (0x00000100)
+#define INTC_IPRH_INT41 (0x00000200)
+#define INTC_IPRH_INT42 (0x00000400)
+#define INTC_IPRH_INT43 (0x00000800)
+#define INTC_IPRH_INT44 (0x00001000)
+#define INTC_IPRH_INT45 (0x00002000)
+#define INTC_IPRH_INT46 (0x00004000)
+#define INTC_IPRH_INT47 (0x00008000)
+#define INTC_IPRH_INT48 (0x00010000)
+#define INTC_IPRH_INT49 (0x00020000)
+#define INTC_IPRH_INT50 (0x00040000)
+#define INTC_IPRH_INT51 (0x00080000)
+#define INTC_IPRH_INT52 (0x00100000)
+#define INTC_IPRH_INT53 (0x00200000)
+#define INTC_IPRH_INT54 (0x00400000)
+#define INTC_IPRH_INT55 (0x00800000)
+#define INTC_IPRH_INT56 (0x01000000)
+#define INTC_IPRH_INT57 (0x02000000)
+#define INTC_IPRH_INT58 (0x04000000)
+#define INTC_IPRH_INT59 (0x08000000)
+#define INTC_IPRH_INT60 (0x10000000)
+#define INTC_IPRH_INT61 (0x20000000)
+#define INTC_IPRH_INT62 (0x40000000)
+#define INTC_IPRH_INT63 (0x80000000)
+
+/* Bit definitions and macros for IPRL */
+#define INTC_IPRL_INT0 (0x00000001)
+#define INTC_IPRL_INT1 (0x00000002)
+#define INTC_IPRL_INT2 (0x00000004)
+#define INTC_IPRL_INT3 (0x00000008)
+#define INTC_IPRL_INT4 (0x00000010)
+#define INTC_IPRL_INT5 (0x00000020)
+#define INTC_IPRL_INT6 (0x00000040)
+#define INTC_IPRL_INT7 (0x00000080)
+#define INTC_IPRL_INT8 (0x00000100)
+#define INTC_IPRL_INT9 (0x00000200)
+#define INTC_IPRL_INT10 (0x00000400)
+#define INTC_IPRL_INT11 (0x00000800)
+#define INTC_IPRL_INT12 (0x00001000)
+#define INTC_IPRL_INT13 (0x00002000)
+#define INTC_IPRL_INT14 (0x00004000)
+#define INTC_IPRL_INT15 (0x00008000)
+#define INTC_IPRL_INT16 (0x00010000)
+#define INTC_IPRL_INT17 (0x00020000)
+#define INTC_IPRL_INT18 (0x00040000)
+#define INTC_IPRL_INT19 (0x00080000)
+#define INTC_IPRL_INT20 (0x00100000)
+#define INTC_IPRL_INT21 (0x00200000)
+#define INTC_IPRL_INT22 (0x00400000)
+#define INTC_IPRL_INT23 (0x00800000)
+#define INTC_IPRL_INT24 (0x01000000)
+#define INTC_IPRL_INT25 (0x02000000)
+#define INTC_IPRL_INT26 (0x04000000)
+#define INTC_IPRL_INT27 (0x08000000)
+#define INTC_IPRL_INT28 (0x10000000)
+#define INTC_IPRL_INT29 (0x20000000)
+#define INTC_IPRL_INT30 (0x40000000)
+#define INTC_IPRL_INT31 (0x80000000)
+
+/* Bit definitions and macros for IMRH */
+#define INTC_IMRH_INT_MASK32 (0x00000001)
+#define INTC_IMRH_INT_MASK33 (0x00000002)
+#define INTC_IMRH_INT_MASK34 (0x00000004)
+#define INTC_IMRH_INT_MASK35 (0x00000008)
+#define INTC_IMRH_INT_MASK36 (0x00000010)
+#define INTC_IMRH_INT_MASK37 (0x00000020)
+#define INTC_IMRH_INT_MASK38 (0x00000040)
+#define INTC_IMRH_INT_MASK39 (0x00000080)
+#define INTC_IMRH_INT_MASK40 (0x00000100)
+#define INTC_IMRH_INT_MASK41 (0x00000200)
+#define INTC_IMRH_INT_MASK42 (0x00000400)
+#define INTC_IMRH_INT_MASK43 (0x00000800)
+#define INTC_IMRH_INT_MASK44 (0x00001000)
+#define INTC_IMRH_INT_MASK45 (0x00002000)
+#define INTC_IMRH_INT_MASK46 (0x00004000)
+#define INTC_IMRH_INT_MASK47 (0x00008000)
+#define INTC_IMRH_INT_MASK48 (0x00010000)
+#define INTC_IMRH_INT_MASK49 (0x00020000)
+#define INTC_IMRH_INT_MASK50 (0x00040000)
+#define INTC_IMRH_INT_MASK51 (0x00080000)
+#define INTC_IMRH_INT_MASK52 (0x00100000)
+#define INTC_IMRH_INT_MASK53 (0x00200000)
+#define INTC_IMRH_INT_MASK54 (0x00400000)
+#define INTC_IMRH_INT_MASK55 (0x00800000)
+#define INTC_IMRH_INT_MASK56 (0x01000000)
+#define INTC_IMRH_INT_MASK57 (0x02000000)
+#define INTC_IMRH_INT_MASK58 (0x04000000)
+#define INTC_IMRH_INT_MASK59 (0x08000000)
+#define INTC_IMRH_INT_MASK60 (0x10000000)
+#define INTC_IMRH_INT_MASK61 (0x20000000)
+#define INTC_IMRH_INT_MASK62 (0x40000000)
+#define INTC_IMRH_INT_MASK63 (0x80000000)
+
+/* Bit definitions and macros for IMRL */
+#define INTC_IMRL_INT_MASK0 (0x00000001)
+#define INTC_IMRL_INT_MASK1 (0x00000002)
+#define INTC_IMRL_INT_MASK2 (0x00000004)
+#define INTC_IMRL_INT_MASK3 (0x00000008)
+#define INTC_IMRL_INT_MASK4 (0x00000010)
+#define INTC_IMRL_INT_MASK5 (0x00000020)
+#define INTC_IMRL_INT_MASK6 (0x00000040)
+#define INTC_IMRL_INT_MASK7 (0x00000080)
+#define INTC_IMRL_INT_MASK8 (0x00000100)
+#define INTC_IMRL_INT_MASK9 (0x00000200)
+#define INTC_IMRL_INT_MASK10 (0x00000400)
+#define INTC_IMRL_INT_MASK11 (0x00000800)
+#define INTC_IMRL_INT_MASK12 (0x00001000)
+#define INTC_IMRL_INT_MASK13 (0x00002000)
+#define INTC_IMRL_INT_MASK14 (0x00004000)
+#define INTC_IMRL_INT_MASK15 (0x00008000)
+#define INTC_IMRL_INT_MASK16 (0x00010000)
+#define INTC_IMRL_INT_MASK17 (0x00020000)
+#define INTC_IMRL_INT_MASK18 (0x00040000)
+#define INTC_IMRL_INT_MASK19 (0x00080000)
+#define INTC_IMRL_INT_MASK20 (0x00100000)
+#define INTC_IMRL_INT_MASK21 (0x00200000)
+#define INTC_IMRL_INT_MASK22 (0x00400000)
+#define INTC_IMRL_INT_MASK23 (0x00800000)
+#define INTC_IMRL_INT_MASK24 (0x01000000)
+#define INTC_IMRL_INT_MASK25 (0x02000000)
+#define INTC_IMRL_INT_MASK26 (0x04000000)
+#define INTC_IMRL_INT_MASK27 (0x08000000)
+#define INTC_IMRL_INT_MASK28 (0x10000000)
+#define INTC_IMRL_INT_MASK29 (0x20000000)
+#define INTC_IMRL_INT_MASK30 (0x40000000)
+#define INTC_IMRL_INT_MASK31 (0x80000000)
+
+/* Bit definitions and macros for INTFRCH */
+#define INTC_INTFRCH_INTFRC32 (0x00000001)
+#define INTC_INTFRCH_INTFRC33 (0x00000002)
+#define INTC_INTFRCH_INTFRC34 (0x00000004)
+#define INTC_INTFRCH_INTFRC35 (0x00000008)
+#define INTC_INTFRCH_INTFRC36 (0x00000010)
+#define INTC_INTFRCH_INTFRC37 (0x00000020)
+#define INTC_INTFRCH_INTFRC38 (0x00000040)
+#define INTC_INTFRCH_INTFRC39 (0x00000080)
+#define INTC_INTFRCH_INTFRC40 (0x00000100)
+#define INTC_INTFRCH_INTFRC41 (0x00000200)
+#define INTC_INTFRCH_INTFRC42 (0x00000400)
+#define INTC_INTFRCH_INTFRC43 (0x00000800)
+#define INTC_INTFRCH_INTFRC44 (0x00001000)
+#define INTC_INTFRCH_INTFRC45 (0x00002000)
+#define INTC_INTFRCH_INTFRC46 (0x00004000)
+#define INTC_INTFRCH_INTFRC47 (0x00008000)
+#define INTC_INTFRCH_INTFRC48 (0x00010000)
+#define INTC_INTFRCH_INTFRC49 (0x00020000)
+#define INTC_INTFRCH_INTFRC50 (0x00040000)
+#define INTC_INTFRCH_INTFRC51 (0x00080000)
+#define INTC_INTFRCH_INTFRC52 (0x00100000)
+#define INTC_INTFRCH_INTFRC53 (0x00200000)
+#define INTC_INTFRCH_INTFRC54 (0x00400000)
+#define INTC_INTFRCH_INTFRC55 (0x00800000)
+#define INTC_INTFRCH_INTFRC56 (0x01000000)
+#define INTC_INTFRCH_INTFRC57 (0x02000000)
+#define INTC_INTFRCH_INTFRC58 (0x04000000)
+#define INTC_INTFRCH_INTFRC59 (0x08000000)
+#define INTC_INTFRCH_INTFRC60 (0x10000000)
+#define INTC_INTFRCH_INTFRC61 (0x20000000)
+#define INTC_INTFRCH_INTFRC62 (0x40000000)
+#define INTC_INTFRCH_INTFRC63 (0x80000000)
+
+/* Bit definitions and macros for INTFRCL */
+#define INTC_INTFRCL_INTFRC0 (0x00000001)
+#define INTC_INTFRCL_INTFRC1 (0x00000002)
+#define INTC_INTFRCL_INTFRC2 (0x00000004)
+#define INTC_INTFRCL_INTFRC3 (0x00000008)
+#define INTC_INTFRCL_INTFRC4 (0x00000010)
+#define INTC_INTFRCL_INTFRC5 (0x00000020)
+#define INTC_INTFRCL_INTFRC6 (0x00000040)
+#define INTC_INTFRCL_INTFRC7 (0x00000080)
+#define INTC_INTFRCL_INTFRC8 (0x00000100)
+#define INTC_INTFRCL_INTFRC9 (0x00000200)
+#define INTC_INTFRCL_INTFRC10 (0x00000400)
+#define INTC_INTFRCL_INTFRC11 (0x00000800)
+#define INTC_INTFRCL_INTFRC12 (0x00001000)
+#define INTC_INTFRCL_INTFRC13 (0x00002000)
+#define INTC_INTFRCL_INTFRC14 (0x00004000)
+#define INTC_INTFRCL_INTFRC15 (0x00008000)
+#define INTC_INTFRCL_INTFRC16 (0x00010000)
+#define INTC_INTFRCL_INTFRC17 (0x00020000)
+#define INTC_INTFRCL_INTFRC18 (0x00040000)
+#define INTC_INTFRCL_INTFRC19 (0x00080000)
+#define INTC_INTFRCL_INTFRC20 (0x00100000)
+#define INTC_INTFRCL_INTFRC21 (0x00200000)
+#define INTC_INTFRCL_INTFRC22 (0x00400000)
+#define INTC_INTFRCL_INTFRC23 (0x00800000)
+#define INTC_INTFRCL_INTFRC24 (0x01000000)
+#define INTC_INTFRCL_INTFRC25 (0x02000000)
+#define INTC_INTFRCL_INTFRC26 (0x04000000)
+#define INTC_INTFRCL_INTFRC27 (0x08000000)
+#define INTC_INTFRCL_INTFRC28 (0x10000000)
+#define INTC_INTFRCL_INTFRC29 (0x20000000)
+#define INTC_INTFRCL_INTFRC30 (0x40000000)
+#define INTC_INTFRCL_INTFRC31 (0x80000000)
+
+/* Bit definitions and macros for ICONFIG */
+#define INTC_ICONFIG_EMASK (0x0020)
+#define INTC_ICONFIG_ELVLPRI1 (0x0200)
+#define INTC_ICONFIG_ELVLPRI2 (0x0400)
+#define INTC_ICONFIG_ELVLPRI3 (0x0800)
+#define INTC_ICONFIG_ELVLPRI4 (0x1000)
+#define INTC_ICONFIG_ELVLPRI5 (0x2000)
+#define INTC_ICONFIG_ELVLPRI6 (0x4000)
+#define INTC_ICONFIG_ELVLPRI7 (0x8000)
+
+/* Bit definitions and macros for SIMR */
+#define INTC_SIMR_SIMR(x) (((x)&0x7F))
+
+/* Bit definitions and macros for CIMR */
+#define INTC_CIMR_CIMR(x) (((x)&0x7F))
+
+/* Bit definitions and macros for CLMASK */
+#define INTC_CLMASK_CLMASK(x) (((x)&0x0F))
+
+/* Bit definitions and macros for SLMASK */
+#define INTC_SLMASK_SLMASK(x) (((x)&0x0F))
+
+/* Bit definitions and macros for ICR group */
+#define INTC_ICR_IL(x) (((x)&0x07))
+
+/*********************************************************************
+* DMA Serial Peripheral Interface (DSPI)
+*********************************************************************/
+
+/* Bit definitions and macros for DMCR */
+#define DSPI_DMCR_HALT (0x00000001)
+#define DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8)
+#define DSPI_DMCR_CRXF (0x00000400)
+#define DSPI_DMCR_CTXF (0x00000800)
+#define DSPI_DMCR_DRXF (0x00001000)
+#define DSPI_DMCR_DTXF (0x00002000)
+#define DSPI_DMCR_CSIS0 (0x00010000)
+#define DSPI_DMCR_CSIS2 (0x00040000)
+#define DSPI_DMCR_CSIS3 (0x00080000)
+#define DSPI_DMCR_CSIS5 (0x00200000)
+#define DSPI_DMCR_ROOE (0x01000000)
+#define DSPI_DMCR_PCSSE (0x02000000)
+#define DSPI_DMCR_MTFE (0x04000000)
+#define DSPI_DMCR_FRZ (0x08000000)
+#define DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28)
+#define DSPI_DMCR_CSCK (0x40000000)
+#define DSPI_DMCR_MSTR (0x80000000)
+
+/* Bit definitions and macros for DTCR */
+#define DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for DCTAR group */
+#define DSPI_DCTAR_BR(x) (((x)&0x0000000F))
+#define DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4)
+#define DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8)
+#define DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12)
+#define DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16)
+#define DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18)
+#define DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20)
+#define DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22)
+#define DSPI_DCTAR_LSBFE (0x01000000)
+#define DSPI_DCTAR_CPHA (0x02000000)
+#define DSPI_DCTAR_CPOL (0x04000000)
+#define DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27)
+#define DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
+#define DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
+#define DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
+#define DSPI_DCTAR_PCSSCK_7CLK (0x00A00000)
+#define DSPI_DCTAR_PASC_1CLK (0x00000000)
+#define DSPI_DCTAR_PASC_3CLK (0x00100000)
+#define DSPI_DCTAR_PASC_5CLK (0x00200000)
+#define DSPI_DCTAR_PASC_7CLK (0x00300000)
+#define DSPI_DCTAR_PDT_1CLK (0x00000000)
+#define DSPI_DCTAR_PDT_3CLK (0x00040000)
+#define DSPI_DCTAR_PDT_5CLK (0x00080000)
+#define DSPI_DCTAR_PDT_7CLK (0x000A0000)
+#define DSPI_DCTAR_PBR_1CLK (0x00000000)
+#define DSPI_DCTAR_PBR_3CLK (0x00010000)
+#define DSPI_DCTAR_PBR_5CLK (0x00020000)
+#define DSPI_DCTAR_PBR_7CLK (0x00030000)
+
+/* Bit definitions and macros for DSR */
+#define DSPI_DSR_RXPTR(x) (((x)&0x0000000F))
+#define DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4)
+#define DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8)
+#define DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12)
+#define DSPI_DSR_RFDF (0x00020000)
+#define DSPI_DSR_RFOF (0x00080000)
+#define DSPI_DSR_TFFF (0x02000000)
+#define DSPI_DSR_TFUF (0x08000000)
+#define DSPI_DSR_EOQF (0x10000000)
+#define DSPI_DSR_TXRXS (0x40000000)
+#define DSPI_DSR_TCF (0x80000000)
+
+/* Bit definitions and macros for DIRSR */
+#define DSPI_DIRSR_RFDFS (0x00010000)
+#define DSPI_DIRSR_RFDFE (0x00020000)
+#define DSPI_DIRSR_RFOFE (0x00080000)
+#define DSPI_DIRSR_TFFFS (0x01000000)
+#define DSPI_DIRSR_TFFFE (0x02000000)
+#define DSPI_DIRSR_TFUFE (0x08000000)
+#define DSPI_DIRSR_EOQFE (0x10000000)
+#define DSPI_DIRSR_TCFE (0x80000000)
+
+/* Bit definitions and macros for DTFR */
+#define DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF))
+#define DSPI_DTFR_CS0 (0x00010000)
+#define DSPI_DTFR_CS2 (0x00040000)
+#define DSPI_DTFR_CS3 (0x00080000)
+#define DSPI_DTFR_CS5 (0x00200000)
+#define DSPI_DTFR_CTCNT (0x04000000)
+#define DSPI_DTFR_EOQ (0x08000000)
+#define DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28)
+#define DSPI_DTFR_CONT (0x80000000)
+
+/* Bit definitions and macros for DRFR */
+#define DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF))
+
+/* Bit definitions and macros for DTFDR group */
+#define DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF))
+#define DSPI_DTFDR_TXCMD(x) (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for DRFDR group */
+#define DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF))
+
+/*********************************************************************
+* Edge Port Module (EPORT)
+*********************************************************************/
+
+/* Bit definitions and macros for EPPAR */
+#define EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
+#define EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
+#define EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
+#define EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
+#define EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
+#define EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
+#define EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
+#define EPORT_EPPAR_LEVEL (0)
+#define EPORT_EPPAR_RISING (1)
+#define EPORT_EPPAR_FALLING (2)
+#define EPORT_EPPAR_BOTH (3)
+#define EPORT_EPPAR_EPPA7_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA7_RISING (0x4000)
+#define EPORT_EPPAR_EPPA7_FALLING (0x8000)
+#define EPORT_EPPAR_EPPA7_BOTH (0xC000)
+#define EPORT_EPPAR_EPPA6_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA6_RISING (0x1000)
+#define EPORT_EPPAR_EPPA6_FALLING (0x2000)
+#define EPORT_EPPAR_EPPA6_BOTH (0x3000)
+#define EPORT_EPPAR_EPPA5_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA5_RISING (0x0400)
+#define EPORT_EPPAR_EPPA5_FALLING (0x0800)
+#define EPORT_EPPAR_EPPA5_BOTH (0x0C00)
+#define EPORT_EPPAR_EPPA4_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA4_RISING (0x0100)
+#define EPORT_EPPAR_EPPA4_FALLING (0x0200)
+#define EPORT_EPPAR_EPPA4_BOTH (0x0300)
+#define EPORT_EPPAR_EPPA3_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA3_RISING (0x0040)
+#define EPORT_EPPAR_EPPA3_FALLING (0x0080)
+#define EPORT_EPPAR_EPPA3_BOTH (0x00C0)
+#define EPORT_EPPAR_EPPA2_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA2_RISING (0x0010)
+#define EPORT_EPPAR_EPPA2_FALLING (0x0020)
+#define EPORT_EPPAR_EPPA2_BOTH (0x0030)
+#define EPORT_EPPAR_EPPA1_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA1_RISING (0x0004)
+#define EPORT_EPPAR_EPPA1_FALLING (0x0008)
+#define EPORT_EPPAR_EPPA1_BOTH (0x000C)
+
+/* Bit definitions and macros for EPDDR */
+#define EPORT_EPDDR_EPDD1 (0x02)
+#define EPORT_EPDDR_EPDD2 (0x04)
+#define EPORT_EPDDR_EPDD3 (0x08)
+#define EPORT_EPDDR_EPDD4 (0x10)
+#define EPORT_EPDDR_EPDD5 (0x20)
+#define EPORT_EPDDR_EPDD6 (0x40)
+#define EPORT_EPDDR_EPDD7 (0x80)
+
+/* Bit definitions and macros for EPIER */
+#define EPORT_EPIER_EPIE1 (0x02)
+#define EPORT_EPIER_EPIE2 (0x04)
+#define EPORT_EPIER_EPIE3 (0x08)
+#define EPORT_EPIER_EPIE4 (0x10)
+#define EPORT_EPIER_EPIE5 (0x20)
+#define EPORT_EPIER_EPIE6 (0x40)
+#define EPORT_EPIER_EPIE7 (0x80)
+
+/* Bit definitions and macros for EPDR */
+#define EPORT_EPDR_EPD1 (0x02)
+#define EPORT_EPDR_EPD2 (0x04)
+#define EPORT_EPDR_EPD3 (0x08)
+#define EPORT_EPDR_EPD4 (0x10)
+#define EPORT_EPDR_EPD5 (0x20)
+#define EPORT_EPDR_EPD6 (0x40)
+#define EPORT_EPDR_EPD7 (0x80)
+
+/* Bit definitions and macros for EPPDR */
+#define EPORT_EPPDR_EPPD1 (0x02)
+#define EPORT_EPPDR_EPPD2 (0x04)
+#define EPORT_EPPDR_EPPD3 (0x08)
+#define EPORT_EPPDR_EPPD4 (0x10)
+#define EPORT_EPPDR_EPPD5 (0x20)
+#define EPORT_EPPDR_EPPD6 (0x40)
+#define EPORT_EPPDR_EPPD7 (0x80)
+
+/* Bit definitions and macros for EPFR */
+#define EPORT_EPFR_EPF1 (0x02)
+#define EPORT_EPFR_EPF2 (0x04)
+#define EPORT_EPFR_EPF3 (0x08)
+#define EPORT_EPFR_EPF4 (0x10)
+#define EPORT_EPFR_EPF5 (0x20)
+#define EPORT_EPFR_EPF6 (0x40)
+#define EPORT_EPFR_EPF7 (0x80)
+
+/*********************************************************************
+* Watchdog Timer Modules (WTM)
+*********************************************************************/
+
+/* Bit definitions and macros for WCR */
+#define WTM_WCR_EN (0x0001)
+#define WTM_WCR_HALTED (0x0002)
+#define WTM_WCR_DOZE (0x0004)
+#define WTM_WCR_WAIT (0x0008)
+
+/*********************************************************************
+* Serial Boot Facility (SBF)
+*********************************************************************/
+
+/* Bit definitions and macros for SBFCR */
+#define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) /* Boot loader clock divider */
+#define SBF_SBFCR_FR (0x0010) /* Fast read */
+
+/*********************************************************************
+* Reset Controller Module (RCM)
+*********************************************************************/
+
+/* Bit definitions and macros for RCR */
+#define RCM_RCR_FRCRSTOUT (0x40)
+#define RCM_RCR_SOFTRST (0x80)
+
+/* Bit definitions and macros for RSR */
+#define RCM_RSR_LOL (0x01)
+#define RCM_RSR_WDR_CORE (0x02)
+#define RCM_RSR_EXT (0x04)
+#define RCM_RSR_POR (0x08)
+#define RCM_RSR_SOFT (0x20)
+
+/*********************************************************************
+* Chip Configuration Module (CCM)
+*********************************************************************/
+
+/* Bit definitions and macros for CCR_360 */
+#define CCM_CCR_360_PLLMULT2(x) (((x)&0x0003)) /* 2-Bit PLL clock mode */
+#define CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
+#define CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */
+#define CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */
+#define CCM_CCR_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
+#define CCM_CCR_360_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL Clock Mode */
+#define CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */
+#define CCM_CCR_360_FBCONFIG_MASK (0x00E0)
+#define CCM_CCR_360_PLLMULT2_MASK (0x0003)
+#define CCM_CCR_360_PLLMULT3_MASK (0x0007)
+#define CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000)
+#define CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020)
+#define CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040)
+#define CCM_CCR_360_FBCONFIG_M_P_16 (0x0060)
+#define CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080)
+#define CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0)
+#define CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0)
+#define CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0)
+#define CCM_CCR_360_PLLMULT2_12X (0x0000)
+#define CCM_CCR_360_PLLMULT2_6X (0x0001)
+#define CCM_CCR_360_PLLMULT2_16X (0x0002)
+#define CCM_CCR_360_PLLMULT2_8X (0x0003)
+#define CCM_CCR_360_PLLMULT3_20X (0x0000)
+#define CCM_CCR_360_PLLMULT3_10X (0x0001)
+#define CCM_CCR_360_PLLMULT3_24X (0x0002)
+#define CCM_CCR_360_PLLMULT3_18X (0x0003)
+#define CCM_CCR_360_PLLMULT3_12X (0x0004)
+#define CCM_CCR_360_PLLMULT3_6X (0x0005)
+#define CCM_CCR_360_PLLMULT3_16X (0x0006)
+#define CCM_CCR_360_PLLMULT3_8X (0x0007)
+
+/* Bit definitions and macros for CCR_256 */
+#define CCM_CCR_256_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL clock mode */
+#define CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */
+#define CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */
+#define CCM_CCR_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
+#define CCM_CCR_256_FBCONFIG_MASK (0x00E0)
+#define CCM_CCR_256_FBCONFIG_NM_32 (0x0000)
+#define CCM_CCR_256_FBCONFIG_NM_8 (0x0020)
+#define CCM_CCR_256_FBCONFIG_NM_16 (0x0040)
+#define CCM_CCR_256_FBCONFIG_M_32 (0x0080)
+#define CCM_CCR_256_FBCONFIG_M_8 (0x00A0)
+#define CCM_CCR_256_FBCONFIG_M_16 (0x00C0)
+#define CCM_CCR_256_PLLMULT3_MASK (0x0007)
+#define CCM_CCR_256_PLLMULT3_20X (0x0000)
+#define CCM_CCR_256_PLLMULT3_10X (0x0001)
+#define CCM_CCR_256_PLLMULT3_24X (0x0002)
+#define CCM_CCR_256_PLLMULT3_18X (0x0003)
+#define CCM_CCR_256_PLLMULT3_12X (0x0004)
+#define CCM_CCR_256_PLLMULT3_6X (0x0005)
+#define CCM_CCR_256_PLLMULT3_16X (0x0006)
+#define CCM_CCR_256_PLLMULT3_8X (0x0007)
+
+/* Bit definitions and macros for RCON_360 */
+#define CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */
+#define CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
+#define CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */
+#define CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */
+#define CCM_RCON_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
+
+/* Bit definitions and macros for RCON_256 */
+#define CCM_RCON_256_PLLMULT(x) (((x)&0x0007)) /* PLL clock mode */
+#define CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */
+#define CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */
+#define CCM_RCON_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
+
+/* Bit definitions and macros for CIR */
+#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */
+#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */
+#define CCM_CIR_PIN_MASK (0xFFC0)
+#define CCM_CIR_PRN_MASK (0x003F)
+#define CCM_CIR_PIN_MCF54450 (0x4F<<6)
+#define CCM_CIR_PIN_MCF54451 (0x4D<<6)
+#define CCM_CIR_PIN_MCF54452 (0x4B<<6)
+#define CCM_CIR_PIN_MCF54453 (0x49<<6)
+#define CCM_CIR_PIN_MCF54454 (0x4A<<6)
+#define CCM_CIR_PIN_MCF54455 (0x48<<6)
+
+/* Bit definitions and macros for MISCCR */
+#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
+#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */
+#define CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */
+#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
+#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */
+#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */
+#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */
+#define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) /* Bus monitor timing field */
+#define CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */
+#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */
+#define CCM_MISCCR_BMT_65536 (0)
+#define CCM_MISCCR_BMT_32768 (1)
+#define CCM_MISCCR_BMT_16384 (2)
+#define CCM_MISCCR_BMT_8192 (3)
+#define CCM_MISCCR_BMT_4096 (4)
+#define CCM_MISCCR_BMT_2048 (5)
+#define CCM_MISCCR_BMT_1024 (6)
+#define CCM_MISCCR_BMT_512 (7)
+#define CCM_MISCCR_SSIPUS_UP (1)
+#define CCM_MISCCR_SSIPUS_DOWN (0)
+#define CCM_MISCCR_TIMDMA_TIM (1)
+#define CCM_MISCCR_TIMDMA_SSI (0)
+#define CCM_MISCCR_SSISRC_CLKIN (0)
+#define CCM_MISCCR_SSISRC_PLL (1)
+#define CCM_MISCCR_USBOC_ACTHI (0)
+#define CCM_MISCCR_USBOV_ACTLO (1)
+#define CCM_MISCCR_USBSRC_CLKIN (0)
+#define CCM_MISCCR_USBSRC_PLL (1)
+
+/* Bit definitions and macros for CDR */
+#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clock divider */
+#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clock divider */
+
+/* Bit definitions and macros for UOCSR */
+#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */
+#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */
+#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */
+#define CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */
+#define CCM_UOCSR_SEND (0x0010) /* Session end */
+#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */
+#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */
+#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */
+#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */
+#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */
+#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */
+#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */
+#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */
+
+/*********************************************************************
+* General Purpose I/O Module (GPIO)
+*********************************************************************/
+
+/* Bit definitions and macros for PAR_FEC */
+#define GPIO_PAR_FEC_FEC0(x) (((x)&0x07))
+#define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4)
+#define GPIO_PAR_FEC_FEC1_MASK (0x8F)
+#define GPIO_PAR_FEC_FEC1_MII (0x70)
+#define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30)
+#define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20)
+#define GPIO_PAR_FEC_FEC1_ATA (0x10)
+#define GPIO_PAR_FEC_FEC1_GPIO (0x00)
+#define GPIO_PAR_FEC_FEC0_MASK (0xF8)
+#define GPIO_PAR_FEC_FEC0_MII (0x07)
+#define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03)
+#define GPIO_PAR_FEC_FEC0_RMII_ATA (0x02)
+#define GPIO_PAR_FEC_FEC0_ATA (0x01)
+#define GPIO_PAR_FEC_FEC0_GPIO (0x00)
+
+/* Bit definitions and macros for PAR_DMA */
+#define GPIO_PAR_DMA_DREQ0 (0x01)
+#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2)
+#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4)
+#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
+#define GPIO_PAR_DMA_DACK1_MASK (0x3F)
+#define GPIO_PAR_DMA_DACK1_DACK1 (0xC0)
+#define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40)
+#define GPIO_PAR_DMA_DACK1_GPIO (0x00)
+#define GPIO_PAR_DMA_DREQ1_MASK (0xCF)
+#define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30)
+#define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10)
+#define GPIO_PAR_DMA_DREQ1_GPIO (0x00)
+#define GPIO_PAR_DMA_DACK0_MASK (0xF3)
+#define GPIO_PAR_DMA_DACK0_DACK1 (0x0C)
+#define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04)
+#define GPIO_PAR_DMA_DACK0_GPIO (0x00)
+#define GPIO_PAR_DMA_DREQ0_DREQ0 (0x01)
+#define GPIO_PAR_DMA_DREQ0_GPIO (0x00)
+
+/* Bit definitions and macros for PAR_FBCTL */
+#define GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3)
+#define GPIO_PAR_FBCTL_RW (0x20)
+#define GPIO_PAR_FBCTL_TA (0x40)
+#define GPIO_PAR_FBCTL_OE (0x80)
+#define GPIO_PAR_FBCTL_OE_OE (0x80)
+#define GPIO_PAR_FBCTL_OE_GPIO (0x00)
+#define GPIO_PAR_FBCTL_TA_TA (0x40)
+#define GPIO_PAR_FBCTL_TA_GPIO (0x00)
+#define GPIO_PAR_FBCTL_RW_RW (0x20)
+#define GPIO_PAR_FBCTL_RW_GPIO (0x00)
+#define GPIO_PAR_FBCTL_TS_MASK (0xE7)
+#define GPIO_PAR_FBCTL_TS_TS (0x18)
+#define GPIO_PAR_FBCTL_TS_ALE (0x10)
+#define GPIO_PAR_FBCTL_TS_TBST (0x08)
+#define GPIO_PAR_FBCTL_TS_GPIO (0x80)
+
+/* Bit definitions and macros for PAR_DSPI */
+#define GPIO_PAR_DSPI_SCK (0x01)
+#define GPIO_PAR_DSPI_SOUT (0x02)
+#define GPIO_PAR_DSPI_SIN (0x04)
+#define GPIO_PAR_DSPI_PCS0 (0x08)
+#define GPIO_PAR_DSPI_PCS1 (0x10)
+#define GPIO_PAR_DSPI_PCS2 (0x20)
+#define GPIO_PAR_DSPI_PCS5 (0x40)
+#define GPIO_PAR_DSPI_PCS5_PCS5 (0x40)
+#define GPIO_PAR_DSPI_PCS5_GPIO (0x00)
+#define GPIO_PAR_DSPI_PCS2_PCS2 (0x20)
+#define GPIO_PAR_DSPI_PCS2_GPIO (0x00)
+#define GPIO_PAR_DSPI_PCS1_PCS1 (0x10)
+#define GPIO_PAR_DSPI_PCS1_GPIO (0x00)
+#define GPIO_PAR_DSPI_PCS0_PCS0 (0x08)
+#define GPIO_PAR_DSPI_PCS0_GPIO (0x00)
+#define GPIO_PAR_DSPI_SIN_SIN (0x04)
+#define GPIO_PAR_DSPI_SIN_GPIO (0x00)
+#define GPIO_PAR_DSPI_SOUT_SOUT (0x02)
+#define GPIO_PAR_DSPI_SOUT_GPIO (0x00)
+#define GPIO_PAR_DSPI_SCK_SCK (0x01)
+#define GPIO_PAR_DSPI_SCK_GPIO (0x00)
+
+/* Bit definitions and macros for PAR_BE */
+#define GPIO_PAR_BE_BS0 (0x01)
+#define GPIO_PAR_BE_BS1 (0x04)
+#define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4)
+#define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6)
+#define GPIO_PAR_BE_BE3_MASK (0x3F)
+#define GPIO_PAR_BE_BE3_BE3 (0xC0)
+#define GPIO_PAR_BE_BE3_TSIZ1 (0x80)
+#define GPIO_PAR_BE_BE3_GPIO (0x00)
+#define GPIO_PAR_BE_BE2_MASK (0xCF)
+#define GPIO_PAR_BE_BE2_BE2 (0x30)
+#define GPIO_PAR_BE_BE2_TSIZ0 (0x20)
+#define GPIO_PAR_BE_BE2_GPIO (0x00)
+#define GPIO_PAR_BE_BE1_BE1 (0x04)
+#define GPIO_PAR_BE_BE1_GPIO (0x00)
+#define GPIO_PAR_BE_BE0_BE0 (0x01)
+#define GPIO_PAR_BE_BE0_GPIO (0x00)
+
+/* Bit definitions and macros for PAR_CS */
+#define GPIO_PAR_CS_CS1 (0x02)
+#define GPIO_PAR_CS_CS2 (0x04)
+#define GPIO_PAR_CS_CS3 (0x08)
+#define GPIO_PAR_CS_CS3_CS3 (0x08)
+#define GPIO_PAR_CS_CS3_GPIO (0x00)
+#define GPIO_PAR_CS_CS2_CS2 (0x04)
+#define GPIO_PAR_CS_CS2_GPIO (0x00)
+#define GPIO_PAR_CS_CS1_CS1 (0x02)
+#define GPIO_PAR_CS_CS1_GPIO (0x00)
+
+/* Bit definitions and macros for PAR_TIMER */
+#define GPIO_PAR_TIMER_T0IN(x) (((x)&0x03))
+#define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
+#define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
+#define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
+#define GPIO_PAR_TIMER_T3IN_MASK (0x3F)
+#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
+#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
+#define GPIO_PAR_TIMER_T3IN_U2RXD (0x40)
+#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
+#define GPIO_PAR_TIMER_T2IN_MASK (0xCF)
+#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
+#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
+#define GPIO_PAR_TIMER_T2IN_U2TXD (0x10)
+#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
+#define GPIO_PAR_TIMER_T1IN_MASK (0xF3)
+#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
+#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
+#define GPIO_PAR_TIMER_T1IN_U2CTS (0x04)
+#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
+#define GPIO_PAR_TIMER_T0IN_MASK (0xFC)
+#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
+#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
+#define GPIO_PAR_TIMER_T0IN_U2RTS (0x01)
+#define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
+
+/* Bit definitions and macros for PAR_USB */
+#define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03))
+#define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2)
+#define GPIO_PAR_USB_VBUSEN_MASK (0xF3)
+#define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C)
+#define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08)
+#define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04)
+#define GPIO_PAR_USB_VBUSEN_GPIO (0x00)
+#define GPIO_PAR_USB_VBUSOC_MASK (0xFC)
+#define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03)
+#define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01)
+#define GPIO_PAR_USB_VBUSOC_GPIO (0x00)
+
+/* Bit definitions and macros for PAR_UART */
+#define GPIO_PAR_UART_U0TXD (0x01)
+#define GPIO_PAR_UART_U0RXD (0x02)
+#define GPIO_PAR_UART_U0RTS (0x04)
+#define GPIO_PAR_UART_U0CTS (0x08)
+#define GPIO_PAR_UART_U1TXD (0x10)
+#define GPIO_PAR_UART_U1RXD (0x20)
+#define GPIO_PAR_UART_U1RTS (0x40)
+#define GPIO_PAR_UART_U1CTS (0x80)
+#define GPIO_PAR_UART_U1CTS_U1CTS (0x80)
+#define GPIO_PAR_UART_U1CTS_GPIO (0x00)
+#define GPIO_PAR_UART_U1RTS_U1RTS (0x40)
+#define GPIO_PAR_UART_U1RTS_GPIO (0x00)
+#define GPIO_PAR_UART_U1RXD_U1RXD (0x20)
+#define GPIO_PAR_UART_U1RXD_GPIO (0x00)
+#define GPIO_PAR_UART_U1TXD_U1TXD (0x10)
+#define GPIO_PAR_UART_U1TXD_GPIO (0x00)
+#define GPIO_PAR_UART_U0CTS_U0CTS (0x08)
+#define GPIO_PAR_UART_U0CTS_GPIO (0x00)
+#define GPIO_PAR_UART_U0RTS_U0RTS (0x04)
+#define GPIO_PAR_UART_U0RTS_GPIO (0x00)
+#define GPIO_PAR_UART_U0RXD_U0RXD (0x02)
+#define GPIO_PAR_UART_U0RXD_GPIO (0x00)
+#define GPIO_PAR_UART_U0TXD_U0TXD (0x01)
+#define GPIO_PAR_UART_U0TXD_GPIO (0x00)
+
+/* Bit definitions and macros for PAR_FECI2C */
+#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003))
+#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2)
+#define GPIO_PAR_FECI2C_MDIO0 (0x0010)
+#define GPIO_PAR_FECI2C_MDC0 (0x0040)
+#define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8)
+#define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10)
+#define GPIO_PAR_FECI2C_MDC1_MASK (0xF3FF)
+#define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00)
+#define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800)
+#define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000)
+#define GPIO_PAR_FECI2C_MDIO1_MASK (0xFCFF)
+#define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300)
+#define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200)
+#define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000)
+#define GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040)
+#define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000)
+#define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010)
+#define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000)
+#define GPIO_PAR_FECI2C_SCL_MASK (0xFFF3)
+#define GPIO_PAR_FECI2C_SCL_SCL (0x000C)
+#define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004)
+#define GPIO_PAR_FECI2C_SCL_GPIO (0x0000)
+#define GPIO_PAR_FECI2C_SDA_MASK (0xFFFC)
+#define GPIO_PAR_FECI2C_SDA_SDA (0x0003)
+#define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001)
+#define GPIO_PAR_FECI2C_SDA_GPIO (0x0000)
+
+/* Bit definitions and macros for PAR_SSI */
+#define GPIO_PAR_SSI_MCLK (0x0001)
+#define GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2)
+#define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4)
+#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6)
+#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8)
+#define GPIO_PAR_SSI_BCLK_MASK (0xFCFF)
+#define GPIO_PAR_SSI_BCLK_BCLK (0x0300)
+#define GPIO_PAR_SSI_BCLK_U1CTS (0x0200)
+#define GPIO_PAR_SSI_BCLK_GPIO (0x0000)
+#define GPIO_PAR_SSI_FS_MASK (0xFF3F)
+#define GPIO_PAR_SSI_FS_FS (0x00C0)
+#define GPIO_PAR_SSI_FS_U1RTS (0x0080)
+#define GPIO_PAR_SSI_FS_GPIO (0x0000)
+#define GPIO_PAR_SSI_SRXD_MASK (0xFFCF)
+#define GPIO_PAR_SSI_SRXD_SRXD (0x0030)
+#define GPIO_PAR_SSI_SRXD_U1RXD (0x0020)
+#define GPIO_PAR_SSI_SRXD_GPIO (0x0000)
+#define GPIO_PAR_SSI_STXD_MASK (0xFFF3)
+#define GPIO_PAR_SSI_STXD_STXD (0x000C)
+#define GPIO_PAR_SSI_STXD_U1TXD (0x0008)
+#define GPIO_PAR_SSI_STXD_GPIO (0x0000)
+#define GPIO_PAR_SSI_MCLK_MCLK (0x0001)
+#define GPIO_PAR_SSI_MCLK_GPIO (0x0000)
+
+/* Bit definitions and macros for PAR_ATA */
+#define GPIO_PAR_ATA_IORDY (0x0001)
+#define GPIO_PAR_ATA_DMARQ (0x0002)
+#define GPIO_PAR_ATA_RESET (0x0004)
+#define GPIO_PAR_ATA_DA0 (0x0020)
+#define GPIO_PAR_ATA_DA1 (0x0040)
+#define GPIO_PAR_ATA_DA2 (0x0080)
+#define GPIO_PAR_ATA_CS0 (0x0100)
+#define GPIO_PAR_ATA_CS1 (0x0200)
+#define GPIO_PAR_ATA_BUFEN (0x0400)
+#define GPIO_PAR_ATA_BUFEN_BUFEN (0x0400)
+#define GPIO_PAR_ATA_BUFEN_GPIO (0x0000)
+#define GPIO_PAR_ATA_CS1_CS1 (0x0200)
+#define GPIO_PAR_ATA_CS1_GPIO (0x0000)
+#define GPIO_PAR_ATA_CS0_CS0 (0x0100)
+#define GPIO_PAR_ATA_CS0_GPIO (0x0000)
+#define GPIO_PAR_ATA_DA2_DA2 (0x0080)
+#define GPIO_PAR_ATA_DA2_GPIO (0x0000)
+#define GPIO_PAR_ATA_DA1_DA1 (0x0040)
+#define GPIO_PAR_ATA_DA1_GPIO (0x0000)
+#define GPIO_PAR_ATA_DA0_DA0 (0x0020)
+#define GPIO_PAR_ATA_DA0_GPIO (0x0000)
+#define GPIO_PAR_ATA_RESET_RESET (0x0004)
+#define GPIO_PAR_ATA_RESET_GPIO (0x0000)
+#define GPIO_PAR_ATA_DMARQ_DMARQ (0x0002)
+#define GPIO_PAR_ATA_DMARQ_GPIO (0x0000)
+#define GPIO_PAR_ATA_IORDY_IORDY (0x0001)
+#define GPIO_PAR_ATA_IORDY_GPIO (0x0000)
+
+/* Bit definitions and macros for PAR_IRQ */
+#define GPIO_PAR_IRQ_IRQ1 (0x02)
+#define GPIO_PAR_IRQ_IRQ4 (0x10)
+#define GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10)
+#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
+#define GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02)
+#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
+
+/* Bit definitions and macros for PAR_PCI */
+#define GPIO_PAR_PCI_REQ0 (0x0001)
+#define GPIO_PAR_PCI_REQ1 (0x0004)
+#define GPIO_PAR_PCI_REQ2 (0x0010)
+#define GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6)
+#define GPIO_PAR_PCI_GNT0 (0x0100)
+#define GPIO_PAR_PCI_GNT1 (0x0400)
+#define GPIO_PAR_PCI_GNT2 (0x1000)
+#define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14)
+#define GPIO_PAR_PCI_GNT3_MASK (0x3FFF)
+#define GPIO_PAR_PCI_GNT3_GNT3 (0xC000)
+#define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000)
+#define GPIO_PAR_PCI_GNT3_GPIO (0x0000)
+#define GPIO_PAR_PCI_GNT2_GNT2 (0x1000)
+#define GPIO_PAR_PCI_GNT2_GPIO (0x0000)
+#define GPIO_PAR_PCI_GNT1_GNT1 (0x0400)
+#define GPIO_PAR_PCI_GNT1_GPIO (0x0000)
+#define GPIO_PAR_PCI_GNT0_GNT0 (0x0100)
+#define GPIO_PAR_PCI_GNT0_GPIO (0x0000)
+#define GPIO_PAR_PCI_REQ3_MASK (0xFF3F)
+#define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0)
+#define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080)
+#define GPIO_PAR_PCI_REQ3_GPIO (0x0000)
+#define GPIO_PAR_PCI_REQ2_REQ2 (0x0010)
+#define GPIO_PAR_PCI_REQ2_GPIO (0x0000)
+#define GPIO_PAR_PCI_REQ1_REQ1 (0x0040)
+#define GPIO_PAR_PCI_REQ1_GPIO (0x0000)
+#define GPIO_PAR_PCI_REQ0_REQ0 (0x0001)
+#define GPIO_PAR_PCI_REQ0_GPIO (0x0000)
+
+/* Bit definitions and macros for MSCR_SDRAM */
+#define GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03))
+#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2)
+#define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4)
+#define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6)
+#define GPIO_MSCR_SDRAM_SDDATA_MASK (0x3F)
+#define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0)
+#define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80)
+#define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40)
+#define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00)
+#define GPIO_MSCR_SDRAM_SDDQS_MASK (0xCF)
+#define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30)
+#define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20)
+#define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10)
+#define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00)
+#define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3)
+#define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C)
+#define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08)
+#define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04)
+#define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00)
+#define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC)
+#define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03)
+#define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02)
+#define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01)
+#define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00)
+
+/* Bit definitions and macros for MSCR_PCI */
+#define GPIO_MSCR_PCI_PCI (0x01)
+#define GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01)
+#define GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00)
+
+/* Bit definitions and macros for DSCR_I2C */
+#define GPIO_DSCR_I2C_I2C(x) (((x)&0x03))
+#define GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03)
+#define GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02)
+#define GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01)
+#define GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_FLEXBUS */
+#define GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03))
+#define GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2)
+#define GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4)
+#define GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6)
+#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0)
+#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF (0x80)
+#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40)
+#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00)
+#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30)
+#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20)
+#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10)
+#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00)
+#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C)
+#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08)
+#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04)
+#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00)
+#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03)
+#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02)
+#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01)
+#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_FEC */
+#define GPIO_DSCR_FEC_FEC0(x) (((x)&0x03))
+#define GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2)
+#define GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C)
+#define GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08)
+#define GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04)
+#define GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00)
+#define GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03)
+#define GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02)
+#define GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01)
+#define GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_UART */
+#define GPIO_DSCR_UART_UART0(x) (((x)&0x03))
+#define GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2)
+#define GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C)
+#define GPIO_DSCR_UART_UART1_LOAD_30PF (0x08)
+#define GPIO_DSCR_UART_UART1_LOAD_20PF (0x04)
+#define GPIO_DSCR_UART_UART1_LOAD_10PF (0x00)
+#define GPIO_DSCR_UART_UART0_LOAD_50PF (0x03)
+#define GPIO_DSCR_UART_UART0_LOAD_30PF (0x02)
+#define GPIO_DSCR_UART_UART0_LOAD_20PF (0x01)
+#define GPIO_DSCR_UART_UART0_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_DSPI */
+#define GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03))
+#define GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03)
+#define GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02)
+#define GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01)
+#define GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_TIMER */
+#define GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03))
+#define GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03)
+#define GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02)
+#define GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01)
+#define GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_SSI */
+#define GPIO_DSCR_SSI_SSI(x) (((x)&0x03))
+#define GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03)
+#define GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02)
+#define GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01)
+#define GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_DMA */
+#define GPIO_DSCR_DMA_DMA(x) (((x)&0x03))
+#define GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03)
+#define GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02)
+#define GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01)
+#define GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_DEBUG */
+#define GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03))
+#define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03)
+#define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02)
+#define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01)
+#define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_RESET */
+#define GPIO_DSCR_RESET_RESET(x) (((x)&0x03))
+#define GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03)
+#define GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02)
+#define GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01)
+#define GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_IRQ */
+#define GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03))
+#define GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03)
+#define GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02)
+#define GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01)
+#define GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_USB */
+#define GPIO_DSCR_USB_USB(x) (((x)&0x03))
+#define GPIO_DSCR_USB_USB_LOAD_50PF (0x03)
+#define GPIO_DSCR_USB_USB_LOAD_30PF (0x02)
+#define GPIO_DSCR_USB_USB_LOAD_20PF (0x01)
+#define GPIO_DSCR_USB_USB_LOAD_10PF (0x00)
+
+/* Bit definitions and macros for DSCR_ATA */
+#define GPIO_DSCR_ATA_ATA(x) (((x)&0x03))
+#define GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03)
+#define GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02)
+#define GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01)
+#define GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00)
+
+/*********************************************************************
+* Random Number Generator (RNG)
+*********************************************************************/
+
+/* Bit definitions and macros for RNGCR */
+#define RNG_RNGCR_GO (0x00000001)
+#define RNG_RNGCR_HA (0x00000002)
+#define RNG_RNGCR_IM (0x00000004)
+#define RNG_RNGCR_CI (0x00000008)
+
+/* Bit definitions and macros for RNGSR */
+#define RNG_RNGSR_SV (0x00000001)
+#define RNG_RNGSR_LRS (0x00000002)
+#define RNG_RNGSR_FUF (0x00000004)
+#define RNG_RNGSR_EI (0x00000008)
+#define RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8)
+#define RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16)
+
+/*********************************************************************
+* SDRAM Controller (SDRAMC)
+*********************************************************************/
+
+/* Bit definitions and macros for SDMR */
+#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
+#define SDRAMC_SDMR_CMD (0x00010000) /* Command */
+#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
+#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
+#define SDRAMC_SDMR_BK_LMR (0x00000000)
+#define SDRAMC_SDMR_BK_LEMR (0x40000000)
+
+/* Bit definitions and macros for SDCR */
+#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
+#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
+#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
+#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
+#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
+#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */
+#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
+#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */
+#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
+#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
+#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
+#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */
+#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */
+#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000)
+
+/* Bit definitions and macros for SDCFG1 */
+#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */
+#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */
+#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */
+#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */
+#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */
+#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */
+#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */
+
+/* Bit definitions and macros for SDCFG2 */
+#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */
+#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */
+#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */
+#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */
+
+/* Bit definitions and macros for SDCS group */
+#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
+#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
+#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
+#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
+#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
+#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
+#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
+#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
+#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
+#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
+#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
+#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
+#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
+#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
+#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
+#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
+#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
+
+/*********************************************************************
+* Synchronous Serial Interface (SSI)
+*********************************************************************/
+
+/* Bit definitions and macros for CR */
+#define SSI_CR_SSI_EN (0x00000001)
+#define SSI_CR_TE (0x00000002)
+#define SSI_CR_RE (0x00000004)
+#define SSI_CR_NET (0x00000008)
+#define SSI_CR_SYN (0x00000010)
+#define SSI_CR_I2S(x) (((x)&0x00000003)<<5)
+#define SSI_CR_MCE (0x00000080)
+#define SSI_CR_TCH (0x00000100)
+#define SSI_CR_CIS (0x00000200)
+#define SSI_CR_I2S_NORMAL (0x00000000)
+#define SSI_CR_I2S_MASTER (0x00000020)
+#define SSI_CR_I2S_SLAVE (0x00000040)
+
+/* Bit definitions and macros for ISR */
+#define SSI_ISR_TFE0 (0x00000001)
+#define SSI_ISR_TFE1 (0x00000002)
+#define SSI_ISR_RFF0 (0x00000004)
+#define SSI_ISR_RFF1 (0x00000008)
+#define SSI_ISR_RLS (0x00000010)
+#define SSI_ISR_TLS (0x00000020)
+#define SSI_ISR_RFS (0x00000040)
+#define SSI_ISR_TFS (0x00000080)
+#define SSI_ISR_TUE0 (0x00000100)
+#define SSI_ISR_TUE1 (0x00000200)
+#define SSI_ISR_ROE0 (0x00000400)
+#define SSI_ISR_ROE1 (0x00000800)
+#define SSI_ISR_TDE0 (0x00001000)
+#define SSI_ISR_TDE1 (0x00002000)
+#define SSI_ISR_RDR0 (0x00004000)
+#define SSI_ISR_RDR1 (0x00008000)
+#define SSI_ISR_RXT (0x00010000)
+#define SSI_ISR_CMDDU (0x00020000)
+#define SSI_ISR_CMDAU (0x00040000)
+
+/* Bit definitions and macros for IER */
+#define SSI_IER_TFE0 (0x00000001)
+#define SSI_IER_TFE1 (0x00000002)
+#define SSI_IER_RFF0 (0x00000004)
+#define SSI_IER_RFF1 (0x00000008)
+#define SSI_IER_RLS (0x00000010)
+#define SSI_IER_TLS (0x00000020)
+#define SSI_IER_RFS (0x00000040)
+#define SSI_IER_TFS (0x00000080)
+#define SSI_IER_TUE0 (0x00000100)
+#define SSI_IER_TUE1 (0x00000200)
+#define SSI_IER_ROE0 (0x00000400)
+#define SSI_IER_ROE1 (0x00000800)
+#define SSI_IER_TDE0 (0x00001000)
+#define SSI_IER_TDE1 (0x00002000)
+#define SSI_IER_RDR0 (0x00004000)
+#define SSI_IER_RDR1 (0x00008000)
+#define SSI_IER_RXT (0x00010000)
+#define SSI_IER_CMDU (0x00020000)
+#define SSI_IER_CMDAU (0x00040000)
+#define SSI_IER_TIE (0x00080000)
+#define SSI_IER_TDMAE (0x00100000)
+#define SSI_IER_RIE (0x00200000)
+#define SSI_IER_RDMAE (0x00400000)
+
+/* Bit definitions and macros for TCR */
+#define SSI_TCR_TEFS (0x00000001)
+#define SSI_TCR_TFSL (0x00000002)
+#define SSI_TCR_TFSI (0x00000004)
+#define SSI_TCR_TSCKP (0x00000008)
+#define SSI_TCR_TSHFD (0x00000010)
+#define SSI_TCR_TXDIR (0x00000020)
+#define SSI_TCR_TFDIR (0x00000040)
+#define SSI_TCR_TFEN0 (0x00000080)
+#define SSI_TCR_TFEN1 (0x00000100)
+#define SSI_TCR_TXBIT0 (0x00000200)
+
+/* Bit definitions and macros for RCR */
+#define SSI_RCR_REFS (0x00000001)
+#define SSI_RCR_RFSL (0x00000002)
+#define SSI_RCR_RFSI (0x00000004)
+#define SSI_RCR_RSCKP (0x00000008)
+#define SSI_RCR_RSHFD (0x00000010)
+#define SSI_RCR_RFEN0 (0x00000080)
+#define SSI_RCR_RFEN1 (0x00000100)
+#define SSI_RCR_RXBIT0 (0x00000200)
+#define SSI_RCR_RXEXT (0x00000400)
+
+/* Bit definitions and macros for CCR */
+#define SSI_CCR_PM(x) (((x)&0x000000FF))
+#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
+#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
+#define SSI_CCR_PSR (0x00020000)
+#define SSI_CCR_DIV2 (0x00040000)
+
+/* Bit definitions and macros for FCSR */
+#define SSI_FCSR_TFWM0(x) (((x)&0x0000000F))
+#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
+#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
+#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
+#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
+#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
+#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
+#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
+
+/* Bit definitions and macros for ACR */
+#define SSI_ACR_AC97EN (0x00000001)
+#define SSI_ACR_FV (0x00000002)
+#define SSI_ACR_TIF (0x00000004)
+#define SSI_ACR_RD (0x00000008)
+#define SSI_ACR_WR (0x00000010)
+#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
+
+/* Bit definitions and macros for ACADD */
+#define SSI_ACADD_SSI_ACADD(x) (((x)&0x0007FFFF))
+
+/* Bit definitions and macros for ACDAT */
+#define SSI_ACDAT_SSI_ACDAT(x) (((x)&0x0007FFFF))
+
+/* Bit definitions and macros for ATAG */
+#define SSI_ATAG_DDI_ATAG(x) (((x)&0x0000FFFF))
+
+/*********************************************************************
+* Phase Locked Loop (PLL)
+*********************************************************************/
+
+/* Bit definitions and macros for PCR */
+#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */
+#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for internal bus clock frequency */
+#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for Flexbus clock frequency */
+#define PLL_PCR_OUTDIV4(x) (((x)&0x0000000F)<<12) /* Output divider for PCI clock frequency */
+#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */
+#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */
+#define PLL_PCR_PFDR_MASK (0x000F0000)
+#define PLL_PCR_OUTDIV5_MASK (0x000F0000)
+#define PLL_PCR_OUTDIV4_MASK (0x0000F000)
+#define PLL_PCR_OUTDIV3_MASK (0x00000F00)
+#define PLL_PCR_OUTDIV2_MASK (0x000000F0)
+#define PLL_PCR_OUTDIV1_MASK (0x0000000F)
+
+/* Bit definitions and macros for PSR */
+#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */
+#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */
+#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */
+#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */
+
+/*********************************************************************
+* PCI
+*********************************************************************/
+
+/* Bit definitions and macros for SCR */
+#define PCI_SCR_PE (0x80000000) /* Parity Error detected */
+#define PCI_SCR_SE (0x40000000) /* System error signalled */
+#define PCI_SCR_MA (0x20000000) /* Master aboart received */
+#define PCI_SCR_TR (0x10000000) /* Target abort received */
+#define PCI_SCR_TS (0x08000000) /* Target abort signalled */
+#define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */
+#define PCI_SCR_DP (0x01000000) /* Master data parity err */
+#define PCI_SCR_FC (0x00800000) /* Fast back-to-back */
+#define PCI_SCR_R (0x00400000) /* Reserved */
+#define PCI_SCR_66M (0x00200000) /* 66Mhz */
+#define PCI_SCR_C (0x00100000) /* Capabilities list */
+#define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */
+#define PCI_SCR_S (0x00000100) /* SERR enable */
+#define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */
+#define PCI_SCR_PER (0x00000040) /* Parity error response */
+#define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */
+#define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */
+#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */
+#define PCI_SCR_B (0x00000004) /* Bus master enable */
+#define PCI_SCR_M (0x00000002) /* Memory access control */
+#define PCI_SCR_IO (0x00000001) /* I/O access control */
+
+#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */
+#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */
+#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */
+#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */
+
+#define PCI_BAR_BAR0(x) (x & 0xFFFC0000)
+#define PCI_BAR_BAR1(x) (x & 0xFFF00000)
+#define PCI_BAR_BAR2(x) (x & 0xFFC00000)
+#define PCI_BAR_BAR3(x) (x & 0xFF000000)
+#define PCI_BAR_BAR4(x) (x & 0xF8000000)
+#define PCI_BAR_BAR5(x) (x & 0xE0000000)
+#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */
+#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */
+#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */
+
+#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */
+#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */
+#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */
+#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */
+
+#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */
+#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */
+#define PCI_GSCR_SE (0x10000000) /* SERR detected */
+#define PCI_GSCR_ER (0x08000000) /* Error response detected */
+#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */
+#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */
+#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */
+#define PCI_GSCR_PR (0x00000001) /* PCI reset */
+
+#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */
+#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */
+#define PCI_TCR1_P (0x00010000) /* Prefetch reads */
+#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
+
+#define PCI_TCR1_B5E (0x00002000) /* */
+#define PCI_TCR1_B4E (0x00001000) /* */
+#define PCI_TCR1_B3E (0x00000800) /* */
+#define PCI_TCR1_B2E (0x00000400) /* */
+#define PCI_TCR1_B1E (0x00000200) /* */
+#define PCI_TCR1_B0E (0x00000100) /* */
+#define PCI_TCR1_CR (0x00000001) /* */
+
+#define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20)
+#define PCI_TBATR_EN (0x00000001) /* Enable */
+
+#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */
+#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */
+#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */
+#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */
+#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */
+#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */
+#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */
+#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */
+#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */
+#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */
+#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */
+#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */
+#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */
+#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */
+#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */
+
+#define PCI_ICR_REE (0x04000000) /* Retry error enable */
+#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */
+#define PCI_ICR_TAE (0x01000000) /* Target abort enable */
+
+#define PCI_IDR_DEVID (
+
+/********************************************************************/
+
+#endif /* __MCF5445X__ */
diff --git a/include/asm-m68k/mcftimer.h b/include/asm-m68k/mcftimer.h
deleted file mode 100644
index a73b80e..0000000
--- a/include/asm-m68k/mcftimer.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * mcftimer.h -- ColdFire internal TIMER support defines.
- *
- * Based on mcftimer.h of uCLinux distribution:
- * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com)
- * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/****************************************************************************/
-#ifndef mcftimer_h
-#define mcftimer_h
-/****************************************************************************/
-
-#include <linux/config.h>
-
-/*
- * Get address specific defines for this ColdFire member.
- */
-#if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
-#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */
-#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */
-#elif defined(CONFIG_M5272)
-#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */
-#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */
-#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */
-#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */
-#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
-#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */
-#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */
-#elif defined(CONFIG_M5282) | defined(CONFIG_M5271)
-#define MCFTIMER_BASE1 0x150000 /* Base address of TIMER1 */
-#define MCFTIMER_BASE2 0x160000 /* Base address of TIMER2 */
-#define MCFTIMER_BASE3 0x170000 /* Base address of TIMER4 */
-#define MCFTIMER_BASE4 0x180000 /* Base address of TIMER3 */
-#endif
-
-/*
- * Define the TIMER register set addresses.
- */
-#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */
-#define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */
-#define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */
-#define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */
-#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
-
-
-/*
- * Define the TIMER register set addresses for 5282.
- */
-#define MCFTIMER_PCSR 0
-#define MCFTIMER_PMR 1
-#define MCFTIMER_PCNTR 2
-
-/*
- * Bit definitions for the Timer Mode Register (TMR).
- * Register bit flags are common accross ColdFires.
- */
-#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */
-#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */
-#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */
-#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */
-#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */
-#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */
-#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */
-#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */
-#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */
-#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */
-#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */
-#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */
-#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */
-#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */
-#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */
-#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */
-#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */
-
-/*
- * Bit definitions for the Timer Event Registers (TER).
- */
-#define MCFTIMER_TER_CAP 0x01 /* Capture event */
-#define MCFTIMER_TER_REF 0x02 /* Refernece event */
-
-/*
- * Bit definitions for the 5282 PIT Control and Status Register (PCSR).
- */
-#define MCFTIMER_PCSR_EN 0x0001
-#define MCFTIMER_PCSR_RLD 0x0002
-#define MCFTIMER_PCSR_PIF 0x0004
-#define MCFTIMER_PCSR_PIE 0x0008
-#define MCFTIMER_PCSR_OVW 0x0010
-#define MCFTIMER_PCSR_HALTED 0x0020
-#define MCFTIMER_PCSR_DOZE 0x0040
-
-
-/****************************************************************************/
-#endif /* mcftimer_h */
diff --git a/include/asm-m68k/mcfuart.h b/include/asm-m68k/mcfuart.h
deleted file mode 100644
index 7c0999d..0000000
--- a/include/asm-m68k/mcfuart.h
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * mcfuart.h -- ColdFire internal UART support defines.
- *
- * File copied from mcfuart.h of uCLinux distribution:
- * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
- * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/****************************************************************************/
-#ifndef mcfuart_h
-#define mcfuart_h
-/****************************************************************************/
-
-#include <linux/config.h>
-
-/*
- * Define the base address of the UARTS within the MBAR address
- * space.
- */
-#if defined(CONFIG_M5272)
-#define MCFUART_BASE1 0x100 /* Base address of UART1 */
-#define MCFUART_BASE2 0x140 /* Base address of UART2 */
-#elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
-#if defined(CONFIG_NETtel)
-#define MCFUART_BASE1 0x180 /* Base address of UART1 */
-#define MCFUART_BASE2 0x140 /* Base address of UART2 */
-#else
-#define MCFUART_BASE1 0x140 /* Base address of UART1 */
-#define MCFUART_BASE2 0x180 /* Base address of UART2 */
-#endif
-#elif defined(CONFIG_M5282) || defined(CONFIG_M5271)
-#define MCFUART_BASE1 0x200 /* Base address of UART1 */
-#define MCFUART_BASE2 0x240 /* Base address of UART2 */
-#define MCFUART_BASE3 0x280 /* Base address of UART3 */
-#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
-#if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3)
-#define MCFUART_BASE1 0x200 /* Base address of UART1 */
-#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
-#else
-#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
-#define MCFUART_BASE2 0x200 /* Base address of UART2 */
-#endif
-#endif
-
-
-/*
- * Define the ColdFire UART register set addresses.
- */
-#define MCFUART_UMR 0x00 /* Mode register (r/w) */
-#define MCFUART_USR 0x04 /* Status register (r) */
-#define MCFUART_UCSR 0x04 /* Clock Select (w) */
-#define MCFUART_UCR 0x08 /* Command register (w) */
-#define MCFUART_URB 0x0c /* Receiver Buffer (r) */
-#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
-#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
-#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
-#define MCFUART_UISR 0x14 /* Interrup Status (r) */
-#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */
-#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
-#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
-#ifdef CONFIG_M5272
-#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
-#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
-#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
-#else
-#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
-#endif
-#define MCFUART_UIPR 0x34 /* Input Port (r) */
-#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
-#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
-
-#ifdef CONFIG_M5249
-/* Note: This isn't in the 5249 docs */
-#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
-#endif
-
-/*
- * Define bit flags in Mode Register 1 (MR1).
- */
-#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
-#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
-#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
-#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
-#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
-
-#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */
-#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */
-#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */
-#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */
-#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */
-
-#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */
-#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */
-#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */
-#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */
-
-/*
- * Define bit flags in Mode Register 2 (MR2).
- */
-#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */
-#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */
-#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */
-#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */
-#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */
-
-#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
-#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */
-#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */
-
-/*
- * Define bit flags in Status Register (USR).
- */
-#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */
-#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */
-#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */
-#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */
-#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */
-#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */
-#define MCFUART_USR_RXFULL 0x02 /* Receiver full */
-#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */
-
-#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
- MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
-
-/*
- * Define bit flags in Clock Select Register (UCSR).
- */
-#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
-#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */
-#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */
-
-#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */
-#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */
-#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */
-
-/*
- * Define bit flags in Command Register (UCR).
- */
-#define MCFUART_UCR_CMDNULL 0x00 /* No command */
-#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */
-#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */
-#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */
-#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */
-#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */
-#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */
-#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */
-
-#define MCFUART_UCR_TXNULL 0x00 /* No TX command */
-#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */
-#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */
-#define MCFUART_UCR_RXNULL 0x00 /* No RX command */
-#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */
-#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */
-
-/*
- * Define bit flags in Input Port Change Register (UIPCR).
- */
-#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */
-#define MCFUART_UIPCR_CTS 0x01 /* CTS value */
-
-/*
- * Define bit flags in Input Port Register (UIP).
- */
-#define MCFUART_UIPR_CTS 0x01 /* CTS value */
-
-/*
- * Define bit flags in Output Port Registers (UOP).
- * Clear bit by writing to UOP0, set by writing to UOP1.
- */
-#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */
-
-/*
- * Define bit flags in the Auxiliary Control Register (UACR).
- */
-#define MCFUART_UACR_IEC 0x01 /* Input enable control */
-
-/*
- * Define bit flags in Interrupt Status Register (UISR).
- * These same bits are used for the Interrupt Mask Register (UIMR).
- */
-#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */
-#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */
-#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */
-#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */
-
-#ifdef CONFIG_M5272
-/*
- * Define bit flags in the Transmitter FIFO Register (UTF).
- */
-#define MCFUART_UTF_TXB 0x1f /* transmitter data level */
-#define MCFUART_UTF_FULL 0x20 /* transmitter fifo full */
-#define MCFUART_UTF_TXS 0xc0 /* transmitter status */
-
-/*
- * Define bit flags in the Receiver FIFO Register (URF).
- */
-#define MCFUART_URF_RXB 0x1f /* receiver data level */
-#define MCFUART_URF_FULL 0x20 /* receiver fifo full */
-#define MCFUART_URF_RXS 0xc0 /* receiver status */
-#endif
-
-/****************************************************************************/
-#endif /* mcfuart_h */
diff --git a/include/asm-m68k/ptrace.h b/include/asm-m68k/ptrace.h
index 75b2418..01535be 100644
--- a/include/asm-m68k/ptrace.h
+++ b/include/asm-m68k/ptrace.h
@@ -28,32 +28,32 @@
#ifndef __ASSEMBLY__
struct pt_regs {
- ulong d0;
- ulong d1;
- ulong d2;
- ulong d3;
- ulong d4;
- ulong d5;
- ulong d6;
- ulong d7;
- ulong a0;
- ulong a1;
- ulong a2;
- ulong a3;
- ulong a4;
- ulong a5;
- ulong a6;
-#if defined(CONFIG_M5272) || defined(CONFIG_M5282) || defined(CONFIG_M5249) || defined(CONFIG_M5271)
- unsigned format : 4; /* frame format specifier */
- unsigned vector : 12; /* vector offset */
+ ulong d0;
+ ulong d1;
+ ulong d2;
+ ulong d3;
+ ulong d4;
+ ulong d5;
+ ulong d6;
+ ulong d7;
+ ulong a0;
+ ulong a1;
+ ulong a2;
+ ulong a3;
+ ulong a4;
+ ulong a5;
+ ulong a6;
+#if defined(__M68K__)
+ unsigned format:4; /* frame format specifier */
+ unsigned vector:12; /* vector offset */
unsigned short sr;
- unsigned long pc;
+ unsigned long pc;
#else
unsigned short sr;
- unsigned long pc;
+ unsigned long pc;
#endif
};
-#endif /* #ifndef __ASSEMBLY__ */
+#endif /* #ifndef __ASSEMBLY__ */
-#endif /* #ifndef _M68K_PTRACE_H */
+#endif /* #ifndef _M68K_PTRACE_H */
diff --git a/include/asm-m68k/rtc.h b/include/asm-m68k/rtc.h
new file mode 100644
index 0000000..7651ca9
--- /dev/null
+++ b/include/asm-m68k/rtc.h
@@ -0,0 +1,109 @@
+/*
+ * RealTime Clock
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MCFRTC_H__
+#define __MCFRTC_H__
+
+/* Real time Clock */
+typedef struct rtc_ctrl {
+ u32 hourmin; /* 0x00 Hours and Minutes Counter Register */
+ u32 seconds; /* 0x04 Seconds Counter Register */
+ u32 alrm_hm; /* 0x08 Hours and Minutes Alarm Register */
+ u32 alrm_sec; /* 0x0C Seconds Alarm Register */
+ u32 cr; /* 0x10 Control Register */
+ u32 isr; /* 0x14 Interrupt Status Register */
+ u32 ier; /* 0x18 Interrupt Enable Register */
+ u32 stpwatch; /* 0x1C Stopwatch Minutes Register */
+ u32 days; /* 0x20 Days Counter Register */
+ u32 alrm_day; /* 0x24 Days Alarm Register */
+ void *extended;
+} rtc_t;
+
+/* Bit definitions and macros for HOURMIN */
+#define RTC_HOURMIN_MINUTES(x) (((x)&0x0000003F))
+#define RTC_HOURMIN_HOURS(x) (((x)&0x0000001F)<<8)
+
+/* Bit definitions and macros for SECONDS */
+#define RTC_SECONDS_SECONDS(x) (((x)&0x0000003F))
+
+/* Bit definitions and macros for ALRM_HM */
+#define RTC_ALRM_HM_MINUTES(x) (((x)&0x0000003F))
+#define RTC_ALRM_HM_HOURS(x) (((x)&0x0000001F)<<8)
+
+/* Bit definitions and macros for ALRM_SEC */
+#define RTC_ALRM_SEC_SECONDS(x) (((x)&0x0000003F))
+
+/* Bit definitions and macros for CR */
+#define RTC_CR_SWR (0x00000001)
+#define RTC_CR_XTL(x) (((x)&0x00000003)<<5)
+#define RTC_CR_EN (0x00000080)
+#define RTC_CR_32768 (0x0)
+#define RTC_CR_32000 (0x1)
+#define RTC_CR_38400 (0x2)
+
+/* Bit definitions and macros for ISR */
+#define RTC_ISR_SW (0x00000001)
+#define RTC_ISR_MIN (0x00000002)
+#define RTC_ISR_ALM (0x00000004)
+#define RTC_ISR_DAY (0x00000008)
+#define RTC_ISR_1HZ (0x00000010)
+#define RTC_ISR_HR (0x00000020)
+#define RTC_ISR_2HZ (0x00000080)
+#define RTC_ISR_SAM0 (0x00000100)
+#define RTC_ISR_SAM1 (0x00000200)
+#define RTC_ISR_SAM2 (0x00000400)
+#define RTC_ISR_SAM3 (0x00000800)
+#define RTC_ISR_SAM4 (0x00001000)
+#define RTC_ISR_SAM5 (0x00002000)
+#define RTC_ISR_SAM6 (0x00004000)
+#define RTC_ISR_SAM7 (0x00008000)
+
+/* Bit definitions and macros for IER */
+#define RTC_IER_SW (0x00000001)
+#define RTC_IER_MIN (0x00000002)
+#define RTC_IER_ALM (0x00000004)
+#define RTC_IER_DAY (0x00000008)
+#define RTC_IER_1HZ (0x00000010)
+#define RTC_IER_HR (0x00000020)
+#define RTC_IER_2HZ (0x00000080)
+#define RTC_IER_SAM0 (0x00000100)
+#define RTC_IER_SAM1 (0x00000200)
+#define RTC_IER_SAM2 (0x00000400)
+#define RTC_IER_SAM3 (0x00000800)
+#define RTC_IER_SAM4 (0x00001000)
+#define RTC_IER_SAM5 (0x00002000)
+#define RTC_IER_SAM6 (0x00004000)
+#define RTC_IER_SAM7 (0x00008000)
+
+/* Bit definitions and macros for STPWCH */
+#define RTC_STPWCH_CNT(x) (((x)&0x0000003F))
+
+/* Bit definitions and macros for DAYS */
+#define RTC_DAYS_DAYS(x) (((x)&0x0000FFFF))
+
+/* Bit definitions and macros for ALRM_DAY */
+#define RTC_ALRM_DAY_DAYS(x) (((x)&0x0000FFFF))
+
+#endif /* __MCFRTC_H__ */
diff --git a/include/asm-m68k/timer.h b/include/asm-m68k/timer.h
new file mode 100644
index 0000000..030720c
--- /dev/null
+++ b/include/asm-m68k/timer.h
@@ -0,0 +1,118 @@
+/*
+ * timer.h -- ColdFire internal TIMER support defines.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************/
+#ifndef timer_h
+#define timer_h
+/****************************************************************************/
+
+/****************************************************************************/
+/* Timer structure */
+/****************************************************************************/
+/* DMA Timer module registers */
+typedef struct dtimer_ctrl {
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
+ u16 tmr; /* 0x00 Mode register */
+ u16 res1; /* 0x02 */
+ u16 trr; /* 0x04 Reference register */
+ u16 res2; /* 0x06 */
+ u16 tcr; /* 0x08 Capture register */
+ u16 res3; /* 0x0A */
+ u16 tcn; /* 0x0C Counter register */
+ u16 res4; /* 0x0E */
+ u8 res6; /* 0x10 */
+ u8 ter; /* 0x11 Event register */
+ u16 res7; /* 0x12 */
+#else
+ u16 tmr; /* 0x00 Mode register */
+ u8 txmr; /* 0x02 Extended Mode register */
+ u8 ter; /* 0x03 Event register */
+ u32 trr; /* 0x04 Reference register */
+ u32 tcr; /* 0x08 Capture register */
+ u32 tcn; /* 0x0C Counter register */
+#endif
+} dtmr_t;
+
+/*Programmable Interrupt Timer */
+typedef struct pit_ctrl {
+ u16 pcsr; /* 0x00 Control and Status Register */
+ u16 pmr; /* 0x02 Modulus Register */
+ u16 pcntr; /* 0x04 Count Register */
+} pit_t;
+
+/*********************************************************************
+* DMA Timers (DTIM)
+*********************************************************************/
+/* Bit definitions and macros for DTMR */
+#define DTIM_DTMR_RST (0x0001) /* Reset */
+#define DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */
+#define DTIM_DTMR_FRR (0x0008) /* Free run/restart */
+#define DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */
+#define DTIM_DTMR_OM (0x0020) /* Output Mode */
+#define DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */
+#define DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */
+#define DTIM_DTMR_RST_EN (0x0001)
+#define DTIM_DTMR_RST_RST (0x0000)
+#define DTIM_DTMR_CE_ANY (0x00C0)
+#define DTIM_DTMR_CE_FALL (0x0080)
+#define DTIM_DTMR_CE_RISE (0x0040)
+#define DTIM_DTMR_CE_NONE (0x0000)
+#define DTIM_DTMR_CLK_DTIN (0x0006)
+#define DTIM_DTMR_CLK_DIV16 (0x0004)
+#define DTIM_DTMR_CLK_DIV1 (0x0002)
+#define DTIM_DTMR_CLK_STOP (0x0000)
+
+/* Bit definitions and macros for DTXMR */
+#define DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */
+#define DTIM_DTXMR_DMAEN (0x80) /* DMA request */
+
+/* Bit definitions and macros for DTER */
+#define DTIM_DTER_CAP (0x01) /* Capture event */
+#define DTIM_DTER_REF (0x02) /* Output reference event */
+
+/*********************************************************************
+*
+* Programmable Interrupt Timer Modules (PIT)
+*
+*********************************************************************/
+
+/* Bit definitions and macros for PCSR */
+#define PIT_PCSR_EN (0x0001)
+#define PIT_PCSR_RLD (0x0002)
+#define PIT_PCSR_PIF (0x0004)
+#define PIT_PCSR_PIE (0x0008)
+#define PIT_PCSR_OVW (0x0010)
+#define PIT_PCSR_HALTED (0x0020)
+#define PIT_PCSR_DOZE (0x0040)
+#define PIT_PCSR_PRE(x) (((x)&0x000F)<<8)
+
+/* Bit definitions and macros for PMR */
+#define PIT_PMR_PM(x) (x)
+
+/* Bit definitions and macros for PCNTR */
+#define PIT_PCNTR_PC(x) (x)
+
+/****************************************************************************/
+#endif /* timer_h */
diff --git a/include/asm-m68k/u-boot.h b/include/asm-m68k/u-boot.h
index 7a6a8c1..93a6959 100644
--- a/include/asm-m68k/u-boot.h
+++ b/include/asm-m68k/u-boot.h
@@ -37,24 +37,44 @@
#ifndef __ASSEMBLY__
typedef struct bd_info {
- unsigned long bi_memstart; /* start of DRAM memory */
- unsigned long bi_memsize; /* size of DRAM memory in bytes */
- unsigned long bi_flashstart; /* start of FLASH memory */
- unsigned long bi_flashsize; /* size of FLASH memory */
- unsigned long bi_flashoffset; /* reserved area for startup monitor */
- unsigned long bi_sramstart; /* start of SRAM memory */
- unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned long bi_mbar_base; /* base of internal registers */
- unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
- unsigned long bi_boot_params; /* where this board expects params */
- unsigned long bi_ip_addr; /* IP Address */
- unsigned char bi_enetaddr[6]; /* Ethernet adress */
- unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
- unsigned long bi_intfreq; /* Internal Freq, in MHz */
- unsigned long bi_busfreq; /* Bus Freq, in MHz */
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned long bi_memstart; /* start of DRAM memory */
+ unsigned long bi_memsize; /* size of DRAM memory in bytes */
+ unsigned long bi_flashstart; /* start of FLASH memory */
+ unsigned long bi_flashsize; /* size of FLASH memory */
+ unsigned long bi_flashoffset; /* reserved area for startup monitor */
+ unsigned long bi_sramstart; /* start of SRAM memory */
+ unsigned long bi_sramsize; /* size of SRAM memory */
+ unsigned long bi_mbar_base; /* base of internal registers */
+ unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
+ unsigned long bi_boot_params; /* where this board expects params */
+ unsigned long bi_ip_addr; /* IP Address */
+ unsigned char bi_enetaddr[6]; /* Ethernet adress */
+ unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
+ unsigned long bi_intfreq; /* Internal Freq, in MHz */
+ unsigned long bi_busfreq; /* Bus Freq, in MHz */
+#ifdef CONFIG_PCI
+ unsigned long bi_pcifreq; /* pci Freq in MHz */
+#endif
+#ifdef CONFIG_EXTRA_CLOCK
+ unsigned long bi_inpfreq; /* input Freq in MHz */
+ unsigned long bi_vcofreq; /* vco Freq in MHz */
+ unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
+#endif
+ unsigned long bi_baudrate; /* Console Baudrate */
+
+#ifdef CONFIG_HAS_ETH1
+ /* second onboard ethernet port */
+ unsigned char bi_enet1addr[6];
+#endif
+#ifdef CONFIG_HAS_ETH2
+ /* third onboard ethernet port */
+ unsigned char bi_enet2addr[6];
+#endif
+#ifdef CONFIG_HAS_ETH3
+ unsigned char bi_enet3addr[6];
+#endif
} bd_t;
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLY__ */
-#endif /* __U_BOOT_H__ */
+#endif /* __U_BOOT_H__ */
diff --git a/include/asm-m68k/uart.h b/include/asm-m68k/uart.h
new file mode 100644
index 0000000..9a528ea
--- /dev/null
+++ b/include/asm-m68k/uart.h
@@ -0,0 +1,171 @@
+/*
+ * uart.h -- ColdFire internal UART support defines.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************/
+#ifndef uart_h
+#define uart_h
+/****************************************************************************/
+
+/* UART module registers */
+/* Register read/write struct */
+typedef struct uart {
+ u8 umr; /* 0x00 Mode Register */
+ u8 resv0[0x3];
+ union {
+ u8 usr; /* 0x04 Status Register */
+ u8 ucsr; /* 0x04 Clock Select Register */
+ };
+ u8 resv1[0x3];
+ u8 ucr; /* 0x08 Command Register */
+ u8 resv2[0x3];
+ union {
+ u8 utb; /* 0x0c Transmit Buffer */
+ u8 urb; /* 0x0c Receive Buffer */
+ };
+ u8 resv3[0x3];
+ union {
+ u8 uipcr; /* 0x10 Input Port Change Register */
+ u8 uacr; /* 0x10 Auxiliary Control reg */
+ };
+ u8 resv4[0x3];
+ union {
+ u8 uimr; /* 0x14 Interrupt Mask reg */
+ u8 uisr; /* 0x14 Interrupt Status reg */
+ };
+ u8 resv5[0x3];
+ u8 ubg1; /* 0x18 Counter Timer Upper Register */
+ u8 resv6[0x3];
+ u8 ubg2; /* 0x1c Counter Timer Lower Register */
+ u8 resv7[0x17];
+ u8 uip; /* 0x34 Input Port Register */
+ u8 resv8[0x3];
+ u8 uop1; /* 0x38 Output Port Set Register */
+ u8 resv9[0x3];
+ u8 uop0; /* 0x3c Output Port Reset Register */
+} uart_t;
+
+/*********************************************************************
+* Universal Asynchronous Receiver Transmitter (UART)
+*********************************************************************/
+/* Bit definitions and macros for UMR */
+#define UART_UMR_BC(x) (((x)&0x03))
+#define UART_UMR_PT (0x04)
+#define UART_UMR_PM(x) (((x)&0x03)<<3)
+#define UART_UMR_ERR (0x20)
+#define UART_UMR_RXIRQ (0x40)
+#define UART_UMR_RXRTS (0x80)
+#define UART_UMR_SB(x) (((x)&0x0F))
+#define UART_UMR_TXCTS (0x10) /* Trsnsmit CTS */
+#define UART_UMR_TXRTS (0x20) /* Transmit RTS */
+#define UART_UMR_CM(x) (((x)&0x03)<<6) /* CM bits */
+#define UART_UMR_PM_MULTI_ADDR (0x1C)
+#define UART_UMR_PM_MULTI_DATA (0x18)
+#define UART_UMR_PM_NONE (0x10)
+#define UART_UMR_PM_FORCE_HI (0x0C)
+#define UART_UMR_PM_FORCE_LO (0x08)
+#define UART_UMR_PM_ODD (0x04)
+#define UART_UMR_PM_EVEN (0x00)
+#define UART_UMR_BC_5 (0x00)
+#define UART_UMR_BC_6 (0x01)
+#define UART_UMR_BC_7 (0x02)
+#define UART_UMR_BC_8 (0x03)
+#define UART_UMR_CM_NORMAL (0x00)
+#define UART_UMR_CM_ECH (0x40)
+#define UART_UMR_CM_LOCAL_LOOP (0x80)
+#define UART_UMR_CM_REMOTE_LOOP (0xC0)
+#define UART_UMR_SB_STOP_BITS_1 (0x07)
+#define UART_UMR_SB_STOP_BITS_15 (0x08)
+#define UART_UMR_SB_STOP_BITS_2 (0x0F)
+
+/* Bit definitions and macros for USR */
+#define UART_USR_RXRDY (0x01)
+#define UART_USR_FFULL (0x02)
+#define UART_USR_TXRDY (0x04)
+#define UART_USR_TXEMP (0x08)
+#define UART_USR_OE (0x10)
+#define UART_USR_PE (0x20)
+#define UART_USR_FE (0x40)
+#define UART_USR_RB (0x80)
+
+/* Bit definitions and macros for UCSR */
+#define UART_UCSR_TCS(x) (((x)&0x0F))
+#define UART_UCSR_RCS(x) (((x)&0x0F)<<4)
+#define UART_UCSR_RCS_SYS_CLK (0xD0)
+#define UART_UCSR_RCS_CTM16 (0xE0)
+#define UART_UCSR_RCS_CTM (0xF0)
+#define UART_UCSR_TCS_SYS_CLK (0x0D)
+#define UART_UCSR_TCS_CTM16 (0x0E)
+#define UART_UCSR_TCS_CTM (0x0F)
+
+/* Bit definitions and macros for UCR */
+#define UART_UCR_RXC(x) (((x)&0x03))
+#define UART_UCR_TXC(x) (((x)&0x03)<<2)
+#define UART_UCR_MISC(x) (((x)&0x07)<<4)
+#define UART_UCR_NONE (0x00)
+#define UART_UCR_STOP_BREAK (0x70)
+#define UART_UCR_START_BREAK (0x60)
+#define UART_UCR_BKCHGINT (0x50)
+#define UART_UCR_RESET_ERROR (0x40)
+#define UART_UCR_RESET_TX (0x30)
+#define UART_UCR_RESET_RX (0x20)
+#define UART_UCR_RESET_MR (0x10)
+#define UART_UCR_TX_DISABLED (0x08)
+#define UART_UCR_TX_ENABLED (0x04)
+#define UART_UCR_RX_DISABLED (0x02)
+#define UART_UCR_RX_ENABLED (0x01)
+
+/* Bit definitions and macros for UIPCR */
+#define UART_UIPCR_CTS (0x01)
+#define UART_UIPCR_COS (0x10)
+
+/* Bit definitions and macros for UACR */
+#define UART_UACR_IEC (0x01)
+
+/* Bit definitions and macros for UIMR */
+#define UART_UIMR_TXRDY (0x01)
+#define UART_UIMR_RXRDY_FU (0x02)
+#define UART_UIMR_DB (0x04)
+#define UART_UIMR_COS (0x80)
+
+/* Bit definitions and macros for UISR */
+#define UART_UISR_TXRDY (0x01)
+#define UART_UISR_RXRDY_FU (0x02)
+#define UART_UISR_DB (0x04)
+#define UART_UISR_RXFTO (0x08)
+#define UART_UISR_TXFIFO (0x10)
+#define UART_UISR_RXFIFO (0x20)
+#define UART_UISR_COS (0x80)
+
+/* Bit definitions and macros for UIP */
+#define UART_UIP_CTS (0x01)
+
+/* Bit definitions and macros for UOP1 */
+#define UART_UOP1_RTS (0x01)
+
+/* Bit definitions and macros for UOP0 */
+#define UART_UOP0_RTS (0x01)
+
+/****************************************************************************/
+#endif /* mcfuart_h */
diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h
new file mode 100644
index 0000000..f10f89c
--- /dev/null
+++ b/include/asm-microblaze/asm.h
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* FSL macros */
+#define NGET(val, fslnum) \
+ __asm__ __volatile__ ("nget %0, rfsl" #fslnum :"=r" (val));
+
+#define GET(val, fslnum) \
+ __asm__ __volatile__ ("get %0, rfsl" #fslnum :"=r" (val));
+
+#define NCGET(val, fslnum) \
+ __asm__ __volatile__ ("ncget %0, rfsl" #fslnum :"=r" (val));
+
+#define CGET(val, fslnum) \
+ __asm__ __volatile__ ("cget %0, rfsl" #fslnum :"=r" (val));
+
+#define NPUT(val, fslnum) \
+ __asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val));
+
+#define PUT(val, fslnum) \
+ __asm__ __volatile__ ("put %0, rfsl" #fslnum ::"r" (val));
+
+#define NCPUT(val, fslnum) \
+ __asm__ __volatile__ ("ncput %0, rfsl" #fslnum ::"r" (val));
+
+#define CPUT(val, fslnum) \
+ __asm__ __volatile__ ("cput %0, rfsl" #fslnum ::"r" (val));
+
+/* CPU dependent */
+/* machine status register */
+#define MFS(val, reg) \
+ __asm__ __volatile__ ("mfs %0," #reg :"=r" (val));
+
+#define MTS(val, reg) \
+ __asm__ __volatile__ ("mts " #reg ", %0"::"r" (val));
+
+/* get return address from interrupt */
+#define R14(val) \
+ __asm__ __volatile__ ("addi %0, r14, 0":"=r" (val));
+
+#define NOP __asm__ __volatile__ ("nop");
+
+/* use machine status registe USE_MSR_REG */
+#ifdef XILINX_USE_MSR_INSTR
+#define MSRSET(val) \
+ __asm__ __volatile__ ("msrset r0," #val );
+
+#define MSRCLR(val) \
+ __asm__ __volatile__ ("msrclr r0," #val );
+
+#else
+#define MSRSET(val) \
+{ \
+ register unsigned tmp; \
+ __asm__ __volatile__ (" \
+ mfs %0, rmsr; \
+ ori %0, %0, "#val"; \
+ mts rmsr, %0; \
+ nop;" \
+ : "=r" (tmp) \
+ : "d" (val) \
+ : "memory"); \
+}
+
+#define MSRCLR(val) \
+{ \
+ register unsigned tmp; \
+ __asm__ __volatile__ (" \
+ mfs %0, rmsr; \
+ andi %0, %0, ~"#val"; \
+ mts rmsr, %0; \
+ nop;" \
+ : "=r" (tmp) \
+ : "d" (val) \
+ : "memory"); \
+}
+#endif
diff --git a/include/asm-microblaze/microblaze_intc.h b/include/asm-microblaze/microblaze_intc.h
index 6635aea..4c385aa 100644
--- a/include/asm-microblaze/microblaze_intc.h
+++ b/include/asm-microblaze/microblaze_intc.h
@@ -38,3 +38,6 @@ struct irq_action {
void *arg;
int count; /* number of interrupt */
};
+
+void install_interrupt_handler (int irq, interrupt_handler_t * hdlr,
+ void *arg);
diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h
index 463a111..c42ad82 100644
--- a/include/asm-mips/string.h
+++ b/include/asm-mips/string.h
@@ -1,126 +1,31 @@
-/* $Id: string.h,v 1.13 2000/02/19 14:12:14 harald Exp $
- *
+/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (c) 1994, 1995, 1996, 1997, 1998 by Ralf Baechle
+ * Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle
+ * Copyright (c) 2000 by Silicon Graphics, Inc.
+ * Copyright (c) 2001 MIPS Technologies, Inc.
*/
-#ifndef __ASM_MIPS_STRING_H
-#define __ASM_MIPS_STRING_H
-
-#include <linux/config.h>
-
-#define __HAVE_ARCH_STRCPY
-extern __inline__ char *strcpy(char *__dest, __const__ char *__src)
-{
- char *__xdest = __dest;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n"
- "1:\tlbu\t$1,(%1)\n\t"
- "addiu\t%1,1\n\t"
- "sb\t$1,(%0)\n\t"
- "bnez\t$1,1b\n\t"
- "addiu\t%0,1\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- : "=r" (__dest), "=r" (__src)
- : "0" (__dest), "1" (__src)
- : "$1","memory");
-
- return __xdest;
-}
-
-#define __HAVE_ARCH_STRNCPY
-extern __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n)
-{
- char *__xdest = __dest;
-
- if (__n == 0)
- return __xdest;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n"
- "1:\tlbu\t$1,(%1)\n\t"
- "subu\t%2,1\n\t"
- "sb\t$1,(%0)\n\t"
- "beqz\t$1,2f\n\t"
- "addiu\t%0,1\n\t"
- "bnez\t%2,1b\n\t"
- "addiu\t%1,1\n"
- "2:\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- : "=r" (__dest), "=r" (__src), "=r" (__n)
- : "0" (__dest), "1" (__src), "2" (__n)
- : "$1","memory");
+#ifndef _ASM_STRING_H
+#define _ASM_STRING_H
- return __dest;
-}
-
-#define __HAVE_ARCH_STRCMP
-extern __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct)
-{
- int __res;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- "lbu\t%2,(%0)\n"
- "1:\tlbu\t$1,(%1)\n\t"
- "addiu\t%0,1\n\t"
- "bne\t$1,%2,2f\n\t"
- "addiu\t%1,1\n\t"
- "bnez\t%2,1b\n\t"
- "lbu\t%2,(%0)\n\t"
-#if defined(CONFIG_CPU_R3000)
- "nop\n\t"
-#endif
- "move\t%2,$1\n"
- "2:\tsubu\t%2,$1\n"
- "3:\t.set\tat\n\t"
- ".set\treorder"
- : "=r" (__cs), "=r" (__ct), "=r" (__res)
- : "0" (__cs), "1" (__ct)
- : "$1");
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
- return __res;
-}
+#undef __HAVE_ARCH_STRCPY
+extern char *strcpy(char *__dest, __const__ char *__src);
-#define __HAVE_ARCH_STRNCMP
-extern __inline__ int
-strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count)
-{
- int __res;
+#undef __HAVE_ARCH_STRNCPY
+extern char *strncpy(char *__dest, __const__ char *__src, size_t __n);
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n"
- "1:\tlbu\t%3,(%0)\n\t"
- "beqz\t%2,2f\n\t"
- "lbu\t$1,(%1)\n\t"
- "subu\t%2,1\n\t"
- "bne\t$1,%3,3f\n\t"
- "addiu\t%0,1\n\t"
- "bnez\t%3,1b\n\t"
- "addiu\t%1,1\n"
- "2:\n\t"
-#if defined(CONFIG_CPU_R3000)
- "nop\n\t"
-#endif
- "move\t%3,$1\n"
- "3:\tsubu\t%3,$1\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- : "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res)
- : "0" (__cs), "1" (__ct), "2" (__count)
- : "$1");
+#undef __HAVE_ARCH_STRCMP
+extern int strcmp(__const__ char *__cs, __const__ char *__ct);
- return __res;
-}
+#undef __HAVE_ARCH_STRNCMP
+extern int strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count);
#undef __HAVE_ARCH_MEMSET
extern void *memset(void *__s, int __c, size_t __count);
@@ -131,27 +36,4 @@ extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
#undef __HAVE_ARCH_MEMMOVE
extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
-/* Don't build bcopy at all ... */
-#define __HAVE_ARCH_BCOPY
-
-#define __HAVE_ARCH_MEMSCAN
-extern __inline__ void *memscan(void *__addr, int __c, size_t __size)
-{
- char *__end = (char *)__addr + __size;
-
- __asm__(".set\tpush\n\t"
- ".set\tnoat\n\t"
- ".set\treorder\n\t"
- "1:\tbeq\t%0,%1,2f\n\t"
- "addiu\t%0,1\n\t"
- "lb\t$1,-1(%0)\n\t"
- "bne\t$1,%4,1b\n"
- "2:\t.set\tpop"
- : "=r" (__addr), "=r" (__end)
- : "0" (__addr), "1" (__end), "r" (__c)
- : "$1");
-
- return __addr;
-}
-
-#endif /* __ASM_MIPS_STRING_H */
+#endif /* _ASM_STRING_H */
diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h
index ff9512f..de82399 100644
--- a/include/asm-ppc/e300.h
+++ b/include/asm-ppc/e300.h
@@ -6,19 +6,10 @@
#ifndef __E300_H__
#define __E300_H__
-/*
- * e300 Processor Version & Revision Numbers
- */
-#define PVR_83xx 0x80830000
-#define PVR_8349_REV10 (PVR_83xx | 0x0010)
-#define PVR_8349_REV11 (PVR_83xx | 0x0011)
-#define PVR_8360_REV10 (PVR_83xx | 0x0020)
-#define PVR_8360_REV11 (PVR_83xx | 0x0020)
-
-#if defined(CONFIG_MPC832X)
-#undef PVR_83xx
-#define PVR_83xx 0x80840000
-#endif
+#define PVR_E300C1 0x80830000
+#define PVR_E300C2 0x80840000
+#define PVR_E300C3 0x80850000
+#define PVR_E300C4 0x80860000
/*
* Hardware Implementation-Dependent Register 0 (HID0)
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 26bc875..4676e2c 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -55,11 +55,13 @@ typedef struct global_data {
#if defined(CONFIG_MPC83XX)
/* There are other clocks in the MPC83XX */
u32 csb_clk;
-#if defined (CONFIG_MPC834X)
+#if defined (CONFIG_MPC834X) || defined(CONFIG_MPC831X)
u32 tsec1_clk;
u32 tsec2_clk;
- u32 usbmph_clk;
u32 usbdr_clk;
+#endif
+#if defined (CONFIG_MPC834X)
+ u32 usbmph_clk;
#endif /* CONFIG_MPC834X */
u32 core_clk;
u32 i2c1_clk;
@@ -69,20 +71,24 @@ typedef struct global_data {
u32 lclk_clk;
u32 ddr_clk;
u32 pci_clk;
+#if defined(CONFIG_MPC8360)
+ u32 ddr_sec_clk;
+#endif /* CONFIG_MPC8360 */
+#endif
#if defined(CONFIG_QE)
u32 qe_clk;
u32 brg_clk;
uint mp_alloc_base;
uint mp_alloc_top;
#endif /* CONFIG_QE */
-#if defined (CONFIG_MPC8360)
- u32 ddr_sec_clk;
-#endif /* CONFIG_MPC8360 */
-#endif
#if defined(CONFIG_MPC5xxx)
unsigned long ipb_clk;
unsigned long pci_clk;
#endif
+#if defined(CONFIG_MPC512X)
+ u32 ipb_clk;
+ u32 csb_clk;
+#endif /* CONFIG_MPC512X */
#if defined(CONFIG_MPC8220)
unsigned long bExtUart;
unsigned long inp_clk;
@@ -127,7 +133,7 @@ typedef struct global_data {
unsigned long do_mdm_init;
unsigned long be_quiet;
#endif
-#ifdef CONFIG_LWMON
+#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
unsigned long kbd_status;
#endif
void **jt; /* jump table */
diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h
index 114dc92..c9b6a36 100644
--- a/include/asm-ppc/gpio.h
+++ b/include/asm-ppc/gpio.h
@@ -45,12 +45,14 @@ typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
typedef enum gpio_out { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t;
typedef struct {
- unsigned long add; /* gpio core base address */
- gpio_driver_t in_out; /* Driver Setting */
- gpio_select_t alt_nb; /* Selected Alternate */
+ unsigned long add; /* gpio core base address */
+ gpio_driver_t in_out; /* Driver Setting */
+ gpio_select_t alt_nb; /* Selected Alternate */
+ gpio_out_t out_val;/* Default Output Value */
} gpio_param_s;
#endif
void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
void gpio_write_bit(int pin, int val);
+int gpio_read_out_bit(int pin);
void gpio_set_chip_configuration(void);
diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h
new file mode 100644
index 0000000..23d10d4
--- /dev/null
+++ b/include/asm-ppc/immap_512x.h
@@ -0,0 +1,569 @@
+/*
+ * (C) Copyright 2007 DENX Software Engineering
+ *
+ * MPC512x Internal Memory Map
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Based on the MPC83xx header.
+ */
+
+#ifndef __IMMAP_512x__
+#define __IMMAP_512x__
+
+#include <asm/types.h>
+
+typedef struct law512x {
+ u32 bar; /* Base Addr Register */
+ u32 ar; /* Attributes Register */
+} law521x_t;
+
+/*
+ * System configuration registers
+ */
+typedef struct sysconf512x {
+ u32 immrbar; /* Internal memory map base address register */
+ u8 res0[0x1c];
+ u32 lpbaw; /* LP Boot Access Window */
+ u32 lpcs0aw; /* LP CS0 Access Window */
+ u32 lpcs1aw; /* LP CS1 Access Window */
+ u32 lpcs2aw; /* LP CS2 Access Window */
+ u32 lpcs3aw; /* LP CS3 Access Window */
+ u32 lpcs4aw; /* LP CS4 Access Window */
+ u32 lpcs5aw; /* LP CS5 Access Window */
+ u32 lpcs6aw; /* LP CS6 Access Window */
+ u32 lpcs7aw; /* LP CS7 Access Window */
+ u8 res1[0x1c];
+ law521x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */
+ u8 res2[0x28];
+ law521x_t ddrlaw; /* DDR Local Access Window */
+ u8 res3[0x18];
+ u32 mbxbar; /* MBX Base Address */
+ u32 srambar; /* SRAM Base Address */
+ u32 nfcbar; /* NFC Base Address */
+ u8 res4[0x34];
+ u32 spridr; /* System Part and Revision ID Register */
+ u32 spcr; /* System Priority Configuration Register */
+ u8 res5[0xf8];
+} sysconf512x_t;
+
+/*
+ * Watch Dog Timer (WDT) Registers
+ */
+typedef struct wdt512x {
+ u8 res0[4];
+ u32 swcrr; /* System watchdog control register */
+ u32 swcnr; /* System watchdog count register */
+ u8 res1[2];
+ u16 swsrr; /* System watchdog service register */
+ u8 res2[0xF0];
+} wdt512x_t;
+
+/*
+ * RTC Module Registers
+ */
+typedef struct rtclk512x {
+ u8 fixme[0x100];
+} rtclk512x_t;
+
+/*
+ * General Purpose Timer
+ */
+typedef struct gpt512x {
+ u8 fixme[0x100];
+} gpt512x_t;
+
+/*
+ * Integrated Programmable Interrupt Controller
+ */
+typedef struct ipic512x {
+ u8 fixme[0x100];
+} ipic512x_t;
+
+/*
+ * System Arbiter Registers
+ */
+typedef struct arbiter512x {
+ u32 acr; /* Arbiter Configuration Register */
+ u32 atr; /* Arbiter Timers Register */
+ u32 ater; /* Arbiter Transfer Error Register */
+ u32 aer; /* Arbiter Event Register */
+ u32 aidr; /* Arbiter Interrupt Definition Register */
+ u32 amr; /* Arbiter Mask Register */
+ u32 aeatr; /* Arbiter Event Attributes Register */
+ u32 aeadr; /* Arbiter Event Address Register */
+ u32 aerr; /* Arbiter Event Response Register */
+ u8 res1[0xDC];
+} arbiter512x_t;
+
+/*
+ * Reset Module
+ */
+typedef struct reset512x {
+ u32 rcwl; /* Reset Configuration Word Low Register */
+ u32 rcwh; /* Reset Configuration Word High Register */
+ u8 res0[8];
+ u32 rsr; /* Reset Status Register */
+ u32 rmr; /* Reset Mode Register */
+ u32 rpr; /* Reset protection Register */
+ u32 rcr; /* Reset Control Register */
+ u32 rcer; /* Reset Control Enable Register */
+ u8 res1[0xDC];
+} reset512x_t;
+
+/*
+ * Clock Module
+ */
+typedef struct clk512x {
+ u32 spmr; /* System PLL Mode Register */
+ u32 sccr[2]; /* System Clock Control Registers */
+ u32 scfr[2]; /* System Clock Frequency Registers */
+ u8 res0[4];
+ u32 bcr; /* Bread Crumb Register */
+ u32 pscccr[12]; /* PSC0-11 Clock Control Registers */
+ u32 spccr; /* SPDIF Clock Control Registers */
+ u32 cccr; /* CFM Clock Control Registers */
+ u32 dccr; /* DIU Clock Control Registers */
+ u8 res1[0xa8];
+} clk512x_t;
+
+/*
+ * Power Management Control Module
+ */
+typedef struct pmc512x {
+ u8 fixme[0x100];
+} pmc512x_t;
+
+/*
+ * General purpose I/O module
+ */
+typedef struct gpio512x {
+ u8 fixme[0x100];
+} gpio512x_t;
+
+/*
+ * DDR Memory Controller Memory Map
+ */
+typedef struct ddr512x {
+ u32 ddr_sys_config; /* System Configuration Register */
+ u32 ddr_time_config0; /* Timing Configuration Register */
+ u32 ddr_time_config1; /* Timing Configuration Register */
+ u32 ddr_time_config2; /* Timing Configuration Register */
+ u32 ddr_command; /* Command Register */
+ u32 ddr_compact_command; /* Compact Command Register */
+ u32 self_refresh_cmd_0; /* Enter/Exit Self Refresh Registers */
+ u32 self_refresh_cmd_1; /* Enter/Exit Self Refresh Registers */
+ u32 self_refresh_cmd_2; /* Enter/Exit Self Refresh Registers */
+ u32 self_refresh_cmd_3; /* Enter/Exit Self Refresh Registers */
+ u32 self_refresh_cmd_4; /* Enter/Exit Self Refresh Registers */
+ u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */
+ u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */
+ u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */
+ u32 DQS_config_offset_count; /* DQS Config Offset Count */
+ u32 DQS_config_offset_time; /* DQS Config Offset Time */
+ u32 DQS_delay_status; /* DQS Delay Status */
+ u32 res0[0xF];
+ u32 prioman_config1; /* Priority Manager Configuration */
+ u32 prioman_config2; /* Priority Manager Configuration */
+ u32 hiprio_config; /* High Priority Configuration */
+ u32 lut_table0_main_upper; /* LUT0 Main Upper */
+ u32 lut_table1_main_upper; /* LUT1 Main Upper */
+ u32 lut_table2_main_upper; /* LUT2 Main Upper */
+ u32 lut_table3_main_upper; /* LUT3 Main Upper */
+ u32 lut_table4_main_upper; /* LUT4 Main Upper */
+ u32 lut_table0_main_lower; /* LUT0 Main Lower */
+ u32 lut_table1_main_lower; /* LUT1 Main Lower */
+ u32 lut_table2_main_lower; /* LUT2 Main Lower */
+ u32 lut_table3_main_lower; /* LUT3 Main Lower */
+ u32 lut_table4_main_lower; /* LUT4 Main Lower */
+ u32 lut_table0_alternate_upper; /* LUT0 Alternate Upper */
+ u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */
+ u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */
+ u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */
+ u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */
+ u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */
+ u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */
+ u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */
+ u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */
+ u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */
+ u32 performance_monitor_config;
+ u32 event_time_counter;
+ u32 event_time_preset;
+ u32 performance_monitor1_address_low;
+ u32 performance_monitor2_address_low;
+ u32 performance_monitor1_address_hi;
+ u32 performance_monitor2_address_hi;
+ u32 res1[2];
+ u32 performance_monitor1_read_counter;
+ u32 performance_monitor2_read_counter;
+ u32 performance_monitor1_write_counter;
+ u32 performance_monitor2_write_counter;
+ u32 granted_ack_counter0;
+ u32 granted_ack_counter1;
+ u32 granted_ack_counter2;
+ u32 granted_ack_counter3;
+ u32 granted_ack_counter4;
+ u32 cumulative_wait_counter0;
+ u32 cumulative_wait_counter1;
+ u32 cumulative_wait_counter2;
+ u32 cumulative_wait_counter3;
+ u32 cumulative_wait_counter4;
+ u32 summed_priority_counter0;
+ u32 summed_priority_counter1;
+ u32 summed_priority_counter2;
+ u32 summed_priority_counter3;
+ u32 summed_priority_counter4;
+ u32 res2[0x3AD];
+} ddr512x_t;
+
+
+/*
+ * DMA/Messaging Unit
+ */
+typedef struct dma512x {
+ u8 fixme[0x1800];
+} dma512x_t;
+
+/*
+ * PCI Software Configuration Registers
+ */
+typedef struct pciconf512x {
+ u8 fixme[0x80];
+} pciconf512x_t;
+
+/*
+ * Sequencer
+ */
+typedef struct ios512x {
+ u8 fixme[0x100];
+} ios512x_t;
+
+/*
+ * PCI Controller
+ */
+typedef struct pcictrl512x {
+ u8 fixme[0x100];
+} pcictrl512x_t;
+
+
+/*
+ * MSCAN
+ */
+typedef struct mscan512x {
+ u8 fixme[0x100];
+} mscan512x_t;
+
+/*
+ * BDLC
+ */
+typedef struct bdlc512x {
+ u8 fixme[0x100];
+} bdlc512x_t;
+
+/*
+ * SDHC
+ */
+typedef struct sdhc512x {
+ u8 fixme[0x100];
+} sdhc512x_t;
+
+/*
+ * SPDIF
+ */
+typedef struct spdif512x {
+ u8 fixme[0x100];
+} spdif512x_t;
+
+/*
+ * I2C
+ */
+typedef struct i2c512x_dev {
+ volatile u32 madr; /* I2Cn + 0x00 */
+ volatile u32 mfdr; /* I2Cn + 0x04 */
+ volatile u32 mcr; /* I2Cn + 0x08 */
+ volatile u32 msr; /* I2Cn + 0x0C */
+ volatile u32 mdr; /* I2Cn + 0x10 */
+ u8 res0[0x0C];
+} i2c512x_dev_t;
+
+typedef struct i2c512x {
+ i2c512x_dev_t dev[3];
+ volatile u32 icr;
+ volatile u32 mifr;
+ u8 res0[0x98];
+} i2c512x_t;
+
+/*
+ * AXE
+ */
+typedef struct axe512x {
+ u8 fixme[0x100];
+} axe512x_t;
+
+/*
+ * DIU
+ */
+typedef struct diu512x {
+ u8 fixme[0x100];
+} diu512x_t;
+
+/*
+ * CFM
+ */
+typedef struct cfm512x {
+ u8 fixme[0x100];
+} cfm512x_t;
+
+/*
+ * FEC
+ */
+typedef struct fec512x {
+ u8 fixme[0x800];
+} fec512x_t;
+
+/*
+ * ULPI
+ */
+typedef struct ulpi512x {
+ u8 fixme[0x600];
+} ulpi512x_t;
+
+/*
+ * UTMI
+ */
+typedef struct utmi512x {
+ u8 fixme[0x3000];
+} utmi512x_t;
+
+/*
+ * PCI DMA
+ */
+typedef struct pcidma512x {
+ u8 fixme[0x300];
+} pcidma512x_t;
+
+/*
+ * IO Control
+ */
+typedef struct ioctrl512x {
+ u32 regs[0x400];
+} ioctrl512x_t;
+
+/*
+ * IIM
+ */
+typedef struct iim512x {
+ u8 fixme[0x1000];
+} iim512x_t;
+
+/*
+ * LPC
+ */
+typedef struct lpc512x {
+ u32 cs_cfg[8]; /* Chip Select N Configuration Registers
+ No dedicated entry for CS Boot as == CS0 */
+ u32 cs_cr; /* Chip Select Control Register */
+ u32 cs_sr; /* Chip Select Status Register */
+ u32 cs_bcr; /* Chip Select Burst Control Register */
+ u32 cs_dccr; /* Chip Select Deadcycle Control Register */
+ u32 cs_hccr; /* Chip Select Holdcycle Control Register */
+ u8 res0[0xcc];
+ u32 sclpc_psr; /* SCLPC Packet Size Register */
+ u32 sclpc_sar; /* SCLPC Start Address Register */
+ u32 sclpc_cr; /* SCLPC Control Register */
+ u32 sclpc_er; /* SCLPC Enable Register */
+ u32 sclpc_nar; /* SCLPC NextAddress Register */
+ u32 sclpc_sr; /* SCLPC Status Register */
+ u32 sclpc_bdr; /* SCLPC Bytes Done Register */
+ u32 emb_scr; /* EMB Share Counter Register */
+ u32 emb_pcr; /* EMB Pause Control Register */
+ u8 res1[0x1c];
+ u32 lpc_fdwr; /* LPC RX/TX FIFO Data Word Register */
+ u32 lpc_fsr; /* LPC RX/TX FIFO Status Register */
+ u32 lpc_cr; /* LPC RX/TX FIFO Control Register */
+ u32 lpc_ar; /* LPC RX/TX FIFO Alarm Register */
+ u8 res2[0xb0];
+} lpc512x_t;
+
+/*
+ * PATA
+ */
+typedef struct pata512x {
+ u8 fixme[0x100];
+} pata512x_t;
+
+/*
+ * PSC
+ */
+typedef struct psc512x {
+ volatile u8 mode; /* PSC + 0x00 */
+ volatile u8 res0[3];
+ union { /* PSC + 0x04 */
+ volatile u16 status;
+ volatile u16 clock_select;
+ } sr_csr;
+#define psc_status sr_csr.status
+#define psc_clock_select sr_csr.clock_select
+ volatile u16 res1;
+ volatile u8 command; /* PSC + 0x08 */
+ volatile u8 res2[3];
+ union { /* PSC + 0x0c */
+ volatile u8 buffer_8;
+ volatile u16 buffer_16;
+ volatile u32 buffer_32;
+ } buffer;
+#define psc_buffer_8 buffer.buffer_8
+#define psc_buffer_16 buffer.buffer_16
+#define psc_buffer_32 buffer.buffer_32
+ union { /* PSC + 0x10 */
+ volatile u8 ipcr;
+ volatile u8 acr;
+ } ipcr_acr;
+#define psc_ipcr ipcr_acr.ipcr
+#define psc_acr ipcr_acr.acr
+ volatile u8 res3[3];
+ union { /* PSC + 0x14 */
+ volatile u16 isr;
+ volatile u16 imr;
+ } isr_imr;
+#define psc_isr isr_imr.isr
+#define psc_imr isr_imr.imr
+ volatile u16 res4;
+ volatile u8 ctur; /* PSC + 0x18 */
+ volatile u8 res5[3];
+ volatile u8 ctlr; /* PSC + 0x1c */
+ volatile u8 res6[3];
+ volatile u32 ccr; /* PSC + 0x20 */
+ volatile u8 res7[12];
+ volatile u8 ivr; /* PSC + 0x30 */
+ volatile u8 res8[3];
+ volatile u8 ip; /* PSC + 0x34 */
+ volatile u8 res9[3];
+ volatile u8 op1; /* PSC + 0x38 */
+ volatile u8 res10[3];
+ volatile u8 op0; /* PSC + 0x3c */
+ volatile u8 res11[3];
+ volatile u32 sicr; /* PSC + 0x40 */
+ volatile u8 res12[60];
+ volatile u32 tfcmd; /* PSC + 0x80 */
+ volatile u32 tfalarm; /* PSC + 0x84 */
+ volatile u32 tfstat; /* PSC + 0x88 */
+ volatile u32 tfintstat; /* PSC + 0x8C */
+ volatile u32 tfintmask; /* PSC + 0x90 */
+ volatile u32 tfcount; /* PSC + 0x94 */
+ volatile u16 tfwptr; /* PSC + 0x98 */
+ volatile u16 tfrptr; /* PSC + 0x9A */
+ volatile u32 tfsize; /* PSC + 0x9C */
+ volatile u8 res13[28];
+ union { /* PSC + 0xBC */
+ volatile u8 buffer_8;
+ volatile u16 buffer_16;
+ volatile u32 buffer_32;
+ } tfdata_buffer;
+#define tfdata_8 tfdata_buffer.buffer_8
+#define tfdata_16 tfdata_buffer.buffer_16
+#define tfdata_32 tfdata_buffer.buffer_32
+
+ volatile u32 rfcmd; /* PSC + 0xC0 */
+ volatile u32 rfalarm; /* PSC + 0xC4 */
+ volatile u32 rfstat; /* PSC + 0xC8 */
+ volatile u32 rfintstat; /* PSC + 0xCC */
+ volatile u32 rfintmask; /* PSC + 0xD0 */
+ volatile u32 rfcount; /* PSC + 0xD4 */
+ volatile u16 rfwptr; /* PSC + 0xD8 */
+ volatile u16 rfrptr; /* PSC + 0xDA */
+ volatile u32 rfsize; /* PSC + 0xDC */
+ volatile u8 res18[28];
+ union { /* PSC + 0xFC */
+ volatile u8 buffer_8;
+ volatile u16 buffer_16;
+ volatile u32 buffer_32;
+ } rfdata_buffer;
+#define rfdata_8 rfdata_buffer.buffer_8
+#define rfdata_16 rfdata_buffer.buffer_16
+#define rfdata_32 rfdata_buffer.buffer_32
+} psc512x_t;
+
+/*
+ * FIFOC
+ */
+typedef struct fifoc512x {
+ u32 fifoc_cmd;
+ u32 fifoc_int;
+ u32 fifoc_dma;
+ u32 fifoc_axe;
+ u32 fifoc_debug;
+ u8 fixme[0xEC];
+} fifoc512x_t;
+
+/*
+ * SATA
+ */
+typedef struct sata512x {
+ u8 fixme[0x2000];
+} sata512x_t;
+
+typedef struct immap {
+ sysconf512x_t sysconf; /* System configuration */
+ u8 res0[0x700];
+ wdt512x_t wdt; /* Watch Dog Timer (WDT) */
+ rtclk512x_t rtc; /* Real Time Clock Module */
+ gpt512x_t gpt; /* General Purpose Timer */
+ ipic512x_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter512x_t arbiter; /* CSB Arbiter */
+ reset512x_t reset; /* Reset Module */
+ clk512x_t clk; /* Clock Module */
+ pmc512x_t pmc; /* Power Management Control Module */
+ gpio512x_t gpio; /* General purpose I/O module */
+ u8 res1[0x100];
+ mscan512x_t mscan; /* MSCAN */
+ bdlc512x_t bdlc; /* BDLC */
+ sdhc512x_t sdhc; /* SDHC */
+ spdif512x_t spdif; /* SPDIF */
+ i2c512x_t i2c; /* I2C Controllers */
+ u8 res2[0x800];
+ axe512x_t axe; /* AXE */
+ diu512x_t diu; /* Display Interface Unit */
+ cfm512x_t cfm; /* Clock Frequency Measurement */
+ u8 res3[0x500];
+ fec512x_t fec; /* Fast Ethernet Controller */
+ ulpi512x_t ulpi; /* USB ULPI */
+ u8 res4[0xa00];
+ utmi512x_t utmi; /* USB UTMI */
+ u8 res5[0x1000];
+ pcidma512x_t pci_dma; /* PCI DMA */
+ pciconf512x_t pci_conf; /* PCI Configuration */
+ u8 res6[0x80];
+ ios512x_t ios; /* PCI Sequencer */
+ pcictrl512x_t pci_ctrl; /* PCI Controller Control and Status */
+ u8 res7[0xa00];
+ ddr512x_t mddrc; /* Multi-port DDR Memory Controller */
+ ioctrl512x_t io_ctrl; /* IO Control */
+ iim512x_t iim; /* IC Identification module */
+ u8 res8[0x4000];
+ lpc512x_t lpc; /* LocalPlus Controller */
+ pata512x_t pata; /* Parallel ATA */
+ u8 res9[0xd00];
+ psc512x_t psc[12]; /* PSCs */
+ u8 res10[0x300];
+ fifoc512x_t fifoc; /* FIFO Controller */
+ u8 res11[0x2000];
+ dma512x_t dma; /* DMA */
+ u8 res12[0xa800];
+ sata512x_t sata; /* Serial ATA */
+ u8 res13[0xde000];
+} immap_t;
+#endif /* __IMMAP_512x__ */
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 5e088d6..0de9338 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -206,7 +206,9 @@ typedef struct pmc83xx {
u32 pmccr; /* PMC Configuration Register */
u32 pmcer; /* PMC Event Register */
u32 pmcmr; /* PMC Mask Register */
- u8 res0[0xF4];
+ u32 pmccr1; /* PMC Configuration Register 1 */
+ u32 pmccr2; /* PMC Configuration Register 2 */
+ u8 res0[0xEC];
} pmc83xx_t;
/*
@@ -355,7 +357,8 @@ typedef struct lbus83xx {
u8 res2[0x8];
u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
u32 mdr; /* UPM Data Register */
- u8 res3[0x8];
+ u8 res3[0x4];
+ u32 lsor; /* Special Operation Initiation Register */
u32 lsdmr; /* SDRAM Mode Register */
u8 res4[0x8];
u32 lurt; /* UPM Refresh Timer */
@@ -369,8 +372,14 @@ typedef struct lbus83xx {
u8 res6[0xC];
u32 lbcr; /* Configuration Register */
u32 lcrr; /* Clock Ratio Register */
- u8 res7[0x28];
- u8 res8[0xF00];
+ u8 res7[0x8];
+ u32 fmr; /* Flash Mode Register */
+ u32 fir; /* Flash Instruction Register */
+ u32 fcr; /* Flash Command Register */
+ u32 fbar; /* Flash Block Addr Register */
+ u32 fpar; /* Flash Page Addr Register */
+ u32 fbcr; /* Flash Byte Count Register */
+ u8 res8[0xF08];
} lbus83xx_t;
/*
@@ -527,7 +536,7 @@ typedef struct pcictrl83xx {
* USB
*/
typedef struct usb83xx {
- u8 fixme[0x2000];
+ u8 fixme[0x1000];
} usb83xx_t;
/*
@@ -574,7 +583,42 @@ typedef struct immap {
ios83xx_t ios; /* Sequencer */
pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
u8 res5[0x19900];
- usb83xx_t usb;
+ usb83xx_t usb[2];
+ tsec83xx_t tsec[2];
+ u8 res6[0xA000];
+ security83xx_t security;
+ u8 res7[0xC0000];
+} immap_t;
+
+#elif defined(CONFIG_MPC831X)
+typedef struct immap {
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ gtm83xx_t gtm[2]; /* Global Timers Module */
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ gpio83xx_t gpio[1]; /* General purpose I/O module */
+ u8 res0[0x1300];
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+ fsl_i2c_t i2c[2]; /* I2C Controllers */
+ u8 res1[0x1300];
+ duart83xx_t duart[2]; /* DUART */
+ u8 res2[0x900];
+ lbus83xx_t lbus; /* Local Bus Controller Registers */
+ u8 res3[0x1000];
+ spi83xx_t spi; /* Serial Peripheral Interface */
+ dma83xx_t dma; /* DMA */
+ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
+ u8 res4[0x80];
+ ios83xx_t ios; /* Sequencer */
+ pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
+ u8 res5[0x1aa00];
+ usb83xx_t usb[1];
tsec83xx_t tsec[2];
u8 res6[0xA000];
security83xx_t security;
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 5377c2e..496fc72 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1,6 +1,8 @@
/*
* MPC85xx Internal Memory Map
*
+ * Copyright 2007 Freescale Semiconductor.
+ *
* Copyright(c) 2002,2003 Motorola Inc.
* Xianghua Xiao (x.xiao@motorola.com)
*
@@ -1520,14 +1522,39 @@ typedef struct ccsr_rio {
char res58[60176];
} ccsr_rio_t;
+/* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */
+typedef struct par_io {
+ uint cpodr; /* 0x100 */
+ uint cpdat; /* 0x104 */
+ uint cpdir1; /* 0x108 */
+ uint cpdir2; /* 0x10c */
+ uint cppar1; /* 0x110 */
+ uint cppar2; /* 0x114 */
+ char res[8];
+}par_io_t;
+
/*
* Global Utilities Register Block(0xe_0000-0xf_ffff)
*/
typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
uint porbmsr; /* 0xe0004 - POR boot mode status register */
+#define MPC85xx_PORBMSR_HA 0x00070000
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
+#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
+#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
+#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
+#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
+#define MPC85xx_PORDEVSR_IO_SEL 0x00380000
+#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
+#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
+#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
+#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
+#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
+#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
+#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
+#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
char res1[12];
uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
@@ -1541,6 +1568,25 @@ typedef struct ccsr_gur {
uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
char res6[12];
uint devdisr; /* 0xe0070 - Device disable control */
+#define MPC85xx_DEVDISR_PCI1 0x80000000
+#define MPC85xx_DEVDISR_PCI2 0x40000000
+#define MPC85xx_DEVDISR_PCIE 0x20000000
+#define MPC85xx_DEVDISR_LBC 0x08000000
+#define MPC85xx_DEVDISR_PCIE2 0x04000000
+#define MPC85xx_DEVDISR_PCIE3 0x02000000
+#define MPC85xx_DEVDISR_SEC 0x01000000
+#define MPC85xx_DEVDISR_SRIO 0x00080000
+#define MPC85xx_DEVDISR_RMSG 0x00040000
+#define MPC85xx_DEVDISR_DDR 0x00010000
+#define MPC85xx_DEVDISR_CPU 0x00008000
+#define MPC85xx_DEVDISR_TB 0x00004000
+#define MPC85xx_DEVDISR_DMA 0x00000400
+#define MPC85xx_DEVDISR_TSEC1 0x00000080
+#define MPC85xx_DEVDISR_TSEC2 0x00000040
+#define MPC85xx_DEVDISR_TSEC3 0x00000020
+#define MPC85xx_DEVDISR_TSEC4 0x00000010
+#define MPC85xx_DEVDISR_I2C 0x00000004
+#define MPC85xx_DEVDISR_DUART 0x00000002
char res7[12];
uint powmgtcsr; /* 0xe0080 - Power management status and control register */
char res8[12];
@@ -1548,7 +1594,15 @@ typedef struct ccsr_gur {
char res9[12];
uint pvr; /* 0xe00a0 - Processor version register */
uint svr; /* 0xe00a4 - System version register */
- char res10[3416];
+ char res10a[8];
+ uint rstcr; /* 0xe00b0 - Reset control register */
+#ifdef CONFIG_MPC8568
+ char res10b[76];
+ par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */
+ char res10c[3136];
+#else
+ char res10b[3404];
+#endif
uint clkocr; /* 0xe0e00 - Clock out select register */
char res11[12];
uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
@@ -1560,7 +1614,7 @@ typedef struct ccsr_gur {
uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */
uint res14; /* 0xe0f28 */
uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
- char res15[61651];
+ char res15[61648]; /* 0xe0f30 to 0xefffff */
} ccsr_gur_t;
#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index 0e3fc34..169725b 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -1257,9 +1257,12 @@ typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
uint porbmsr; /* 0xe0004 - POR boot mode status register */
#define MPC86xx_PORBMSR_HA 0x00060000
+#define MPC85xx_PORBMSR_HA 0x00070000
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
-#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
+#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
+#define MPC85xx_PORDEVSR_IO_SEL 0x00380000 /* 85xx platform type */
+#define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */
uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
char res1[12];
uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
@@ -1273,8 +1276,11 @@ typedef struct ccsr_gur {
uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
char res6[12];
uint devdisr; /* 0xe0070 - Device disable control */
-#define MPC86xx_DEVDISR_PCIEX1 0x80000000
-#define MPC86xx_DEVDISR_PCIEX2 0x40000000
+#define MPC86xx_DEVDISR_PCIEX1 0x80000000
+#define MPC86xx_DEVDISR_PCIEX2 0x40000000
+#define MPC86xx_DEVDISR_PCI1 0x80000000
+#define MPC86xx_DEVDISR_PCIE1 0x40000000
+#define MPC86xx_DEVDISR_PCIE2 0x20000000
char res7[12];
uint powmgtcsr; /* 0xe0080 - Power management status and control register */
char res8[12];
@@ -1282,7 +1288,9 @@ typedef struct ccsr_gur {
char res9[12];
uint pvr; /* 0xe00a0 - Processor version register */
uint svr; /* 0xe00a4 - System version register */
- char res10[3416];
+ char res10a[1880];
+ uint clkdvdr; /* 0xe0800 - Clock Divide register */
+ char res10b[1532];
uint clkocr; /* 0xe0e00 - Clock out select register */
char res11[12];
uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
diff --git a/include/asm-ppc/immap_fsl_pci.h b/include/asm-ppc/immap_fsl_pci.h
new file mode 100644
index 0000000..bd732b6
--- /dev/null
+++ b/include/asm-ppc/immap_fsl_pci.h
@@ -0,0 +1,150 @@
+/* (C) Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __IMMAP_85xx_fsl_pci__
+#define __IMMAP_85xx_fsl_pci__
+
+/*
+ * Common PCI/PCIE Register structure for mpc85xx and mpc86xx
+ */
+
+/*
+ * PCI Translation Registers
+ */
+typedef struct pci_outbound_window {
+ u32 potar; /* 0x00 - Address */
+ u32 potear; /* 0x04 - Address Extended */
+ u32 powbar; /* 0x08 - Window Base Address */
+ u32 res1;
+ u32 powar; /* 0x10 - Window Attributes */
+#define POWAR_EN 0x80000000
+#define POWAR_IO_READ 0x00080000
+#define POWAR_MEM_READ 0x00040000
+#define POWAR_IO_WRITE 0x00008000
+#define POWAR_MEM_WRITE 0x00004000
+ u32 res2[3];
+} pot_t;
+
+typedef struct pci_inbound_window {
+ u32 pitar; /* 0x00 - Address */
+ u32 res1;
+ u32 piwbar; /* 0x08 - Window Base Address */
+ u32 piwbear; /* 0x0c - Window Base Address Extended */
+ u32 piwar; /* 0x10 - Window Attributes */
+#define PIWAR_EN 0x80000000
+#define PIWAR_PF 0x20000000
+#define PIWAR_LOCAL 0x00f00000
+#define PIWAR_READ_SNOOP 0x00050000
+#define PIWAR_WRITE_SNOOP 0x00005000
+ u32 res2[3];
+} pit_t;
+
+/* PCI/PCI Express Registers */
+typedef struct ccsr_pci {
+ u32 cfg_addr; /* 0x000 - PCI Configuration Address Register */
+ u32 cfg_data; /* 0x004 - PCI Configuration Data Register */
+ u32 int_ack; /* 0x008 - PCI Interrupt Acknowledge Register */
+ u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */
+ u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */
+ u32 config; /* 0x014 - PCIE CONFIG Register */
+ char res2[8];
+ u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */
+ u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */
+ u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */
+ u32 pm_command; /* 0x02c - PCIE PM Command register */
+ char res4[3016]; /* (- #xbf8 #x30)3016 */
+ u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */
+ u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */
+
+ pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
+ u32 res5[64];
+ pit_t pit[3]; /* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */
+#define PIT3 0
+#define PIT2 1
+#define PIT1 2
+
+#if 0
+ u32 potar0; /* 0xc00 - PCI Outbound Transaction Address Register 0 */
+ u32 potear0; /* 0xc04 - PCI Outbound Translation Extended Address Register 0 */
+ char res5[8];
+ u32 powar0; /* 0xc10 - PCI Outbound Window Attributes Register 0 */
+ char res6[12];
+ u32 potar1; /* 0xc20 - PCI Outbound Transaction Address Register 1 */
+ u32 potear1; /* 0xc24 - PCI Outbound Translation Extended Address Register 1 */
+ u32 powbar1; /* 0xc28 - PCI Outbound Window Base Address Register 1 */
+ char res7[4];
+ u32 powar1; /* 0xc30 - PCI Outbound Window Attributes Register 1 */
+ char res8[12];
+ u32 potar2; /* 0xc40 - PCI Outbound Transaction Address Register 2 */
+ u32 potear2; /* 0xc44 - PCI Outbound Translation Extended Address Register 2 */
+ u32 powbar2; /* 0xc48 - PCI Outbound Window Base Address Register 2 */
+ char res9[4];
+ u32 powar2; /* 0xc50 - PCI Outbound Window Attributes Register 2 */
+ char res10[12];
+ u32 potar3; /* 0xc60 - PCI Outbound Transaction Address Register 3 */
+ u32 potear3; /* 0xc64 - PCI Outbound Translation Extended Address Register 3 */
+ u32 powbar3; /* 0xc68 - PCI Outbound Window Base Address Register 3 */
+ char res11[4];
+ u32 powar3; /* 0xc70 - PCI Outbound Window Attributes Register 3 */
+ char res12[12];
+ u32 potar4; /* 0xc80 - PCI Outbound Transaction Address Register 4 */
+ u32 potear4; /* 0xc84 - PCI Outbound Translation Extended Address Register 4 */
+ u32 powbar4; /* 0xc88 - PCI Outbound Window Base Address Register 4 */
+ char res13[4];
+ u32 powar4; /* 0xc90 - PCI Outbound Window Attributes Register 4 */
+ char res14[268];
+ u32 pitar3; /* 0xda0 - PCI Inbound Translation Address Register 3 */
+ char res15[4];
+ u32 piwbar3; /* 0xda8 - PCI Inbound Window Base Address Register 3 */
+ u32 piwbear3; /* 0xdac - PCI Inbound Window Base Extended Address Register 3 */
+ u32 piwar3; /* 0xdb0 - PCI Inbound Window Attributes Register 3 */
+ char res16[12];
+ u32 pitar2; /* 0xdc0 - PCI Inbound Translation Address Register 2 */
+ char res17[4];
+ u32 piwbar2; /* 0xdc8 - PCI Inbound Window Base Address Register 2 */
+ u32 piwbear2; /* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */
+ u32 piwar2; /* 0xdd0 - PCI Inbound Window Attributes Register 2 */
+ char res18[12];
+ u32 pitar1; /* 0xde0 - PCI Inbound Translation Address Register 1 */
+ char res19[4];
+ u32 piwbar1; /* 0xde8 - PCI Inbound Window Base Address Register 1 */
+ char res20[4];
+ u32 piwar1; /* 0xdf0 - PCI Inbound Window Attributes Register 1 */
+ char res21[12];
+#endif
+ u32 pedr; /* 0xe00 - PCI Error Detect Register */
+ u32 pecdr; /* 0xe04 - PCI Error Capture Disable Register */
+ u32 peer; /* 0xe08 - PCI Error Interrupt Enable Register */
+ u32 peattrcr; /* 0xe0c - PCI Error Attributes Capture Register */
+ u32 peaddrcr; /* 0xe10 - PCI Error Address Capture Register */
+/* u32 perr_disr * 0xe10 - PCIE Erorr Disable Register */
+ u32 peextaddrcr; /* 0xe14 - PCI Error Extended Address Capture Register */
+ u32 pedlcr; /* 0xe18 - PCI Error Data Low Capture Register */
+ u32 pedhcr; /* 0xe1c - PCI Error Error Data High Capture Register */
+ u32 gas_timr; /* 0xe20 - PCI Gasket Timer Register */
+/* u32 perr_cap_stat; * 0xe20 - PCIE Error Capture Status Register */
+ char res22[4];
+ u32 perr_cap0; /* 0xe28 - PCIE Error Capture Register 0 */
+ u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */
+ u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */
+ u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */
+ char res23[456]; /* (- #x1000 #xe38) 456 */
+} ccsr_fsl_pci_t;
+
+#endif /*__IMMAP_fsl_pci__*/
diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h
index 950b949..a16a6d3 100644
--- a/include/asm-ppc/immap_qe.h
+++ b/include/asm-ppc/immap_qe.h
@@ -281,6 +281,17 @@ typedef struct ucc_slow {
u8 res4[0x200 - 0x091];
} __attribute__ ((packed)) ucc_slow_t;
+typedef struct ucc_mii_mng {
+ u32 miimcfg; /* MII management configuration reg */
+ u32 miimcom; /* MII management command reg */
+ u32 miimadd; /* MII management address reg */
+ u32 miimcon; /* MII management control reg */
+ u32 miimstat; /* MII management status reg */
+ u32 miimind; /* MII management indication reg */
+ u32 ifctl; /* interface control reg */
+ u32 ifstat; /* interface statux reg */
+} __attribute__ ((packed))uec_mii_t;
+
typedef struct ucc_ethernet {
u32 maccfg1; /* mac configuration reg. 1 */
u32 maccfg2; /* mac configuration reg. 2 */
@@ -540,14 +551,21 @@ typedef struct qe_immap {
u8 res14[0x300];
u8 res15[0x3A00];
u8 res16[0x8000]; /* 0x108000 - 0x110000 */
+#if defined(CONFIG_MPC8568)
+ u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */
+ u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */
+#else
u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */
u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
+#endif
} __attribute__ ((packed)) qe_map_t;
extern qe_map_t *qe_immr;
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_MPC8568)
+#define QE_MURAM_SIZE 0x10000UL
+#elif defined(CONFIG_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#elif defined(CONFIG_MPC832X)
#define QE_MURAM_SIZE 0x4000UL
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index bbc9ba0..11dfa1c 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -13,6 +13,9 @@
#define SIO_CONFIG_RA 0x398
#define SIO_CONFIG_RD 0x399
+#ifndef _IO_BASE
+#define _IO_BASE 0
+#endif
#define readb(addr) in_8((volatile u8 *)(addr))
#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
@@ -105,6 +108,11 @@ static inline void sync(void)
__asm__ __volatile__ ("sync" : : : "memory");
}
+static inline void isync(void)
+{
+ __asm__ __volatile__ ("isync" : : : "memory");
+}
+
/* Enforce in-order execution of data I/O.
* No distinction between read/write on PPC; use eieio for all three.
*/
@@ -114,74 +122,90 @@ static inline void sync(void)
/*
* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
+ *
+ * Read operations have additional twi & isync to make sure the read
+ * is actually performed (i.e. the data has come back) before we start
+ * executing any following instructions.
*/
-extern inline int in_8(volatile u8 *addr)
+#define __iomem
+extern inline int in_8(const volatile unsigned char __iomem *addr)
{
- int ret;
+ int ret;
- __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
- return ret;
+ __asm__ __volatile__(
+ "sync; lbz%U1%X1 %0,%1;\n"
+ "twi 0,%0,0;\n"
+ "isync" : "=r" (ret) : "m" (*addr));
+ return ret;
}
-extern inline void out_8(volatile u8 *addr, int val)
+extern inline void out_8(volatile unsigned char __iomem *addr, int val)
{
- __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+ __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
}
-extern inline int in_le16(volatile u16 *addr)
+extern inline int in_le16(const volatile unsigned short __iomem *addr)
{
- int ret;
+ int ret;
- __asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) :
- "r" (addr), "m" (*addr));
- return ret;
+ __asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
+ "twi 0,%0,0;\n"
+ "isync" : "=r" (ret) :
+ "r" (addr), "m" (*addr));
+ return ret;
}
-extern inline int in_be16(volatile u16 *addr)
+extern inline int in_be16(const volatile unsigned short __iomem *addr)
{
- int ret;
+ int ret;
- __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
- return ret;
+ __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
+ "twi 0,%0,0;\n"
+ "isync" : "=r" (ret) : "m" (*addr));
+ return ret;
}
-extern inline void out_le16(volatile u16 *addr, int val)
+extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
{
- __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
- "r" (val), "r" (addr));
+ __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
+ "r" (val), "r" (addr));
}
-extern inline void out_be16(volatile u16 *addr, int val)
+extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
{
- __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+ __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
}
-extern inline unsigned in_le32(volatile u32 *addr)
+extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
{
- unsigned ret;
+ unsigned ret;
- __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) :
- "r" (addr), "m" (*addr));
- return ret;
+ __asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
+ "twi 0,%0,0;\n"
+ "isync" : "=r" (ret) :
+ "r" (addr), "m" (*addr));
+ return ret;
}
-extern inline unsigned in_be32(volatile u32 *addr)
+extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
{
- unsigned ret;
+ unsigned ret;
- __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
- return ret;
+ __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
+ "twi 0,%0,0;\n"
+ "isync" : "=r" (ret) : "m" (*addr));
+ return ret;
}
-extern inline void out_le32(volatile unsigned *addr, int val)
+extern inline void out_le32(volatile unsigned __iomem *addr, int val)
{
- __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
- "r" (val), "r" (addr));
+ __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
+ "r" (val), "r" (addr));
}
-extern inline void out_be32(volatile unsigned *addr, int val)
+extern inline void out_be32(volatile unsigned __iomem *addr, int val)
{
- __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+ __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
}
#endif
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 48fd982..b3cfa9b 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -645,6 +645,9 @@ void mttlb3(unsigned long index, unsigned long value);
unsigned long mftlb1(unsigned long index);
unsigned long mftlb2(unsigned long index);
unsigned long mftlb3(unsigned long index);
+
+void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
+void remove_tlb(u32 vaddr, u32 size);
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_440 */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 5efc3ee..0a160e2 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -35,18 +35,18 @@
#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
#define MSR_BE (1<<9) /* Branch Trace */
-#define MSR_DE (1<<9) /* Debug Exception Enable */
+#define MSR_DE (1<<9) /* Debug Exception Enable */
#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
-#define MSR_IR (1<<5) /* Instruction Relocate */
+#define MSR_IR (1<<5) /* Instruction Relocate */
#define MSR_IS (1<<5) /* Book E Instruction space */
-#define MSR_DR (1<<4) /* Data Relocate */
+#define MSR_DR (1<<4) /* Data Relocate */
#define MSR_DS (1<<4) /* Book E Data space */
#define MSR_PE (1<<3) /* Protection Enable */
#define MSR_PX (1<<2) /* Protection Exclusive Mode */
#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
#define MSR_RI (1<<1) /* Recoverable Exception */
-#define MSR_LE (1<<0) /* Little Endian */
+#define MSR_LE (1<<0) /* Little Endian */
#ifdef CONFIG_APUS_FAST_EXCEPT
#define MSR_ MSR_ME|MSR_IP|MSR_RI
@@ -58,7 +58,6 @@
#else
#define MSR_KERNEL MSR_ME
#endif
-#define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE
/* Floating Point Status and Control Register (FPSCR) Fields */
@@ -123,9 +122,9 @@
#define DBCR_EDM 0x80000000
#define DBCR_IDM 0x40000000
#define DBCR_RST(x) (((x) & 0x3) << 28)
-#define DBCR_RST_NONE 0
-#define DBCR_RST_CORE 1
-#define DBCR_RST_CHIP 2
+#define DBCR_RST_NONE 0
+#define DBCR_RST_CORE 1
+#define DBCR_RST_CHIP 2
#define DBCR_RST_SYSTEM 3
#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
@@ -218,12 +217,14 @@
#define HID0_DPM (1<<20)
#define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
#define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
+#define HID0_TBEN (1<<14) /* Time Base Enable */
#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */
#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
#define HID0_DCI HID0_DCFI
#define HID0_SPD (1<<9) /* Speculative disable */
+#define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */
#define HID0_SGE (1<<7) /* Store Gathering Enable */
#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */
#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
@@ -266,7 +267,7 @@
#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
-#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
+#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
#define SPRN_LR 0x008 /* Link Register */
@@ -308,7 +309,7 @@
#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
-#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
+#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
#ifdef CONFIG_BOOKE
#define SPRN_SVR 0x3FF /* System Version Register */
#else
@@ -451,10 +452,23 @@
#define SPRN_PID1 0x279 /* Process ID Register 1 */
#define SPRN_PID2 0x27a /* Process ID Register 2 */
#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
+#define SPRN_MCAR 0x23d /* Machine Check Address register */
+#ifdef CONFIG_440
+#define MCSR_MCS 0x80000000 /* Machine Check Summary */
+#define MCSR_IB 0x40000000 /* Instruction PLB Error */
+#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
+#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
+#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
+#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
+#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
+#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
+#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
+#endif
#define ESR_ST 0x00800000 /* Store Operation */
#if defined(CONFIG_MPC86xx)
-#define SPRN_MSSCRO 0x3f6
+#define SPRN_MSSCR0 0x3f6
+#define SPRN_MSSSR0 0x3f7
#endif
@@ -484,17 +498,17 @@
#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
#define DBSR SPRN_DBSR /* Debug Status Register */
-#define DCMP SPRN_DCMP /* Data TLB Compare Register */
-#define DEC SPRN_DEC /* Decrement Register */
-#define DMISS SPRN_DMISS /* Data TLB Miss Register */
+#define DCMP SPRN_DCMP /* Data TLB Compare Register */
+#define DEC SPRN_DEC /* Decrement Register */
+#define DMISS SPRN_DMISS /* Data TLB Miss Register */
#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
-#define EAR SPRN_EAR /* External Address Register */
+#define EAR SPRN_EAR /* External Address Register */
#define ESR SPRN_ESR /* Exception Syndrome Register */
#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
-#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
+#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
@@ -511,17 +525,17 @@
#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
-#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
+#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
-#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
+#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
-#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
+#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
#define LR SPRN_LR
#define MBAR SPRN_MBAR /* System memory base address */
#if defined(CONFIG_MPC86xx)
-#define MSSCR0 SPRN_MSSCRO
+#define MSSCR0 SPRN_MSSCR0
#endif
#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define PIR SPRN_PIR
@@ -529,7 +543,7 @@
#define SVR SPRN_SVR /* System-On-Chip Version Register */
#define PVR SPRN_PVR /* Processor Version */
#define RPA SPRN_RPA /* Required Physical Address Register */
-#define SDR1 SPRN_SDR1 /* MMU hash base register */
+#define SDR1 SPRN_SDR1 /* MMU hash base register */
#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
#define SPR1 SPRN_SPRG1
#define SPR2 SPRN_SPRG2
@@ -544,6 +558,8 @@
#define SPRG7 SPRN_SPRG7
#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
+#define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */
+#define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */
#define SVR SPRN_SVR /* System Version Register */
#define TBRL SPRN_TBRL /* Time Base Read Lower Register */
#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
@@ -598,7 +614,7 @@
#define IVOR35 SPRN_IVOR35
#define MCSRR0 SPRN_MCSRR0
#define MCSRR1 SPRN_MCSRR1
-#define L1CSR0 SPRN_L1CSR0
+#define L1CSR0 SPRN_L1CSR0
#define L1CSR1 SPRN_L1CSR1
#define MCSR SPRN_MCSR
#define MMUCSR0 SPRN_MMUCSR0
@@ -607,7 +623,7 @@
#define PID1 SPRN_PID1
#define PID2 SPRN_PID2
#define MAS0 SPRN_MAS0
-#define MAS1 SPRN_MAS1
+#define MAS1 SPRN_MAS1
#define MAS2 SPRN_MAS2
#define MAS3 SPRN_MAS3
#define MAS4 SPRN_MAS4
@@ -615,11 +631,17 @@
#define MAS6 SPRN_MAS6
#define MAS7 SPRN_MAS7
+#if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx)
+#define DAR_DEAR DEAR
+#else
+#define DAR_DEAR DAR
+#endif
+
/* Device Control Registers */
#define DCRN_BEAR 0x090 /* Bus Error Address Register */
#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
-#define BESR_DSES 0x80000000 /* Data-Side Error Status */
+#define BESR_DSES 0x80000000 /* Data-Side Error Status */
#define BESR_DMES 0x40000000 /* DMA Error Status */
#define BESR_RWS 0x20000000 /* Read/Write Status */
#define BESR_ETMASK 0x1C000000 /* Error Type */
@@ -676,8 +698,8 @@
#define IOCR_E3LP 0x01000000
#define IOCR_E4TE 0x00800000
#define IOCR_E4LP 0x00400000
-#define IOCR_EDT 0x00080000
-#define IOCR_SOR 0x00040000
+#define IOCR_EDT 0x00080000
+#define IOCR_SOR 0x00040000
#define IOCR_EDO 0x00008000
#define IOCR_2XC 0x00004000
#define IOCR_ATC 0x00002000
@@ -802,7 +824,7 @@
#define PVR_823 PVR_821
#define PVR_850 PVR_821
#define PVR_860 PVR_821
-#define PVR_7400 0x000C0000
+#define PVR_7400 0x000C0000
#define PVR_8240 0x00810100
/*
diff --git a/include/at45.h b/include/at45.h
new file mode 100644
index 0000000..40bb4a0
--- /dev/null
+++ b/include/at45.h
@@ -0,0 +1,69 @@
+
+#ifndef _AT45_H_
+#define _AT45_H_
+#ifdef DATAFLASH_MMC_SELECT
+extern void AT91F_SelectMMC(void);
+extern void AT91F_SelectSPI(void);
+extern int AT91F_GetMuxStatus(void);
+#endif
+extern void AT91F_SpiInit(void);
+extern void AT91F_SpiEnable(int cs);
+extern unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc );
+extern AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char OpCode,
+ unsigned int CmdSize,
+ unsigned int DataflashAddress);
+extern AT91S_DataFlashStatus AT91F_DataFlashGetStatus (
+ AT91PS_DataflashDesc pDesc);
+extern AT91S_DataFlashStatus AT91F_DataFlashWaitReady (
+ AT91PS_DataflashDesc pDataFlashDesc,
+ unsigned int timeout);
+extern AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
+ AT91PS_DataFlash pDataFlash,
+ int src,
+ unsigned char *dataBuffer,
+ int sizeToRead );
+extern AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ unsigned int dest,
+ unsigned int SizeToWrite);
+extern AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char BufferCommand,
+ unsigned int page);
+extern AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
+ AT91PS_DataFlash pDataFlash,
+ unsigned char BufferCommand,
+ unsigned char *dataBuffer,
+ unsigned int bufferAddress,
+ int SizeToWrite );
+extern AT91S_DataFlashStatus AT91F_PageErase(
+ AT91PS_DataFlash pDataFlash,
+ unsigned int page);
+extern AT91S_DataFlashStatus AT91F_BlockErase(
+ AT91PS_DataFlash pDataFlash,
+ unsigned int block);
+extern AT91S_DataFlashStatus AT91F_WriteBufferToMain (
+ AT91PS_DataFlash pDataFlash,
+ unsigned char BufferCommand,
+ unsigned int dest );
+extern AT91S_DataFlashStatus AT91F_PartialPageWrite (
+ AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ unsigned int dest,
+ unsigned int size);
+extern AT91S_DataFlashStatus AT91F_DataFlashWrite(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ int dest,
+ int size );
+extern int AT91F_DataFlashRead(
+ AT91PS_DataFlash pDataFlash,
+ unsigned long addr,
+ unsigned long size,
+ char *buffer);
+extern int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc);
+
+#endif
diff --git a/include/ata.h b/include/ata.h
index 8584226..aa6e90d 100644
--- a/include/ata.h
+++ b/include/ata.h
@@ -83,6 +83,66 @@
#define ATA_DEVICE(x) ((x & 1)<<4)
#define ATA_LBA 0xE0
+enum {
+ ATA_MAX_DEVICES = 1, /* per bus/port */
+ ATA_MAX_PRD = 256, /* we could make these 256/256 */
+ ATA_SECT_SIZE = 256, /*256 words per sector */
+
+ /* bits in ATA command block registers */
+ ATA_HOB = (1 << 7), /* LBA48 selector */
+ ATA_NIEN = (1 << 1), /* disable-irq flag */
+ /*ATA_LBA = (1 << 6), */ /* LBA28 selector */
+ ATA_DEV1 = (1 << 4), /* Select Device 1 (slave) */
+ ATA_DEVICE_OBS = (1 << 7) | (1 << 5), /* obs bits in dev reg */
+ ATA_DEVCTL_OBS = (1 << 3), /* obsolete bit in devctl reg */
+ ATA_BUSY = (1 << 7), /* BSY status bit */
+ ATA_DRDY = (1 << 6), /* device ready */
+ ATA_DF = (1 << 5), /* device fault */
+ ATA_DRQ = (1 << 3), /* data request i/o */
+ ATA_ERR = (1 << 0), /* have an error */
+ ATA_SRST = (1 << 2), /* software reset */
+ ATA_ABORTED = (1 << 2), /* command aborted */
+ /* ATA command block registers */
+ ATA_REG_DATA = 0x00,
+ ATA_REG_ERR = 0x01,
+ ATA_REG_NSECT = 0x02,
+ ATA_REG_LBAL = 0x03,
+ ATA_REG_LBAM = 0x04,
+ ATA_REG_LBAH = 0x05,
+ ATA_REG_DEVICE = 0x06,
+ ATA_REG_STATUS = 0x07,
+ ATA_PCI_CTL_OFS = 0x02,
+ /* and their aliases */
+ ATA_REG_FEATURE = ATA_REG_ERR,
+ ATA_REG_CMD = ATA_REG_STATUS,
+ ATA_REG_BYTEL = ATA_REG_LBAM,
+ ATA_REG_BYTEH = ATA_REG_LBAH,
+ ATA_REG_DEVSEL = ATA_REG_DEVICE,
+ ATA_REG_IRQ = ATA_REG_NSECT,
+
+ /* SETFEATURES stuff */
+ SETFEATURES_XFER = 0x03,
+ XFER_UDMA_7 = 0x47,
+ XFER_UDMA_6 = 0x46,
+ XFER_UDMA_5 = 0x45,
+ XFER_UDMA_4 = 0x44,
+ XFER_UDMA_3 = 0x43,
+ XFER_UDMA_2 = 0x42,
+ XFER_UDMA_1 = 0x41,
+ XFER_UDMA_0 = 0x40,
+ XFER_MW_DMA_2 = 0x22,
+ XFER_MW_DMA_1 = 0x21,
+ XFER_MW_DMA_0 = 0x20,
+ XFER_PIO_4 = 0x0C,
+ XFER_PIO_3 = 0x0B,
+ XFER_PIO_2 = 0x0A,
+ XFER_PIO_1 = 0x09,
+ XFER_PIO_0 = 0x08,
+ XFER_SW_DMA_2 = 0x12,
+ XFER_SW_DMA_1 = 0x11,
+ XFER_SW_DMA_0 = 0x10,
+ XFER_PIO_SLOW = 0x00
+};
/*
* ATA Commands (only mandatory commands listed here)
*/
diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h
deleted file mode 100644
index cf36583..0000000
--- a/include/cmd_confdefs.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * (C) Copyright 2000-2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Definitions for Configuring the monitor commands
- */
-#ifndef _CMD_CONFIG_H
-#define _CMD_CONFIG_H
-
-/*
- * Configurable monitor commands
- */
-#define CFG_CMD_BDI 0x00000001ULL /* bdinfo */
-#define CFG_CMD_LOADS 0x00000002ULL /* loads */
-#define CFG_CMD_LOADB 0x00000004ULL /* loadb */
-#define CFG_CMD_IMI 0x00000008ULL /* iminfo */
-#define CFG_CMD_CACHE 0x00000010ULL /* icache, dcache */
-#define CFG_CMD_FLASH 0x00000020ULL /* flinfo, erase, protect */
-#define CFG_CMD_MEMORY 0x00000040ULL /* md, mm, nm, mw, cp, cmp, */
- /* crc, base, loop, mtest */
-#define CFG_CMD_NET 0x00000080ULL /* bootp, tftpboot, rarpboot */
-#define CFG_CMD_ENV 0x00000100ULL /* saveenv */
-#define CFG_CMD_KGDB 0x0000000000000200ULL /* kgdb */
-#define CFG_CMD_PCMCIA 0x00000400ULL /* PCMCIA support */
-#define CFG_CMD_IDE 0x00000800ULL /* IDE harddisk support */
-#define CFG_CMD_PCI 0x00001000ULL /* pciinfo */
-#define CFG_CMD_IRQ 0x00002000ULL /* irqinfo */
-#define CFG_CMD_BOOTD 0x00004000ULL /* bootd */
-#define CFG_CMD_CONSOLE 0x00008000ULL /* coninfo */
-#define CFG_CMD_EEPROM 0x00010000ULL /* EEPROM read/write support */
-#define CFG_CMD_ASKENV 0x00020000ULL /* ask for env variable */
-#define CFG_CMD_RUN 0x00040000ULL /* run command in env variable */
-#define CFG_CMD_ECHO 0x00080000ULL /* echo arguments */
-#define CFG_CMD_I2C 0x00100000ULL /* I2C serial bus support */
-#define CFG_CMD_REGINFO 0x00200000ULL /* Register dump */
-#define CFG_CMD_IMMAP 0x00400000ULL /* IMMR dump support */
-#define CFG_CMD_DATE 0x00800000ULL /* support for RTC, date/time...*/
-#define CFG_CMD_DHCP 0x01000000ULL /* DHCP Support */
-#define CFG_CMD_BEDBUG 0x02000000ULL /* Include BedBug Debugger */
-#define CFG_CMD_FDC 0x04000000ULL /* Floppy Disk Support */
-#define CFG_CMD_SCSI 0x08000000ULL /* SCSI Support */
-#define CFG_CMD_AUTOSCRIPT 0x10000000ULL /* Autoscript Support */
-#define CFG_CMD_MII 0x20000000ULL /* MII support */
-#define CFG_CMD_SETGETDCR 0x40000000ULL /* DCR support on 4xx */
-#define CFG_CMD_BSP 0x80000000ULL /* Board Specific functions */
-
-#define CFG_CMD_ELF 0x0000000100000000ULL /* ELF (VxWorks) load/boot cmd */
-#define CFG_CMD_MISC 0x0000000200000000ULL /* Misc functions like sleep etc*/
-#define CFG_CMD_USB 0x0000000400000000ULL /* USB Support */
-#define CFG_CMD_DOC 0x0000000800000000ULL /* Disk-On-Chip Support */
-#define CFG_CMD_JFFS2 0x0000001000000000ULL /* JFFS2 Support */
-#define CFG_CMD_DTT 0x0000002000000000ULL /* Digital Therm and Thermostat */
-#define CFG_CMD_SDRAM 0x0000004000000000ULL /* SDRAM DIMM SPD info printout */
-#define CFG_CMD_DIAG 0x0000008000000000ULL /* Diagnostics */
-#define CFG_CMD_FPGA 0x0000010000000000ULL /* FPGA configuration Support */
-#define CFG_CMD_HWFLOW 0x0000020000000000ULL /* RTS/CTS hw flow control */
-#define CFG_CMD_SAVES 0x0000040000000000ULL /* save S record dump */
-#define CFG_CMD_SPI 0x0000100000000000ULL /* SPI utility */
-#define CFG_CMD_FDOS 0x0000200000000000ULL /* Floppy DOS support */
-#define CFG_CMD_VFD 0x0000400000000000ULL /* VFD support (TRAB) */
-#define CFG_CMD_NAND 0x0000800000000000ULL /* NAND support */
-#define CFG_CMD_BMP 0x0001000000000000ULL /* BMP support */
-#define CFG_CMD_PORTIO 0x0002000000000000ULL /* Port I/O */
-#define CFG_CMD_PING 0x0004000000000000ULL /* ping support */
-#define CFG_CMD_MMC 0x0008000000000000ULL /* MMC support */
-#define CFG_CMD_FAT 0x0010000000000000ULL /* FAT support */
-#define CFG_CMD_IMLS 0x0020000000000000ULL /* List all found images */
-#define CFG_CMD_ITEST 0x0040000000000000ULL /* Integer (and string) test */
-#define CFG_CMD_NFS 0x0080000000000000ULL /* NFS support */
-#define CFG_CMD_REISER 0x0100000000000000ULL /* Reiserfs support */
-#define CFG_CMD_CDP 0x0200000000000000ULL /* Cisco Discovery Protocol */
-#define CFG_CMD_XIMG 0x0400000000000000ULL /* Load part of Multi Image */
-#define CFG_CMD_UNIVERSE 0x0800000000000000ULL /* Tundra Universe Support */
-#define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */
-#define CFG_CMD_SNTP 0x2000000000000000ULL /* SNTP support */
-#define CFG_CMD_DISPLAY 0x4000000000000000ULL /* Display support */
-
-#define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFULL /* ALL commands */
-
-/* Commands that are considered "non-standard" for some reason
- * (memory hogs, requires special hardware, not fully tested, etc.)
- */
-#define CFG_CMD_NONSTD (CFG_CMD_ASKENV | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_BMP | \
- CFG_CMD_BSP | \
- CFG_CMD_CACHE | \
- CFG_CMD_CDP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_DISPLAY | \
- CFG_CMD_DOC | \
- CFG_CMD_DTT | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_EXT2 | \
- CFG_CMD_FDC | \
- CFG_CMD_FAT | \
- CFG_CMD_FDOS | \
- CFG_CMD_HWFLOW | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_IMMAP | \
- CFG_CMD_IRQ | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_KGDB | \
- CFG_CMD_MII | \
- CFG_CMD_MMC | \
- CFG_CMD_NAND | \
- CFG_CMD_PCI | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_PING | \
- CFG_CMD_PORTIO | \
- CFG_CMD_REGINFO | \
- CFG_CMD_REISER | \
- CFG_CMD_SAVES | \
- CFG_CMD_SCSI | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP | \
- CFG_CMD_SPI | \
- CFG_CMD_UNIVERSE | \
- CFG_CMD_USB | \
- CFG_CMD_VFD )
-
-/* Default configuration
- */
-#define CONFIG_CMD_DFL (CFG_CMD_ALL & ~CFG_CMD_NONSTD)
-
-#ifndef CONFIG_COMMANDS
-#define CONFIG_COMMANDS CONFIG_CMD_DFL
-#endif
-
-
-/*
- * optional BOOTP fields
- */
-
-#define CONFIG_BOOTP_SUBNETMASK 0x00000001
-#define CONFIG_BOOTP_GATEWAY 0x00000002
-#define CONFIG_BOOTP_HOSTNAME 0x00000004
-#define CONFIG_BOOTP_NISDOMAIN 0x00000008
-#define CONFIG_BOOTP_BOOTPATH 0x00000010
-#define CONFIG_BOOTP_BOOTFILESIZE 0x00000020
-#define CONFIG_BOOTP_DNS 0x00000040
-#define CONFIG_BOOTP_DNS2 0x00000080
-#define CONFIG_BOOTP_SEND_HOSTNAME 0x00000100
-#define CONFIG_BOOTP_NTPSERVER 0x00000200
-#define CONFIG_BOOTP_TIMEOFFSET 0x00000400
-
-#define CONFIG_BOOTP_VENDOREX 0x80000000
-
-#define CONFIG_BOOTP_ALL (~CONFIG_BOOTP_VENDOREX)
-
-
-#define CONFIG_BOOTP_DEFAULT (CONFIG_BOOTP_SUBNETMASK | \
- CONFIG_BOOTP_GATEWAY | \
- CONFIG_BOOTP_HOSTNAME | \
- CONFIG_BOOTP_BOOTPATH)
-
-#ifndef CONFIG_BOOTP_MASK
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-#endif
-
-#endif /* _CMD_CONFIG_H */
diff --git a/include/command.h b/include/command.h
index a2936ad..0597c10 100644
--- a/include/command.h
+++ b/include/command.h
@@ -84,12 +84,6 @@ typedef void command_t (cmd_tbl_t *, int, int, char *[]);
#define CMD_FLAG_REPEAT 0x0001 /* repeat last command */
#define CMD_FLAG_BOOTD 0x0002 /* command is from bootd */
-/*
- * Configurable monitor commands definitions have been moved
- * to include/cmd_confdefs.h
- */
-
-
#define Struct_Section __attribute__ ((unused,section (".u_boot_cmd")))
#ifdef CFG_LONGHELP
diff --git a/include/common.h b/include/common.h
index b162dbd..aca281b 100644
--- a/include/common.h
+++ b/include/common.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2004
+ * (C) Copyright 2000-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -38,7 +38,7 @@ typedef volatile unsigned char vu_char;
#include <linux/string.h>
#include <asm/ptrace.h>
#include <stdarg.h>
-#if defined(CONFIG_PCI) && defined(CONFIG_440)
+#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
#include <pci.h>
#endif
#if defined(CONFIG_8xx)
@@ -63,10 +63,19 @@ typedef volatile unsigned char vu_char;
#endif
#elif defined(CONFIG_5xx)
#include <asm/5xx_immap.h>
+#define CONFIG_RELOC_FIXUP_WORKS
#elif defined(CONFIG_MPC5xxx)
#include <mpc5xxx.h>
+#define CONFIG_RELOC_FIXUP_WORKS
+#elif defined(CONFIG_MPC512X)
+#include <mpc512x.h>
+#include <asm/immap_512x.h>
+#define CONFIG_RELOC_FIXUP_WORKS
#elif defined(CONFIG_MPC8220)
#include <asm/immap_8220.h>
+#define CONFIG_RELOC_FIXUP_WORKS
+#elif defined(CONFIG_824X)
+#define CONFIG_RELOC_FIXUP_WORKS
#elif defined(CONFIG_8260)
#if defined(CONFIG_MPC8247) \
|| defined(CONFIG_MPC8248) \
@@ -78,6 +87,7 @@ typedef volatile unsigned char vu_char;
#define CONFIG_MPC8260 1
#endif
#include <asm/immap_8260.h>
+#define CONFIG_RELOC_FIXUP_WORKS
#endif
#ifdef CONFIG_MPC86xx
#include <mpc86xx.h>
@@ -90,6 +100,7 @@ typedef volatile unsigned char vu_char;
#ifdef CONFIG_MPC83XX
#include <mpc83xx.h>
#include <asm/immap_83xx.h>
+#define CONFIG_RELOC_FIXUP_WORKS
#endif
#ifdef CONFIG_4xx
#include <ppc4xx.h>
@@ -230,6 +241,9 @@ int saveenv (void);
void inline setenv (char *, char *);
#else
void setenv (char *, char *);
+#ifdef CONFIG_HAS_UID
+void forceenv (char *, char *);
+#endif
#endif /* CONFIG_PPC */
#ifdef CONFIG_ARM
# include <asm/mach-types.h>
@@ -248,10 +262,11 @@ void pci_init (void);
void pci_init_board(void);
void pciinfo (int, int);
-#if defined(CONFIG_PCI) && defined(CONFIG_440)
-# if defined(CFG_PCI_PRE_INIT)
+#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
int pci_pre_init (struct pci_controller * );
-# endif
+#endif
+
+#if defined(CONFIG_PCI) && defined(CONFIG_440)
# if defined(CFG_PCI_TARGET_INIT)
void pci_target_init (struct pci_controller *);
# endif
@@ -260,7 +275,7 @@ void pciinfo (int, int);
# endif
int is_pci_host (struct pci_controller *);
#if defined(CONFIG_440SPE)
- void pcie_setup_hoses(void);
+ void pcie_setup_hoses(int busno);
#endif
#endif
@@ -402,6 +417,10 @@ void ppcDcbi(unsigned long value);
void ppcSync(void);
void ppcDcbz(unsigned long value);
#endif
+#if defined (CONFIG_MICROBLAZE)
+unsigned short in16(unsigned int);
+void out16(unsigned int, unsigned short value);
+#endif
#if defined (CONFIG_MPC83XX)
void ppcDWload(unsigned int *addr, unsigned int *ret);
@@ -415,6 +434,13 @@ int checkdcache (void);
void upmconfig (unsigned int, unsigned int *, unsigned int);
ulong get_tbclk (void);
void reset_cpu (ulong addr);
+#if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
+void ft_cpu_setup(void *blob, bd_t *bd);
+#ifdef CONFIG_PCI
+void ft_pci_setup(void *blob, bd_t *bd);
+#endif
+#endif
+
/* $(CPU)/serial.c */
int serial_init (void);
@@ -440,11 +466,12 @@ int sdram_adjust_866 (void);
int adjust_sdram_tbs_8xx (void);
#if defined(CONFIG_8260)
int prt_8260_clks (void);
-#elif defined(CONFIG_MPC83XX)
-int print_clock_conf(void);
#elif defined(CONFIG_MPC5xxx)
int prt_mpc5xxx_clks (void);
#endif
+#if defined(CONFIG_MPC512x)
+int prt_mpc512xxx_clks (void);
+#endif
#if defined(CONFIG_MPC8220)
int prt_mpc8220_clks (void);
#endif
@@ -509,6 +536,8 @@ void cpu_init_f (void);
int cpu_init_r (void);
#if defined(CONFIG_8260)
int prt_8260_rsr (void);
+#elif defined(CONFIG_MPC83XX)
+int prt_83xx_rsr (void);
#endif
/* $(CPU)/interrupts.c */
@@ -623,9 +652,13 @@ int fgetc(int file);
int pcmcia_init (void);
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-void show_boot_progress (int status);
+#ifdef CONFIG_STATUS_LED
+# include <status_led.h>
#endif
+/*
+ * Board-specific Platform code can reimplement show_boot_progress () if needed
+ */
+void inline show_boot_progress (int val);
#ifdef CONFIG_INIT_CRITICAL
#error CONFIG_INIT_CRITICAL is deprecated!
diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h
new file mode 100644
index 0000000..3d91e99
--- /dev/null
+++ b/include/config_cmd_all.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License Version 2. This file is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef _CONFIG_CMD_ALL_H
+#define _CONFIG_CMD_ALL_H
+
+/*
+ * Alphabetical list of all possible commands.
+ */
+
+#define CONFIG_CMD_ASKENV /* ask for env variable */
+#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */
+#define CONFIG_CMD_BDI /* bdinfo */
+#define CONFIG_CMD_BEDBUG /* Include BedBug Debugger */
+#define CONFIG_CMD_BMP /* BMP support */
+#define CONFIG_CMD_BOOTD /* bootd */
+#define CONFIG_CMD_BSP /* Board Specific functions */
+#define CONFIG_CMD_CACHE /* icache, dcache */
+#define CONFIG_CMD_CDP /* Cisco Discovery Protocol */
+#define CONFIG_CMD_CONSOLE /* coninfo */
+#define CONFIG_CMD_DATE /* support for RTC, date/time...*/
+#define CONFIG_CMD_DHCP /* DHCP Support */
+#define CONFIG_CMD_DIAG /* Diagnostics */
+#define CONFIG_CMD_DISPLAY /* Display support */
+#define CONFIG_CMD_DOC /* Disk-On-Chip Support */
+#define CONFIG_CMD_DTT /* Digital Therm and Thermostat */
+#define CONFIG_CMD_ECHO /* echo arguments */
+#define CONFIG_CMD_EEPROM /* EEPROM read/write support */
+#define CONFIG_CMD_ELF /* ELF (VxWorks) load/boot cmd */
+#define CONFIG_CMD_ENV /* saveenv */
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_FDC /* Floppy Disk Support */
+#define CONFIG_CMD_FDOS /* Floppy DOS support */
+#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#define CONFIG_CMD_FPGA /* FPGA configuration Support */
+#define CONFIG_CMD_HWFLOW /* RTS/CTS hw flow control */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_IDE /* IDE harddisk support */
+#define CONFIG_CMD_IMI /* iminfo */
+#define CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_CMD_IMMAP /* IMMR dump support */
+#define CONFIG_CMD_IRQ /* irqinfo */
+#define CONFIG_CMD_ITEST /* Integer (and string) test */
+#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define CONFIG_CMD_KGDB /* kgdb */
+#define CONFIG_CMD_LOADB /* loadb */
+#define CONFIG_CMD_LOADS /* loads */
+#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MFSL /* FSL support for Microblaze */
+#define CONFIG_CMD_MII /* MII support */
+#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_NAND /* NAND support */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_PCI /* pciinfo */
+#define CONFIG_CMD_PCMCIA /* PCMCIA support */
+#define CONFIG_CMD_PING /* ping support */
+#define CONFIG_CMD_PORTIO /* Port I/O */
+#define CONFIG_CMD_REGINFO /* Register dump */
+#define CONFIG_CMD_REISER /* Reiserfs support */
+#define CONFIG_CMD_RUN /* run command in env variable */
+#define CONFIG_CMD_SAVES /* save S record dump */
+#define CONFIG_CMD_SCSI /* SCSI Support */
+#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
+#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
+#define CONFIG_CMD_SNTP /* SNTP support */
+#define CONFIG_CMD_SPI /* SPI utility */
+#define CONFIG_CMD_UNIVERSE /* Tundra Universe Support */
+#define CONFIG_CMD_USB /* USB Support */
+#define CONFIG_CMD_VFD /* VFD support (TRAB) */
+#define CONFIG_CMD_XIMG /* Load part of Multi Image */
+#define CONFIG_CMD_MUX /* AT91 MMC/SPI Mux Support */
+
+#endif /* _CONFIG_CMD_ALL_H */
diff --git a/include/config_cmd_default.h b/include/config_cmd_default.h
new file mode 100644
index 0000000..f61cfc9
--- /dev/null
+++ b/include/config_cmd_default.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License Version 2. This file is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef _CONFIG_CMD_DEFAULT_H
+#define _CONFIG_CMD_DEFAULT_H
+
+/*
+ * Alphabetical list of all commands that are configured by default.
+ * This is essentially all commands minus those that are considered
+ * "non-standard" for some reason (memory hogs, requires special
+ * hardware, not fully tested, etc.).
+ */
+
+#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */
+#define CONFIG_CMD_BDI /* bdinfo */
+#define CONFIG_CMD_BOOTD /* bootd */
+#define CONFIG_CMD_CONSOLE /* coninfo */
+#define CONFIG_CMD_ECHO /* echo arguments */
+#define CONFIG_CMD_ENV /* saveenv */
+#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#define CONFIG_CMD_FPGA /* FPGA configuration Support */
+#define CONFIG_CMD_IMI /* iminfo */
+#define CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_CMD_ITEST /* Integer (and string) test */
+#define CONFIG_CMD_LOADB /* loadb */
+#define CONFIG_CMD_LOADS /* loads */
+#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_RUN /* run command in env variable */
+#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
+#define CONFIG_CMD_XIMG /* Load part of Multi Image */
+
+#endif /* _CONFIG_CMD_DEFAULT_H */
diff --git a/include/configs/A3000.h b/include/configs/A3000.h
index ca9592c..0a9a1ff 100644
--- a/include/configs/A3000.h
+++ b/include/configs/A3000.h
@@ -52,23 +52,20 @@
#define CONFIG_BOOTDELAY 5
-#if 0
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_BSP | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_FLASH | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_NET | \
- CFG_CMD_PCI )
-#endif
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
/*
@@ -309,7 +306,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h
index 821efe5..4632991 100644
--- a/include/configs/ADCIOP.h
+++ b/include/configs/ADCIOP.h
@@ -59,21 +59,32 @@
#define CONFIG_IPADDR 10.0.18.222
#define CONFIG_SERVERIP 10.0.18.190
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_ASKENV )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ASKENV
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -185,7 +196,7 @@
*/
#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */
#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h
index 2efca10..77938b1 100644
--- a/include/configs/ADNPESC1.h
+++ b/include/configs/ADNPESC1.h
@@ -401,15 +401,8 @@
#define CONFIG_RTC_DS1306 1 /* Dallas 1306 real time clock */
#define CFG_SPI_RTC_DEVID 0 /* as 1st SPI device */
-#define __SPI_CMD_OFF 0 /* allow default commands: */
- /* CFG_CMD_SPI */
- /* CFG_CMD_DATE */
-
#else
#undef CONFIG_NIOS_SPI /* NO SPI support */
-#define __SPI_CMD_OFF ( CFG_CMD_SPI \
- | CFG_CMD_DATE \
- )
#endif
/*------------------------------------------------------------------------
@@ -570,45 +563,55 @@
#define CONFIG_POST CFG_POST_RTC
#define CFG_NIOS_POST_WORD_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-/*------------------------------------------------------------------------
- * COMMANDS
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
- CFG_CMD_ASKENV | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_BMP | \
- CFG_CMD_CACHE | \
- CFG_CMD_DOC | \
- CFG_CMD_DTT | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_FAT | \
- CFG_CMD_FDC | \
- CFG_CMD_FDOS | \
- CFG_CMD_HWFLOW | \
- CFG_CMD_IDE | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_KGDB | \
- CFG_CMD_NAND | \
- CFG_CMD_NFS | \
- CFG_CMD_MMC | \
- CFG_CMD_MII | \
- CFG_CMD_PCI | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_SCSI | \
- CFG_CMD_VFD | \
- CFG_CMD_USB | \
- CFG_CMD_XIMG | \
- __SPI_CMD_OFF ) )
-
-
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_ASKENV
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_BMP
+#undef CONFIG_CMD_CACHE
+#undef CONFIG_CMD_DOC
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_FAT
+#undef CONFIG_CMD_FDC
+#undef CONFIG_CMD_FDOS
+#undef CONFIG_CMD_HWFLOW
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_KGDB
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_MMC
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PCI
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_SCSI
+#undef CONFIG_CMD_VFD
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_XIMG
+
+#if (CFG_NIOS_CPU_SPI_NUMS != 1)
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_DATE
+#endif
/*------------------------------------------------------------------------
* KGDB
*----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 9600
#endif
@@ -651,7 +654,6 @@
#undef CFG_LOAD_ADDR /* force error break */
#endif
-
/* MEM test area */
#if (CFG_SDRAM_SIZE != 0)
diff --git a/include/configs/ADS860.h b/include/configs/ADS860.h
index df20965..2ee8c61 100644
--- a/include/configs/ADS860.h
+++ b/include/configs/ADS860.h
@@ -37,13 +37,19 @@
#define CONFIG_DRAM_50MHZ 1
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_DHCP \
- | CFG_CMD_IMMAP \
- | CFG_CMD_PCMCIA \
- | CFG_CMD_PING \
- )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_PING
+
+/* This is picked up again in fads.h */
+#define FADS_COMMANDS_ALREADY_DEFINED
#include "fads.h"
diff --git a/include/configs/AMX860.h b/include/configs/AMX860.h
index 14d56bf..6f64038 100644
--- a/include/configs/AMX860.h
+++ b/include/configs/AMX860.h
@@ -61,7 +61,25 @@
#undef CONFIG_BOOTARGS
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
+
+#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -70,29 +88,22 @@
#endif
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -196,7 +207,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h
index ba4b1a2..d25aa74 100644
--- a/include/configs/AP1000.h
+++ b/include/configs/AP1000.h
@@ -66,18 +66,28 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_IRQ | \
- CFG_CMD_MVENV | \
- CFG_CMD_PCI | \
- CFG_CMD_PING \
- )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MVENV
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -89,7 +99,7 @@
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -188,7 +198,7 @@
*/
#define CFG_DCACHE_SIZE 16384
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -228,7 +238,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/APC405.h b/include/configs/APC405.h
index 3df99a0..f6495e4 100644
--- a/include/configs/APC405.h
+++ b/include/configs/APC405.h
@@ -67,27 +67,38 @@
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
@@ -106,7 +117,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -266,7 +277,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/AR405.h b/include/configs/AR405.h
index 1cd0280..0f301ec 100644
--- a/include/configs/AR405.h
+++ b/include/configs/AR405.h
@@ -71,17 +71,29 @@
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_BSP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -92,7 +104,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -207,7 +219,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index d03c05b..9adbba9 100644
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -53,25 +53,41 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
+
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_NAND | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -91,7 +107,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -132,40 +148,18 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
@@ -270,7 +264,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/Adder.h b/include/configs/Adder.h
index 0e6b50f..4304ecc 100644
--- a/include/configs/Adder.h
+++ b/include/configs/Adder.h
@@ -52,15 +52,26 @@
#define CFG_8xx_CPUCLK_MAX 133000000
#endif /* CONFIG_MPC852T */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_DHCP \
- | CFG_CMD_IMMAP \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- )
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */
diff --git a/include/configs/AdderUSB.h b/include/configs/AdderUSB.h
new file mode 100644
index 0000000..a4f7f9a
--- /dev/null
+++ b/include/configs/AdderUSB.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2006 CodeHermit.
+ * Bryan O'Donoghue <bodonoghue@codehermit.ie>
+ *
+ * Provides support for USB console on the Analogue & Micro Adder87x
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ADDERUSB__
+#define __ADDERUSB__
+
+/* Include the board port */
+#include "Adder.h"
+
+#define CONFIG_USB_DEVICE /* Include UDC driver */
+#define CONFIG_USB_TTY /* Bind the TTY driver to UDC */
+#define CFG_USB_EXTC_CLK 0x02 /* Oscillator on EXTC_CLK 2 */
+#define CFG_USB_BRG_CLK 0x04 /* or use Baud rate generator 0x04 */
+#define CFG_CONSOLE_IS_IN_ENV /* Console is in env */
+
+/* If you have a USB-IF assigned VendorID then you may wish to define
+ * your own vendor specific values either in BoardName.h or directly in
+ * usbd_vendor_info.h
+ */
+
+/*
+#define CONFIG_USBD_MANUFACTURER "CodeHermit.ie"
+#define CONFIG_USBD_PRODUCT_NAME "Das U-Boot"
+#define CONFIG_USBD_VENDORID 0xFFFF
+#define CONFIG_USBD_PRODUCTID_GSERIAL 0xFFFF
+#define CONFIG_USBD_PRODUCTID_CDCACM 0xFFFE
+*/
+
+#endif /* __ADDERUSB_H__ */
diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h
index c08b2c3..3f2f614 100644
--- a/include/configs/Alaska8220.h
+++ b/include/configs/Alaska8220.h
@@ -39,12 +39,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -70,31 +64,40 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BOOTD | \
- CFG_CMD_CACHE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP )
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#define CONFIG_NET_MULTI
#define CONFIG_MII
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Autobooting
*/
@@ -282,7 +285,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -298,6 +301,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/AmigaOneG3SE.h b/include/configs/AmigaOneG3SE.h
index ea50f41..d914dcc 100644
--- a/include/configs/AmigaOneG3SE.h
+++ b/include/configs/AmigaOneG3SE.h
@@ -56,38 +56,46 @@
#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=4096"
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_AMIGA_PARTITION
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_NET | \
- CFG_CMD_IDE | \
- CFG_CMD_FDC | \
- CFG_CMD_CACHE | \
- CFG_CMD_CONSOLE| \
- CFG_CMD_USB | \
- CFG_CMD_BSP | \
- CFG_CMD_PCI )
-
-/* CFG_CMD_MII | \ */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FDC
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CONSOLE|
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_PCI
+
#define CONFIG_PCI 1
/* #define CONFIG_PCI_SCAN_SHOW 1 */
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-#include <cmd_confdefs.h>
-
+#define atoi(x) simple_strtoul(x,NULL,10)
/*
* Miscellaneous configurable options
@@ -247,7 +255,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -348,8 +356,6 @@
#define CONFIG_3COM
/* #define CONFIG_BOOTP_RANDOM_DELAY */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
/*
* USB configuration
diff --git a/include/configs/B2.h b/include/configs/B2.h
index e55858d..f1411db 100644
--- a/include/configs/B2.h
+++ b/include/configs/B2.h
@@ -72,16 +72,26 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C )
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 5
#define CONFIG_ETHADDR 00:50:c2:1e:af:fb
diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h
index 46bdfa2..c11e9c9 100644
--- a/include/configs/BAB7xx.h
+++ b/include/configs/BAB7xx.h
@@ -66,14 +66,30 @@
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 |\
- CFG_CMD_SCSI | CFG_CMD_IDE | CFG_CMD_DATE |\
- CFG_CMD_FDC | CFG_CMD_ELF)
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_FDC
+#define CONFIG_CMD_ELF
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -86,7 +102,7 @@
*/
#define CONFIG_CONS_INDEX 1
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -436,7 +452,7 @@ extern unsigned long bab7xx_get_gclk_freq (void);
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h
index 5b54f30..5c2bfc9 100644
--- a/include/configs/BC3450.h
+++ b/include/configs/BC3450.h
@@ -61,11 +61,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -106,12 +101,6 @@
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
-#ifdef CONFIG_PCI
-# define ADD_PCI_CMD CFG_CMD_PCI
-#else
-# define ADD_PCI_CMD 0
-#endif
-
/*
* Video console
*/
@@ -126,12 +115,6 @@
# define CONFIG_SPLASH_SCREEN
# define CFG_CONSOLE_IS_IN_ENV
-#ifdef CONFIG_VIDEO
-# define ADD_BMP_CMD CFG_CMD_BMP
-#else
-# define ADD_BMP_CMD 0
-#endif
-
/*
* Partitions
*/
@@ -144,10 +127,7 @@
*/
#ifdef CONFIG_BC3450_USB
# define CONFIG_USB_OHCI
-# define ADD_USB_CMD CFG_CMD_USB
# define CONFIG_USB_STORAGE
-#else /* !CONFIG_BC3450_USB */
-# define ADD_USB_CMD 0
#endif /* CONFIG_BC3450_USB */
/*
@@ -158,66 +138,69 @@
CFG_POST_I2C)
#ifdef CONFIG_POST
-# define CFG_CMD_POST_DIAG CFG_CMD_DIAG
/* preserve space for the post_word at end of on-chip SRAM */
# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#else
-# define CFG_CMD_POST_DIAG 0
#endif /* CONFIG_POST */
-/*
- * IDE
- */
-#ifdef CONFIG_BC3450_IDE
-# define ADD_IDE_CMD CFG_CMD_IDE
-#else
-# define ADD_IDE_CMD 0
-#endif /* CONFIG_BC3450_IDE */
/*
- * Filesystem support
+ * BOOTP options
*/
-#if defined (CONFIG_BC3450_IDE) || defined (CONFIG_BC3450_USB)
-#ifdef CONFIG_FAT
-# define ADD_FAT_CMD CFG_CMD_FAT
-#else
-# define ADD_FAT_CMD 0
-#endif /* CONFIG_FAT */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#ifdef CONFIG_EXT2
-# define ADD_EXT2_CMD CFG_CMD_EXT2
-#else
-# define ADD_EXT2_CMD 0
-#endif /* CONFIG_EXT2 */
-#endif /* CONFIG_BC3450_IDE / _USB */
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- ADD_BMP_CMD | \
- ADD_IDE_CMD | \
- ADD_FAT_CMD | \
- ADD_EXT2_CMD | \
- ADD_PCI_CMD | \
- ADD_USB_CMD | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SNTP | \
- CFG_CMD_BSP)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_BSP
+
+#ifdef CONFIG_VIDEO
+ #define CONFIG_CMD_BMP
+#endif
+
+#ifdef CONFIG_BC3450_IDE
+ #define CONFIG_CMD_IDE
+#endif
+
+#if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
+ #ifdef CONFIG_FAT
+ #define CONFIG_CMD_FAT
+ #endif
+
+ #ifdef CONFIG_EXT2
+ #define CONFIG_CMD_EXT2
+ #endif
+#endif
+
+#ifdef CONFIG_BC3450_USB
+ #define CONFIG_CMD_USB
+#endif
+
+#ifdef CONFIG_PCI
+ #define CONFIG_CMD_PCI
+#endif
+
+#ifdef CONFIG_POST
+ #define CONFIG_CMD_DIAG
+#endif
+
#define CONFIG_TIMESTAMP /* display image timestamps */
@@ -282,17 +265,17 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet
- * hasn't been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
-#if defined(CFG_IPBSPEED_133)
-# define CFG_PCISPEED_66 /* define for 66MHz speed */
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
+# define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@@ -450,7 +433,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -469,9 +452,13 @@
#define CFG_HZ 1000 /* dec freq: 1ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
@@ -488,7 +475,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
# define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
# define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/BMW.h b/include/configs/BMW.h
index 3bd43d8..bb7856f 100644
--- a/include/configs/BMW.h
+++ b/include/configs/BMW.h
@@ -64,28 +64,35 @@
#define CFG_DOC_SUPPORT_2000 1
#define CFG_DOC_SUPPORT_MILLENNIUM 1
#define CFG_DOC_SHORT_TIMEOUT 1
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DOC | \
- CFG_CMD_ELF | \
- 0 )
-/* CFG_CMD_DOC required legacy NAND support */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_ELF
+
+
+/* CONFIG_CMD_DOC required legacy NAND support */
#define CFG_NAND_LEGACY
#if 0
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | \
- CFG_CMD_PCI | CFG_CMD_DOC | CFG_CMD_DATE)
-
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
#endif
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-#include <cmd_confdefs.h>
-
-
/*
* Miscellaneous configurable options
*/
@@ -293,7 +300,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h
index e0262a8..ae32f6b 100644
--- a/include/configs/CANBT.h
+++ b/include/configs/CANBT.h
@@ -56,13 +56,26 @@
#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_COMMANDS (( CONFIG_CMD_DFL | \
- CFG_CMD_IRQ | \
- CFG_CMD_EEPROM ) & \
- ~CFG_CMD_NET)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_EEPROM
+
+#undef CONFIG_CMD_NET
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -73,7 +86,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -173,7 +186,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
index 7ec4599..0321650 100644
--- a/include/configs/CATcenter.h
+++ b/include/configs/CATcenter.h
@@ -119,24 +119,36 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_NAND | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
@@ -155,7 +167,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -387,6 +399,8 @@
#define CFG_ENV_ADDR_REDUND 0xFFFFA000
#define CFG_ENV_SIZE_REDUND 0x2000
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
#define CFG_NVRAM_SIZE 242 /* NVRAM size */
@@ -413,7 +427,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CCM.h b/include/configs/CCM.h
index e8994ff..9f06957 100644
--- a/include/configs/CCM.h
+++ b/include/configs/CCM.h
@@ -94,27 +94,35 @@
#define CONFIG_MAC_PARTITION /* nod used yet */
#define CONFIG_DOS_PARTITION
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BSP | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE | \
- CFG_CMD_EEPROM | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
-/*----------------------------------------------------------------------*/
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
index 1cca285..21cd9c1 100644
--- a/include/configs/CMS700.h
+++ b/include/configs/CMS700.h
@@ -60,28 +60,35 @@
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_BSP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_NAND | \
- CFG_CMD_I2C | \
- CFG_CMD_DATE | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -100,7 +107,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -148,36 +155,18 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
@@ -289,7 +278,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h
index b882f7a..aea8523 100644
--- a/include/configs/CPC45.h
+++ b/include/configs/CPC45.h
@@ -54,27 +54,36 @@
#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_EXT2 | \
- CFG_CMD_FAT | \
- CFG_CMD_FLASH | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP )
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
*/
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
/*
@@ -325,7 +334,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
index 56fd9a6..a3717b9 100644
--- a/include/configs/CPCI2DP.h
+++ b/include/configs/CPCI2DP.h
@@ -54,16 +54,29 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_BSP | \
- CFG_CMD_EEPROM )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
+#undef CONFIG_CMD_NET
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -80,7 +93,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -216,7 +229,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index 047e2f1..1b948f6 100644
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -55,32 +55,43 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_EEPROM
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_ELF | \
- CFG_CMD_MII | \
- CFG_CMD_EEPROM )
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
@@ -96,7 +107,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -260,7 +271,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index d756f44..fb71c5f 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -37,6 +37,7 @@
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
+#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
@@ -56,28 +57,44 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_BSP | \
- CFG_CMD_EEPROM )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
#if 0 /* test-only */
#define CONFIG_NETCONSOLE
@@ -97,11 +114,6 @@
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
@@ -117,7 +129,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -311,7 +323,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index 852d94a..4994319 100644
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -57,38 +57,48 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SUPPORT_VFAT
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-#define CFG_NAND_LEGACY
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -105,7 +115,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -284,7 +294,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
index 2260327..29f9292 100644
--- a/include/configs/CPCI405DT.h
+++ b/include/configs/CPCI405DT.h
@@ -56,28 +56,44 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_BSP | \
- CFG_CMD_EEPROM )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
#if 0 /* test-only */
#define CONFIG_NETCONSOLE
@@ -95,11 +111,6 @@
#undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
@@ -115,7 +126,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -314,7 +325,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h
index 90d3a8d..318ada1 100644
--- a/include/configs/CPCI440.h
+++ b/include/configs/CPCI440.h
@@ -33,6 +33,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_CPCI440 1 /* Board is ebony */
#define CONFIG_440GP 1 /* Specifc GP support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
@@ -171,29 +172,27 @@
#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#if 0 /* test-only */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_IRQ | \
- CFG_CMD_I2C | \
- CFG_CMD_KGDB | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_ELF )
-#else
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM )
-/* test-only: support fehlt bisher... */
-/* CFG_CMD_IDE | \*/
-/* CFG_CMD_PCI | \*/
-#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -204,7 +203,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -268,7 +267,7 @@
*/
#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -290,7 +289,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h
index bc23fc0..48e29a2 100644
--- a/include/configs/CPCI750.h
+++ b/include/configs/CPCI750.h
@@ -133,29 +133,36 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_ALTIVEC /* undef to disable */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
-
-
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_ASKENV \
- | CFG_CMD_I2C \
- | CFG_CMD_CACHE \
- | CFG_CMD_EEPROM \
- | CFG_CMD_PCI \
- | CFG_CMD_ELF \
- | CFG_CMD_DATE \
- | CFG_CMD_NET \
- | CFG_CMD_PING \
- | CFG_CMD_IDE \
- | CFG_CMD_FAT \
- | CFG_CMD_EXT2 \
- )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_DOS_PARTITION
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+
+#define CONFIG_DOS_PARTITION
#define CONFIG_USE_CPCIDVI
@@ -179,7 +186,7 @@
#define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -585,7 +592,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h
index 93d49f3..c7b623a 100644
--- a/include/configs/CPCIISER4.h
+++ b/include/configs/CPCIISER4.h
@@ -54,15 +54,36 @@
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -73,7 +94,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -189,7 +210,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
index 16a9ea5..c589f28 100644
--- a/include/configs/CPU86.h
+++ b/include/configs/CPU86.h
@@ -68,9 +68,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- *
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
@@ -163,27 +161,37 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DOC | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -348,7 +356,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index ce969ec..b087eba 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -69,9 +69,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- *
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
@@ -167,27 +165,31 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
#ifdef CONFIG_PCI
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DOC | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_PCI)
-#else /* ! PCI */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DOC | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C )
-#endif /* CONFIG_PCI */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+ #define CONFIG_CMD_PCI
+#endif
+
#define CFG_NAND_LEGACY
@@ -196,7 +198,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -369,7 +371,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h
index 63d7a92..a965c12 100644
--- a/include/configs/CRAYL1.h
+++ b/include/configs/CRAYL1.h
@@ -75,38 +75,42 @@
#define CONFIG_AUTOSCRIPT 1
-#define CONFIG_COMMANDS (\
- CFG_CMD_BDI|\
- CFG_CMD_IMI|\
- CFG_CMD_FLASH|\
- CFG_CMD_MEMORY|\
- CFG_CMD_NET|\
- CFG_CMD_ENV|\
- CFG_CMD_CONSOLE|\
- CFG_CMD_ASKENV|\
- CFG_CMD_ECHO|\
- CFG_CMD_IMMAP|\
- CFG_CMD_REGINFO|\
- CFG_CMD_DHCP|\
- CFG_CMD_DATE|\
- CFG_CMD_RUN|\
- CFG_CMD_I2C|\
- CFG_CMD_EEPROM|\
- CFG_CMD_DIAG|\
- CFG_CMD_AUTOSCRIPT|\
- CFG_CMD_SETGETDCR)
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_SETGETDCR
+
/*
- * optional BOOTP / DHCP fields
+ * BOOTP options
*/
-#define CONFIG_BOOTP_MASK (\
- CONFIG_BOOTP_VENDOREX|\
- CONFIG_BOOTP_SUBNETMASK|\
- CONFIG_BOOTP_GATEWAY|\
- CONFIG_BOOTP_DNS|\
- CONFIG_BOOTP_HOSTNAME|\
- CONFIG_BOOTP_BOOTFILESIZE|\
- CONFIG_BOOTP_BOOTPATH)
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_VENDOREX
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_BOOTFILESIZE
+
/*
* how many time to fail & restart a net-TFTP before giving up & resetting
@@ -123,9 +127,6 @@
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/CU824.h b/include/configs/CU824.h
index acc8484..68e816a 100644
--- a/include/configs/CU824.h
+++ b/include/configs/CU824.h
@@ -55,21 +55,29 @@
#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */
#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- 0 /* CFG_CMD_DATE */ | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+/*
+ * Command line configuration.
*/
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
/*
@@ -278,7 +286,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/DASA_SIM.h b/include/configs/DASA_SIM.h
index 997e1ba..627ea14 100644
--- a/include/configs/DASA_SIM.h
+++ b/include/configs/DASA_SIM.h
@@ -57,32 +57,35 @@
#define CONFIG_IPADDR 10.0.18.222
#define CONFIG_SERVERIP 10.0.18.190
-#if 0
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_IRQ | \
- CFG_CMD_BSP | \
- CFG_CMD_ASKENV | \
- CFG_CMD_ELF )
-#else
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BSP )
-#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+
#if 0 /* Does not appear to be used?! If it is used, needs to be fixed */
#define CONFIG_SOFT_I2C /* Software I2C support enabled */
#endif
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -184,7 +187,7 @@
*/
#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */
#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h
index bd7aff1..db2e96c 100644
--- a/include/configs/DB64360.h
+++ b/include/configs/DB64360.h
@@ -215,8 +215,16 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_ALTIVEC /* undef to disable */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
/*
* JFFS2 partitions
*
@@ -239,17 +247,20 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
#define MTDPARTS_DEFAULT "mtdparts=db64360-1:-(jffs2)"
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_ASKENV \
- | CFG_CMD_I2C \
- | CFG_CMD_EEPROM \
- | CFG_CMD_CACHE \
- | CFG_CMD_JFFS2 \
- | CFG_CMD_PCI \
- | CFG_CMD_NET )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+
/*
* Miscellaneous configurable options
@@ -261,7 +272,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
/* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -558,7 +569,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h
index 4b72e9b..b5d3f77 100644
--- a/include/configs/DB64460.h
+++ b/include/configs/DB64460.h
@@ -153,8 +153,16 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_ALTIVEC /* undef to disable */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
/*
* JFFS2 partitions
*
@@ -177,17 +185,20 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
#define MTDPARTS_DEFAULT "mtdparts=db64460-1:-(jffs2)"
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_ASKENV \
- | CFG_CMD_I2C \
- | CFG_CMD_EEPROM \
- | CFG_CMD_CACHE \
- | CFG_CMD_JFFS2 \
- | CFG_CMD_PCI \
- | CFG_CMD_NET )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+
/*
* Miscellaneous configurable options
@@ -199,7 +210,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
/* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -496,7 +507,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h
index b58846d..0ddf0e3 100644
--- a/include/configs/DK1C20.h
+++ b/include/configs/DK1C20.h
@@ -446,46 +446,55 @@
#define CONFIG_NIOS_ASMI /* Enable ASMI */
#define CFG_NIOS_ASMIBASE CFG_NIOS_CPU_ASMI0 /* ASMI base address */
-/*------------------------------------------------------------------------
- * COMMANDS
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
- CFG_CMD_ASKENV | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_BMP | \
- CFG_CMD_BSP | \
- CFG_CMD_CACHE | \
- CFG_CMD_DATE | \
- CFG_CMD_DOC | \
- CFG_CMD_DTT | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_FDC | \
- CFG_CMD_FDOS | \
- CFG_CMD_HWFLOW | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_KGDB | \
- CFG_CMD_NAND | \
- CFG_CMD_NFS | \
- CFG_CMD_MMC | \
- CFG_CMD_MII | \
- CFG_CMD_PCI | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_REISER | \
- CFG_CMD_SCSI | \
- CFG_CMD_SPI | \
- CFG_CMD_VFD | \
- CFG_CMD_USB | \
- CFG_CMD_XIMG ) )
-
-
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_ASKENV
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_BMP
+#undef CONFIG_CMD_BSP
+#undef CONFIG_CMD_CACHE
+#undef CONFIG_CMD_DATE
+#undef CONFIG_CMD_DOC
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_FDC
+#undef CONFIG_CMD_FDOS
+#undef CONFIG_CMD_HWFLOW
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_KGDB
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_MMC
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PCI
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_REISER
+#undef CONFIG_CMD_SCSI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_VFD
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_XIMG
+
/*------------------------------------------------------------------------
* COMPACT FLASH
*----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(CONFIG_CMD_IDE)
#define CONFIG_IDE_PREINIT /* Implement id_preinit */
#define CFG_IDE_MAXBUS 1 /* 1 IDE bus */
#define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */
@@ -503,12 +512,12 @@
#define CFG_CF_POWER 0x009209c0 /* CF Power FET PIO base*/
#define CFG_CF_ATASEL 0x009209d0 /* CF ATASEL PIO base */
-#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */
+#endif
/*------------------------------------------------------------------------
* KGDB
*----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 9600
#endif
diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h
index 3e3803c..0032fd3 100644
--- a/include/configs/DK1S10.h
+++ b/include/configs/DK1S10.h
@@ -454,47 +454,55 @@
#endif /* CFG_NIOS_CPU_PIO_NUMS */
-/*------------------------------------------------------------------------
- * COMMANDS
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
- CFG_CMD_ASKENV | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_BMP | \
- CFG_CMD_BSP | \
- CFG_CMD_CACHE | \
- CFG_CMD_DATE | \
- CFG_CMD_DOC | \
- CFG_CMD_DTT | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_FAT | \
- CFG_CMD_FDC | \
- CFG_CMD_FDOS | \
- CFG_CMD_HWFLOW | \
- CFG_CMD_IDE | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_KGDB | \
- CFG_CMD_NAND | \
- CFG_CMD_NFS | \
- CFG_CMD_MMC | \
- CFG_CMD_MII | \
- CFG_CMD_PCI | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_SCSI | \
- CFG_CMD_SPI | \
- CFG_CMD_VFD | \
- CFG_CMD_USB | \
- CFG_CMD_XIMG ) )
-
-
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_ASKENV
+#undef COND_CMD_BEDBUG
+#undef COND_CMD_BMP
+#undef COND_CMD_BSP
+#undef COND_CMD_CACHE
+#undef COND_CMD_DATE
+#undef COND_CMD_DOC
+#undef COND_CMD_DTT
+#undef COND_CMD_EEPROM
+#undef COND_CMD_ELF
+#undef COND_CMD_FAT
+#undef COND_CMD_FDC
+#undef COND_CMD_FDOS
+#undef COND_CMD_HWFLOW
+#undef COND_CMD_IDE
+#undef COND_CMD_I2C
+#undef COND_CMD_JFFS2
+#undef COND_CMD_KGDB
+#undef COND_CMD_NAND
+#undef COND_CMD_NFS
+#undef COND_CMD_MMC
+#undef COND_CMD_MII
+#undef COND_CMD_PCI
+#undef COND_CMD_PCMCIA
+#undef COND_CMD_SCSI
+#undef COND_CMD_SPI
+#undef COND_CMD_VFD
+#undef COND_CMD_USB
+#undef COND_CMD_XIMG
+
/*------------------------------------------------------------------------
* KGDB
*----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 9600
#endif
diff --git a/include/configs/DP405.h b/include/configs/DP405.h
index 2ae794d..2eadbea 100644
--- a/include/configs/DP405.h
+++ b/include/configs/DP405.h
@@ -55,17 +55,29 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BSP | \
- CFG_CMD_DHCP | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -87,7 +99,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -235,7 +247,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/DU405.h b/include/configs/DU405.h
index 5489a53..5c595f5 100644
--- a/include/configs/DU405.h
+++ b/include/configs/DU405.h
@@ -58,21 +58,33 @@
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_IDE | \
- CFG_CMD_ELF | \
- CFG_CMD_MII | \
- CFG_CMD_DATE | \
- CFG_CMD_EEPROM )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MC146818 /* BQ3285 is MC146818 compatible*/
@@ -85,7 +97,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -225,7 +237,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
index 720b335..dae5295 100644
--- a/include/configs/EB+MCF-EV123.h
+++ b/include/configs/EB+MCF-EV123.h
@@ -40,9 +40,8 @@
#define CONFIG_MISC_INIT_R
-#define FEC_ENET
-#define CONFIG_ETHADDR 00:CF:52:82:EB:01
-
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 9600
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
@@ -68,17 +67,61 @@
#define CFG_ENV_IS_IN_FLASH 1
#endif
-/*#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) ) */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADB))
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_LOADB
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
+
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:CF:52:82:EB:01
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* CONFIG_MCFFEC */
#define CONFIG_BOOTDELAY 5
#define CFG_PROMPT "\nEV123 U-Boot> "
#define CFG_LONGHELP /* undef to save memory */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -110,9 +153,6 @@
*/
#define CFG_MBAR 0x40000000
-#define CFG_DISCOVER_PHY
-/* #define CFG_ENET_BD_BASE 0x380000 */
-
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
@@ -139,6 +179,7 @@
#define CFG_FLASH_BASE 0xFFE00000
#define CFG_INT_FLASH_BASE 0xF0000000
+#define CFG_INT_FLASH_ENABLE 0x21
/* If M5282 port is fully implemented the monitor base will be behind
* the vector table. */
diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h
index 2c99b4b..bb77188 100644
--- a/include/configs/ELPPC.h
+++ b/include/configs/ELPPC.h
@@ -66,12 +66,25 @@
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2)
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_JFFS2
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -84,7 +97,7 @@
*/
#define CONFIG_CONS_INDEX 1
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -317,7 +330,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h
index e73bcec..f927a2c 100644
--- a/include/configs/ELPT860.h
+++ b/include/configs/ELPT860.h
@@ -81,7 +81,15 @@
""
#define CONFIG_BOOTCOMMAND "run ramboot"
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
@@ -91,12 +99,15 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+
/*
* Miscellaneous configurable options
@@ -104,7 +115,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -224,7 +235,7 @@
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h
index 5507f35..cfa6335 100644
--- a/include/configs/EP1C20.h
+++ b/include/configs/EP1C20.h
@@ -160,25 +160,36 @@
#define CONFIG_IPADDR 192.168.2.21
#define CONFIG_SERVERIP 192.168.2.16
-/*------------------------------------------------------------------------
- * COMMANDS
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMI | \
- CFG_CMD_IRQ | \
- CFG_CMD_LOADS | \
- CFG_CMD_LOADB | \
- CFG_CMD_MEMORY | \
- CFG_CMD_MISC | \
- CFG_CMD_NET | \
- CFG_CMD_PING | \
- CFG_CMD_RUN | \
- CFG_CMD_SAVES )
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_CONSOLE
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
/*------------------------------------------------------------------------
* MISC
diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h
index 6eca9f2..7c526f7 100644
--- a/include/configs/EP1S10.h
+++ b/include/configs/EP1S10.h
@@ -154,25 +154,35 @@
#define CONFIG_IPADDR 192.168.2.21
#define CONFIG_SERVERIP 192.168.2.16
-/*------------------------------------------------------------------------
- * COMMANDS
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMI | \
- CFG_CMD_IRQ | \
- CFG_CMD_LOADS | \
- CFG_CMD_LOADB | \
- CFG_CMD_MEMORY | \
- CFG_CMD_MISC | \
- CFG_CMD_NET | \
- CFG_CMD_PING | \
- CFG_CMD_RUN | \
- CFG_CMD_SAVES )
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVES
+
/*------------------------------------------------------------------------
* MISC
diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h
index 976e79a..1fe8f68 100644
--- a/include/configs/EP1S40.h
+++ b/include/configs/EP1S40.h
@@ -154,25 +154,35 @@
#define CONFIG_IPADDR 192.168.2.21
#define CONFIG_SERVERIP 192.168.2.16
-/*------------------------------------------------------------------------
- * COMMANDS
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMI | \
- CFG_CMD_IRQ | \
- CFG_CMD_LOADS | \
- CFG_CMD_LOADB | \
- CFG_CMD_MEMORY | \
- CFG_CMD_MISC | \
- CFG_CMD_NET | \
- CFG_CMD_PING | \
- CFG_CMD_RUN | \
- CFG_CMD_SAVES )
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVES
+
/*------------------------------------------------------------------------
* MISC
diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h
index 738763b..89e0eeb 100644
--- a/include/configs/EP88x.h
+++ b/include/configs/EP88x.h
@@ -50,15 +50,25 @@
#define CFG_8xx_CPUCLK_MIN 40000000
#define CFG_8xx_CPUCLK_MAX 133000000
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_DHCP \
- | CFG_CMD_IMMAP \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- )
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm fe060000" /* Autoboot command */
diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h
index c203aea..5d48d2b 100644
--- a/include/configs/ERIC.h
+++ b/include/configs/ERIC.h
@@ -96,23 +96,26 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH)
/*
- * #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | \
- * CFG_CMD_KGDB | CFG_CMD_I2C | CFG_CMD_EEPROM | \
- * CFG_CMD_ENV | CFG_CMD_FLASH)
+ * BOOTP options
*/
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-/* CFG_CMD_ENV est definie */
-/* ((CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_KGDB) & ~(CFG_CMD_ENV))
+
+/*
+ * Command line configuration.
*/
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -121,7 +124,7 @@
*/
#undef CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -325,7 +328,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -365,7 +368,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/ESTEEM192E.h b/include/configs/ESTEEM192E.h
index b176c6f..66e1203 100644
--- a/include/configs/ESTEEM192E.h
+++ b/include/configs/ESTEEM192E.h
@@ -70,10 +70,21 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "BOOT: " /* Monitor Command Prompt */
diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h
index d55eb7d..ed439b1 100644
--- a/include/configs/ETX094.h
+++ b/include/configs/ETX094.h
@@ -82,17 +82,29 @@
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -179,7 +191,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h
index 78e5716..1c44a0c 100644
--- a/include/configs/EVB64260.h
+++ b/include/configs/EVB64260.h
@@ -103,21 +103,30 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_ALTIVEC /* undef to disable */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ASKENV)
+#define CONFIG_CMD_ASKENV
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -391,7 +400,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h
index d85be42..a3f38bb 100644
--- a/include/configs/EXBITGEN.h
+++ b/include/configs/EXBITGEN.h
@@ -82,10 +82,21 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -94,7 +105,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -206,7 +217,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h
index 1b562d6..f810af2 100644
--- a/include/configs/FADS823.h
+++ b/include/configs/FADS823.h
@@ -46,7 +46,6 @@
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
-/*Now included by CFG_CMD_PCMCIA */
/*#define CONFIG_PCMCIA 1 / * To enable PCMCIA support */
/* Video related */
@@ -105,17 +104,39 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NISDOMAIN
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_TIMEOFFSET
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT ":>" /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -185,12 +206,13 @@
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h
index 2a986f0..a09c0e0 100644
--- a/include/configs/FADS850SAR.h
+++ b/include/configs/FADS850SAR.h
@@ -61,15 +61,28 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
/*
* Miscellaneous configurable options
*/
#undef CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT ":>" /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -143,12 +156,13 @@
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/FLAGADM.h b/include/configs/FLAGADM.h
index 8babee1..431844c 100644
--- a/include/configs/FLAGADM.h
+++ b/include/configs/FLAGADM.h
@@ -62,21 +62,39 @@
/*#define CONFIG_WATCHDOG*/ /* watchdog enabled */
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
-#define CONFIG_COMMANDS (CFG_CMD_BDI | CFG_CMD_IMI | CFG_CMD_CACHE | \
- CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_LOADS | \
- CFG_CMD_ENV | CFG_CMD_REGINFO | CFG_CMD_IMMAP | CFG_CMD_NET)
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_NET
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "EEG> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -152,7 +170,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h
index 0dd21bc..3b0ddb4 100644
--- a/include/configs/FPS850L.h
+++ b/include/configs/FPS850L.h
@@ -39,45 +39,90 @@
#undef CONFIG_8xx_CONS_SMC1
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 19200
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_BOOTCOMMAND "bootm 40020000" /* autoboot command */
+#define CONFIG_BAUDRATE 115200
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
+#define CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOARD_TYPES 1 /* support board types */
-#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
- "nfsaddrs=10.0.0.99:10.0.0.2"
+#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
+ "rootpath=/opt/eldk/ppc_8xx\0" \
+ "bootfile=/tftpboot/fps850L/uImage\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NISDOMAIN
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_TIMEOFFSET
+
+#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~( \
- CFG_CMD_CONSOLE | \
- CFG_CMD_BDI | \
- CFG_CMD_LOADS | \
- CFG_CMD_LOADB | \
- CFG_CMD_CACHE ) )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -160,7 +205,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h
index 423d74e..6fec075 100644
--- a/include/configs/FPS860L.h
+++ b/include/configs/FPS860L.h
@@ -40,44 +40,89 @@
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 115200
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_BOOTCOMMAND "bootm 40040000" /* autoboot command */
#define CONFIG_BOARD_TYPES 1 /* support board types */
-#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
- "nfsaddrs=10.0.0.99:10.0.0.2"
+#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
+ "rootpath=/opt/eldk/ppc_8xx\0" \
+ "bootfile=/tftpboot/fps850L/uImage\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NISDOMAIN
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_TIMEOFFSET
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -160,7 +205,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/G2000.h b/include/configs/G2000.h
index db42fd0..9c713c6 100644
--- a/include/configs/G2000.h
+++ b/include/configs/G2000.h
@@ -88,20 +88,32 @@
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
#endif
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_BSP | \
- CFG_CMD_EEPROM )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -120,7 +132,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -324,7 +336,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h
index 6613f90..bfbf3a8 100644
--- a/include/configs/GEN860T.h
+++ b/include/configs/GEN860T.h
@@ -132,9 +132,12 @@
/*
* BOOTP options
*/
-#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE \
- )
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
/*
* The GEN860T network interface uses the on-chip 10/100 FEC with
@@ -222,35 +225,30 @@
CFG_POST_UART | \
CFG_POST_SPR )
-#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
-#else
-#define CFG_CMD_POST_DIAG 0
-#endif
/*
- * List of available monitor commands. Use the system default list
- * plus add some of the "non-standard" commands back in.
- * See ./cmd_confdefs.h
- */
-#define BASE_CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_REGINFO | \
- CFG_CMD_IMMAP | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_FPGA | \
- CFG_CMD_MII | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_POST_DIAG )
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_BEDBUG
#if !defined(CONFIG_SC)
-#define CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC )
-#else
-#define CONFIG_COMMANDS BASE_CONFIG_COMMANDS
+ #define CONFIG_CMD_DOC
+#endif
+
+#ifdef CONFIG_POST
+#define CONFIG_CMD_DIAG
#endif
/*
@@ -279,11 +277,6 @@
#define CFG_FPGA_PROG_FEEDBACK
-/************************************************************************
- * This must be included AFTER the definition of any CONFIG_COMMANDS
- */
-#include <cmd_confdefs.h>
-
#define CFG_NAND_LEGACY
/*
@@ -306,7 +299,7 @@
/*
* Set buffer size for console I/O
*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024
#else
#define CFG_CBSIZE 256
@@ -471,7 +464,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of above value */
#endif
diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h
index 8c01d97..785355a 100644
--- a/include/configs/GENIETV.h
+++ b/include/configs/GENIETV.h
@@ -105,15 +105,28 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT ":>" /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -193,7 +206,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/GTH.h b/include/configs/GTH.h
index 03b9659..79f5714 100644
--- a/include/configs/GTH.h
+++ b/include/configs/GTH.h
@@ -97,18 +97,32 @@
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
#endif
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE)
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IDE
+
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_PROMPT "=>" /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -190,7 +204,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index dc40ebc..8967b3f 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -98,26 +98,40 @@
#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
#define CFG_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */
-#define ADD_BMP_CMD CFG_CMD_BMP
-#else
-#define ADD_BMP_CMD 0
#endif /* CONFIG_VIDEO */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_EXT2 | \
- CFG_CMD_ELF | \
- CFG_CMD_NAND | \
- CFG_CMD_I2C | \
- CFG_CMD_DATE | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- ADD_BMP_CMD | \
- CFG_CMD_EEPROM )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#endif
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -127,11 +141,6 @@
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
#undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
-
#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -148,7 +157,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -198,36 +207,18 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
@@ -377,7 +368,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h
index 6864740..26dd954 100644
--- a/include/configs/HIDDEN_DRAGON.h
+++ b/include/configs/HIDDEN_DRAGON.h
@@ -52,16 +52,27 @@
#define CONFIG_BAUDRATE 9600
#define CONFIG_DRAM_SPEED 100 /* MHz */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_NET | \
- CFG_CMD_PCI | \
- CFG_CMD_PING )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
/*
* Miscellaneous configurable options
@@ -363,7 +374,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/HMI10.h b/include/configs/HMI10.h
index 7cce876..02ae5d0 100644
--- a/include/configs/HMI10.h
+++ b/include/configs/HMI10.h
@@ -117,7 +117,15 @@
#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -125,31 +133,25 @@
#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
#ifdef CONFIG_SPLASH_SCREEN
-# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BMP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#else
-# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+ #define CONFIG_CMD_BMP
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -164,7 +166,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -247,7 +249,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
index f84e356..1ff7108 100644
--- a/include/configs/HUB405.h
+++ b/include/configs/HUB405.h
@@ -60,18 +60,30 @@
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_NAND | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -88,7 +100,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -135,38 +147,18 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
@@ -271,7 +263,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h
index 35d84ae..bd0894c 100644
--- a/include/configs/IAD210.h
+++ b/include/configs/IAD210.h
@@ -84,7 +84,15 @@
/* #define CONFIG_STATUS_LED 1*/ /* Status LED enabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
# undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
# define CONFIG_FEC_ENET 1 /* use FEC ethernet */
@@ -123,20 +131,23 @@
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -217,7 +228,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h
index cd17935..da54cef 100644
--- a/include/configs/ICU862.h
+++ b/include/configs/ICU862.h
@@ -81,7 +81,15 @@
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
@@ -123,25 +131,28 @@
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -223,12 +234,13 @@
#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */
#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
index 29eb874..85d2bb3 100644
--- a/include/configs/IDS8247.h
+++ b/include/configs/IDS8247.h
@@ -128,9 +128,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- *
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
@@ -159,24 +157,34 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_NFS | \
- CFG_CMD_NAND | \
- CFG_CMD_I2C | \
- CFG_CMD_SNTP )
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SNTP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -234,7 +242,7 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if defined(CONFIG_CMD_NAND)
#define CFG_NAND_LEGACY
#define CFG_NAND0_BASE 0xE1000000
@@ -295,7 +303,7 @@
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0)))
-#endif /* CFG_CMD_NAND */
+#endif /* CONFIG_CMD_NAND */
/*-----------------------------------------------------------------------
* Hard Reset Configuration Words
@@ -355,7 +363,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -474,7 +482,7 @@
#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\
ORxG_SCY_6_CLK )
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if defined(CONFIG_CMD_NAND)
/* Bank 1 - NAND Flash
*/
#define CFG_NAND_BASE CFG_NAND0_BASE
diff --git a/include/configs/IP860.h b/include/configs/IP860.h
index 0e20e56..bd961d8 100644
--- a/include/configs/IP860.h
+++ b/include/configs/IP860.h
@@ -88,28 +88,32 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-
-/*----------------------------------------------------------------------*/
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
-/*----------------------------------------------------------------------*/
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -202,7 +206,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h
index c1565fc..6fee455 100644
--- a/include/configs/IPHASE4539.h
+++ b/include/configs/IPHASE4539.h
@@ -67,8 +67,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
@@ -95,7 +94,14 @@
#define CONFIG_8260_CLKIN 66666666 /* in Hz */
#define CONFIG_BAUDRATE 19200
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
/*
* select i2c support configuration
@@ -124,17 +130,18 @@
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
#endif /* CONFIG_SOFT_I2C */
-#define CONFIG_COMMANDS CONFIG_CMD_DFL
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/ram rw"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -149,7 +156,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -257,7 +264,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h
index 706bdb9..965b515 100644
--- a/include/configs/ISPAN.h
+++ b/include/configs/ISPAN.h
@@ -58,8 +58,7 @@
* for FCC).
*
* If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
- * be defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */
#define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */
@@ -106,17 +105,28 @@
#define CONFIG_8260_CLKIN 65536000 /* in Hz */
#define CONFIG_BAUDRATE 38400
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \
- | CFG_CMD_ASKENV \
- | CFG_CMD_DHCP \
- | CFG_CMD_IMMAP \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- | CFG_CMD_REGINFO \
- )
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */
diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h
index a0cb1dd..1142f2a 100644
--- a/include/configs/IVML24.h
+++ b/include/configs/IVML24.h
@@ -72,24 +72,33 @@
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE)
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IDE
+
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-#define CONFIG_BOOTP_MASK \
- ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-/*----------------------------------------------------------------------*/
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -182,7 +191,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h
index 46b4d53..bd19dad 100644
--- a/include/configs/IVMS8.h
+++ b/include/configs/IVMS8.h
@@ -72,24 +72,32 @@
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE)
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IDE
+
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-#define CONFIG_BOOTP_MASK \
- ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-/*----------------------------------------------------------------------*/
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -179,7 +187,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index 5988112..4c16d22 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -37,11 +37,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -69,7 +64,6 @@
#define CONFIG_PCI_IO_BUS 0x50000000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
-#define ADD_PCI_CMD CFG_CMD_PCI
#endif
#define CFG_XLB_PIPELINING 1
@@ -80,11 +74,8 @@
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
-#else /* MPC5100 */
-
+#else
#define CONFIG_MII 1
-#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
-
#endif
/* Partitions */
@@ -93,31 +84,44 @@
#define CONFIG_ISO_PARTITION
/* USB */
-#if 1
-#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD 0
-#endif
+#define CFG_OHCI_BE_CONTROLLER
+#undef CFG_USB_OHCI_BOARD_INIT
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE MPC5XXX_USB
+#define CFG_USB_OHCI_SLOT_NAME "mpc5200"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_EEPROM | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP | \
- ADD_PCI_CMD | \
- ADD_USB_CMD )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CFG_LOWBOOT 1
@@ -167,19 +171,16 @@
* IPB Bus clocking configuration.
*/
#if defined(CONFIG_LITE5200B)
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#else
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
#endif /* CONFIG_MPC5200 */
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,5200@0"
#define OF_SOC "soc5200@f0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
@@ -312,7 +313,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -328,6 +329,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/JSE.h b/include/configs/JSE.h
index ccd1f19..ea3b0b4 100644
--- a/include/configs/JSE.h
+++ b/include/configs/JSE.h
@@ -49,6 +49,7 @@
/* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
#define CONFIG_SYSTEMACE 1
#define CFG_SYSTEMACE_BASE 0xf0000000
+#define CFG_SYSTEMACE_WIDTH 8
#define CONFIG_DOS_PARTITION 1
/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
@@ -134,20 +135,32 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_FAT | \
- CFG_CMD_FLASH | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_PCI | \
- CFG_CMD_PING )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
/* watchdog disabled */
#undef CONFIG_WATCHDOG
@@ -166,7 +179,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -271,7 +284,7 @@
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405GPr CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -297,7 +310,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h
index 2ad6f06..3644e43 100644
--- a/include/configs/KAREF.h
+++ b/include/configs/KAREF.h
@@ -38,6 +38,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */
#define CONFIG_440GX 1 /* Specifc GX support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
@@ -177,23 +178,34 @@
#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
-/*-----------------------------------------------------------------------
- * Console/Commands/Parser
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_I2C | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_PING | \
- CFG_CMD_DIAG | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_ELF | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+
/* Include NetConsole support */
#define CONFIG_NETCONSOLE
@@ -202,10 +214,6 @@
#define CONFIG_AUTO_COMPLETE 1
#define CFG_ALT_MEMTEST 1 /* use real memory test */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "KaRefDes=> " /* Monitor Command Prompt */
@@ -216,7 +224,7 @@
/*-----------------------------------------------------------------------
* Console Buffer
*----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -262,7 +270,6 @@
#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE)
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/
#define CFG_PCI_TARGET_INIT /* let board init pci target*/
#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
@@ -279,7 +286,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
#endif
@@ -291,7 +298,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
#endif
diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h
index 9b950fc..f6c31ea 100644
--- a/include/configs/KUP4K.h
+++ b/include/configs/KUP4K.h
@@ -89,7 +89,15 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -156,32 +164,31 @@
#define CONFIG_POST (CFG_POST_CPU | \
CFG_POST_RTC | \
CFG_POST_I2C)
-
-#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
-#else
-#define CFG_CMD_POST_DIAG 0
-#endif
#endif
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+#ifdef CONFIG_POST
+ #define CONFIG_CMD_DIAG
+#endif
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -269,7 +276,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h
index cd38b0f..e558aa4 100644
--- a/include/configs/KUP4X.h
+++ b/include/configs/KUP4X.h
@@ -99,7 +99,15 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -167,34 +175,33 @@
#define CONFIG_POST (CFG_POST_CPU | \
CFG_POST_RTC | \
CFG_POST_I2C)
-
-#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
-#else
-#define CFG_CMD_POST_DIAG 0
-#endif
#endif
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_SNTP | \
- CFG_CMD_USB )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_POST
+ #define CONFIG_CMD_DIAG
+#endif
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -281,7 +288,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h
index e44f1cc..46edd08 100644
--- a/include/configs/LANTEC.h
+++ b/include/configs/LANTEC.h
@@ -74,64 +74,68 @@
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_CMD_MINIMAL 0
-#define CONFIG_CMD_TINY (CFG_CMD_FLASH | \
- CFG_CMD_MEMORY | \
- CFG_CMD_LOADS | \
- CFG_CMD_LOADB)
-#define CONFIG_CMD_NORMAL (CONFIG_CMD_DFL & ~CFG_CMD_BOOTD & ~CFG_CMD_REISER)
-#define CONFIG_CMD_GDB (CONFIG_CMD_NORMAL | CFG_CMD_KGDB)
-#define CONFIG_CMD_FULL (CFG_CMD_ALL & ~CFG_CMD_BEDBUG \
- & ~CFG_CMD_BMP \
- & ~CFG_CMD_BSP \
- & ~CFG_CMD_DISPLAY \
- & ~CFG_CMD_DOC \
- & ~CFG_CMD_DTT \
- & ~CFG_CMD_EEPROM \
- & ~CFG_CMD_ELF \
- & ~CFG_CMD_EXT2 \
- & ~CFG_CMD_FDC \
- & ~CFG_CMD_FDOS \
- & ~CFG_CMD_HWFLOW \
- & ~CFG_CMD_I2C \
- & ~CFG_CMD_IDE \
- & ~CFG_CMD_IRQ \
- & ~CFG_CMD_JFFS2 \
- & ~CFG_CMD_KGDB \
- & ~CFG_CMD_MII \
- & ~CFG_CMD_MMC \
- & ~CFG_CMD_NAND \
- & ~CFG_CMD_PCI \
- & ~CFG_CMD_PCMCIA \
- & ~CFG_CMD_REISER \
- & ~CFG_CMD_SCSI \
- & ~CFG_CMD_SPI \
- & ~CFG_CMD_UNIVERSE\
- & ~CFG_CMD_USB \
- & ~CFG_CMD_VFD \
- & ~CFG_CMD_XIMG )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-#if CONFIG_LANTEC >= 2
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_BMP
+#undef CONFIG_CMD_BSP
+#undef CONFIG_CMD_DISPLAY
+#undef CONFIG_CMD_DOC
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_EXT2
+#undef CONFIG_CMD_FDC
+#undef CONFIG_CMD_FDOS
+#undef CONFIG_CMD_HWFLOW
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_IRQ
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_KGDB
+#undef CONFIG_CMD_MFSL
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_MMC
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_PCI
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_REISER
+#undef CONFIG_CMD_SCSI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_UNIVERSE
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_VFD
+#undef CONFIG_CMD_XIMG
+
+#if !(CONFIG_LANTEC >= 2)
+ #undef CONFIG_CMD_DATE
+ #undef CONFIG_CMD_NET
#endif
+
#if CONFIG_LANTEC >= 2
-# define CONFIG_COMMANDS CONFIG_CMD_FULL
-#else
-# define CONFIG_COMMANDS (CONFIG_CMD_FULL & ~CFG_CMD_DATE & ~CFG_CMD_NET)
+#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -203,7 +207,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
new file mode 100644
index 0000000..7f544c8
--- /dev/null
+++ b/include/configs/M5235EVB.h
@@ -0,0 +1,261 @@
+/*
+ * Configuation settings for the Freescale MCF5329 FireEngine board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5235EVB_H
+#define _M5235EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF523x /* define processor family */
+#define CONFIG_M5235 /* define processor type */
+
+#undef DEBUG
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 80000
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x00000300
+#define CFG_IMMR CFG_MBAR
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
+#define CONFIG_BOOTFILE "u-boot.bin"
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* FEC_ENET */
+
+#define CONFIG_HOSTNAME M5235EVB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=10000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off ffe00000 ffe3ffff;" \
+ "era ffe00000 ffe3ffff;" \
+ "cp.b ${loadaddr} ffe00000 ${filesize};"\
+ "save\0" \
+ ""
+
+#define CONFIG_PRAM 512 /* 512 KB */
+#define CFG_PROMPT "-> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#if defined(CONFIG_KGDB)
+# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE+0x20000)
+
+#define CFG_HZ 1000
+#define CFG_CLK 75000000
+#define CFG_CPU_CLK CFG_CLK * 2
+
+#define CFG_MBAR 0x40000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR 0x20000000
+#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
+#define CFG_INIT_RAM_CTRL 0x21
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE - 0x10)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+
+#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
+#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
+
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+
+#define CFG_BOOTPARAMS_LEN 64*1024
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+# define CFG_FLASH_CFI_DRIVER 1
+# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
+#ifdef NORFLASH_PS32BIT
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
+#else
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#endif
+# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+#endif
+
+#define CFG_FLASH_BASE (CFG_CS0_BASE << 16)
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_IS_EMBEDDED 1
+#ifdef NORFLASH_PS32BIT
+# define CFG_ENV_OFFSET (0x8000)
+# define CFG_ENV_SIZE 0x4000
+# define CFG_ENV_SECT_SIZE 0x4000
+#else
+# define CFG_ENV_OFFSET (0x4000)
+# define CFG_ENV_SIZE 0x2000
+# define CFG_ENV_SECT_SIZE 0x2000
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ * CS6 - Available
+ * CS7 - Available
+ */
+#ifdef NORFLASH_PS32BIT
+# define CFG_CS0_BASE 0xFFC0
+# define CFG_CS0_MASK 0x003f0001
+# define CFG_CS0_CTRL 0x1D00
+#else
+# define CFG_CS0_BASE 0xFFE0
+# define CFG_CS0_MASK 0x001f0001
+# define CFG_CS0_CTRL 0x1D80
+#endif
+
+#endif /* _M5329EVB_H */
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
new file mode 100644
index 0000000..de7ea42
--- /dev/null
+++ b/include/configs/M5249EVB.h
@@ -0,0 +1,194 @@
+/*
+ * Configuation settings for the esd TASREG board.
+ *
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5249EVB_H
+#define _M5249EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF52x2 /* define processor family */
+#define CONFIG_M5249 /* define processor type */
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
+#define CONFIG_BAUDRATE 19200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+
+#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
+
+/*
+ * BOOTP options
+ */
+#undef CONFIG_BOOTP_BOOTFILESIZE
+#undef CONFIG_BOOTP_BOOTPATH
+#undef CONFIG_BOOTP_GATEWAY
+#undef CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_NET
+
+#define CFG_PROMPT "=> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
+#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup */
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+
+#define CFG_LOAD_ADDR 0x200000 /* default load address */
+
+#define CFG_MEMTEST_START 0x400
+#define CFG_MEMTEST_END 0x380000
+
+#define CFG_HZ 1000
+
+/*
+ * Clock configuration: enable only one of the following options
+ */
+
+#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */
+#define CFG_FAST_CLK 1 /* MCF5249 can run at 140MHz */
+#define CFG_CLK 132025600 /* MCF5249 can run at 140MHz */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_MBAR 0x10000000 /* Register Base Addrs */
+#define CFG_MBAR2 0x80000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR 0x20000000
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_FLASH_BASE (CFG_CSAR0 << 16)
+
+#if 0 /* test-only */
+#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
+#endif
+
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+
+#define CFG_MONITOR_LEN 0x20000
+#define CFG_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */
+#define CFG_BOOTPARAMS_LEN 64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+
+# define CFG_FLASH_CFI_DRIVER 1
+# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+# define CFG_FLASH_CHECKSUM
+# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+
+/* CS0 - AMD Flash, address 0xffc00000 */
+#define CFG_CSAR0 0xffe0
+#define CFG_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */
+/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
+#define CFG_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
+
+/* CS1 - FPGA, address 0xe0000000 */
+#define CFG_CSAR1 0xe000
+#define CFG_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */
+#define CFG_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
+#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
+#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */
+#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */
+#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */
+#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
+#define CFG_GPIO1_LED 0x00400000 /* user led */
+
+#endif /* M5249 */
diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
new file mode 100644
index 0000000..48170e7
--- /dev/null
+++ b/include/configs/M5253EVBE.h
@@ -0,0 +1,212 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _M5253EVBE_H
+#define _M5253EVBE_H
+
+#define CONFIG_MCF52x2 /* define processor family */
+#define CONFIG_M5253 /* define processor type */
+#define CONFIG_M5253EVBE /* define board type */
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
+#define CONFIG_BAUDRATE 19200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG /* disable watchdog */
+
+#define CONFIG_BOOTDELAY 5
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CFG_ENV_OFFSET 0x4000
+#define CFG_ENV_SECT_SIZE 0x2000
+#define CFG_ENV_IS_IN_FLASH 1
+#else
+#define CFG_ENV_ADDR 0xffe04000
+#define CFG_ENV_SECT_SIZE 0x2000
+#define CFG_ENV_IS_IN_FLASH 1
+#endif
+
+/*
+ * BOOTP options
+ */
+#undef CONFIG_BOOTP_BOOTFILESIZE
+#undef CONFIG_BOOTP_BOOTPATH
+#undef CONFIG_BOOTP_GATEWAY
+#undef CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_NET
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+
+/* ATA */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_IDE_RESET 1
+#define CONFIG_IDE_PREINIT 1
+#define CONFIG_ATAPI
+#undef CONFIG_LBA48
+
+#define CFG_IDE_MAXBUS 1
+#define CFG_IDE_MAXDEVICE 2
+
+#define CFG_ATA_BASE_ADDR (CFG_MBAR2 + 0x800)
+#define CFG_ATA_IDE0_OFFSET 0
+
+#define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
+#define CFG_ATA_STRIDE 4 /* Interval between registers */
+#define _IO_BASE 0
+
+#define CFG_PROMPT "=> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_LOAD_ADDR 0x00100000
+
+#define CFG_MEMTEST_START 0x400
+#define CFG_MEMTEST_END 0x380000
+
+#define CFG_HZ 1000
+
+#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */
+#define CFG_FAST_CLK
+#ifdef CFG_FAST_CLK
+# define CFG_PLLCR 0x1243E054
+# define CFG_CLK 140000000
+#else
+# define CFG_PLLCR 0x135a4140
+# define CFG_CLK 70000000
+#endif
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_MBAR 0x10000000 /* Register Base Addrs */
+#define CFG_MBAR2 0x80000000 /* Module Base Addrs 2 */
+
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR 0x20000000
+#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CFG_MONITOR_BASE 0x20000
+#else
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+#endif
+
+#define CFG_MONITOR_LEN 0x40000
+#define CFG_MALLOC_LEN (256 << 10)
+#define CFG_BOOTPARAMS_LEN (64*1024)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/* FLASH organization */
+#define CFG_FLASH_BASE 0xffe00000
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
+#define CFG_FLASH_ERASE_TOUT 1000
+
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#define CFG_FLASH_SIZE 0x200000
+#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+
+/* Cache Configuration */
+#define CFG_CACHELINE_SIZE 16
+
+/* Port configuration */
+#define CFG_FECI2C 0xF0
+
+#define CFG_CSAR0 0xFFE0
+#define CFG_CSMR0 0x001F0021
+#define CFG_CSCR0 0x1D80
+
+#define CFG_CSAR1 0
+#define CFG_CSMR1 0
+#define CFG_CSCR1 0
+
+#define CFG_CSAR2 0
+#define CFG_CSMR2 0
+#define CFG_CSCR2 0
+
+#define CFG_CSAR3 0
+#define CFG_CSMR3 0
+#define CFG_CSCR3 0
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
+#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
+#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */
+#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */
+#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */
+#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
+#define CFG_GPIO1_LED 0x00400000 /* user led */
+
+#endif /* _M5253EVB_H */
diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h
index f0fc013..798ec0c 100644
--- a/include/configs/M5271EVB.h
+++ b/include/configs/M5271EVB.h
@@ -31,7 +31,6 @@
#ifndef _M5271EVB_H
#define _M5271EVB_H
-#define DEBUG
#undef DEBUG
/*
@@ -41,46 +40,119 @@
#define CONFIG_M5271 /* define processor type */
#define CONFIG_M5271EVB /* define board type */
-#define CONFIG_IPADDR 192.168.30.1
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_ETHADDR 00:06:3b:01:41:55
+#define CONFIG_MCFTMR
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG /* disable watchdog */
-#define CONFIG_BOOTDELAY 5
-
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CFG_ENV_OFFSET 0x4000
-#define CFG_ENV_SECT_SIZE 0x2000
-#define CFG_ENV_IS_IN_FLASH 1
#else
#define CFG_ENV_ADDR 0xffe04000
+#endif
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
-#endif
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_NET ) & ~(CFG_CMD_LOADS | CFG_CMD_LOADB))
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 80000
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x00000300
+#define CFG_IMMR CFG_MBAR
+
+#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
+#define CONFIG_BOOTFILE "u-boot.bin"
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_RETRY_COUNT 5
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* FEC_ENET */
+
+#define CONFIG_HOSTNAME M5235EVB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=10000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off ffe00000 ffe2ffff;" \
+ "era ffe00000 ffe2ffff;" \
+ "cp.b ${loadaddr} 0 ${filesize};" \
+ "save\0" \
+ ""
#define CFG_PROMPT "=> "
-#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LONGHELP /* undef to save memory */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x00100000
@@ -98,16 +170,11 @@
#define CFG_MBAR 0x40000000 /* Register Base Addrs */
-/* Enable FEC ethernet */
-#define FEC_ENET
-#define CONFIG_NET_RETRY_COUNT 5
-#define CFG_ENET_BD_BASE 0x480000
-
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
-#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -118,7 +185,7 @@
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_FLASH_BASE 0xffe00000
#ifdef CONFIG_MONITOR_IS_IN_RAM
@@ -136,11 +203,11 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/* FLASH organization */
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 1000
#define CFG_FLASH_CFI 1
@@ -153,4 +220,4 @@
/* Port configuration */
#define CFG_FECI2C 0xF0
-#endif /* _M5271EVB_H */
+#endif /* _M5271EVB_H */
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index 5fd6a95..2b8734b 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -33,18 +33,20 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_MCF52x2 /* define processor family */
-#define CONFIG_M5272 /* define processor type */
+#define CONFIG_MCF52x2 /* define processor family */
+#define CONFIG_M5272 /* define processor type */
-#define FEC_ENET
+#define CONFIG_MCFTMR
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
-#define CONFIG_WATCHDOG
+#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
-#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
+#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -60,30 +62,90 @@
#define CFG_ENV_IS_IN_FLASH 1
#endif
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) | \
- CFG_CMD_MII)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 5
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
+
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* CONFIG_MCFFEC */
+
+#define CONFIG_HOSTNAME M5272C3
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=10000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off ffe00000 ffe3ffff;" \
+ "era ffe00000 ffe3ffff;" \
+ "cp.b ${loadaddr} ffe00000 ${filesize};"\
+ "save\0" \
+ ""
#define CFG_PROMPT "-> "
-#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LONGHELP /* undef to save memory */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x20000
-
#define CFG_MEMTEST_START 0x400
#define CFG_MEMTEST_END 0x380000
-
#define CFG_HZ 1000
#define CFG_CLK 66000000
@@ -92,20 +154,15 @@
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
-
#define CFG_MBAR 0x10000000 /* Register Base Addrs */
-
#define CFG_SCR 0x0003;
#define CFG_SPR 0xffff;
-#define CFG_DISCOVER_PHY
-#define CFG_ENET_BD_BASE 0x380000
-
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
-#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -116,7 +173,7 @@
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */
+#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */
#define CFG_FLASH_BASE 0xffe00000
#ifdef CONFIG_MONITOR_IS_IN_RAM
@@ -134,13 +191,13 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 1000
/*-----------------------------------------------------------------------
@@ -153,25 +210,18 @@
*/
#define CFG_BR0_PRELIM 0xFFE00201
#define CFG_OR0_PRELIM 0xFFE00014
-
#define CFG_BR1_PRELIM 0
#define CFG_OR1_PRELIM 0
-
#define CFG_BR2_PRELIM 0x30000001
#define CFG_OR2_PRELIM 0xFFF80000
-
#define CFG_BR3_PRELIM 0
#define CFG_OR3_PRELIM 0
-
#define CFG_BR4_PRELIM 0
#define CFG_OR4_PRELIM 0
-
#define CFG_BR5_PRELIM 0
#define CFG_OR5_PRELIM 0
-
#define CFG_BR6_PRELIM 0
#define CFG_OR6_PRELIM 0
-
#define CFG_BR7_PRELIM 0x00000701
#define CFG_OR7_PRELIM 0xFFC0007C
@@ -181,9 +231,8 @@
#define CFG_PACNT 0x00000000
#define CFG_PADDR 0x0000
#define CFG_PADAT 0x0000
-#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */
+#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */
#define CFG_PBDDR 0x0000
#define CFG_PBDAT 0x0000
#define CFG_PDCNT 0x00000000
-
-#endif /* _M5272C3_H */
+#endif /* _M5272C3_H */
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index cbb3e3b..3c17c1e 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -33,15 +33,17 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_MCF52x2 /* define processor family */
-#define CONFIG_M5282 /* define processor type */
+#define CONFIG_MCF52x2 /* define processor family */
+#define CONFIG_M5282 /* define processor type */
-#define FEC_ENET
+#define CONFIG_MCFTMR
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
-#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
+#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -50,24 +52,81 @@
#define CFG_ENV_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 5
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* CONFIG_MCFFEC */
+
+#define CONFIG_HOSTNAME M5272C3
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=10000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off ffe00000 ffe3ffff;" \
+ "era ffe00000 ffe3ffff;" \
+ "cp.b ${loadaddr} ffe00000 ${filesize};"\
+ "save\0" \
+ ""
#define CFG_PROMPT "-> "
-#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LONGHELP /* undef to save memory */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x20000
@@ -77,6 +136,10 @@
#define CFG_HZ 1000000
#define CFG_CLK 64000000
+/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
+
+#define CFG_MFD 0x02 /* PLL Multiplication Factor Devider */
+#define CFG_RFD 0x00 /* PLL Reduce Frecuency Devider */
/*
* Low Level Configuration Settings
@@ -85,15 +148,12 @@
*/
#define CFG_MBAR 0x40000000
-#undef CFG_DISCOVER_PHY
-#define CFG_ENET_BD_BASE 0x380000
-
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CFG_INIT_RAM_ADDR 0x20000000
-#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
-#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_RAM_ADDR 0x20000000
+#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -103,49 +163,88 @@
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */
+#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */
#define CFG_FLASH_BASE 0xffe00000
#define CFG_INT_FLASH_BASE 0xf0000000
+#define CFG_INT_FLASH_ENABLE 0x21
/* If M5282 port is fully implemented the monitor base will be behind
* the vector table. */
-/* #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) */
-#define CFG_MONITOR_BASE 0x20000
+#if (TEXT_BASE != CFG_INT_FLASH_BASE)
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+#else
+#define CFG_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
+#endif
#define CFG_MONITOR_LEN 0x20000
#define CFG_MALLOC_LEN (256 << 10)
#define CFG_BOOTPARAMS_LEN 64*1024
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_SECT 35
-#define CFG_MAX_FLASH_BANKS 1
-#define CFG_FLASH_ERASE_TOUT 10000000
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+
+# define CFG_FLASH_CFI_DRIVER 1
+# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+# define CFG_FLASH_CHECKSUM
+# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16
-
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
-
-
+#define CFG_CS0_BASE CFG_FLASH_BASE
+#define CFG_CS0_SIZE 2*1024*1024
+#define CFG_CS0_WIDTH 16
+#define CFG_CS0_RO 0
+#define CFG_CS0_WS 6
+/*
+#define CFG_CS3_BASE 0xE0000000
+#define CFG_CS3_SIZE 1*1024*1024
+#define CFG_CS3_WIDTH 16
+#define CFG_CS3_RO 0
+#define CFG_CS3_WS 6
+*/
/*-----------------------------------------------------------------------
* Port configuration
*/
+#define CFG_PACNT 0x0000000 /* Port A D[31:24] */
+#define CFG_PADDR 0x0000000
+#define CFG_PADAT 0x0000000
+
+#define CFG_PBCNT 0x0000000 /* Port B D[23:16] */
+#define CFG_PBDDR 0x0000000
+#define CFG_PBDAT 0x0000000
+
+#define CFG_PCCNT 0x0000000 /* Port C D[15:08] */
+#define CFG_PCDDR 0x0000000
+#define CFG_PCDAT 0x0000000
+
+#define CFG_PDCNT 0x0000000 /* Port D D[07:00] */
+#define CFG_PCDDR 0x0000000
+#define CFG_PCDAT 0x0000000
+#define CFG_PEHLPAR 0xC0
+#define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
+#define CFG_DDRUA 0x05
+#define CFG_PJPAR 0xFF;
-#endif /* _CONFIG_M5282EVB_H */
+#endif /* _CONFIG_M5282EVB_H */
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
new file mode 100644
index 0000000..d3b1605
--- /dev/null
+++ b/include/configs/M5329EVB.h
@@ -0,0 +1,267 @@
+/*
+ * Configuation settings for the Freescale MCF5329 FireEngine board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5329EVB_H
+#define _M5329EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF532x /* define processor family */
+#define CONFIG_M5329 /* define processor type */
+
+#undef DEBUG
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#ifdef NANDFLASH_SIZE
+# define CONFIG_CMD_NAND
+#endif
+
+#define CFG_UNIFY_CACHE
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
+
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 80000
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x58000
+#define CFG_IMMR CFG_MBAR
+
+#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* FEC_ENET */
+
+#define CONFIG_HOSTNAME M5329EVB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=40010000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off 0 2ffff;" \
+ "era 0 2ffff;" \
+ "cp.b ${loadaddr} 0 ${filesize};" \
+ "save\0" \
+ ""
+
+#define CONFIG_PRAM 512 /* 512 KB */
+#define CFG_PROMPT "-> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x40010000
+
+#define CFG_HZ 1000
+#define CFG_CLK 80000000
+#define CFG_CPU_CLK CFG_CLK * 3
+
+#define CFG_MBAR 0xFC000000
+
+#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR 0x80000000
+#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
+#define CFG_INIT_RAM_CTRL 0x221
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x40000000
+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SDRAM_CFG1 0x53722730
+#define CFG_SDRAM_CFG2 0x56670000
+#define CFG_SDRAM_CTRL 0xE1092000
+#define CFG_SDRAM_EMOD 0x40010000
+#define CFG_SDRAM_MODE 0x018D0000
+
+#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
+#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
+
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+
+#define CFG_BOOTPARAMS_LEN 64*1024
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+# define CFG_FLASH_CFI_DRIVER 1
+# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+#endif
+
+#ifdef NANDFLASH_SIZE
+# define CFG_MAX_NAND_DEVICE 1
+# define CFG_NAND_BASE (CFG_CS2_BASE << 16)
+# define CFG_NAND_SIZE 1
+# define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+# define NAND_MAX_CHIPS 1
+# define NAND_ALLOW_ERASE_ALL 1
+# define CONFIG_JFFS2_NAND 1
+# define CONFIG_JFFS2_DEV "nand0"
+# define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1)
+# define CONFIG_JFFS2_PART_OFFSET 0x00000000
+#endif
+
+#define CFG_FLASH_BASE (CFG_CS0_BASE << 16)
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CFG_ENV_OFFSET 0x4000
+#define CFG_ENV_SECT_SIZE 0x2000
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_IS_EMBEDDED 1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - CompactFlash and registers
+ * CS2 - NAND Flash 16, 32, or 64MB
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CFG_CS0_BASE 0
+#define CFG_CS0_MASK 0x007f0001
+#define CFG_CS0_CTRL 0x00001fa0
+
+#define CFG_CS1_BASE 0x1000
+#define CFG_CS1_MASK 0x001f0001
+#define CFG_CS1_CTRL 0x002A3780
+
+#ifdef NANDFLASH_SIZE
+#define CFG_CS2_BASE 0x2000
+#define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1)
+#define CFG_CS2_CTRL 0x00001f60
+#endif
+
+#endif /* _M5329EVB_H */
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
new file mode 100644
index 0000000..6f4859c
--- /dev/null
+++ b/include/configs/M54455EVB.h
@@ -0,0 +1,391 @@
+/*
+ * Configuation settings for the Freescale MCF54455 EVB board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _JAMICA54455_H
+#define _JAMICA54455_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF5445x /* define processor family */
+#define CONFIG_M54455 /* define processor type */
+#define CONFIG_M54455EVB /* M54455EVB board */
+
+#undef DEBUG
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+/* Network configuration */
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CONFIG_CF_DOMII
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC1_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+# define CONFIG_HAS_ETH1
+
+# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
+# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
+# define CONFIG_ETHPRIME "FEC0"
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
+
+#define CONFIG_HOSTNAME M54455EVB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \
+ "loadaddr=40010000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off 0 2ffff;" \
+ "era 0 2ffff;" \
+ "cp.b ${loadaddr} 0 ${filesize};" \
+ "save\0" \
+ ""
+
+/* ATA configuration */
+#define CONFIG_ISO_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_IDE_RESET 1
+#define CONFIG_IDE_PREINIT 1
+#define CONFIG_ATAPI
+#undef CONFIG_LBA48
+
+#define CFG_IDE_MAXBUS 1
+#define CFG_IDE_MAXDEVICE 2
+
+#define CFG_ATA_BASE_ADDR 0x90000000
+#define CFG_ATA_IDE0_OFFSET 0
+
+#define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
+#define CFG_ATA_STRIDE 4 /* Interval between registers */
+#define _IO_BASE 0
+
+/* Realtime clock */
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+#define CFG_RTC_OSCILLATOR (32 * CFG_HZ)
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2c */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 80000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x58000
+#define CFG_IMMR CFG_MBAR
+
+/* PCI */
+#define CONFIG_PCI 1
+
+#define CFG_PCI_MEM_BUS 0xA0000000
+#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS
+#define CFG_PCI_MEM_SIZE 0x10000000
+
+#define CFG_PCI_IO_BUS 0xB1000000
+#define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS
+#define CFG_PCI_IO_SIZE 0x01000000
+
+#define CFG_PCI_CFG_BUS 0xB0000000
+#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS
+#define CFG_PCI_CFG_SIZE 0x01000000
+
+/* FPGA - Spartan 2 */
+/* experiment
+#define CONFIG_FPGA CFG_SPARTAN3
+#define CONFIG_FPGA_COUNT 1
+#define CFG_FPGA_PROG_FEEDBACK
+#define CFG_FPGA_CHECK_CTRLC
+*/
+
+/* Input, PCI, Flexbus, and VCO */
+#define CONFIG_EXTRA_CLOCK
+
+#define CONFIG_PRAM 512 /* 512 KB */
+
+#define CFG_PROMPT "-> "
+#define CFG_LONGHELP /* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000)
+
+#define CFG_HZ 1000
+
+#define CFG_MBAR 0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR 0x80000000
+#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
+#define CFG_INIT_RAM_CTRL 0x221
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x40000000
+#define CFG_SDRAM_BASE1 0x48000000
+#define CFG_SDRAM_SIZE 256 /* SDRAM size in MB */
+#define CFG_SDRAM_CFG1 0x65311610
+#define CFG_SDRAM_CFG2 0x59670000
+#define CFG_SDRAM_CTRL 0xEA0B2000
+#define CFG_SDRAM_EMOD 0x40010000
+#define CFG_SDRAM_MODE 0x00010033
+
+#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
+#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
+
+#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
+#define CFG_BOOTPARAMS_LEN 64*1024
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CFG_ENV_OFFSET 0x4000
+#define CFG_ENV_SECT_SIZE 0x2000
+#define CFG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OVERWRITE 1
+#undef CFG_ENV_IS_EMBEDDED
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#ifdef CFG_ATMEL_BOOT
+# define CFG_FLASH_BASE 0
+# define CFG_FLASH0_BASE CFG_CS0_BASE
+# define CFG_FLASH1_BASE CFG_CS1_BASE
+#else
+# define CFG_FLASH_BASE CFG_FLASH0_BASE
+# define CFG_FLASH0_BASE CFG_CS1_BASE
+# define CFG_FLASH1_BASE CFG_CS0_BASE
+#endif
+
+/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
+/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
+ keep reset. */
+#undef CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+
+# define CFG_FLASH_CFI_DRIVER 1
+# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
+# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+# define CFG_FLASH_CHECKSUM
+# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE }
+
+#else
+
+# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+
+# define CFG_ATMEL_REGION 4
+# define CFG_ATMEL_TOTALSECT 11
+# define CFG_ATMEL_SECT {1, 2, 1, 7}
+# define CFG_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
+# define CFG_INTEL_SECT 137
+
+/* max number of sectors on one chip */
+# define CFG_MAX_FLASH_SECT (CFG_ATMEL_TOTALSECT + CFG_INTEL_SECT)
+# define CFG_FLASH_ERASE_TOUT 2000 /* Atmel needs longer timeout */
+# define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
+# define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
+# define CFG_FLASH_UNLOCK_TOUT 100 /* Timeout for Flash Clear Lock Bits (in ms) */
+# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+# define CFG_FLASH_CHECKSUM
+
+#endif
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
+ */
+#ifdef CFG_ATMEL_BOOT
+# define CONFIG_JFFS2_DEV "nor0"
+# define CONFIG_JFFS2_PART_SIZE 0x01000000
+# define CONFIG_JFFS2_PART_OFFSET CFG_FLASH1_BASE
+#else
+# define CONFIG_JFFS2_DEV "nor0"
+# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
+# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - CompactFlash and registers
+ * CS2 - CPLD
+ * CS3 - FPGA
+ * CS4 - Available
+ * CS5 - Available
+ */
+
+#ifdef CFG_ATMEL_BOOT
+ /* Atmel Flash */
+#define CFG_CS0_BASE 0
+#define CFG_CS0_MASK 0x00070001
+#define CFG_CS0_CTRL 0x00001140
+/* Intel Flash */
+#define CFG_CS1_BASE 0x04000000
+#define CFG_CS1_MASK 0x01FF0001
+#define CFG_CS1_CTRL 0x003F3D60
+
+#define CFG_ATMEL_BASE CFG_CS0_BASE
+#else
+/* Intel Flash */
+#define CFG_CS0_BASE 0
+#define CFG_CS0_MASK 0x01FF0001
+#define CFG_CS0_CTRL 0x003F3D60
+ /* Atmel Flash */
+#define CFG_CS1_BASE 0x04000000
+#define CFG_CS1_MASK 0x00070001
+#define CFG_CS1_CTRL 0x00001140
+
+#define CFG_ATMEL_BASE CFG_CS1_BASE
+#endif
+
+/* CPLD */
+#define CFG_CS2_BASE 0x08000000
+#define CFG_CS2_MASK 0x00070001
+#define CFG_CS2_CTRL 0x003f1140
+
+/* FPGA */
+#define CFG_CS3_BASE 0x09000000
+#define CFG_CS3_MASK 0x00070001
+#define CFG_CS3_CTRL 0x00000020
+
+#endif /* _JAMICA54455_H */
diff --git a/include/configs/MBX.h b/include/configs/MBX.h
index d6e3fb8..d9f2add 100644
--- a/include/configs/MBX.h
+++ b/include/configs/MBX.h
@@ -71,13 +71,27 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_COMMANDS ( CFG_CMD_NET | CONFIG_CMD_DFL | CFG_CMD_SDRAM | \
- CFG_CMD_PCMCIA | CFG_CMD_IDE )
-#define CONFIG_DOS_PARTITION
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_IDE
+
+
+#define CONFIG_DOS_PARTITION
/*
* Miscellaneous configurable options
@@ -88,7 +102,7 @@
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -187,7 +201,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/MBX860T.h b/include/configs/MBX860T.h
index 0ca0970..69d195d 100644
--- a/include/configs/MBX860T.h
+++ b/include/configs/MBX860T.h
@@ -151,7 +151,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h
index 465a4ec..8d7ec59 100644
--- a/include/configs/METROBOX.h
+++ b/include/configs/METROBOX.h
@@ -104,6 +104,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_METROBOX 1 /* Board is Metrobox */
#define CONFIG_440GX 1 /* Specifc GX support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
@@ -241,26 +242,33 @@
#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
-/*-----------------------------------------------------------------------
- * Console/Commands/Parser
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_I2C | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_PING | \
- CFG_CMD_DIAG | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_ELF | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT)
-
-/* tbs 09-March-2005 Removed to be able to use 2nd serial */
-/* CFG_CMD_KGDB | \ */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
/* Include NetConsole support */
@@ -271,10 +279,6 @@
#define CONFIG_AUTO_COMPLETE 1
#define CFG_ALT_MEMTEST 1 /* use real memory test */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "MetroBox=> " /* Monitor Command Prompt */
@@ -285,7 +289,7 @@
/*-----------------------------------------------------------------------
* Console Buffer
*----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -331,7 +335,6 @@
#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE)
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/
#define CFG_PCI_TARGET_INIT /* let board init pci target*/
#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
@@ -348,7 +351,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
#endif
@@ -360,7 +363,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
#endif
diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h
index 53684ca..dde7742 100644
--- a/include/configs/MHPC.h
+++ b/include/configs/MHPC.h
@@ -115,25 +115,36 @@
#define CONFIG_BR0_WORKAROUND 1
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_REGINFO )
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_REGINFO
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -225,7 +236,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 7e57a0f..5b526a0 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -50,41 +50,43 @@
***********************************************************/
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
-/***********************************************************
- * Command definitions
- ***********************************************************/
-#define MIP405_COMMON_CMDS \
- (CONFIG_CMD_DFL | \
- CFG_CMD_CACHE | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_IRQ | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SAVES | \
- CFG_CMD_BSP )
-#if defined(CONFIG_MIP405T)
-#define CONFIG_COMMANDS \
- MIP405_COMMON_CMDS
-#else
-#define CONFIG_COMMANDS \
- (MIP405_COMMON_CMDS | \
- CFG_CMD_USB | \
- CFG_CMD_DOC )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_BSP
+
+#if !defined(CONFIG_MIP405T)
+ #define CONFIG_CMD_USB
+ #define CONFIG_CMD_DOC
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
@@ -165,7 +167,7 @@
**********************************************************/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -260,7 +262,7 @@
*/
#define CFG_DCACHE_SIZE 0x4000 /* For AMCC 405GPr CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -426,7 +428,7 @@
/************************************************************
* Debug support
************************************************************/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/ML2.h b/include/configs/ML2.h
index d8805ea..f488275 100644
--- a/include/configs/ML2.h
+++ b/include/configs/ML2.h
@@ -76,20 +76,31 @@
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & \
- ~( CFG_CMD_NET | \
- CFG_CMD_RTC | \
- CFG_CMD_PCI | \
- CFG_CMD_I2C \
- ) ) | \
- CFG_CMD_IRQ | \
- CFG_CMD_KGDB | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_ELF | \
- CFG_CMD_JFFS2 )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_KGDB
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_JFFS2
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_RTC
+#undef CONFIG_CMD_PCI
+#undef CONFIG_CMD_I2C
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -102,7 +113,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -195,7 +206,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -236,7 +247,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h
index 6ad2feb..9370c24 100644
--- a/include/configs/MOUSSE.h
+++ b/include/configs/MOUSSE.h
@@ -58,14 +58,31 @@
#endif
#define CONFIG_BOOTARGS "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138"
#define CONFIG_BOOTDELAY 3
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL|CFG_CMD_ASKENV|CFG_CMD_DATE)
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+
+
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ETH_ADDR "00:10:18:10:00:06"
#define CONFIG_DOS_PARTITION 1 /* MSDOS bootable partitiion support */
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-#include <cmd_confdefs.h>
+
#include "../board/mousse/mousse.h"
/*
diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h
index 6195bca..713518d 100644
--- a/include/configs/MPC8260ADS.h
+++ b/include/configs/MPC8260ADS.h
@@ -101,8 +101,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
@@ -198,59 +197,69 @@
#define CONFIG_BAUDRATE 115200
-#define CFG_EXCLUDE CFG_CMD_BEDBUG | \
- CFG_CMD_BMP | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DISPLAY | \
- CFG_CMD_DOC | \
- CFG_CMD_DTT | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_EXT2 | \
- CFG_CMD_FAT | \
- CFG_CMD_FDC | \
- CFG_CMD_FDOS | \
- CFG_CMD_HWFLOW | \
- CFG_CMD_IDE | \
- CFG_CMD_KGDB | \
- CFG_CMD_MMC | \
- CFG_CMD_NAND | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_REISER | \
- CFG_CMD_SCSI | \
- CFG_CMD_SPI | \
- CFG_CMD_SNTP | \
- CFG_CMD_UNIVERSE | \
- CFG_CMD_USB | \
- CFG_CMD_VFD | \
- CFG_CMD_XIMG
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_BMP
+#undef CONFIG_CMD_BSP
+#undef CONFIG_CMD_DATE
+#undef CONFIG_CMD_DISPLAY
+#undef CONFIG_CMD_DOC
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_EXT2
+#undef CONFIG_CMD_FAT
+#undef CONFIG_CMD_FDC
+#undef CONFIG_CMD_FDOS
+#undef CONFIG_CMD_HWFLOW
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_KGDB
+#undef CONFIG_CMD_MFSL
+#undef CONFIG_CMD_MMC
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_REISER
+#undef CONFIG_CMD_SCSI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_SNTP
+#undef CONFIG_CMD_UNIVERSE
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_VFD
+#undef CONFIG_CMD_XIMG
#if CONFIG_ADSTYPE == CFG_8272ADS
-#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
- CFG_CMD_SDRAM | \
- CFG_CMD_I2C | \
- CFG_EXCLUDE ) )
+ #undef CONFIG_CMD_SDRAM
+ #undef CONFIG_CMD_I2C
+
#elif CONFIG_ADSTYPE >= CFG_PQ2FADS
-#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
- CFG_CMD_SDRAM | \
- CFG_CMD_I2C | \
- CFG_CMD_PCI | \
- CFG_EXCLUDE ) )
+ #undef CONFIG_CMD_SDRAM
+ #undef CONFIG_CMD_I2C
+ #undef CONFIG_CMD_PCI
+
#else
-#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
- CMD_CFG_PCI | \
- CFG_EXCLUDE ) )
+ #undef CONFIG_CMD_PCI
+
#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/mtdblock2"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -268,7 +277,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -384,7 +393,7 @@
#endif /* CFG_RAMBOOT */
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -397,9 +406,9 @@
#define CFG_BCR 0x100C0000
#define CFG_SIUMCR 0x0A200000
#define CFG_SCCR SCCR_DFBRG01
-#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00001801
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801)
#define CFG_OR0_PRELIM 0xFF800876
-#define CFG_BR1_PRELIM CFG_BCSR | 0x00001801
+#define CFG_BR1_PRELIM (CFG_BCSR | 0x00001801)
#define CFG_OR1_PRELIM 0xFFFF8010
/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
index 4953b70..14b041e 100644
--- a/include/configs/MPC8266ADS.h
+++ b/include/configs/MPC8266ADS.h
@@ -83,8 +83,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
@@ -141,40 +140,43 @@
*/
#define SPD_EEPROM_ADDRESS 0x50
-
#define CONFIG_8260_CLKIN 66000000 /* in Hz */
#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_COMMANDS ( CFG_CMD_ALL & ~( \
- CFG_CMD_BEDBUG | \
- CFG_CMD_BMP | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DISPLAY | \
- CFG_CMD_DOC | \
- CFG_CMD_DTT | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_EXT2 | \
- CFG_CMD_FDC | \
- CFG_CMD_FDOS | \
- CFG_CMD_HWFLOW | \
- CFG_CMD_IDE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_KGDB | \
- CFG_CMD_MMC | \
- CFG_CMD_NAND | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_REISER | \
- CFG_CMD_SCSI | \
- CFG_CMD_SPI | \
- CFG_CMD_SNTP | \
- CFG_CMD_VFD | \
- CFG_CMD_UNIVERSE | \
- CFG_CMD_USB | \
- CFG_CMD_XIMG ) )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_BMP
+#undef CONFIG_CMD_BSP
+#undef CONFIG_CMD_DATE
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DISPLAY
+#undef CONFIG_CMD_DOC
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_EXT2
+#undef CONFIG_CMD_FDC
+#undef CONFIG_CMD_FDOS
+#undef CONFIG_CMD_HWFLOW
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_KGDB
+#undef CONFIG_CMD_MFSL
+#undef CONFIG_CMD_MMC
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_REISER
+#undef CONFIG_CMD_SCSI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_SNTP
+#undef CONFIG_CMD_VFD
+#undef CONFIG_CMD_UNIVERSE
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_XIMG
/* Define a command string that is automatically executed when no character
* is read on the console interface withing "Boot Delay" after reset.
@@ -202,21 +204,19 @@
"bootm"
#endif /* CONFIG_BOOT_ROOT_NFS */
-/* Add support for a few extra bootp options like:
- * - File size
- * - DNS
+/*
+ * BOOTP options
*/
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE | \
- CONFIG_BOOTP_DNS)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -231,7 +231,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -283,7 +283,6 @@
#define SDRAM_SPD_ADDR 0x50
-
/*-----------------------------------------------------------------------
* BR2,BR3 - Base Register
* Ref: Section 10.3.1 on page 10-14
@@ -381,7 +380,6 @@
#error "INVALID SDRAM CONFIGURATION"
#endif
-
#define RS232EN_1 0x02000002
#define RS232EN_2 0x01000001
#define FETHIEN 0x08000008
@@ -393,7 +391,6 @@
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */
/* 0x0EB2B645 */
#define CFG_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP ) |\
@@ -450,13 +447,11 @@
# define CFG_ENV_SIZE 0x200
#endif /* CFG_RAMBOOT */
-
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-
/*-----------------------------------------------------------------------
* HIDx - Hardware Implementation-dependent Registers 2-11
*-----------------------------------------------------------------------
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
new file mode 100644
index 0000000..6568fe1
--- /dev/null
+++ b/include/configs/MPC8313ERDB.h
@@ -0,0 +1,569 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * mpc8313epb board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1
+#define CONFIG_MPC83XX 1
+#define CONFIG_MPC831X 1
+#define CONFIG_MPC8313 1
+#define CONFIG_MPC8313ERDB 1
+
+#define CONFIG_PCI
+#define CONFIG_83XX_GENERIC_PCI
+
+#ifdef CFG_66MHZ
+#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
+#elif defined(CFG_33MHZ)
+#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
+#else
+#error Unknown oscillator frequency.
+#endif
+
+#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+
+#define CFG_IMMR 0xE0000000
+
+#define CFG_MEMTEST_START 0x00001000
+#define CFG_MEMTEST_END 0x07f00000
+
+/* Early revs of this board will lock up hard when attempting
+ * to access the PMC registers, unless a JTAG debugger is
+ * connected, or some resistor modifications are made.
+ */
+#define CFG_8313ERDB_BROKEN_PMC 1
+
+#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
+#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+
+/*
+ * Manually set up DDR parameters, as this board does not
+ * seem to have the SPD connected to I2C.
+ */
+#define CFG_DDR_SIZE 128 /* MB */
+#define CFG_DDR_CONFIG ( CSCONFIG_EN | CSCONFIG_AP \
+ | 0x00040000 /* TODO */ \
+ | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
+ /* 0x80840102 */
+
+#define CFG_DDR_TIMING_3 0x00000000
+#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
+ | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
+ | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
+ | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
+ | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
+ | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
+ | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
+ | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+ /* 0x00220802 */
+#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
+ | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
+ | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
+ | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
+ | (13 << TIMING_CFG1_REFREC_SHIFT ) \
+ | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
+ | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
+ | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+ /* 0x3935d322 */
+#define CFG_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+ | (31 << TIMING_CFG2_CPO_SHIFT ) \
+ | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
+ | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
+ | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
+ | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
+ | (10 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+ /* 0x0f9048ca */ /* P9-45,may need tuning */
+#define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+ | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+ /* 0x03200064 */
+#if defined(CONFIG_DDR_2T_TIMING)
+#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_2T_EN \
+ | SDRAM_CFG_DBW_32 )
+#else
+#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_32_BE )
+ /* 0x43080000 */
+#endif
+#define CFG_SDRAM_CFG2 0x00401000;
+/* set burst length to 8 for 32-bit data path */
+#define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
+ | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
+ /* 0x44400232 */
+#define CFG_DDR_MODE_2 0x8000C000;
+
+#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+ /*0x02000000*/
+#define CFG_DDRCDR_VALUE ( DDRCDR_EN \
+ | DDRCDR_PZ_NOMZ \
+ | DDRCDR_NZ_NOMZ \
+ | DDRCDR_M_ODR )
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI /* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
+#define CFG_FLASH_SIZE 8 /* flash size in MB */
+#define CFG_FLASH_EMPTY_INFO /* display empty sectors */
+#define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
+
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \
+ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+ BR_V) /* valid */
+#define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_9 \
+ | OR_GPCM_EHTR \
+ | OR_GPCM_EAD )
+ /* 0xFF006FF7 TODO SLOW 16 MB flash size */
+#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */
+#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */
+
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 135 /* sectors per device */
+
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#endif
+
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ */
+#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */
+#define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \
+ | (0xFF << LBCR_BMT_SHIFT) \
+ | 0xF ) /* 0x0004ff0f */
+
+#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */
+
+/* drivers/nand/nand.c */
+#define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */
+#define CFG_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+
+#define CFG_BR1_PRELIM ( CFG_NAND_BASE \
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V ) /* valid */
+#define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_1 \
+ | OR_FCM_TRLX \
+ | OR_FCM_EHTR )
+ /* 0xFFFF8396 */
+#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE
+#define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
+
+#define CFG_VSC7385_BASE 0xF0000000
+
+#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
+#define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */
+#define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
+#define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */
+#define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */
+
+/* local bus read write buffer mapping */
+#define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */
+#define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */
+#define CFG_LBLAWBAR3_PRELIM 0xFA000000
+#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_CPU "PowerPC,8313@0"
+#define OF_SOC "soc8313@e0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc8313@e0000000/serial@4500"
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
+#define CFG_I2C2_OFFSET 0x3100
+
+/* TSEC */
+#define CFG_TSEC1_OFFSET 0x24000
+#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET 0x25000
+#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
+#define CONFIG_NET_MULTI
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_MMIO_BASE 0x90000000
+#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
+#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xE2000000
+#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+/*
+ * TSEC configuration
+ */
+#define CONFIG_TSEC_ENET /* TSEC ethernet support */
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+#define CONFIG_GMII 1 /* MII PHY management */
+#define CONFIG_TSEC1 1
+
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
+#define TSEC1_PHY_ADDR 0x1c
+#define TSEC2_PHY_ADDR 4
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC1"
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1337
+#define CFG_I2C_RTC_ADDR 0x68
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+ #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
+ #define CFG_ENV_SIZE 0x2000
+
+/* Address and size of Redundant Environment Sector */
+#else
+ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+ #define CFG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PCI
+
+#if defined(CFG_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
+#endif
+
+#define CONFIG_CMDLINE_EDITING 1
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 16384
+#define CFG_CACHELINE_SIZE 32
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+
+#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */
+
+#ifdef CFG_66MHZ
+
+/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
+/* 0x62040000 */
+#define CFG_HRCW_LOW (\
+ 0x20000000 /* reserved, must be set */ |\
+ HRCWL_DDRCM |\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_2X1 |\
+ HRCWL_CSB_TO_CLKIN_2X1 |\
+ HRCWL_CORE_TO_CSB_2X1)
+
+#elif defined(CFG_33MHZ)
+
+/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
+/* 0x65040000 */
+#define CFG_HRCW_LOW (\
+ 0x20000000 /* reserved, must be set */ |\
+ HRCWL_DDRCM |\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_2X1 |\
+ HRCWL_CSB_TO_CLKIN_5X1 |\
+ HRCWL_CORE_TO_CSB_2X1)
+
+#endif
+
+/* 0xa0606c00 */
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_RL_EXT_LEGACY |\
+ HRCWH_TSEC1M_IN_RGMII |\
+ HRCWH_TSEC2M_IN_RGMII |\
+ HRCWH_BIG_ENDIAN |\
+ HRCWH_LALE_NORMAL)
+
+/* System IO Config */
+#define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
+#define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */
+
+#define CFG_HID0_INIT 0x000000000
+#define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+
+#define CFG_HID2 HID2_HBE
+
+/* DDR @ 0x00000000 */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI @ 0x80000000 */
+#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10)
+#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI2 not supported on 8313 */
+#define CFG_IBAT3L (0)
+#define CFG_IBAT3U (0)
+#define CFG_IBAT4L (0)
+#define CFG_IBAT4U (0)
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
+#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CFG_IBAT6L (0xF0000000 | BATL_PP_10)
+#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT7L (0)
+#define CFG_IBAT7U (0)
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+#define CFG_DBAT4L CFG_IBAT4L
+#define CFG_DBAT4U CFG_IBAT4U
+#define CFG_DBAT5L CFG_IBAT5L
+#define CFG_DBAT5U CFG_IBAT5U
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+#define CFG_DBAT7L CFG_IBAT7L
+#define CFG_DBAT7U CFG_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ETHADDR 00:E0:0C:00:95:01
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETH1ADDR 00:E0:0C:00:95:02
+
+#define CONFIG_IPADDR 10.0.0.2
+#define CONFIG_SERVERIP 10.0.0.1
+#define CONFIG_GATEWAYIP 10.0.0.1
+#define CONFIG_NETMASK 255.0.0.0
+#define CONFIG_NETDEV eth1
+
+#define CONFIG_HOSTNAME mpc8313erdb
+#define CONFIG_ROOTPATH /nfs/root/path
+#define CONFIG_BOOTFILE uImage
+#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
+#define CONFIG_FDTFILE mpc8313erdb.dtb
+
+#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
+#define CONFIG_BAUDRATE 115200
+
+#define XMK_STR(x) #x
+#define MK_STR(x) XMK_STR(x)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
+ "ethprime=TSEC1\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
+ "console=ttyS0\0" \
+ "setbootargs=setenv bootargs " \
+ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+ "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv rootdev /dev/nfs;" \
+ "run setbootargs;" \
+ "run setipargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv rootdev /dev/ram;" \
+ "run setbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#undef MK_STR
+#undef XMK_STR
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
new file mode 100644
index 0000000..376973b
--- /dev/null
+++ b/include/configs/MPC8323ERDB.h
@@ -0,0 +1,583 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 family */
+#define CONFIG_QE 1 /* Has QE */
+#define CONFIG_MPC83XX 1 /* MPC83xx family */
+#define CONFIG_MPC832X 1 /* MPC832x CPU specific */
+
+#define CONFIG_PCI 1
+#define CONFIG_83XX_GENERIC_PCI 1
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
+#endif
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CFG_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_2X1 |\
+ HRCWL_VCO_1X2 |\
+ HRCWL_CSB_TO_CLKIN_2X1 |\
+ HRCWL_CORE_TO_CSB_2_5X1 |\
+ HRCWL_CE_PLL_VCO_DIV_2 |\
+ HRCWL_CE_PLL_DIV_1X1 |\
+ HRCWL_CE_TO_PLL_1X3)
+
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_BIG_ENDIAN |\
+ HRCWH_LALE_NORMAL)
+
+/*
+ * System IO Config
+ */
+#define CFG_SICRL 0x00000000
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+
+/*
+ * IMMR new address
+ */
+#define CFG_IMMR 0xE0000000
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
+
+#undef CONFIG_SPD_EEPROM
+#if defined(CONFIG_SPD_EEPROM)
+/* Determine DDR configuration from I2C interface
+ */
+#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
+#else
+/* Manually set up DDR parameters
+ */
+#define CFG_DDR_SIZE 64 /* MB */
+#define CFG_DDR_CS0_CONFIG 0x80840101
+#define CFG_DDR_TIMING_0 0x00220802
+#define CFG_DDR_TIMING_1 0x3935d322
+#define CFG_DDR_TIMING_2 0x0f9048ca
+#define CFG_DDR_TIMING_3 0x00000000
+#define CFG_DDR_CLK_CNTL 0x02000000
+#define CFG_DDR_MODE 0x44400232
+#define CFG_DDR_MODE2 0x8000c000
+#define CFG_DDR_INTERVAL 0x03200064
+#define CFG_DDR_CS0_BNDS 0x00000003
+#define CFG_DDR_SDRAM_CFG 0x43080000
+#define CFG_DDR_SDRAM_CFG2 0x00401000
+#endif
+
+/*
+ * Memory test
+ */
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00030000 /* memtest region */
+#define CFG_MEMTEST_END 0x03f00000
+
+/*
+ * The reserved memory
+ */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2)
+#define CFG_LBC_LBCR 0x00000000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI /* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
+#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
+
+#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
+#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
+
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
+ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+ BR_V) /* valid */
+#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
+
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+
+/*
+ * SDRAM on the Local Bus
+ */
+#undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */
+
+#ifdef CFG_LB_SDRAM
+#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
+#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+
+#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE
+#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
+
+/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ * port size = 32-bits = BR2[19:20] = 11
+ * no parity checking = BR2[21:22] = 00
+ * SDRAM for MSEL = BR2[24:26] = 011
+ * Valid = BR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ * 64MB mask for AM, OR2[0:7] = 1111 1100
+ * XAM, OR2[17:18] = 11
+ * 9 columns OR2[19-21] = 010
+ * 13 rows OR2[23-25] = 100
+ * EAD set for extra time OR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CFG_OR2_PRELIM 0xfc006901
+
+#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
+#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
+
+#define CFG_LBC_LSDMR_COMMON 0x0063b723
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_PCHALL)
+#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_MRW)
+#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_NORMAL)
+
+#endif
+
+/*
+ * Windows to access PIB via local bus
+ */
+#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
+#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_CPU "PowerPC,8323@0"
+#define OF_SOC "soc8323@e0000000"
+#define OF_QE "qe@e0100000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500"
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_FSL_I2C
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
+#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_MMIO_BASE 0x90000000
+#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
+#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_IO_BASE 0xd0000000
+#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE 0x04000000 /* 64M */
+
+#ifdef CONFIG_PCI
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
+
+#endif /* CONFIG_PCI */
+
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME "Freescale GETH"
+
+#define CONFIG_UEC_ETH1 /* ETH3 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CFG_UEC1_UCC_NUM 2 /* UCC3 */
+#define CFG_UEC1_RX_CLK QE_CLK9
+#define CFG_UEC1_TX_CLK QE_CLK10
+#define CFG_UEC1_ETH_TYPE FAST_ETH
+#define CFG_UEC1_PHY_ADDR 4
+#define CFG_UEC1_INTERFACE_MODE ENET_100_MII
+#endif
+
+#define CONFIG_UEC_ETH2 /* ETH4 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CFG_UEC2_UCC_NUM 1 /* UCC2 */
+#define CFG_UEC2_RX_CLK QE_CLK16
+#define CFG_UEC2_TX_CLK QE_CLK3
+#define CFG_UEC2_ETH_TYPE FAST_ETH
+#define CFG_UEC2_PHY_ADDR 0
+#define CFG_UEC2_INTERFACE_MODE ENET_100_MII
+#endif
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+ #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+ #define CFG_ENV_SIZE 0x2000
+#else
+ #define CFG_NO_FLASH 1 /* Flash is not usable now */
+ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+ #define CFG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_ASKENV
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+#if defined(CFG_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
+#endif
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if (CONFIG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CFG_HID0_INIT 0x000000000
+#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CFG_HID2 HID2_HBE
+
+/*
+ * Cache Config
+ */
+#define CFG_DCACHE_SIZE 16384
+#define CFG_CACHELINE_SIZE 32
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
+#endif
+
+/*
+ * MMU Setup
+ */
+
+/* DDR: cache cacheable */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+
+/* IMMRBAR & PCI IO: cache-inhibit and guarded */
+#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CFG_IBAT2L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT2U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_DBAT2L (CFG_FLASH_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U CFG_IBAT2U
+
+#define CFG_IBAT3L (0)
+#define CFG_IBAT3U (0)
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10)
+#define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT4L CFG_IBAT4L
+#define CFG_DBAT4U CFG_IBAT4U
+
+#ifdef CONFIG_PCI
+/* PCI MEM space: cacheable */
+#define CFG_IBAT5L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT5U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT5L CFG_IBAT5L
+#define CFG_DBAT5U CFG_IBAT5U
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CFG_IBAT6L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT6U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+#else
+#define CFG_IBAT5L (0)
+#define CFG_IBAT5U (0)
+#define CFG_IBAT6L (0)
+#define CFG_IBAT6U (0)
+#define CFG_DBAT5L CFG_IBAT5L
+#define CFG_DBAT5U CFG_IBAT5U
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+#endif
+
+/* Nothing in BAT7 */
+#define CFG_IBAT7L (0)
+#define CFG_IBAT7U (0)
+#define CFG_DBAT7L CFG_IBAT7L
+#define CFG_DBAT7U CFG_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ETHADDR 00:04:9f:ef:03:01
+#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
+#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02
+
+#define CONFIG_IPADDR 10.0.0.2
+#define CONFIG_SERVERIP 10.0.0.1
+#define CONFIG_GATEWAYIP 10.0.0.1
+#define CONFIG_NETMASK 255.0.0.0
+#define CONFIG_NETDEV eth1
+
+#define CONFIG_HOSTNAME mpc8323erdb
+#define CONFIG_ROOTPATH /nfsroot
+#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
+#define CONFIG_BOOTFILE uImage
+#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
+#define CONFIG_FDTFILE mpc832x_rdb.dtb
+
+#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
+#define CONFIG_BAUDRATE 115200
+
+#define XMK_STR(x) #x
+#define MK_STR(x) XMK_STR(x)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftp $loadaddr $uboot;" \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
+ "ramdiskaddr=1000000\0" \
+ "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
+ "console=ttyS0\0" \
+ "setbootargs=setenv bootargs " \
+ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+ "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv rootdev /dev/nfs;" \
+ "run setbootargs;" \
+ "run setipargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv rootdev /dev/ram;" \
+ "run setbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#undef MK_STR
+#undef XMK_STR
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index cecb225..c9c6d88 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -30,6 +30,8 @@
#define CONFIG_MPC83XX 1 /* MPC83xx family */
#define CONFIG_MPC832X 1 /* MPC832x CPU specific */
#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
+#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
+#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
/*
* System Clock Setup
@@ -87,6 +89,7 @@
#define CFG_SICRL 0x00000000
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R
/*
* IMMR new address
@@ -315,12 +318,9 @@
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8323@0"
#define OF_SOC "soc8323@e0000000"
#define OF_QE "qe@e0100000"
@@ -423,41 +423,33 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#if defined(CFG_RAMBOOT)
-#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_ASKENV \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
-#else
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_ASKENV \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
-#endif
-#else
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_ASKENV
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_ASKENV \
- | CFG_CMD_I2C)
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_ASKENV \
- | CFG_CMD_I2C )
+ #define CONFIG_CMD_PCI
#endif
+
+#if defined(CFG_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -468,7 +460,7 @@
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -498,7 +490,7 @@
*/
#define CFG_DCACHE_SIZE 16384
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
#endif
@@ -575,7 +567,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 0460be9..92555ba 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -339,12 +339,9 @@
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8349@0"
#define OF_SOC "soc8349@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
@@ -432,14 +429,16 @@
#endif
#define CONFIG_GMII 1 /* MII PHY management */
-#define CONFIG_MPC83XX_TSEC1 1
-#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC83XX_TSEC2 1
-#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
@@ -475,44 +474,35 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#if defined(CFG_RAMBOOT)
-#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C \
- | CFG_CMD_DATE) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
-#else
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_DATE) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
-#endif
-#else
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_MII
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_DATE \
- )
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII \
- | CFG_CMD_DATE \
- )
+ #define CONFIG_CMD_PCI
#endif
+
+#if defined(CFG_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -523,7 +513,7 @@
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -544,7 +534,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -695,7 +685,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -708,6 +698,7 @@
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_ETHADDR 00:04:9f:ef:23:33
#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH0
#define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21
#endif
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 37bbfb3..54cab52 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -154,6 +154,9 @@
#define CFG_MEMTEST_START 0x1000 /* memtest region */
#define CFG_MEMTEST_END 0x2000
+#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
#ifdef CONFIG_HARD_I2C
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
#endif
@@ -286,18 +289,16 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_CONSOLE ttyS0
#define CONFIG_BAUDRATE 115200
#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500)
#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600)
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8349@0"
#define OF_SOC "soc8349@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
@@ -369,24 +370,27 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_NET_MULTI
#define CONFIG_MII
-#define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */
+#define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */
-#define CONFIG_MPC83XX_TSEC1
+#define CONFIG_TSEC1
-#ifdef CONFIG_MPC83XX_TSEC1
-#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME "TSEC0"
#define CFG_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
#define TSEC1_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
#endif
-#ifdef CONFIG_MPC83XX_TSEC2
+#ifdef CONFIG_TSEC2
#define CONFIG_HAS_ETH1
-#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
+#define CONFIG_TSEC2_NAME "TSEC1"
#define CFG_TSEC2_OFFSET 0x25000
#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */
#define TSEC2_PHY_ADDR 4
#define TSEC2_PHYIDX 0
+#define TSEC2_FLAGS TSEC_GIGABIT
#endif
#define CONFIG_ETHPRIME "Freescale TSEC"
@@ -405,6 +409,7 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH /* Flash is not usable now */
+ #undef CFG_FLASH_CFI_DRIVER
#define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
@@ -413,40 +418,41 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
-/* CONFIG_COMMANDS */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
#ifdef CONFIG_COMPACT_FLASH
-#define CONFIG_COMMANDS_CF (CFG_CMD_IDE | CFG_CMD_FAT)
-#else
-#define CONFIG_COMMANDS_CF 0
+ #define CONFIG_CMD_IDE
+ #define CONFIG_CMD_FAT
#endif
#ifdef CONFIG_PCI
-#define CONFIG_COMMANDS_PCI CFG_CMD_PCI
-#else
-#define CONFIG_COMMANDS_PCI 0
+ #define CONFIG_CMD_PCI
#endif
#ifdef CONFIG_HARD_I2C
-#define CONFIG_COMMANDS_I2C CFG_CMD_I2C
-#else
-#define CONFIG_COMMANDS_I2C 0
+ #define CONFIG_CMD_I2C
#endif
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CONFIG_COMMANDS_CF | \
- CFG_CMD_NET | \
- CFG_CMD_PING | \
- CONFIG_COMMANDS_I2C | \
- CONFIG_COMMANDS_PCI | \
- CFG_CMD_SDRAM | \
- CFG_CMD_DATE | \
- CFG_CMD_CACHE | \
- CFG_CMD_IRQ)
-#include <cmd_confdefs.h>
-
/* Watchdog */
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
@@ -466,7 +472,7 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CFG_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -489,7 +495,7 @@ boards, we say we have two, but don't display a message if we find only one. */
*/
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */
#endif
@@ -614,7 +620,7 @@ boards, we say we have two, but don't display a message if we find only one. */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -625,11 +631,11 @@ boards, we say we have two, but don't display a message if we find only one. */
*/
#define CONFIG_ENV_OVERWRITE
-#ifdef CONFIG_MPC83XX_TSEC1
+#ifdef CONFIG_TSEC1
#define CONFIG_ETHADDR 00:E0:0C:00:8C:01
#endif
-#ifdef CONFIG_MPC83XX_TSEC2
+#ifdef CONFIG_TSEC2
#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02
#endif
@@ -667,9 +673,10 @@ boards, we say we have two, but don't display a message if we find only one. */
" ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \
MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \
- " console=ttyS0," MK_STR(CONFIG_BAUDRATE)
+ " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE)
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=" MK_STR(CONFIG_CONSOLE) "\0" \
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 79937dc..41f062c 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -32,6 +32,8 @@
#define CONFIG_MPC83XX 1 /* MPC83XX family */
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
+#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
+#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
/*
* System Clock Setup
@@ -88,6 +90,7 @@
#define CFG_SICRL 0x40000000
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R
/*
* IMMR new address
@@ -309,13 +312,13 @@
/*
* CS4 on Local Bus, to PIB
*/
-#define CFG_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */
+#define CFG_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */
#define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
/*
* CS5 on Local Bus, to PIB
*/
-#define CFG_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */
+#define CFG_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */
#define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
/*
@@ -348,10 +351,6 @@
#define CONFIG_OF_HAS_BD_T 1
#define CONFIG_OF_HAS_UBOOT_ENV 1
-
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8360@0"
#define OF_SOC "soc8360@e0000000"
#define OF_QE "qe@e0100000"
@@ -457,41 +456,33 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#if defined(CFG_RAMBOOT)
-#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_ASKENV \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
-#else
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_ASKENV \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
-#endif
-#else
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_ASKENV
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_ASKENV \
- | CFG_CMD_I2C)
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_ASKENV \
- | CFG_CMD_I2C )
+ #define CONFIG_CMD_PCI
#endif
+
+#if defined(CFG_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -502,7 +493,7 @@
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -532,7 +523,7 @@
*/
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
#endif
@@ -610,7 +601,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 5aeea58..be603ac 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -301,9 +301,6 @@
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8540@0"
#define OF_SOC "soc8540@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -366,14 +363,16 @@
#endif
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#if CONFIG_HAS_FEC
@@ -381,6 +380,7 @@
#define CONFIG_MPC85XX_FEC_NAME "FEC"
#define FEC_PHY_ADDR 3
#define FEC_PHYIDX 0
+#define FEC_FLAGS 0
#endif
/* Options are: TSEC[0-1], FEC */
@@ -407,37 +407,33 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
#if defined(CFG_RAMBOOT)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
- #else
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
- #endif
-#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #else
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #endif
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -448,7 +444,7 @@
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -469,7 +465,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -481,7 +477,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -493,6 +489,7 @@
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
@@ -520,7 +517,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
- "ramdiskaddr=600000\0" \
+ "ramdiskaddr=1000000\0" \
"ramdiskfile=your.ramdisk.u-boot\0" \
"fdtaddr=400000\0" \
"fdtfile=your.fdt.dtb\0"
@@ -540,7 +537,7 @@
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr"
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index 418a3a3..e376c11 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -212,11 +212,14 @@
#elif defined(CONFIG_TSEC_ENET)
#define CONFIG_NET_MULTI 1
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
+#define CONFIG_TSEC1 1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_MPC85XX_FEC 1
+#define CONFIG_HAS_ETH2
#define CONFIG_MPC85XX_FEC_NAME "FEC"
#define TSEC1_PHY_ADDR 7
#define TSEC2_PHY_ADDR 4
@@ -224,6 +227,10 @@
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define FEC_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define FEC_FLAGS 0
+
/* Options are: TSEC[0-1], FEC */
#define CONFIG_ETHPRIME "TSEC0"
@@ -259,26 +266,33 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
-#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING \
- | CFG_CMD_PCI | CFG_CMD_I2C ) & \
- ~(CFG_CMD_ENV | CFG_CMD_LOADS ))
-#else
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING \
- | CFG_CMD_I2C ) & \
- ~(CFG_CMD_ENV | CFG_CMD_LOADS ))
-#endif
-#else
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \
- | CFG_CMD_PING | CFG_CMD_I2C )
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C )
+ #define CONFIG_CMD_PCI
#endif
+
+#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -288,7 +302,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "MPC8540EVAL=> "/* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -308,7 +322,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -320,7 +334,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index fb360d2..4e061bd 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -312,9 +312,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8541@0"
#define OF_SOC "soc8541@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -350,6 +347,13 @@ extern unsigned long get_clock_freq(void);
#define CFG_PCI2_IO_PHYS 0xe2100000
#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
#if defined(CONFIG_PCI)
@@ -373,17 +377,16 @@ extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
-#undef CONFIG_MPC85XX_FEC
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
-#define FEC_PHY_ADDR 3
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
-#define FEC_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
@@ -401,19 +404,28 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
+ #define CONFIG_CMD_PCI
#endif
-#include <cmd_confdefs.h>
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -423,7 +435,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -443,7 +455,7 @@ extern unsigned long get_clock_freq(void);
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -455,7 +467,7 @@ extern unsigned long get_clock_freq(void);
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -466,6 +478,7 @@ extern unsigned long get_clock_freq(void);
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 4c34308..f580cca 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -34,14 +34,14 @@
#define CONFIG_MPC8544 1
#define CONFIG_MPC8544DS 1
-#undef CONFIG_PCI /* Enable PCI/PCIE */
-#undef CONFIG_PCI1 /* PCI controller 1 */
-#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
-#undef CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
-#undef CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
-#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_PCI 1 /* Enable PCI/PCIE */
+#define CONFIG_PCI1 1 /* PCI controller 1 */
+#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_DLL
@@ -52,6 +52,7 @@
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_DDR_ECC_CMD
+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
/*
* When initializing flash, if we cannot find the manufacturer ID,
@@ -70,7 +71,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
@@ -86,13 +87,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
#define CFG_MEMTEST_END 0x00400000
#define CFG_ALT_MEMTEST
-#define CONFIG_PANIC_HANG /* do not reset board on panic */
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
@@ -180,6 +181,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */
#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
+#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
@@ -251,9 +253,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8544@0"
#define OF_SOC "soc8544@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -281,7 +280,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe1000000
-#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
+#define CFG_PCI1_IO_SIZE 0x00010000 /* 64k */
/* PCI view of System Memory */
#define CFG_PCI_MEMORY_BUS 0x00000000
@@ -293,27 +292,27 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE
#define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCIE2_IO_BASE 0x00000000
-#define CFG_PCIE2_IO_PHYS 0xe2000000
-#define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */
+#define CFG_PCIE2_IO_PHYS 0xe1010000
+#define CFG_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 1, Slot 2,tgtid 2, Base address a000 */
#define CFG_PCIE1_MEM_BASE 0xa0000000
#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
-#define CFG_PCIE1_MEM_SIZE 0x08000000 /* 128M */
-#define CFG_PCIE1_MEM_BASE2 0xa8000000
-#define CFG_PCIE1_MEM_PHYS2 CFG_PCIE1_MEM_BASE2
-#define CFG_PCIE1_MEM_SIZE2 0x04000000 /* 64M */
-#define CFG_PCIE1_IO_BASE 0x00000000 /* reuse mem LAW */
-#define CFG_PCIE1_IO_PHYS 0xaf000000
-#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
+#define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCIE1_IO_BASE 0x00000000
+#define CFG_PCIE1_IO_PHYS 0xe1020000
+#define CFG_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 3, direct to uli, tgtid 3, Base address b000 */
#define CFG_PCIE3_MEM_BASE 0xb0000000
#define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE
-#define CFG_PCIE3_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCIE3_MEM_SIZE 0x00100000 /* 1M */
#define CFG_PCIE3_IO_BASE 0x00000000
-#define CFG_PCIE3_IO_PHYS 0xe3000000
+#define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
#define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */
+#define CFG_PCIE3_MEM_BASE2 0xb0200000
+#define CFG_PCIE3_MEM_PHYS2 CFG_PCIE3_MEM_BASE2
+#define CFG_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
#if defined(CONFIG_PCI)
@@ -344,7 +343,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SATA_ULI5288
#define CFG_SCSI_MAX_SCSI_ID 4
#define CFG_SCSI_MAX_LUN 1
-#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
#endif /* SCSCI */
@@ -354,27 +353,28 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC1"
-#define CONFIG_MPC85XX_TSEC3 1
-#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC3"
-#undef CONFIG_MPC85XX_FEC
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC3"
#define TSEC1_PHY_ADDR 0
#define TSEC3_PHY_ADDR 1
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+
#define TSEC1_PHYIDX 0
#define TSEC3_PHYIDX 0
#define CONFIG_ETHPRIME "eTSEC1"
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
#endif /* CONFIG_TSEC_ENET */
/*
@@ -392,21 +392,32 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII \
- | CFG_CMD_BEDBUG \
- | CFG_CMD_NET)
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
+ #define CONFIG_CMD_PCI
+ #define CONFIG_CMD_BEDBUG
+ #define CONFIG_CMD_NET
+ #define CONFIG_CMD_SCSI
+ #define CONFIG_CMD_EXT2
#endif
-#include <cmd_confdefs.h>
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -416,7 +427,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -431,12 +442,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
+#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -448,7 +459,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -459,6 +470,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
@@ -472,7 +484,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_HOSTNAME 8544ds_unknown
#define CONFIG_ROOTPATH /nfs/mpc85xx
-#define CONFIG_BOOTFILE 8544ds_tmt/uImage.uboot
+#define CONFIG_BOOTFILE 8544ds/uImage.uboot
+#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
#define CONFIG_SERVERIP 192.168.0.1
#define CONFIG_GATEWAYIP 192.168.0.1
@@ -481,7 +494,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
#define CONFIG_BAUDRATE 115200
@@ -489,10 +502,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define PCIE_ENV \
"pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
- "pcie1regs=setenv a e000a; run pciereg\0" \
- "pcie2regs=setenv a e0009; run pciereg\0" \
- "pcie3regs=setenv a e000b; run pciereg\0" \
- "pcieerr=md ${a}020 1; md ${a}e00;" \
+ "pcieerr=md ${a}020 1; md ${a}e00 e;" \
"pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
"pci d.w $b.0 56 1;" \
"pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \
@@ -501,12 +511,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
"pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \
"pci w $b.0 130 ffffffff\0" \
"pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
- "pcie1err=setenv a e000a; run pcieerr\0" \
- "pcie2err=setenv a e0009; run pcieerr\0" \
- "pcie3err=setenv a e000b; run pcieerr\0" \
- "pcie1errc=setenv a e000a; run pcieerrc\0" \
- "pcie2errc=setenv a e0009; run pcieerrc\0" \
- "pcie3errc=setenv a e000b; run pcieerrc\0"
+ "pcie1regs=setenv a e000a; run pciereg\0" \
+ "pcie2regs=setenv a e0009; run pciereg\0" \
+ "pcie3regs=setenv a e000b; run pciereg\0" \
+ "pcie1cfg=setenv b 3; run pciecfg\0" \
+ "pcie2cfg=setenv b 5; run pciecfg\0" \
+ "pcie3cfg=setenv b 0; run pciecfg\0" \
+ "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
+ "pcie2err=setenv a e0009; setenv b 5; run pcieerr\0" \
+ "pcie3err=setenv a e000b; setenv b 0; run pcieerr\0" \
+ "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" \
+ "pcie2errc=setenv a e0009; setenv b 5; run pcieerrc\0" \
+ "pcie3errc=setenv a e000b; setenv b 0; run pcieerrc\0"
#else
#define PCIE_ENV ""
#endif
@@ -514,14 +530,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#if defined(CONFIG_PCI1)
#define PCI_ENV \
"pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
- "echo e;md ${a}e00 9\0" \
+ "echo e;md ${a}e00 9\0" \
"pci1regs=setenv a e0008; run pcireg\0" \
"pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
"pci d.w $b.0 56 1\0" \
- "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
- "pci w.w $b.0 56 ffff\0" \
- "pci1err=setenv a e0008; run pcierr\0" \
- "pci1errc=setenv a e0008; run pcierrc\0"
+ "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
+ "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" \
+ "pci1err=setenv a e0008; setenv b 7; run pcierr\0" \
+ "pci1errc=setenv a e0008; setenv b 7; run pcierrc\0"
#else
#define PCI_ENV ""
#endif
@@ -541,25 +557,39 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define ENET_ENV ""
#endif
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
- "ramdiskfile=8544ds_tmt/ramdisk.uboot\0" \
- "fdtaddr=400000\0" \
- "fdtfile=8544ds_tmt/mpc8544ds.dtb\0" \
- "eoi=mw e00400b0 0\0" \
- "iack=md e00400a0 1\0" \
+ "ramdiskfile=8544ds/ramdisk.uboot\0" \
+ "dtbaddr=c00000\0" \
+ "dtbfile=8544ds/mpc8544ds.dtb\0" \
+ "bdev=sda3\0" \
+ "eoi=mw e00400b0 0\0" \
+ "iack=md e00400a0 1\0" \
"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
"md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
- "ddrregs=setenv a e0002; run ddrreg\0" \
+ "ddrregs=setenv a e0002; run ddrreg\0" \
"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
- "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
- "guregs=setenv a e00e0; run gureg\0" \
+ "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
+ "guregs=setenv a e00e0; run gureg\0" \
"ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
- "ecmregs=setenv a e0001; run ecmreg\0" \
- PCIE_ENV \
- PCI_ENV \
+ "ecmregs=setenv a e0001; run ecmreg\0" \
+ "lawregs=md e0000c08 4b\0" \
+ "lbcregs=md e0005000 36\0" \
+ "dma0regs=md e0021100 12\0" \
+ "dma1regs=md e0021180 12\0" \
+ "dma2regs=md e0021200 12\0" \
+ "dma3regs=md e0021280 12\0" \
+ PCIE_ENV \
+ PCI_ENV \
ENET_ENV
@@ -569,23 +599,23 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr - $dtbaddr"
-#define CONFIG_RAMBOOTCOMMAND \
+#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr $ramdiskaddr $dtbaddr"
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs root=/dev/sda3 rw " \
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr - $dtbaddr"
#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 680009d..6083715 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -11,7 +11,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -36,8 +36,14 @@
#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
-#define CONFIG_PCI
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_PCI /* enable any pci type devices */
+#define CONFIG_PCI1 /* PCI controller 1 */
+#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
+#undef CONFIG_RIO
+#undef CONFIG_PCI2
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
@@ -46,6 +52,7 @@
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
/*
@@ -65,16 +72,16 @@ extern unsigned long get_clock_freq(void);
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
/*
* Only possible on E500 Version 2 or newer cores.
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
-
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */
@@ -85,10 +92,14 @@ extern unsigned long get_clock_freq(void);
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
+#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
+#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
+
/*
* DDR Setup
*/
@@ -106,7 +117,6 @@ extern unsigned long get_clock_freq(void);
#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* Local Bus Definitions
*/
@@ -124,9 +134,9 @@ extern unsigned long get_clock_freq(void);
* Use GPCM = BRx[24:26] = 000
* Valid = BRx[31] = 1
*
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
- * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
*
* OR0, OR1:
* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
@@ -137,11 +147,12 @@ extern unsigned long get_clock_freq(void);
* TRLX = use relaxed timing = ORx[29] = 1
* EAD = use external address latch delay = OR[31] = 1
*
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
*/
-#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */
+#define CFG_BOOT_BLOCK 0xff000000 /* boot TLB block */
+#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */
#define CFG_BR0_PRELIM 0xff801001
#define CFG_BR1_PRELIM 0xff001001
@@ -156,7 +167,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
@@ -166,7 +177,12 @@ extern unsigned long get_clock_freq(void);
/*
* SDRAM on the Local Bus
*/
-#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
+#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
+#define CFG_LBC_CACHE_SIZE 64
+#define CFG_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */
+#define CFG_LBC_NONCACHE_SIZE 64
+
+#define CFG_LBC_SDRAM_BASE CFG_LBC_CACHE_BASE /* Localbus SDRAM */
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/*
@@ -180,14 +196,14 @@ extern unsigned long get_clock_freq(void);
* SDRAM for MSEL = BR2[24:26] = 011
* Valid = BR[31] = 1
*
- * 0 4 8 12 16 20 24 28
+ * 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
*
* FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
* FIXME: the top 17 bits of BR2.
*/
-#define CFG_BR2_PRELIM 0xf0001861
+#define CFG_BR2_PRELIM 0xf0001861
/*
* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
@@ -196,19 +212,19 @@ extern unsigned long get_clock_freq(void);
* 64MB mask for AM, OR2[0:7] = 1111 1100
* XAM, OR2[17:18] = 11
* 9 columns OR2[19-21] = 010
- * 13 rows OR2[23-25] = 100
+ * 13 rows OR2[23-25] = 100
* EAD set for extra time OR[31] = 1
*
- * 0 4 8 12 16 20 24 28
+ * 0 4 8 12 16 20 24 28
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
#define CFG_OR2_PRELIM 0xfc006901
-#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
-#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
-#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
+#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
+#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
+#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/*
* LSDMR masks
@@ -236,7 +252,7 @@ extern unsigned long get_clock_freq(void);
/*
* Common settings for all Local Bus SDRAM commands.
* At run time, either BSMA1516 (for CPU 1.1)
- * or BSMA1617 (for CPU 1.0) (old)
+ * or BSMA1617 (for CPU 1.0) (old)
* is OR'ed in too.
*/
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
@@ -256,61 +272,63 @@ extern unsigned long get_clock_freq(void);
* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
* port-size = 8-bits = BR[19:20] = 01
* no parity checking = BR[21:22] = 00
- * GPMC for MSEL = BR[24:26] = 000
- * Valid = BR[31] = 1
+ * GPMC for MSEL = BR[24:26] = 000
+ * Valid = BR[31] = 1
*
- * 0 4 8 12 16 20 24 28
+ * 0 4 8 12 16 20 24 28
* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
*
* For OR3, need:
- * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
+ * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
* disable buffer ctrl OR[19] = 0
- * CSNT OR[20] = 1
- * ACS OR[21:22] = 11
- * XACS OR[23] = 1
+ * CSNT OR[20] = 1
+ * ACS OR[21:22] = 11
+ * XACS OR[23] = 1
* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
- * SETA OR[28] = 0
- * TRLX OR[29] = 1
- * EHTR OR[30] = 1
- * EAD extra time OR[31] = 1
+ * SETA OR[28] = 0
+ * TRLX OR[29] = 1
+ * EHTR OR[30] = 1
+ * EAD extra time OR[31] = 1
*
- * 0 4 8 12 16 20 24 28
+ * 0 4 8 12 16 20 24 28
* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
*/
#define CADMUS_BASE_ADDR 0xf8000000
-#define CFG_BR3_PRELIM 0xf8000801
-#define CFG_OR3_PRELIM 0xfff00ff7
+#define CFG_BR3_PRELIM 0xf8000801
+#define CFG_OR3_PRELIM 0xfff00ff7
#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
-#define CONFIG_CONS_INDEX 2
+#define CONFIG_CONS_INDEX 2
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
-#define CFG_BAUDRATE_TABLE \
+#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
-#ifdef CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
@@ -318,9 +336,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8548@0"
#define OF_SOC "soc8548@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -331,55 +346,74 @@ extern unsigned long get_clock_freq(void);
*/
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
+#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
+
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
-#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
+#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
-#define CFG_PCI2_MEM_BASE 0x90000000
+#ifdef CONFIG_PCI2
+#define CFG_PCI2_MEM_BASE 0xa0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI2_IO_BASE 0x00000000
#define CFG_PCI2_IO_PHYS 0xe2800000
-#define CFG_PCI2_IO_SIZE 0x00800000 /* 8M */
+#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
+#endif
-#define CFG_PEX_MEM_BASE 0xa0000000
-#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE
-#define CFG_PEX_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PEX_IO_BASE 0x00000000
-#define CFG_PEX_IO_PHYS 0xe3000000
-#define CFG_PEX_IO_SIZE 0x01000000 /* 16M */
+#ifdef CONFIG_PCIE1
+#define CFG_PCIE1_MEM_BASE 0xa0000000
+#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCIE1_IO_BASE 0x00000000
+#define CFG_PCIE1_IO_PHYS 0xe3000000
+#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
+#endif
+#ifdef CONFIG_RIO
/*
* RapidIO MMU
*/
#define CFG_RIO_MEM_BASE 0xC0000000
#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */
+#endif
+
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_85XX_PCI2
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
#endif /* CONFIG_PCI */
@@ -387,18 +421,18 @@ extern unsigned long get_clock_freq(void);
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
-#define CONFIG_MPC85XX_TSEC3 1
-#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2"
-#undef CONFIG_MPC85XX_TSEC4
-#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3"
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC1"
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC2"
+#define CONFIG_TSEC4
+#define CONFIG_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
@@ -410,10 +444,14 @@ extern unsigned long get_clock_freq(void);
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#define TSEC4_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
/* Options are: eTSEC[0-3] */
#define CONFIG_ETHPRIME "eTSEC0"
-
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#endif /* CONFIG_TSEC_ENET */
/*
@@ -427,19 +465,28 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
+ #define CONFIG_CMD_PCI
#endif
-#include <cmd_confdefs.h>
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -449,7 +496,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -464,12 +511,12 @@ extern unsigned long get_clock_freq(void);
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -481,7 +528,7 @@ extern unsigned long get_clock_freq(void);
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -492,58 +539,154 @@ extern unsigned long get_clock_freq(void);
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
+#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
+#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
#define CONFIG_HAS_ETH3
-#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
+#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
-#define CONFIG_IPADDR 192.168.1.253
+#define CONFIG_IPADDR 192.168.1.253
-#define CONFIG_HOSTNAME unknown
-#define CONFIG_ROOTPATH /nfsroot
-#define CONFIG_BOOTFILE your.uImage
+#define CONFIG_HOSTNAME unknown
+#define CONFIG_ROOTPATH /nfsroot
+#define CONFIG_BOOTFILE 8548cds/uImage.uboot
+#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
-#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
+#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
-#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
#define CONFIG_BAUDRATE 115200
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS1\0" \
- "ramdiskaddr=600000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0" \
- "fdtaddr=400000\0" \
- "fdtfile=your.fdt.dtb\0"
+#if defined(CONFIG_PCIE1)
+#define PCIE_ENV \
+ "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
+ "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
+ "pcieerr=md ${a}020 1; md ${a}e00 e; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
+ "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
+ "pci d $b.0 130 1\0" \
+ "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;" \
+ "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;"\
+ "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
+ "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
+ "pcie1regs=setenv a e000a; run pciereg\0" \
+ "pcie1cfg=setenv b 3; run pciecfg\0" \
+ "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
+ "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0"
+#else
+#define PCIE_ENV ""
+#endif
+
+#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
+#define PCI_ENV \
+ "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
+ "echo e;md ${a}e00 9\0" \
+ "pcierr=md ${a}e00 8; pci d.b $b.0 7 1;pci d.w $b.0 1e 1;" \
+ "pci d.w $b.0 56 1\0" \
+ "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
+ "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0"
+#else
+#define PCI_ENV ""
+#endif
+
+#if defined(CONFIG_PCI1)
+#define PCI_ENV1 \
+ "pci1regs=setenv a e0008; run pcireg\0" \
+ "pci1err=setenv a e0008; setenv b 0; run pcierr\0" \
+ "pci1errc=setenv a e0008; setenv b 0; run pcierrc\0"
+#else
+#define PCI_ENV1 ""
+#endif
+
+#if defined(CONFIG_PCI2)
+#define PCI_ENV2 \
+ "pci2regs=setenv a e0009; run pcireg\0" \
+ "pci2err=setenv a e0009; setenv b 123; run pcierr\0" \
+ "pci2errc=setenv a e0009; setenv b 123; run pcierrc\0"
+#else
+#define PCI_ENV2 ""
+#endif
+#if defined(CONFIG_TSEC_ENET)
+#define ENET_ENV \
+ "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \
+ "md ${a}098 2\0" \
+ "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \
+ "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \
+ "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \
+ "echo mib;md ${a}680 31\0" \
+ "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \
+ "enet1regs=setenv a e0024; run enetreg\0" \
+ "enet2regs=setenv a e0025; run enetreg\0" \
+ "enet3regs=setenv a e0026; run enetreg\0" \
+ "enet4regs=setenv a e0027; run enetreg\0"
+#else
+#define ENET_ENV ""
+#endif
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "consoledev=ttyS1\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=mpc8548cds.dtb\0" \
+ "eoi=mw e00400b0 0\0" \
+ "iack=md e00400a0 1\0" \
+ "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
+ "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
+ "ddrregs=setenv a e0002; run ddrreg\0" \
+ "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
+ "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
+ "guregs=setenv a e00e0; run gureg\0" \
+ "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
+ "ecmregs=setenv a e0001; run ecmreg\0" \
+ "lawregs=md e0000c08 4b\0" \
+ "lbcregs=md e0005000 36\0" \
+ "dma0regs=md e0021100 12\0" \
+ "dma1regs=md e0021180 12\0" \
+ "dma2regs=md e0021200 12\0" \
+ "dma3regs=md e0021280 12\0" \
+ PCIE_ENV \
+ PCI_ENV \
+ PCI_ENV1 \
+ PCI_ENV2 \
+ ENET_ENV
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "bootm $loadaddr $ramdiskaddr"
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 4c8b4e7..1d1b7c9 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -312,9 +312,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8555@0"
#define OF_SOC "soc8555@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -350,6 +347,13 @@ extern unsigned long get_clock_freq(void);
#define CFG_PCI2_IO_PHYS 0xe2100000
#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
#if defined(CONFIG_PCI)
@@ -373,17 +377,16 @@ extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
-#undef CONFIG_MPC85XX_FEC
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
-#define FEC_PHY_ADDR 3
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
-#define FEC_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
@@ -401,19 +404,28 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
+ #define CONFIG_CMD_PCI
#endif
-#include <cmd_confdefs.h>
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -423,7 +435,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -443,7 +455,7 @@ extern unsigned long get_clock_freq(void);
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -455,7 +467,7 @@ extern unsigned long get_clock_freq(void);
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -466,6 +478,7 @@ extern unsigned long get_clock_freq(void);
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 21e6637..a8f362f 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -43,9 +43,7 @@
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#undef CONFIG_TSEC_ENET /* tsec ethernet support */
-#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
-#define CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
+#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
@@ -294,9 +292,6 @@
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8560@0"
#define OF_SOC "soc8560@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -349,29 +344,33 @@
#endif /* CONFIG_PCI */
-#if defined(CONFIG_TSEC_ENET)
+#ifdef CONFIG_TSEC_ENET
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
+#ifndef CONFIG_MII
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
-#undef CONFIG_MPC85XX_FEC
+#endif
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
-#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
+#endif /* CONFIG_TSEC_ENET */
+
+#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
-#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
#undef CONFIG_ETHER_NONE /* define if ether on something else */
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
@@ -392,7 +391,10 @@
#define FETH3_RST 0x80
#endif /* CONFIG_ETHER_INDEX */
-#define CONFIG_MII /* MII PHY management */
+#ifndef CONFIG_MII
+#define CONFIG_MII 1 /* MII PHY management */
+#endif
+
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
/*
@@ -432,46 +434,36 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_ETHER_ON_FCC)
+ #define CONFIG_CMD_MII
+#endif
+
#if defined(CFG_RAMBOOT)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
- #elif defined(CONFIG_TSEC_ENET)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C) \
- & ~(CFG_CMD_ENV))
- #elif defined(CONFIG_ETHER_ON_FCC)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- | CFG_CMD_I2C) \
- & ~(CFG_CMD_ENV))
- #endif
-#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #elif defined(CONFIG_TSEC_ENET)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #elif defined(CONFIG_ETHER_ON_FCC)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #endif
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -482,7 +474,7 @@
#define CFG_LOAD_ADDR 0x1000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -503,7 +495,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -515,7 +507,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -527,6 +519,7 @@
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
@@ -553,9 +546,11 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=400000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0"
+ "consoledev=ttyCPM\0" \
+ "ramdiskaddr=1000000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=mpc8560ads.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
@@ -563,14 +558,16 @@
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "bootm $loadaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
- "bootm $loadaddr $ramdiskaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 3f65644..ba744e9 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -28,20 +28,21 @@
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
#define CONFIG_MPC8568 1 /* MPC8568 specific */
#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
-#undef CONFIG_PCI
+#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
/*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */
/*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */
-/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */
+/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
@@ -62,9 +63,9 @@ extern unsigned long get_clock_freq(void);
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-/*#define CONFIG_L2_CACHE*/ /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
/*
* Only possible on E500 Version 2 or newer cores.
@@ -292,11 +293,9 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8568@0"
#define OF_SOC "soc8568@e0000000"
+#define OF_QE "qe@e0080000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600"
@@ -306,11 +305,14 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_EEPROM_ADDR 0x57
+#define CFG_I2C_EEPROM_ADDR 0x52
#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
+#define CFG_I2C2_OFFSET 0x3100
/*
* General PCI
@@ -318,7 +320,7 @@ extern unsigned long get_clock_freq(void);
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
@@ -337,6 +339,44 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#ifdef CONFIG_QE
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#ifndef CONFIG_TSEC_ENET
+#define CONFIG_ETHPRIME "FSL UEC0"
+#endif
+#define CONFIG_PHY_MODE_NEED_CHANGE
+#define CONFIG_eTSEC_MDIO_BUS
+
+#ifdef CONFIG_eTSEC_MDIO_BUS
+#define CONFIG_MIIM_ADDRESS 0xE0024520
+#endif
+
+#define CONFIG_UEC_ETH1 /* GETH1 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CFG_UEC1_UCC_NUM 0 /* UCC1 */
+#define CFG_UEC1_RX_CLK QE_CLK_NONE
+#define CFG_UEC1_TX_CLK QE_CLK16
+#define CFG_UEC1_ETH_TYPE GIGA_ETH
+#define CFG_UEC1_PHY_ADDR 7
+#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
+#endif
+
+#define CONFIG_UEC_ETH2 /* GETH2 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CFG_UEC2_UCC_NUM 1 /* UCC2 */
+#define CFG_UEC2_RX_CLK QE_CLK_NONE
+#define CFG_UEC2_TX_CLK QE_CLK16
+#define CFG_UEC2_ETH_TYPE GIGA_ETH
+#define CFG_UEC2_PHY_ADDR 1
+#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
+#endif
+#endif /* CONFIG_QE */
+
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -345,21 +385,17 @@ extern unsigned long get_clock_freq(void);
#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
+#if defined(CONFIG_TSEC_ENET)
+
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
-#undef CONFIG_MPC85XX_TSEC3
-#undef CONFIG_MPC85XX_TSEC4
-#undef CONFIG_MPC85XX_FEC
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC1"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 3
@@ -367,7 +403,10 @@ extern unsigned long get_clock_freq(void);
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
-/* Options are: eTSEC[0-3] */
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+
+/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME "eTSEC0"
#endif /* CONFIG_TSEC_ENET */
@@ -383,19 +422,29 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
+ #define CONFIG_CMD_PCI
#endif
-#include <cmd_confdefs.h>
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -405,7 +454,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -425,7 +474,7 @@ extern unsigned long get_clock_freq(void);
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -437,7 +486,7 @@ extern unsigned long get_clock_freq(void);
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -447,12 +496,15 @@ extern unsigned long get_clock_freq(void);
*/
/* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
#define CONFIG_IPADDR 192.168.1.253
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index bbe3505..7d8a380 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -46,8 +46,10 @@
#define CFG_RESET_ADDRESS 0xfff00100
-/*#undef CONFIG_PCI*/
-#define CONFIG_PCI
+#define CONFIG_PCI 1 /* Enable PCI/PCIE */
+#define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */
+#define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@@ -76,6 +78,9 @@
#define L2_ENABLE (L2CR_L2E)
#ifndef CONFIG_SYS_CLK_FREQ
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
#endif
@@ -93,6 +98,9 @@
#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
+#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
+
/*
* DDR Setup
*/
@@ -177,6 +185,7 @@
#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
+#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
@@ -232,7 +241,7 @@
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 1
@@ -260,9 +269,6 @@
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8641@0"
#define OF_SOC "soc8641@f8000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
@@ -296,9 +302,9 @@
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI1_IO_BASE 0xe2000000
-#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xe2000000
+#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
/* PCI view of System Memory */
#define CFG_PCI_MEMORY_BUS 0x00000000
@@ -311,10 +317,10 @@
#define CFG_PCI2_MEM_BASE 0xa0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
-#define CFG_PCI2_IO_BASE 0xe3000000
-#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
-#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI2_IO_BASE 0x00000000
+#define CFG_PCI2_IO_PHYS 0xe3000000
+#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
#if defined(CONFIG_PCI)
@@ -330,12 +336,43 @@
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
+/************************************************************
+ * USB support
+ ************************************************************/
+#define CONFIG_PCI_OHCI 1
+#define CONFIG_USB_OHCI_NEW 1
+#define CONFIG_USB_KEYBOARD 1
+#define CFG_DEVICE_DEREGISTER
+#define CFG_USB_EVENT_POLL 1
+#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET CFG_PCI2_IO_PHYS
+
+/*PCI video card used*/
+/*#define VIDEO_IO_OFFSET CFG_PCI1_IO_PHYS*/
+
+/* video */
+#define CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_BIOSEMU
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+/*#define CONFIG_CONSOLE_CURSOR*/
+#define CFG_ISA_IO_BASE_ADDRESS CFG_PCI2_IO_PHYS
+#endif
+
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
@@ -349,6 +386,8 @@
#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
#endif
+#define CONFIG_MPC86XX_PCI2
+
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
@@ -359,14 +398,14 @@
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC86XX_TSEC1 1
-#define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1"
-#define CONFIG_MPC86XX_TSEC2 1
-#define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2"
-#define CONFIG_MPC86XX_TSEC3 1
-#define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3"
-#define CONFIG_MPC86XX_TSEC4 1
-#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4"
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC3"
+#define CONFIG_TSEC4 1
+#define CONFIG_TSEC4_NAME "eTSEC4"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
@@ -376,6 +415,10 @@
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#define TSEC4_PHYIDX 0
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define CONFIG_ETHPRIME "eTSEC1"
@@ -396,20 +439,20 @@
* 0xa000_0000 512M PCI-Express 2 Memory
* Changed it for operating from 0xd0000000
*/
-#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \
+#define CFG_DBAT1L ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_DBAT1U (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
+#define CFG_IBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT1U CFG_DBAT1U
/*
* BAT2 512M Cache-inhibited, guarded
* 0xc000_0000 512M RapidIO Memory
*/
-#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \
+#define CFG_DBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
-#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_DBAT2U (CFG_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT2U CFG_DBAT2U
/*
@@ -428,10 +471,10 @@
* 0xe300_0000 16M PCI-Express 2 I/0
* Note that this is at 0xe0000000
*/
-#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \
+#define CFG_DBAT4L ( CFG_PCI1_IO_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_DBAT4U (CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT4U CFG_DBAT4U
/*
@@ -463,8 +506,8 @@
*/
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
- #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
- #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x60000)
+ #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
@@ -475,39 +518,34 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+
#if defined(CFG_RAMBOOT)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C \
- | CFG_CMD_SCSI \
- | CFG_CMD_EXT2) \
- & \
- ~(CFG_CMD_ENV))
- #else
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV))
- #endif
-#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_SCSI \
- | CFG_CMD_EXT2)
- #else
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #endif
+ #undef CONFIG_CMD_ENV
+#endif
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+ #define CONFIG_CMD_SCSI
+ #define CONFIG_CMD_EXT2
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -518,7 +556,7 @@
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -539,8 +577,8 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#if defined(CONFIG_CMD_KGDB)
+ #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
/*
@@ -551,9 +589,9 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#if defined(CONFIG_CMD_KGDB)
+ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
@@ -568,6 +606,7 @@
#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
+#define CONFIG_HAS_ETH0 1
#define CONFIG_HAS_ETH1 1
#define CONFIG_HAS_ETH2 1
#define CONFIG_HAS_ETH3 1
@@ -577,6 +616,7 @@
#define CONFIG_HOSTNAME unknown
#define CONFIG_ROOTPATH /opt/nfsroot
#define CONFIG_BOOTFILE uImage
+#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
@@ -592,10 +632,17 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=your.ramdisk.u-boot\0" \
- "dtbaddr=400000\0" \
+ "dtbaddr=c00000\0" \
"dtbfile=mpc8641_hpcn.dtb\0" \
"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h
index da52e0e..f8cf01e 100644
--- a/include/configs/MUSENKI.h
+++ b/include/configs/MUSENKI.h
@@ -52,11 +52,20 @@
#define CONFIG_BOOTDELAY 5
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
/*
@@ -280,7 +289,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h
index 88eefa1..0defafe 100644
--- a/include/configs/MVBLUE.h
+++ b/include/configs/MVBLUE.h
@@ -76,15 +76,44 @@
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_RESET_TO_RETRY 60
-#define CONFIG_COMMANDS ( CFG_CMD_ASKENV | CFG_CMD_BOOTD | CFG_CMD_CACHE | CFG_CMD_DHCP | \
- CFG_CMD_ECHO | CFG_CMD_ENV | CFG_CMD_FLASH | CFG_CMD_IMI | \
- CFG_CMD_IRQ | CFG_CMD_NET | CFG_CMD_PCI | CFG_CMD_RUN )
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_RUN
-#define CONFIG_BOOTP_MASK ( 0xffffffff )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NISDOMAIN
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_TIMEOFFSET
+
/*
* Miscellaneous configurable options
@@ -310,7 +339,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h
index 5995918..75efd1e 100644
--- a/include/configs/MVS1.h
+++ b/include/configs/MVS1.h
@@ -63,27 +63,36 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_VENDOREX )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_VENDOREX
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-/* MVsensor uses a really minimal U-Boot ! */
-#define CONFIG_COMMANDS (CFG_CMD_LOADS | \
- CFG_CMD_LOADB | \
- CFG_CMD_IMI | \
- CFG_CMD_FLASH | \
- CFG_CMD_MEMORY | \
- CFG_CMD_NET | \
- CFG_CMD_DHCP | \
- CFG_CMD_ENV | \
- CFG_CMD_BOOTD | \
- CFG_CMD_RUN )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_RUN
+
/*
* Miscellaneous configurable options
@@ -96,7 +105,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -172,7 +181,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/NC650.h b/include/configs/NC650.h
index a12c8da..c051a35 100644
--- a/include/configs/NC650.h
+++ b/include/configs/NC650.h
@@ -85,7 +85,15 @@
#undef CONFIG_STATUS_LED /* Status LED disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
#define FEC_ENET
@@ -134,25 +142,28 @@
#define CONFIG_RTC_PCF8563
#define CFG_I2C_RTC_ADDR 0x51
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_NAND | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -230,7 +241,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h
index 444f721..bb3d19d 100644
--- a/include/configs/NETPHONE.h
+++ b/include/configs/NETPHONE.h
@@ -82,7 +82,15 @@
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
@@ -105,20 +113,22 @@
#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_NAND | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_MII | \
- CFG_CMD_CDP \
- )
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_CDP
+
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
@@ -128,7 +138,7 @@
#define CFG_HUSH_PARSER 1
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -220,7 +230,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
index 25b6345..19743c0 100644
--- a/include/configs/NETTA.h
+++ b/include/configs/NETTA.h
@@ -77,7 +77,16 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
+
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
@@ -111,26 +120,28 @@
CFG_POST_CODEC | \
CFG_POST_DSP )
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_CDP | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_FAT | \
- CFG_CMD_IDE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_NAND | \
- CFG_CMD_NFS | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_PING | \
- 0)
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_PING
+
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
@@ -140,7 +151,7 @@
#define CFG_HUSH_PARSER 1
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -223,7 +234,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h
index e20e724..fb8085d 100644
--- a/include/configs/NETTA2.h
+++ b/include/configs/NETTA2.h
@@ -82,7 +82,16 @@
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
+
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
@@ -105,20 +114,22 @@
#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_NAND | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_MII | \
- CFG_CMD_CDP \
- )
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_CDP
+
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
@@ -128,7 +139,7 @@
#define CFG_HUSH_PARSER 1
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -220,7 +231,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h
index e30be09..d4cb9e7 100644
--- a/include/configs/NETVIA.h
+++ b/include/configs/NETVIA.h
@@ -81,35 +81,45 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
+
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS_BASE ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING )
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
-#define CONFIG_COMMANDS (CONFIG_COMMANDS_BASE | CFG_CMD_NAND)
-#else
-#define CONFIG_COMMANDS CONFIG_COMMANDS_BASE
+#define CONFIG_CMD_NAND
#endif
+
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -192,7 +202,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h
index d994420..4cd4472 100644
--- a/include/configs/NSCU.h
+++ b/include/configs/NSCU.h
@@ -84,7 +84,15 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -93,16 +101,19 @@
#define CONFIG_ISP1362_USB /* ISP1362 USB OTG controller */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
@@ -117,7 +128,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -201,7 +212,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/NX823.h b/include/configs/NX823.h
index 1cb8b8f..524aa06 100644
--- a/include/configs/NX823.h
+++ b/include/configs/NX823.h
@@ -55,22 +55,35 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled, for now */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_AUTOSCRIPT)
#define CONFIG_AUTOSCRIPT
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_AUTOSCRIPT
+
+
/* call various generic functions */
#define CONFIG_MISC_INIT_R
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -152,7 +165,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h
index aa9d1ba..5840ea2 100644
--- a/include/configs/OCRTC.h
+++ b/include/configs/OCRTC.h
@@ -54,20 +54,32 @@
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ASKENV | \
- CFG_CMD_ELF | \
- CFG_CMD_BSP | \
- CFG_CMD_EEPROM )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
@@ -77,7 +89,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -215,7 +227,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h
index 2e7c505..937df22 100644
--- a/include/configs/ORSG.h
+++ b/include/configs/ORSG.h
@@ -54,20 +54,32 @@
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ASKENV | \
- CFG_CMD_ELF | \
- CFG_CMD_BSP | \
- CFG_CMD_EEPROM )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
@@ -77,7 +89,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -213,7 +225,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/OXC.h b/include/configs/OXC.h
index 787407c..8d61bcd 100644
--- a/include/configs/OXC.h
+++ b/include/configs/OXC.h
@@ -51,10 +51,23 @@
#define CONFIG_BAUDRATE 9600
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+
/*
* Miscellaneous configurable options
@@ -299,7 +312,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h
index a933e1b..ef970f1 100644
--- a/include/configs/P3G4.h
+++ b/include/configs/P3G4.h
@@ -120,30 +120,40 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_ALTIVEC /* undef to disable */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_ELF | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_UNIVERSE| \
- CFG_CMD_BSP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_UNIVERSE
+#define CONFIG_CMD_BSP
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -396,7 +406,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/PATI.h b/include/configs/PATI.h
index d88fff3..0de7591 100644
--- a/include/configs/PATI.h
+++ b/include/configs/PATI.h
@@ -39,14 +39,35 @@
#define CONFIG_BAUDRATE 9600
-#define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | \
- CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ENV | CFG_CMD_REGINFO | \
- CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_RUN | CFG_CMD_BSP | \
- CFG_CMD_IMI | CFG_CMD_EEPROM | CFG_CMD_IRQ | CFG_CMD_MISC \
-)
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MISC
+
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
@@ -71,7 +92,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "pati=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
index 027dd22..d6e7082 100644
--- a/include/configs/PCI405.h
+++ b/include/configs/PCI405.h
@@ -68,17 +68,29 @@
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_BSP | \
- CFG_CMD_EEPROM )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -97,7 +109,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -244,7 +256,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h
index 3a7f7f0..24b25d9 100644
--- a/include/configs/PCI5441.h
+++ b/include/configs/PCI5441.h
@@ -122,22 +122,32 @@
#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
-/*------------------------------------------------------------------------
- * COMMANDS
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_ECHO | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMI | \
- CFG_CMD_IRQ | \
- CFG_CMD_LOADS | \
- CFG_CMD_LOADB | \
- CFG_CMD_MEMORY | \
- CFG_CMD_MISC | \
- CFG_CMD_RUN | \
- CFG_CMD_SAVES )
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVES
+
/*------------------------------------------------------------------------
* MISC
diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h
index 3a97fbc..268b034 100644
--- a/include/configs/PCIPPC2.h
+++ b/include/configs/PCIPPC2.h
@@ -53,30 +53,37 @@
#define CONFIG_PREBOOT ""
#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DOC | \
- CFG_CMD_ELF | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_SNTP )
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SNTP
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-#include <cmd_confdefs.h>
-
#define CFG_NAND_LEGACY
/*
@@ -223,7 +230,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h
index 130beb7..250b586 100644
--- a/include/configs/PCIPPC6.h
+++ b/include/configs/PCIPPC6.h
@@ -53,32 +53,39 @@
#define CONFIG_PREBOOT ""
#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DOC | \
- CFG_CMD_ELF | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_SCSI | \
- CFG_CMD_SNTP )
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_SNTP
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-#include <cmd_confdefs.h>
-
#define CFG_NAND_LEGACY
/*
@@ -225,7 +232,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index 806e95f..efa0157 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -40,33 +40,42 @@
***********************************************************/
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
-/***********************************************************
- * Command definitions
- ***********************************************************/
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | \
- CFG_CMD_IDE | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_CACHE | \
- CFG_CMD_IRQ | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_REGINFO | \
- CFG_CMD_FDC | \
- CFG_CMD_SCSI | \
- CFG_CMD_FAT | \
- CFG_CMD_DATE | \
- CFG_CMD_ELF | \
- CFG_CMD_USB | \
- CFG_CMD_MII | \
- CFG_CMD_SDRAM | \
- CFG_CMD_DOC | \
- CFG_CMD_PING | \
- CFG_CMD_SAVES | \
- CFG_CMD_BSP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_FDC
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_BSP
+
#define CFG_NAND_LEGACY
@@ -150,7 +159,7 @@
**********************************************************/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -227,7 +236,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -366,7 +375,7 @@
/************************************************************
* Debug support
************************************************************/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h
index 83a7ec2..d90351a 100644
--- a/include/configs/PK1C20.h
+++ b/include/configs/PK1C20.h
@@ -160,30 +160,41 @@
#define CONFIG_IPADDR 192.168.2.21
#define CONFIG_SERVERIP 192.168.2.16
-/*------------------------------------------------------------------------
- * COMMANDS
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMI | \
- CFG_CMD_IRQ | \
- CFG_CMD_LOADS | \
- CFG_CMD_LOADB | \
- CFG_CMD_MEMORY | \
- CFG_CMD_MISC | \
- CFG_CMD_NET | \
- CFG_CMD_PING | \
- CFG_CMD_RUN | \
- CFG_CMD_SAVES )
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVES
+
/*------------------------------------------------------------------------
* COMPACT FLASH
*----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(CONFIG_CMD_IDE)
#define CONFIG_IDE_PREINIT /* Implement id_preinit */
#define CFG_IDE_MAXBUS 1 /* 1 IDE bus */
#define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */
@@ -201,12 +212,12 @@
#define CFG_CF_POWER 0x00900890 /* CF Power FET PIO base*/
#define CFG_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */
-#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */
+#endif
/*------------------------------------------------------------------------
* JFFS2
*----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#if defined(CONFIG_CMD_JFFS2)
#define CFG_JFFS_CUSTOM_PART /* board defined part */
#endif
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index d02c39b..652210c 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -61,19 +61,34 @@
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_ELF | \
- CFG_CMD_NAND | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -81,10 +96,6 @@
#define CONFIG_SUPPORT_VFAT
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
-#define CONFIG_AUTO_UPDATE_SHOW 1 /* use board show routine */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -104,7 +115,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -156,38 +167,18 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
@@ -264,11 +255,6 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-#endif
-
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
@@ -294,9 +280,6 @@
#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
/* total size of a CAT24WC16 is 2048 bytes */
-#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
-#define CFG_NVRAM_SIZE 242 /* NVRAM size */
-
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
@@ -305,7 +288,7 @@
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
-#if 1 /* test-only */
+
/* CAT24WC08/16... */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
@@ -313,15 +296,6 @@
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
/* 16 byte page write mode using*/
/* last 4 bits of the address */
-#else
-/* CAT24WC32/64... */
-#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
-#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
- /* 32 byte page write mode using*/
- /* last 5 bits of the address */
-#endif
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
@@ -331,7 +305,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
index 9c241e6..5ba8f4a 100644
--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -40,11 +40,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -77,12 +72,6 @@
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#undef CONFIG_NS8382X
-#define ADD_PCI_CMD CFG_CMD_PCI
-
-#else /* MPC5100 */
-
-#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
-
#endif
/* Partitions */
@@ -91,39 +80,48 @@
/* USB */
#if 1
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD 0
#endif
-#if defined(CONFIG_BOOT_ROM)
-#define ADD_DOC_CMD 0
-#else
-#define ADD_DOC_CMD CFG_CMD_DOC
+#if !defined(CONFIG_BOOT_ROM)
/* DoC requires legacy NAND for now */
#define CFG_NAND_LEGACY
#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- ADD_DOC_CMD | \
- ADD_PCI_CMD | \
- ADD_USB_CMD | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+#if !defined(CONFIG_BOOT_ROM)
+#define CONFIG_CMD_DOC
+#endif
+
+#if defined(CONFIG_MPC5200)
+#define CONFIG_CMD_PCI
+#endif
+
/*
* Autobooting
@@ -160,7 +158,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*
* I2C configuration
@@ -294,7 +292,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -310,6 +308,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/PM826.h b/include/configs/PM826.h
index 88fdb51..c80b153 100644
--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -103,8 +103,7 @@
* - CONFIG_NET_MULTI must be defined
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#define CONFIG_NET_MULTI
#undef CONFIG_ETHER_NONE /* define if ether on something else */
@@ -152,33 +151,34 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
#ifdef CONFIG_PCI
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DOC | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_SNTP )
-#else /* ! PCI */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DOC | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#endif /* CONFIG_PCI */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_CMD_PCI
+#endif
+
#define CFG_NAND_LEGACY
@@ -197,7 +197,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -345,7 +345,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/PM828.h b/include/configs/PM828.h
index 37ee977..8f5be5f 100644
--- a/include/configs/PM828.h
+++ b/include/configs/PM828.h
@@ -103,8 +103,7 @@
* - CONFIG_NET_MULTI must be defined
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#define CONFIG_NET_MULTI
#undef CONFIG_ETHER_NONE /* define if ether on something else */
@@ -152,33 +151,34 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
#ifdef CONFIG_PCI
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DOC | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_SNTP )
-#else /* ! PCI */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DOC | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#endif /* CONFIG_PCI */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_CMD_PCI
+#endif
+
/*
* Disk-On-Chip configuration
@@ -196,7 +196,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -338,7 +338,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index 4fb5440..a6a1e73 100644
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -262,23 +262,27 @@
#endif
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#define CONFIG_MPC85XX_FEC 1
#define CONFIG_MPC85XX_FEC_NAME "FEC"
#define FEC_PHY_ADDR 3
#define FEC_PHYIDX 0
+#define FEC_FLAGS 0
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
+#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1 1
#define CONFIG_HAS_ETH2 1
@@ -303,43 +307,36 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
#if defined(CFG_RAMBOOT)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
- #else
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
- #endif
-#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_EEPROM \
- | CFG_CMD_DATE \
- | CFG_CMD_MII \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #else
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_EEPROM \
- | CFG_CMD_DATE \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #endif
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -350,7 +347,7 @@
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -372,7 +369,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -384,7 +381,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index 87ab934..9a17e3d 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -258,15 +258,16 @@
#endif
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
-#undef CONFIG_MPC85XX_FEC
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#endif /* CONFIG_TSEC_ENET */
@@ -306,41 +307,35 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
#if defined(CFG_RAMBOOT)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
- #else
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
- #endif
-#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_EEPROM \
- | CFG_CMD_DATE \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #else
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_EEPROM \
- | CFG_CMD_DATE \
- | CFG_CMD_PING \
- | CFG_CMD_I2C)
- #endif
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -351,7 +346,7 @@
#define CFG_LOAD_ADDR 0x1000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -373,7 +368,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -385,7 +380,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -397,6 +392,7 @@
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:40:42:01:00:00
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:40:42:01:00:01
diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
index 6e0bd7f..b29f368 100644
--- a/include/configs/PMC405.h
+++ b/include/configs/PMC405.h
@@ -63,25 +63,37 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BSP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_I2C | \
- CFG_CMD_PING | \
- CFG_CMD_UNIVERSE | \
- CFG_CMD_EEPROM )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_UNIVERSE
+#define CONFIG_CMD_EEPROM
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
@@ -100,7 +112,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -263,7 +275,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/PN62.h b/include/configs/PN62.h
index a717659..72acf5a 100644
--- a/include/configs/PN62.h
+++ b/include/configs/PN62.h
@@ -42,15 +42,29 @@
#define CONFIG_CONS_INDEX 1
-#define REMOVE_COMMANDS ( CFG_CMD_AUTOSCRIPT | \
- CFG_CMD_LOADS | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMLS )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_BSP
+
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
-#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~REMOVE_COMMANDS) |\
- CFG_CMD_PCI |\
- CFG_CMD_BSP)
#define CONFIG_BAUDRATE 19200 /* console baudrate */
@@ -82,10 +96,6 @@
"loadp 200000; bootm"
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-
/*
* Miscellaneous configurable options
*/
@@ -287,7 +297,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index 16e2cc6..8a74c4f 100644
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -113,26 +113,38 @@
#endif
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_NAND | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_SNTP )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SNTP
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */
@@ -162,7 +174,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -417,6 +429,8 @@
#define CFG_ENV_ADDR_REDUND 0xFFFFA000
#define CFG_ENV_SIZE_REDUND 0x2000
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
#endif /* ENVIRONMENT_IN_EEPROM */
@@ -446,7 +460,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/QS823.h b/include/configs/QS823.h
index 235bc48..3657fea 100644
--- a/include/configs/QS823.h
+++ b/include/configs/QS823.h
@@ -189,27 +189,37 @@
#undef CONFIG_STATUS_LED /* Status LED disabled */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_BOOTD | \
- CFG_CMD_CONSOLE | \
- CFG_CMD_DATE | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMI | \
- CFG_CMD_IMMAP | \
- CFG_CMD_MEMORY | \
- CFG_CMD_NET | \
- CFG_CMD_RUN)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_RUN
+
/*-----------------------------------------------------------------------
* Environment variable storage is in FLASH, one sector before U-boot
@@ -228,7 +238,7 @@
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -303,7 +313,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/QS850.h b/include/configs/QS850.h
index 967582b..3db539f 100644
--- a/include/configs/QS850.h
+++ b/include/configs/QS850.h
@@ -189,27 +189,37 @@
#undef CONFIG_STATUS_LED /* Status LED disabled */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_BOOTD | \
- CFG_CMD_CONSOLE | \
- CFG_CMD_DATE | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMI | \
- CFG_CMD_IMMAP | \
- CFG_CMD_MEMORY | \
- CFG_CMD_NET | \
- CFG_CMD_RUN)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_RUN
+
/*-----------------------------------------------------------------------
* Environment variable storage is in FLASH, one sector before U-boot
@@ -228,7 +238,7 @@
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -303,7 +313,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/QS860T.h b/include/configs/QS860T.h
index 32faa61..b3442de 100644
--- a/include/configs/QS860T.h
+++ b/include/configs/QS860T.h
@@ -92,23 +92,33 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_REGINFO | \
- CFG_CMD_IMMAP | \
- CFG_CMD_ASKENV | \
- CFG_CMD_NET | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
/* TODO */
@@ -136,7 +146,7 @@ CONFIG_SPI
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -210,7 +220,7 @@ CONFIG_SPI
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h
index 82228c0..a98b4af 100644
--- a/include/configs/R360MPI.h
+++ b/include/configs/R360MPI.h
@@ -79,7 +79,14 @@
#define CONFIG_CAN_DRIVER /* CAN Driver support enabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -111,20 +118,23 @@
#define CFG_I2C_KEY_ADDR 0x9 /* Keyboard coprocessor */
#define CFG_I2C_TEM_ADDR 0x49 /* Temperature Sensors */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BMP | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_NFS | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
@@ -134,7 +144,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -223,12 +233,13 @@
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment */
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment sector */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h
index 242c837..2f6de81 100644
--- a/include/configs/RBC823.h
+++ b/include/configs/RBC823.h
@@ -79,7 +79,15 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#undef CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -94,42 +102,45 @@
#define CFG_EEPROM_WRITE_BITS 4
#define CFG_EEPROM_WRITE_DELAY_MS 10
-#define CONFIG_COMMANDS ( CFG_CMD_ALL & \
- ~CFG_CMD_BSP & \
- ~CFG_CMD_DATE & \
- ~CFG_CMD_DISPLAY& \
- ~CFG_CMD_DTT & \
- ~CFG_CMD_EXT2 & \
- ~CFG_CMD_FDC & \
- ~CFG_CMD_FDOS & \
- ~CFG_CMD_HWFLOW & \
- ~CFG_CMD_IDE & \
- ~CFG_CMD_IRQ & \
- ~CFG_CMD_JFFS2 & \
- ~CFG_CMD_MII & \
- ~CFG_CMD_MMC & \
- ~CFG_CMD_NAND & \
- ~CFG_CMD_PCI & \
- ~CFG_CMD_PCMCIA & \
- ~CFG_CMD_REISER & \
- ~CFG_CMD_SCSI & \
- ~CFG_CMD_SETGETDCR & \
- ~CFG_CMD_SNTP & \
- ~CFG_CMD_SPI & \
- ~CFG_CMD_UNIVERSE & \
- ~CFG_CMD_USB & \
- ~CFG_CMD_VFD & \
- ~CFG_CMD_XIMG )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_BSP
+#undef CONFIG_CMD_DATE
+#undef CONFIG_CMD_DISPLAY
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_EXT2
+#undef CONFIG_CMD_FDC
+#undef CONFIG_CMD_FDOS
+#undef CONFIG_CMD_HWFLOW
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_IRQ
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_MFSL
+#undef CONFIG_CMD_MMC
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_PCI
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_REISER
+#undef CONFIG_CMD_SCSI
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_SNTP
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_UNIVERSE
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_VFD
+#undef CONFIG_CMD_XIMG
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -205,7 +216,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h
index 591382c..793b1db 100644
--- a/include/configs/RPXClassic.h
+++ b/include/configs/RPXClassic.h
@@ -88,15 +88,26 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-#define CONFIG_COMMANDS ((CFG_CMD_ALL & ~CFG_CMD_NONSTD) | CFG_CMD_ELF)
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -104,7 +115,7 @@
#define CFG_RESET_ADDRESS 0x80000000
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -182,7 +193,7 @@
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFF000000
-#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || defined(CONFIG_CMD_IDE)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
@@ -222,7 +233,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h
index 48ada0e..3c5e6b8 100644
--- a/include/configs/RPXlite.h
+++ b/include/configs/RPXlite.h
@@ -62,17 +62,28 @@
#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -154,7 +165,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h
index 3102547..872765c 100644
--- a/include/configs/RPXlite_DW.h
+++ b/include/configs/RPXlite_DW.h
@@ -115,29 +115,36 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_STATUS_LED /* disturbs display. Status LED disabled. */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#if 1 /* Enable this stuff could make image enlarge about 25KB. Mask it if you
don't want the advanced function */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_DHCP
+
#ifdef CONFIG_SPLASH_SCREEN
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BMP | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_PING | \
- CFG_CMD_ELF | \
- CFG_CMD_REGINFO | \
- CFG_CMD_DHCP )
-#else
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_PING | \
- CFG_CMD_ELF | \
- CFG_CMD_REGINFO | \
- CFG_CMD_DHCP )
-#endif /* CONFIG_SPLASH_SCREEN */
+#define CONFIG_CMD_BMP
+#endif
+
/* test-only */
#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
@@ -147,16 +154,13 @@
#endif /* 1 */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "u-boot>" /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -200,7 +204,7 @@
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFF000000
-#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
@@ -239,7 +243,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h
index 45907aa..dfadd2a 100644
--- a/include/configs/RPXsuper.h
+++ b/include/configs/RPXsuper.h
@@ -91,8 +91,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
@@ -150,13 +149,28 @@
/* Monitor Command Prompt */
#define CFG_PROMPT "=> "
-/* What U-Boot subsytems do you want enabled? */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_IMMAP | \
- CFG_CMD_ASKENV | \
- CFG_CMD_I2C | \
- CFG_CMD_REGINFO & \
- ~CFG_CMD_KGDB )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
+
+#undef CONFIG_CMD_KGDB
+
/* Where do the internal registers live? */
#define CFG_IMMR 0xF0000000
@@ -176,13 +190,10 @@
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -310,7 +321,7 @@
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h
index 3885bcd..32e2285 100644
--- a/include/configs/RRvision.h
+++ b/include/configs/RRvision.h
@@ -92,7 +92,15 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -135,23 +143,26 @@
#endif /* CONFIG_SOFT_I2C */
-#define CONFIG_COMMANDS ( ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_DATE ) & \
- ~( CFG_CMD_PCMCIA | \
- CFG_CMD_IDE ) )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DATE
+
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_IDE
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -224,11 +235,13 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h
index dbc57e8..d7652fa 100644
--- a/include/configs/Rattler.h
+++ b/include/configs/Rattler.h
@@ -62,8 +62,8 @@
* SCC, 1-3 for FCC)
*
* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
- * must be defined elsewhere (as for the console), or CFG_CMD_NET must
- * be removed from CONFIG_COMMANDS to remove support for networking.
+ * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
+ * must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
@@ -125,22 +125,33 @@
#define CONFIG_BAUDRATE 38400
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_DHCP \
- | CFG_CMD_IMMAP \
- | CFG_CMD_JFFS2 \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -158,7 +169,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -184,7 +195,7 @@
#define CFG_DIRECT_FLASH_TFTP
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#if defined(CONFIG_CMD_JFFS2)
#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS
#define CFG_JFFS2_SORT_FRAGMENTS
@@ -205,7 +216,7 @@
#define MTDIDS_DEFAULT "nor0=rattler-0"
#define MTDPARTS_DEFAULT "mtdparts=rattler-0:-@1m(jffs2)"
*/
-#endif /* CFG_CMD_JFFS2 */
+#endif /* CONFIG_CMD_JFFS2 */
#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
@@ -256,7 +267,7 @@
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index f8e3397..f2c3699 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -338,28 +338,37 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV | \
- CFG_CMD_LOADS ))
- #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV))
- #endif
-#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_PING | CFG_CMD_I2C)
- #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_PING | CFG_CMD_I2C)
- #endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+ #define CONFIG_CMD_MII
+#endif
+
+#if defined(CFG_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -368,7 +377,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "SBC8540=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -389,7 +398,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -401,7 +410,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/SCM.h b/include/configs/SCM.h
index e263db6..f900968 100644
--- a/include/configs/SCM.h
+++ b/include/configs/SCM.h
@@ -133,8 +133,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*
* (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
* X.29 connector, and FCC2 is hardwired to the X.1 connector)
@@ -191,23 +190,33 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_BSP)
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_BSP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -353,7 +362,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/SL8245.h b/include/configs/SL8245.h
index 61896d0..4d9d41b 100644
--- a/include/configs/SL8245.h
+++ b/include/configs/SL8245.h
@@ -53,11 +53,22 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#include <cmd_confdefs.h>
+#define CONFIG_CMD_PCI
/*
@@ -255,7 +266,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/SM850.h b/include/configs/SM850.h
index 4977629..41a54f0 100644
--- a/include/configs/SM850.h
+++ b/include/configs/SM850.h
@@ -68,23 +68,34 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB) && defined(KGDB_DEBUG)
+#if defined(CONFIG_CMD_KGDB) && defined(KGDB_DEBUG)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -167,7 +178,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/SMN42.h b/include/configs/SMN42.h
new file mode 100644
index 0000000..a5d3d69
--- /dev/null
+++ b/include/configs/SMN42.h
@@ -0,0 +1,206 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Configuation settings for the SMN42 board from Siemens.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start u-boot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#undef CONFIG_INIT_CRITICAL /* undef for developing */
+
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
+#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */
+#define CONFIG_LPC2292
+#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
+
+#undef CONFIG_USE_IRQ /* don't need them anymore */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1 1 /* we use Serial line 1 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/* enable I2C and select the hardware/software driver */
+#undef CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+/* this would be 0xAE if E0, E1 and E2 were pulled high */
+#define CFG_I2C_SLAVE 0xA0
+#define CFG_I2C_EEPROM_ADDR (0xA0 >> 1)
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit address */
+#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+/* not used but required by devices.c */
+#define CFG_I2C_SPEED 10000
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define SCL 0x00000004 /* P0.2 */
+#define SDA 0x00000008 /* P0.3 */
+
+#define I2C_READ ((GET32(IO0PIN) & SDA) ? 1 : 0)
+#define I2C_SDA(x) { if (x) PUT32(IO0SET, SDA); else PUT32(IO0CLR, SDA); }
+#define I2C_SCL(x) { if (x) PUT32(IO0SET, SCL); else PUT32(IO0CLR, SCL); }
+#define I2C_DELAY { udelay(100); }
+#define I2C_ACTIVE { unsigned int i2ctmp; \
+ i2ctmp = GET32(IO0DIR); \
+ i2ctmp |= SDA; \
+ PUT32(IO0DIR, i2ctmp); }
+#define I2C_TRISTATE { unsigned int i2ctmp; \
+ i2ctmp = GET32(IO0DIR); \
+ i2ctmp &= ~SDA; \
+ PUT32(IO0DIR, i2ctmp); }
+#endif /* CONFIG_SOFT_I2C */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_PING
+
+
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_BOOTDELAY 5
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "SMN42 # " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x81800000 /* memtest works on */
+#define CFG_MEMTEST_END 0x83000000 /* 24 MB in SRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0x81000000 /* default load address */
+ /* for uClinux img is here*/
+
+#define CFG_SYS_CLK_FREQ 58982400 /* Hz */
+#define CFG_HZ 2048 /* decrementer freq in Hz */
+
+ /* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SRAM */
+#define PHYS_SDRAM_1 0x81000000 /* SRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB SRAM */
+
+/* This is the external flash */
+#define PHYS_FLASH_1 0x80000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/*
+ * The first entry in CFG_FLASH_BANKS_LIST is a dummy, but it must be present.
+ */
+#define CFG_FLASH_BANKS_LIST { 0, PHYS_FLASH_1 }
+#define CFG_FLASH_ADDR0 0x555
+#define CFG_FLASH_ADDR1 0x2AA
+#define CFG_FLASH_ERASE_TOUT 16384 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
+
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+
+#define CFG_ENV_IS_IN_FLASH 1
+/* The Environment Sector is in the CPU-internal flash */
+#define CFG_FLASH_BASE 0
+#define CFG_ENV_OFFSET 0x3C000
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_MMC 1
+/* we use this ethernet chip */
+#define CONFIG_ENC28J60
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h
index ae4dcc2..395c7a1 100644
--- a/include/configs/SPD823TS.h
+++ b/include/configs/SPD823TS.h
@@ -59,15 +59,29 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_COMMANDS \
-((CONFIG_CMD_DFL & ~(CFG_CMD_FLASH)) | CFG_CMD_IDE) /* no Flash, but IDE */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IDE
+
+#undef CONFIG_CMD_FLASH
+
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*----------------------------------------------------------------------*/
#define CONFIG_ETHADDR 00:D0:93:00:01:CB
@@ -82,7 +96,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -160,7 +174,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/SX1.h b/include/configs/SX1.h
index 6ed98b8..05cef87 100644
--- a/include/configs/SX1.h
+++ b/include/configs/SX1.h
@@ -93,12 +93,26 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_COMMANDS (( CONFIG_CMD_DFL | \
- CFG_CMD_I2C ) & \
- ~CFG_CMD_NET)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_I2C
+
+#undef CONFIG_CMD_NET
+
+
#include <configs/omap1510.h>
#define CONFIG_BOOTARGS "mem=16M console=ttyS0,115200n8 root=/dev/mtdblock3 rw"
diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h
index a8454d9..8f2a5ec 100644
--- a/include/configs/SXNI855T.h
+++ b/include/configs/SXNI855T.h
@@ -146,14 +146,26 @@
#define CFG_DISCOVER_PHY
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_EEPROM | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_NAND | \
- CFG_CMD_DATE)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DATE
+
#define CFG_JFFS2_SORT_FRAGMENTS
@@ -226,7 +238,7 @@
*/
#define CFG_LONGHELP /* undef to save a little memory */
#define CFG_PROMPT "=>" /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -309,7 +321,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h
index f4339ec..5bbe3c5 100644
--- a/include/configs/Sandpoint8240.h
+++ b/include/configs/Sandpoint8240.h
@@ -80,18 +80,30 @@
""
#define CONFIG_BOOTCOMMAND "run flash_self"
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_SDRAM | \
- CFG_CMD_EEPROM | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SNTP
+
#define CONFIG_DRAM_SPEED 100 /* MHz */
@@ -384,7 +396,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h
index d42bd69..a08451e 100644
--- a/include/configs/Sandpoint8245.h
+++ b/include/configs/Sandpoint8245.h
@@ -51,17 +51,28 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SNTP
/*
@@ -363,7 +374,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h
index 119bc24..dccdf0c 100644
--- a/include/configs/TASREG.h
+++ b/include/configs/TASREG.h
@@ -43,6 +43,10 @@
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
@@ -50,20 +54,34 @@
#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
- CFG_CMD_BSP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C ) & \
- ~(CFG_CMD_NET))
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+
+#undef CONFIG_CMD_NET
+
+
#define CONFIG_BOOTDELAY 3
#define CFG_PROMPT "=> "
#define CFG_LONGHELP /* undef to save memory */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h
index 8a6e5a6..1c6a9ae 100644
--- a/include/configs/TB5200.h
+++ b/include/configs/TB5200.h
@@ -42,11 +42,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -72,12 +67,6 @@
#define CFG_CONSOLE_IS_IN_ENV
#endif
-#ifdef CONFIG_VIDEO
-#define ADD_BMP_CMD CFG_CMD_BMP
-#else
-#define ADD_BMP_CMD 0
-#endif
-
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -85,7 +74,6 @@
/* USB */
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
/* POST support */
@@ -94,41 +82,51 @@
CFG_POST_I2C)
#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#else
-#define CFG_CMD_POST_DIAG 0
#endif
-/* IDE */
-#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
/*
- * Supported commands
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- ADD_BMP_CMD | \
- ADD_IDE_CMD | \
- ADD_PCI_CMD | \
- ADD_USB_CMD | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SNTP | \
- CFG_CMD_BSP)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#endif
+
+#ifdef CONFIG_POST
+#define CONFIG__CMD_DIAG
+#endif
+
#define CONFIG_TIMESTAMP /* display image timestamps */
@@ -200,17 +198,17 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
-#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@@ -394,7 +392,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -403,6 +401,11 @@
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/* Enable an alternate, more extensive memory test */
#define CFG_ALT_MEMTEST
@@ -414,8 +417,7 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
@@ -432,7 +434,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h
index f41dbd0..7240ce1 100644
--- a/include/configs/TOP5200.h
+++ b/include/configs/TOP5200.h
@@ -50,11 +50,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -81,12 +76,6 @@
# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
# define CONFIG_PCI_IO_SIZE 0x01000000
-# define ADD_PCI_CMD CFG_CMD_PCI
-
-#else /* no Evaluation board */
-
-# define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
-
#endif
/* USB */
@@ -99,49 +88,49 @@
# else
# define CONFIG_USB_CONFIG 0x00001000
# endif
-# define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
# define CONFIG_DOS_PARTITION
# define CONFIG_USB_STORAGE
-#else
-
-# define ADD_USB_CMD 0
-
#endif
/* IDE */
#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
-
-# define ADD_IDE_CMD CFG_CMD_IDE | CFG_CMD_FAT
# define CONFIG_DOS_PARTITION
+#endif
-#else
-# define ADD_IDE_CMD 0
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#endif
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- ADD_PCI_CMD | \
- ADD_USB_CMD | \
- ADD_IDE_CMD | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_REGINFO | \
- CFG_CMD_IMMAP | \
- CFG_CMD_ELF | \
- CFG_CMD_MII | \
- CFG_CMD_BEDBUG \
- )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_REGINFO
+
+#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_PCI
+#endif
+
/*
* MUST be low boot - HIGHBOOT is not supported anymore
@@ -186,7 +175,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration
@@ -336,7 +325,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -352,6 +341,12 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+
#ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */
#define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */
#define RTC(reg) (0xf0010000+reg)
diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h
index 2344b96..66f7a11 100644
--- a/include/configs/TOP860.h
+++ b/include/configs/TOP860.h
@@ -107,30 +107,28 @@
*/
#define CFG_MATCH_PARTIAL_CMD
+
/*
- * List of available monitor commands. Use the system default list
- * plus add some of the "non-standard" commands back in.
- * See ./cmd_confdefs.h
- */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_REGINFO | \
- CFG_CMD_IMMAP | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_MII | \
- CFG_CMD_BEDBUG \
- )
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_BEDBUG
+
#define CONFIG_AUTOSCRIPT 1
#define CFG_LOADS_BAUD_CHANGE 1
#undef CONFIG_LOADS_ECHO /* NO echo on for serial download */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
@@ -141,7 +139,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -239,7 +237,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
@@ -411,10 +409,11 @@
/*
* BOOTP options
*/
-#undef CONFIG_BOOTP_MASK
-#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE \
- )
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
/*
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 7069b35..e0c9d81 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -44,14 +44,9 @@
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -105,12 +100,6 @@
#define CONFIG_NS8382X 1
#endif /* CONFIG_STK52XX */
-#ifdef CONFIG_PCI
-#define ADD_PCI_CMD CFG_CMD_PCI
-#else
-#define ADD_PCI_CMD 0
-#endif
-
/*
* Video console
*/
@@ -133,11 +122,6 @@
#define CFG_CONSOLE_IS_IN_ENV
#endif /* #ifndef CONFIG_TQM5200S */
-#ifdef CONFIG_VIDEO
-#define ADD_BMP_CMD CFG_CMD_BMP
-#else
-#define ADD_BMP_CMD 0
-#endif
/* Partitions */
#define CONFIG_MAC_PARTITION
@@ -146,11 +130,17 @@
/* USB */
#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
-#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD 0
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+
+#undef CFG_USB_OHCI_BOARD_INIT
+#define CFG_USB_OHCI_CPU_INIT
+#define CFG_USB_OHCI_REGS_BASE MPC5XXX_USB
+#define CFG_USB_OHCI_SLOT_NAME "mpc5200"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+
#endif
#ifndef CONFIG_CAM5200
@@ -161,44 +151,61 @@
#endif
#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#else
-#define CFG_CMD_POST_DIAG 0
#endif
-/* IDE */
-#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) || defined(CONFIG_FO300)
-#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
-#else
-#define ADD_IDE_CMD 0
-#endif
/*
- * Supported commands
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- ADD_BMP_CMD | \
- ADD_IDE_CMD | \
- ADD_PCI_CMD | \
- ADD_USB_CMD | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SNTP | \
- CFG_CMD_BSP)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_BSP
+
+#ifdef CONFIG_VIDEO
+ #define CONFIG_CMD_BMP
+#endif
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_CMD_PCI
+#endif
+
+#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
+ #define CONFIG_CMD_IDE
+ #define CONFIG_CMD_FAT
+ #define CONFIG_CMD_EXT2
+#endif
+
+#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
+ #define CONFIG_CFG_USB
+ #define CONFIG_CFG_FAT
+#endif
+
+#ifdef CONFIG_POST
+ #define CONFIG_CMD_DIAG
+#endif
+
#define CONFIG_TIMESTAMP /* display image timestamps */
@@ -234,15 +241,21 @@
#ifndef CONFIG_CAM5200
#define CUSTOM_ENV_SETTINGS \
"bootfile=/tftpboot/tqm5200/uImage\0" \
+ "bootfile_fdt=/tftpboot/tqm5200/uImage_fdt\0" \
+ "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0"
#else
-#define CUSTOM_ENV_SETTINGS \
+#define CUSTOM_ENV_SETTINGS \
"bootfile=cam5200/uImage\0" \
"u-boot=cam5200/u-boot.bin\0" \
"setup=tftp 200000 cam5200/setup.img; autoscr 200000\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=ttyS0\0" \
+ "kernel_addr=200000\0" \
+ "fdt_addr=400000\0" \
+ "hostname=tqm5200\0" \
"netdev=eth0\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
@@ -252,13 +265,17 @@
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addcons=setenv bootargs ${bootargs} " \
- "console=ttyS0,${baudrate}\0" \
+ "console=${console},${baudrate}\0" \
"flash_self=run ramargs addip addcons;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip addcons;" \
"bootm ${kernel_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
- "bootm\0" \
+ "net_nfs=tftp ${kernel_addr} ${bootfile};" \
+ "run nfsargs addip addcons;bootm\0" \
+ "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt};" \
+ "tftp ${fdt_addr} ${fdt_file};setenv console ttyPSC0;" \
+ "run nfsargs addip addcons;" \
+ "bootm ${kernel_addr} - ${fdt_addr}\0" \
CUSTOM_ENV_SETTINGS \
"load=tftp 200000 ${u-boot}\0" \
ENV_UPDT \
@@ -269,17 +286,17 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#if defined(CFG_IPBSPEED_133) && !defined(CONFIG_CAM5200)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
+ * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
-#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@@ -556,7 +573,12 @@
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -576,8 +598,7 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
@@ -594,7 +615,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
@@ -676,4 +697,16 @@
/* Interval between registers */
#define CFG_ATA_STRIDE 4
+/*-----------------------------------------------------------------------
+ * Open firmware flat tree support
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_CPU "PowerPC,5200@0"
+#define OF_SOC "soc5200@f0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
+
#endif /* __CONFIG_H */
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index 247f705..7a38010 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -70,8 +70,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM823L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -88,34 +89,38 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
#ifdef CONFIG_SPLASH_SCREEN
-# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BMP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#else
-# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+ #define CONFIG_CMD_BMP
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -129,7 +134,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -201,6 +206,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -212,7 +219,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index 1461b5f..e8b6a80 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -70,8 +70,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM823M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -88,23 +89,34 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
@@ -118,7 +130,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -191,6 +203,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -202,7 +216,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h
index ffd5c0b..3b78323 100644
--- a/include/configs/TQM8260.h
+++ b/include/configs/TQM8260.h
@@ -167,8 +167,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*
* (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
* X.29 connector, and FCC2 is hardwired to the X.1 connector)
@@ -220,17 +219,28 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -244,7 +254,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -385,7 +395,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h
index 925bf34..50f6752 100644
--- a/include/configs/TQM8272.h
+++ b/include/configs/TQM8272.h
@@ -97,10 +97,6 @@
/* enable I2C and select the hardware/software driver */
#undef CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-#define ADD_CMD_I2C CFG_CMD_I2C | \
- CFG_CMD_DATE |\
- CFG_CMD_DTT |\
- CFG_CMD_EEPROM
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
@@ -140,7 +136,6 @@
#else
#undef CONFIG_HARD_I2C
#undef CONFIG_SOFT_I2C
-#define ADD_CMD_I2C 0
#endif
/*
@@ -177,8 +172,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*
* (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
* X.29 connector, and FCC2 is hardwired to the X.1 connector)
@@ -272,20 +266,37 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_NAND | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- ADD_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_MII | \
- CFG_CMD_PCI | \
- CFG_CMD_SNTP )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+
+#if CONFIG_I2C
+ #define CONFIG_CMD_I2C
+ #define CONFIG_CMD_DATE
+ #define CONFIG_CMD_DTT
+ #define CONFIG_CMD_EEPROM
+#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -301,7 +312,7 @@
#endif
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -392,7 +403,7 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if defined(CONFIG_CMD_NAND)
#define CFG_NAND_CS_DIST 0x80
#define CFG_NAND_UPM_WRITE_CMD_OFS 0x20
@@ -430,7 +441,7 @@
WRITE_NAND(d, addr); \
} while(0)
-#endif /* CFG_CMD_NAND */
+#endif /* CONFIG_CMD_NAND */
#define CONFIG_PCI
#ifdef CONFIG_PCI
@@ -502,7 +513,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index ed03577..0147252 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -28,9 +28,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define DEBUG
-#undef DEBUG
-
/*
* High Level Configuration Options
*/
@@ -248,14 +245,16 @@ extern int tqm834x_num_flash_banks;
#define CONFIG_NET_MULTI
#endif
-#define CONFIG_MPC83XX_TSEC1 1
-#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC83XX_TSEC2 1
-#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
@@ -281,7 +280,6 @@ extern int tqm834x_num_flash_banks;
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
-
#undef CONFIG_EEPRO100
#define CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -316,38 +314,36 @@ extern int tqm834x_num_flash_banks;
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-/* Common commands */
-#define CFG_CMD_TQM8349_COMMON CFG_CMD_DATE | CFG_CMD_I2C | CFG_CMD_DTT\
- | CFG_CMD_PING | CFG_CMD_EEPROM \
- | CFG_CMD_MII | CFG_CMD_JFFS2
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#if defined(CFG_RAMBOOT)
-#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI \
- | CFG_CMD_TQM8349_COMMON) \
- & \
- ~(CFG_CMD_ENV | CFG_CMD_LOADS))
-#else
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_TQM8349_COMMON) \
- & \
- ~(CFG_CMD_ENV | CFG_CMD_LOADS))
-#endif
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#else /* CFG_RAMBOOT */
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \
- | CFG_CMD_TQM8349_COMMON)
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_TQM8349_COMMON)
+ #define CONFIG_CMD_PCI
#endif
-#endif /* CFG_RAMBOOT */
-
-#include <cmd_confdefs.h>
+#if defined(CFG_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
+#endif
/*
* Miscellaneous configurable options
@@ -362,7 +358,7 @@ extern int tqm834x_num_flash_banks;
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -387,7 +383,7 @@ extern int tqm834x_num_flash_banks;
*/
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -495,7 +491,7 @@ extern int tqm834x_num_flash_banks;
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -505,6 +501,7 @@ extern int tqm834x_num_flash_banks;
*/
#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR D2:DA:5E:44:BC:29
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 1E:F3:40:21:92:53
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index 90ecbad..beeca63 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -66,8 +66,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM850L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -80,23 +81,33 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -110,7 +121,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -182,6 +193,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -193,7 +206,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index b3f8f8d..d5609c1 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -64,8 +64,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM850M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -78,23 +79,33 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -108,7 +119,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -181,6 +192,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -192,7 +205,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index 49aaeea..e35b5b2 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -69,8 +69,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM855L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -83,23 +84,34 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
@@ -113,7 +125,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -185,6 +197,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -196,7 +210,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index 50df49e..cd5212e 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -69,8 +69,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM855M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -116,24 +117,35 @@
#define CFG_EEPROM_PAGE_WRITE_BITS 5
#endif
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
@@ -147,7 +159,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -220,6 +232,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -231,7 +245,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index f45f3a2..6dbd392 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -94,7 +94,6 @@
*/
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
-#define CONFIG_ADD_RAM_INFO 1 /* print additional info*/
#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
/* TQM8540 & 8560 need DLL-override */
@@ -258,16 +257,20 @@
#define CONFIG_NET_MULTI 1
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#define FEC_PHY_ADDR 3
#define FEC_PHYIDX 0
+#define FEC_FLAGS 0
+#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
@@ -357,24 +360,35 @@
#define CONFIG_TIMESTAMP /* Print image info with ts */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_MII
+
#if defined(CONFIG_PCI)
-# define ADD_PCI_CMD (CFG_CMD_PCI)
-#else
-# define ADD_PCI_CMD 0
+ #define CONFIG_CMD_PCI
#endif
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP | \
- ADD_PCI_CMD | \
- CFG_CMD_I2C | \
- CFG_CMD_DATE | \
- CFG_CMD_EEPROM | \
- CFG_CMD_DTT | \
- CFG_CMD_MII | \
- CFG_CMD_PING )
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -385,7 +399,7 @@
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -406,7 +420,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
#endif
@@ -418,7 +432,7 @@
#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -435,7 +449,7 @@
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
- CFG_BOOTFILE \
+ "bootfile="CFG_BOOTFILE_PATH"\0" \
"netdev=eth0\0" \
"consdev=ttyS0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index 9be5db1..d5838db 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -69,8 +69,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM860L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -83,26 +84,37 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#define CONFIG_NETCONSOLE
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+#define CONFIG_NETCONSOLE
/*
* Miscellaneous configurable options
@@ -116,7 +128,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -188,6 +200,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -199,7 +213,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 37f6c98..684b86f 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -69,8 +69,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM860M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -83,24 +84,35 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
@@ -114,7 +126,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -187,6 +199,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -198,7 +212,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index f03690a..f09d3d1 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -72,8 +72,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM862L/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
+ "fdt_addr=40040000\0" \
+ "kernel_addr=40060000\0" \
+ "ramdisk_addr=40200000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -86,23 +87,34 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
@@ -116,7 +128,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -189,6 +201,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -200,7 +214,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index 4959340..039aa3a 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -72,8 +72,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM862M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -86,23 +87,34 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
@@ -116,7 +128,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -190,6 +202,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -201,7 +215,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index 148490b..0d77891 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -81,8 +81,9 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM866M/uImage\0" \
- "kernel_addr=40080000\0" \
- "ramdisk_addr=40180000\0" \
+ "fdt_addr=40080000\0" \
+ "kernel_addr=400A0000\0" \
+ "ramdisk_addr=40280000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -125,7 +126,15 @@
#define CFG_EEPROM_PAGE_WRITE_BITS 4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -134,16 +143,19 @@
#define CONFIG_TIMESTAMP /* but print image timestmps */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+
/*
* Miscellaneous configurable options
@@ -157,7 +169,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -230,6 +242,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -241,7 +255,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
index d470ade..f36b729 100644
--- a/include/configs/TQM885D.h
+++ b/include/configs/TQM885D.h
@@ -131,7 +131,15 @@
# define CONFIG_RTC_DS1337 1
# define CFG_I2C_RTC_ADDR 0x68
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -140,19 +148,22 @@
#define CONFIG_TIMESTAMP /* but print image timestmps */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_MII | \
- CFG_CMD_NFS | \
- CFG_CMD_PING )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+
/*
* Miscellaneous configurable options
@@ -166,7 +177,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -187,8 +198,7 @@
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
- * Enable loopw commando. This has only effect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
@@ -258,7 +268,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
@@ -478,7 +488,7 @@
#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
-#if (CONFIG_COMMANDS & CFG_CMD_MII)
+#if defined(CONFIG_CMD_MII)
#define CFG_DISCOVER_PHY
#endif
diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h
index 8175703..9edf790 100644
--- a/include/configs/Total5200.h
+++ b/include/configs/Total5200.h
@@ -48,11 +48,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -63,7 +58,6 @@
/*
* Video console
*/
-#if 1
#define CONFIG_VIDEO
#define CONFIG_VIDEO_SED13806
#define CONFIG_VIDEO_SED13806_16BPP
@@ -76,10 +70,6 @@
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
-#define ADD_VIDEO_CMD CFG_CMD_BMP
-#else
-#define ADD_VIDEO_CMD 0
-#endif
#ifdef CONFIG_MPC5200 /* MGT5100 PCI is not supported yet. */
/*
@@ -105,12 +95,9 @@
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
-#define ADD_PCI_CMD CFG_CMD_PCI
-
#else /* MGT5100 */
#define CONFIG_MII 1
-#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
#endif
@@ -119,29 +106,36 @@
#define CONFIG_DOS_PARTITION
/* USB */
-#if 1
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD 0
-#endif
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PING | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_FAT | \
- CFG_CMD_IDE | \
- ADD_VIDEO_CMD | \
- ADD_PCI_CMD | \
- ADD_USB_CMD)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#if defined(CONFIG_MPC5200)
+ #define CONFIG_CMD_PCI
+#endif
+
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
#if (TEXT_BASE == 0xFE000000) /* Boot low */
# define CFG_LOWBOOT 1
@@ -183,7 +177,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*
@@ -303,7 +297,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -319,6 +313,12 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+
/*
* Various low-level settings
*/
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 5f48a70..df6894f 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -48,27 +48,33 @@
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
-/***********************************************************
- * Command definition
- ***********************************************************/
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | \
- CFG_CMD_CACHE | \
- /*CFG_CMD_JFFS2 |*/ \
- /*CFG_CMD_NAND |*/ \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_USB | \
- CFG_CMD_REGINFO | \
- CFG_CMD_FAT | \
- CFG_CMD_DATE | \
- CFG_CMD_ELF | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_BSP)
-
-/* this must be included after the definiton of CONFIG_COMMANDS */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
+
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
@@ -145,7 +151,7 @@
#define CONFIG_IPADDR 10.0.0.110
#define CONFIG_SERVERIP 10.0.0.1
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
@@ -246,7 +252,7 @@
/*-----------------------------------------------------------------------
* NAND flash settings
*/
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if defined(CONFIG_CMD_NAND)
#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
@@ -280,6 +286,6 @@
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_MTD_NAND_ECC_JFFS2 1
-#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */
+#endif
#endif /* __CONFIG_H */
diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
index 96f3d26..14848ab 100644
--- a/include/configs/VOH405.h
+++ b/include/configs/VOH405.h
@@ -58,28 +58,40 @@
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_ELF | \
- CFG_CMD_NAND | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
@@ -98,7 +110,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -141,38 +153,18 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
+#define CFG_NAND_QUIET 1
/*-----------------------------------------------------------------------
* PCI stuff
@@ -319,7 +311,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index f2f3ea7..5512f4b 100644
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -60,24 +60,33 @@
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_BSP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -96,7 +105,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -244,7 +253,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h
index 92bade5..1405784 100644
--- a/include/configs/VoVPN-GW.h
+++ b/include/configs/VoVPN-GW.h
@@ -95,8 +95,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC
#define CONFIG_ETHER_ON_FCC
@@ -138,24 +137,34 @@
#endif
-/* configure commands */
-#define CONFIG_COMMANDS ( CFG_CMD_AUTOSCRIPT | \
- CFG_CMD_BDI | \
- CFG_CMD_CONSOLE | \
- CFG_CMD_ECHO | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMI | \
- CFG_CMD_IMLS | \
- CFG_CMD_LOADB | \
- CFG_CMD_MEMORY | \
- CFG_CMD_MISC | \
- CFG_CMD_NET | \
- CFG_CMD_PING | \
- CFG_CMD_RUN )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IMLS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+
/*
* boot options & environment
@@ -206,7 +215,7 @@
#define CFG_PROMPT "=> "
/* console i/o buffer size */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024
#else
#define CFG_CBSIZE 256
@@ -305,7 +314,7 @@
/* cache configuration */
#define CFG_CACHELINE_SIZE 32 /* for MPC8260 */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of above */
#endif
diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h
index 8dc623e..fc177fb 100644
--- a/include/configs/W7OLMC.h
+++ b/include/configs/W7OLMC.h
@@ -70,13 +70,31 @@
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \
- CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_REGINFO
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
@@ -92,7 +110,7 @@
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -277,7 +295,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */
#endif
@@ -309,7 +327,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h
index 2bd98b3..20d693f 100644
--- a/include/configs/W7OLMG.h
+++ b/include/configs/W7OLMG.h
@@ -75,14 +75,34 @@
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \
- CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO | \
- CFG_CMD_DTT)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_DTT
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
@@ -98,7 +118,7 @@
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -278,7 +298,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */
#endif
@@ -310,7 +330,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
index faf855d..656784a 100644
--- a/include/configs/WUH405.h
+++ b/include/configs/WUH405.h
@@ -60,19 +60,31 @@
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_IRQ | \
- CFG_CMD_ELF | \
- CFG_CMD_NAND | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -92,7 +104,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -133,38 +145,16 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
-#define CFG_NAND_LEGACY
-
-#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
-#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
-#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
-#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
-#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US 25
+
+#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
+
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
/*-----------------------------------------------------------------------
@@ -270,7 +260,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h
index 9b32514..611f5a6 100644
--- a/include/configs/XPEDITE1K.h
+++ b/include/configs/XPEDITE1K.h
@@ -182,25 +182,33 @@ extern void out32(unsigned int, unsigned long);
#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */
#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_I2C | \
- CFG_CMD_DATE | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_PING | \
- CFG_CMD_ELF | \
- CFG_CMD_MII | \
- CFG_CMD_DIAG | \
- CFG_CMD_FAT )
-
-/* CFG_CMD_DHCP | \ */
-/* CFG_CMD_KGDB | \ */
-
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_FAT
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -209,7 +217,7 @@ extern void out32(unsigned int, unsigned long);
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -238,7 +246,6 @@ extern void out32(unsigned int, unsigned long);
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
@@ -255,7 +262,7 @@ extern void out32(unsigned int, unsigned long);
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 440GX CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -267,7 +274,7 @@ extern void out32(unsigned int, unsigned long);
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h
index 37ef105..00c4ff0 100644
--- a/include/configs/Yukon8220.h
+++ b/include/configs/Yukon8220.h
@@ -39,12 +39,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -70,31 +64,40 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BOOTD | \
- CFG_CMD_CACHE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP )
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#define CONFIG_NET_MULTI
#define CONFIG_MII
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Autobooting
*/
@@ -293,7 +296,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -309,6 +312,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h
index a5085cf..7c1a5b9 100644
--- a/include/configs/ZPC1900.h
+++ b/include/configs/ZPC1900.h
@@ -55,8 +55,8 @@
* SCC, 1-3 for FCC)
*
* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
- * must be defined elsewhere (as for the console), or CFG_CMD_NET must
- * be removed from CONFIG_COMMANDS to remove support for networking.
+ * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
+ * must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
@@ -106,22 +106,33 @@
#define CONFIG_BAUDRATE 38400
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_ASKENV \
- | CFG_CMD_DHCP \
- | CFG_CMD_IMMAP \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "dhcp;bootm" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=:::::eth0:dhcp"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -139,7 +150,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -223,7 +234,7 @@
#endif
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -248,18 +259,18 @@
#define CFG_LSRT 0x0F
#define CFG_MPTPR 0x4000
-#define CFG_PSDRAM_BR CFG_SDRAM_BASE | 0x00000041
+#define CFG_PSDRAM_BR (CFG_SDRAM_BASE | 0x00000041)
#define CFG_PSDRAM_OR 0xFC0028C0
-#define CFG_LSDRAM_BR CFG_LSDRAM_BASE | 0x00001861
+#define CFG_LSDRAM_BR (CFG_LSDRAM_BASE | 0x00001861)
#define CFG_LSDRAM_OR 0xFF803480
-#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00000801
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00000801)
#define CFG_OR0_PRELIM 0xFFE00856
-#define CFG_BR5_PRELIM CFG_EEPROM | 0x00000801
+#define CFG_BR5_PRELIM (CFG_EEPROM | 0x00000801)
#define CFG_OR5_PRELIM 0xFFFF03F6
-#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00001801
+#define CFG_BR6_PRELIM (CFG_FLSIMM_BASE | 0x00001801)
#define CFG_OR6_PRELIM 0xFF000856
-#define CFG_BR7_PRELIM CFG_BCSR | 0x00000801
+#define CFG_BR7_PRELIM (CFG_BCSR | 0x00000801)
#define CFG_OR7_PRELIM 0xFFFF83F6
#define CFG_RESET_ADDRESS 0xC0000000
diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h
index f163d00..5ba8d1a 100644
--- a/include/configs/ZUMA.h
+++ b/include/configs/ZUMA.h
@@ -101,17 +101,29 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_ALTIVEC /* undef to disable */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_MII /* enable MII commands */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BSP | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_DATE)
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+
/*
* JFFS2 partitions
@@ -131,15 +143,12 @@
#define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
*/
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -349,7 +358,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index 35b6a51..e3f6e2c 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -34,7 +34,9 @@
#define CONFIG_ACADIA 1 /* Board is Acadia */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
-#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
+/* Detect Acadia PLL input clock automatically via CPLD bit */
+#define CONFIG_SYS_CLK_FREQ ((in8(CFG_CPLD_BASE + 0) == 0x0c) ? \
+ 66666666 : 33333000)
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */
@@ -73,7 +75,7 @@
#define CFG_TEMP_STACK_OCM 1 /* OCM as init ram */
/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR 0xF8000000
+#define CFG_OCM_DATA_ADDR 0xf8000000
#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
@@ -107,6 +109,7 @@
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
@@ -120,6 +123,10 @@
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#else
+#define CFG_NO_FLASH 1 /* No NOR on Acadia when NAND-booting */
+#endif
+
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
@@ -130,6 +137,63 @@
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
+/*
+ * IPL (Initial Program Loader, integrated inside CPU)
+ * Will load first 4k from NAND (SPL) into cache and execute it from there.
+ *
+ * SPL (Secondary Program Loader)
+ * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
+ * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
+ * controller and the NAND controller so that the special U-Boot image can be
+ * loaded from NAND to SDRAM.
+ *
+ * NUB (NAND U-Boot)
+ * This NAND U-Boot (NUB) is a special U-Boot version which can be started
+ * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+ *
+ * On 440EPx the SPL is copied to SDRAM before the NAND controller is
+ * set up. While still running from cache, I experienced problems accessing
+ * the NAND controller. sr - 2006-08-25
+ */
+#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
+#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
+#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
+#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
+#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
+#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
+
+/*
+ * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
+ */
+#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
+#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
+
+/*
+ * Now the NAND chip has to be defined (no autodetection used!)
+ */
+#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
+#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
+#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
+#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
+#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
+
+#define CFG_NAND_ECCSIZE 256
+#define CFG_NAND_ECCBYTES 3
+#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
+#define CFG_NAND_OOBSIZE 16
+#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
+#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
+
+#ifdef CFG_ENV_IS_IN_NAND
+/*
+ * For NAND booting the environment is embedded in the U-Boot image. Please take
+ * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
+ */
+#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
+#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
+#endif
+
/*-----------------------------------------------------------------------
* RAM (CRAM)
*----------------------------------------------------------------------*/
@@ -207,7 +271,11 @@
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b ${fileaddr} fffc0000 ${filesize};" \
"setenv filesize;saveenv\0" \
- "upd=run load;run update\0" \
+ "upd=run load update\0" \
+ "nload=tftp 200000 acadia/u-boot-nand.bin\0" \
+ "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \
+ "setenv filesize;saveenv\0" \
+ "nupd=run nload nupdate\0" \
"kozio=bootm ffc60000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -224,16 +292,6 @@
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
-#if 0 /* test-only */
-#define TEST_ONLY_NAND
-#endif
-
-#ifdef TEST_ONLY_NAND
-#define CMD_NAND CFG_CMD_NAND
-#else
-#define CMD_NAND 0
-#endif
-
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -241,27 +299,45 @@
#define CONFIG_SUPPORT_VFAT
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_DTT | \
- CFG_CMD_DIAG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CMD_NAND | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_USB)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_USB
+
+/*
+ * No NOR on Acadia when NAND-booting
+ */
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -270,7 +346,7 @@
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -300,7 +376,6 @@
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-#ifdef TEST_ONLY_NAND
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
@@ -308,26 +383,29 @@
#define NAND_MAX_CHIPS 1
#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
-#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EZ CPU */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
#endif
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
-#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
-
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CFG_NAND_CS 3
/* Memory Bank 0 (Flash) initialization */
#define CFG_EBC_PB0AP 0x03337200
#define CFG_EBC_PB0CR 0xfe0bc000
+/* Memory Bank 3 (NAND-FLASH) initialization */
+#define CFG_EBC_PB3AP 0x018003c0
+#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000)
+
/* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
/* Memory Bank 1 (CRAM) initialization */
#define CFG_EBC_PB1AP 0x030400c0
@@ -336,10 +414,24 @@
/* Memory Bank 2 (CRAM) initialization */
#define CFG_EBC_PB2AP 0x030400c0
#define CFG_EBC_PB2CR 0x020bc000
+#else
+#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
+/* Memory Bank 0 (NAND-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x018003c0
+#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000)
-/* Memory Bank 3 (NAND-FLASH) initialization */
-#define CFG_EBC_PB3AP 0x018003c0
-#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000)
+/*
+ * When NAND-booting the CRAM EBC setup must be done in sync mode, since the
+ * NAND-SPL already initialized the CRAM and EBC to sync mode.
+ */
+/* Memory Bank 1 (CRAM) initialization */
+#define CFG_EBC_PB1AP 0x9C0201C0
+#define CFG_EBC_PB1CR 0x000bc000
+
+/* Memory Bank 2 (CRAM) initialization */
+#define CFG_EBC_PB2AP 0x9C0201C0
+#define CFG_EBC_PB2CR 0x020bc000
+#endif
/* Memory Bank 4 (CPLD) initialization */
#define CFG_EBC_PB4AP 0x04006000
@@ -351,14 +443,15 @@
* GPIO Setup
*----------------------------------------------------------------------*/
#define CFG_GPIO_CRAM_CLK 8
-#define CFG_GPIO_CRAM_WAIT 9
+#define CFG_GPIO_CRAM_WAIT 9 /* GPIO-In */
#define CFG_GPIO_CRAM_ADV 10
-#define CFG_GPIO_CRAM_CRE (32 + 21)
+#define CFG_GPIO_CRAM_CRE (32 + 21) /* GPIO-Out */
/*-----------------------------------------------------------------------
* Definitions for GPIO_0 setup (PPC405EZ specific)
*
- * GPIO0[0-3] - External Bus Controller CS_4 - CS_7 Outputs
+ * GPIO0[0-2] - External Bus Controller CS_4 - CS_6 Outputs
+ * GPIO0[3] - NAND FLASH Controller CE3 (NFCE3) Output
* GPIO0[4] - External Bus Controller Hold Input
* GPIO0[5] - External Bus Controller Priority Input
* GPIO0[6] - External Bus Controller HLDA Output
@@ -374,12 +467,12 @@
* GPIO0[28-30] - Trace Outputs / PWM Inputs
* GPIO0[31] - PWM_8 I/O
*/
-#define CFG_GPIO0_TCR 0xC0000000
-#define CFG_GPIO0_OSRL 0x50000000
-#define CFG_GPIO0_OSRH 0x00000055
-#define CFG_GPIO0_ISR1L 0x00000000
+#define CFG_GPIO0_TCR 0xC0A00000
+#define CFG_GPIO0_OSRL 0x50004400
+#define CFG_GPIO0_OSRH 0x02000055
+#define CFG_GPIO0_ISR1L 0x00001000
#define CFG_GPIO0_ISR1H 0x00000055
-#define CFG_GPIO0_TSRL 0x00000000
+#define CFG_GPIO0_TSRL 0x02000000
#define CFG_GPIO0_TSRH 0x00000055
/*-----------------------------------------------------------------------
@@ -396,13 +489,13 @@
* GPIO1[16] - SPI_SS_1_N Output
* GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
*/
-#define CFG_GPIO1_OSRH 0x55455555
+#define CFG_GPIO1_TCR 0xFFFF8414
#define CFG_GPIO1_OSRL 0x40000110
-#define CFG_GPIO1_ISR1H 0x00000000
+#define CFG_GPIO1_OSRH 0x55455555
#define CFG_GPIO1_ISR1L 0x15555445
-#define CFG_GPIO1_TSRH 0x00000000
+#define CFG_GPIO1_ISR1H 0x00000000
#define CFG_GPIO1_TSRL 0x00000000
-#define CFG_GPIO1_TCR 0xFFFF8014
+#define CFG_GPIO1_TSRH 0x00000000
/*
* Internal Definitions
@@ -412,7 +505,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
new file mode 100644
index 0000000..22eac1b
--- /dev/null
+++ b/include/configs/ads5121.h
@@ -0,0 +1,401 @@
+/*
+ * (C) Copyright 2007 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * ADS5121 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define DEBUG
+#undef DEBUG
+
+/*
+ * Memory map for the ADS5121 board:
+ *
+ * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB)
+ * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
+ * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
+ * 0x8200_0000 - 0x8200_001F CPLD (32 B)
+ * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
+ */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 Family */
+#define CONFIG_MPC512X 1 /* MPC512X family */
+
+#undef CONFIG_PCI
+
+#define CFG_MPC512X_CLKIN 66000000 /* in Hz */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
+
+#define CFG_IMMR 0x80000000
+
+#define CFG_MEMTEST_START 0x00200000 /* memtest region */
+#define CFG_MEMTEST_END 0x00400000
+
+/*
+ * DDR Setup - manually set all parameters as there's no SPD etc.
+ */
+#define CFG_DDR_SIZE 256 /* MB */
+#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+
+/* DDR Controller Configuration
+ *
+ * SYS_CFG:
+ * [31:31] MDDRC Soft Reset: Diabled
+ * [30:30] DRAM CKE pin: Enabled
+ * [29:29] DRAM CLK: Enabled
+ * [28:28] Command Mode: Enabled (For initialization only)
+ * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
+ * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
+ * [20:19] Read Test: DON'T USE
+ * [18:18] Self Refresh: Enabled
+ * [17:17] 16bit Mode: Disabled
+ * [16:13] Ready Delay: 2
+ * [12:12] Half DQS Delay: Disabled
+ * [11:11] Quarter DQS Delay: Disabled
+ * [10:08] Write Delay: 2
+ * [07:07] Early ODT: Disabled
+ * [06:06] On DIE Termination: Disabled
+ * [05:05] FIFO Overflow Clear: DON'T USE here
+ * [04:04] FIFO Underflow Clear: DON'T USE here
+ * [03:03] FIFO Overflow Pending: DON'T USE here
+ * [02:02] FIFO Underlfow Pending: DON'T USE here
+ * [01:01] FIFO Overlfow Enabled: Enabled
+ * [00:00] FIFO Underflow Enabled: Enabled
+ * TIME_CFG0
+ * [31:16] DRAM Refresh Time: 0 CSB clocks
+ * [15:8] DRAM Command Time: 0 CSB clocks
+ * [07:00] DRAM Precharge Time: 0 CSB clocks
+ * TIME_CFG1
+ * [31:26] DRAM tRFC:
+ * [25:21] DRAM tWR1:
+ * [20:17] DRAM tWRT1:
+ * [16:11] DRAM tDRR:
+ * [10:05] DRAM tRC:
+ * [04:00] DRAM tRAS:
+ * TIME_CFG2
+ * [31:28] DRAM tRCD:
+ * [27:23] DRAM tFAW:
+ * [22:19] DRAM tRTW1:
+ * [18:15] DRAM tCCD:
+ * [14:10] DRAM tRTP:
+ * [09:05] DRAM tRP:
+ * [04:00] DRAM tRPA
+ */
+
+#define CFG_MDDRC_SYS_CFG 0xF8604200
+#define CFG_MDDRC_SYS_CFG_RUN 0xE8604200
+#define CFG_MDDRC_SYS_CFG_EN 0x30000000
+#define CFG_MDDRC_TIME_CFG0 0x0000281E
+#define CFG_MDDRC_TIME_CFG0_RUN 0x01F4281E
+#define CFG_MDDRC_TIME_CFG1 0x54EC1168
+#define CFG_MDDRC_TIME_CFG2 0x35210864
+
+#define CFG_MICRON_NOP 0x01380000
+#define CFG_MICRON_PCHG_ALL 0x01100400
+#define CFG_MICRON_MR 0x01000022
+#define CFG_MICRON_EM2 0x01020000
+#define CFG_MICRON_EM3 0x01030000
+#define CFG_MICRON_EN_DLL 0x01010000
+#define CFG_MICRON_RST_DLL 0x01000932
+#define CFG_MICRON_RFSH 0x01080000
+#define CFG_MICRON_INIT_DEV_OP 0x01000832
+#define CFG_MICRON_OCD_DEFAULT 0x01010780
+#define CFG_MICRON_OCD_EXIT 0x01010400
+
+/* DDR Priority Manager Configuration */
+#define CFG_MDDRCGRP_PM_CFG1 0x000777AA
+#define CFG_MDDRCGRP_PM_CFG2 0x00000055
+#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000000
+#define CFG_MDDRCGRP_LUT0_MU 0x11111117
+#define CFG_MDDRCGRP_LUT0_ML 0x7777777A
+#define CFG_MDDRCGRP_LUT1_MU 0x4444EEEE
+#define CFG_MDDRCGRP_LUT1_ML 0xEEEEEEEE
+#define CFG_MDDRCGRP_LUT2_MU 0x44444444
+#define CFG_MDDRCGRP_LUT2_ML 0x44444444
+#define CFG_MDDRCGRP_LUT3_MU 0x55555555
+#define CFG_MDDRCGRP_LUT3_ML 0x55555558
+#define CFG_MDDRCGRP_LUT4_MU 0x11111111
+#define CFG_MDDRCGRP_LUT4_ML 0x1111117C
+#define CFG_MDDRCGRP_LUT0_AU 0x33333377
+#define CFG_MDDRCGRP_LUT0_AL 0x7777EEEE
+#define CFG_MDDRCGRP_LUT1_AU 0x11111111
+#define CFG_MDDRCGRP_LUT1_AL 0x11111111
+#define CFG_MDDRCGRP_LUT2_AU 0x11111111
+#define CFG_MDDRCGRP_LUT2_AL 0x11111111
+#define CFG_MDDRCGRP_LUT3_AU 0x11111111
+#define CFG_MDDRCGRP_LUT3_AL 0x11111111
+#define CFG_MDDRCGRP_LUT4_AU 0x11111111
+#define CFG_MDDRCGRP_LUT4_AL 0x11111111
+
+/*
+ * NOR FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI /* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CFG_FLASH_BASE 0xFC000000 /* start of FLASH */
+#define CFG_FLASH_SIZE 0x04000000 /* max flash size in bytes */
+#define CFG_FLASH_USE_BUFFER_WRITE
+
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+
+/*
+ * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
+ * window is 64KB
+ */
+#define CFG_CPLD_BASE 0x82000000
+#define CFG_CPLD_SIZE 0x00010000 /* 64 KB */
+
+#define CFG_SRAM_BASE 0x30000000
+#define CFG_SRAM_SIZE 0x00020000 /* 128 KB */
+
+#define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
+#define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
+
+/* Use SRAM for initial stack */
+#define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */
+#define CFG_INIT_RAM_END CFG_SRAM_SIZE /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
+#if CONFIG_PSC_CONSOLE != 3
+#error CONFIG_PSC_CONSOLE must be 3
+#endif
+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
+#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
+#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
+#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#if 0
+#define CFG_I2C_NOPROBES {{0,0x69}} * Don't probe these addrs */
+#endif
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC512x_FEC 1
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_ADDR 0x1
+#define CONFIG_MII 1 /* MII PHY management */
+
+#if 0
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
+#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+#endif
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+/* This has to be a multiple of the Flash sector size */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_ENV_SIZE 0x2000
+#define CFG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+/*
+ * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock.
+ * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set
+ * to 0xFFFF, watchdog timeouts after about 64s. For details refer
+ * to chapter 36 of the MPC5121e Reference Manual.
+ */
+#define CONFIG_WATCHDOG /* enable watchdog */
+#define CFG_WATCHDOG_VALUE 0xFFFF
+
+ /*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#ifdef CONFIG_CMD_KGDB
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#ifdef CONFIG_CMD_KGDB
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+#define CFG_HID0_INIT 0x000000000
+#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CFG_HID2 HID2_HBE
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_HOSTNAME ads5121
+#define CONFIG_BOOTFILE uImage
+
+#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "load=tftp 200000 /tftpboot/ads5121/u-boot.bin\0" \
+ "update=protect off FFF00000 +${filesize};" \
+ "era FFF00000 +${filesize};cp.b 200000 FFF00000 ${filesize}\0" \
+ "upd=run load;run update\0" \
+ ""
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/adsvix.h b/include/configs/adsvix.h
index c410891..703d312 100644
--- a/include/configs/adsvix.h
+++ b/include/configs/adsvix.h
@@ -68,10 +68,28 @@
#define CONFIG_DOS_PARTITION 1
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_NET) | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_IDE | CFG_CMD_PCMCIA)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PCMCIA
+
+#undef CONFIG_CMD_NET
+
#undef CONFIG_SHOW_BOOT_PROGRESS
@@ -162,7 +180,7 @@
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
/* #define CONFIG_INITRD_TAG 1 */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/aev.h b/include/configs/aev.h
index 8d9f0a1..5bab793 100644
--- a/include/configs/aev.h
+++ b/include/configs/aev.h
@@ -44,11 +44,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -91,34 +86,42 @@
CFG_POST_I2C)
#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#else
-#define CFG_CMD_POST_DIAG 0
#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- ADD_BMP_CMD | \
- CFG_CMD_PCI | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+
+#ifdef CONFIG_POST
+#define CONFIG_CMD_DIAG
+#endif
+
#define CONFIG_TIMESTAMP /* display image timestamps */
@@ -166,17 +169,17 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
-#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@@ -324,7 +327,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -343,9 +346,13 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
@@ -362,7 +369,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index 67f62d3..d88c3ad 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -29,6 +29,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_ALPR 1 /* Board is ebony */
#define CONFIG_440GX 1 /* Specifc GX support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
@@ -94,7 +95,7 @@
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@@ -209,25 +210,37 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_FPGA | \
- CFG_CMD_NAND | \
- CFG_CMD_REGINFO)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -236,7 +249,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -256,7 +269,7 @@
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
@@ -274,7 +287,6 @@
#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_MASTER_INIT
@@ -358,7 +370,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h
index 9a1c559..73a8885 100644
--- a/include/configs/armadillo.h
+++ b/include/configs/armadillo.h
@@ -71,12 +71,21 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL) /* | CFG_CMD_JFFS2)*/
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200"
diff --git a/include/configs/assabet.h b/include/configs/assabet.h
index 1a69ebe..226ad54 100644
--- a/include/configs/assabet.h
+++ b/include/configs/assabet.h
@@ -66,18 +66,30 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySA0,115200n8 root=/dev/nfs ip=bootp"
#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
#define CFG_AUTOLOAD "n" /* No autoload */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index 8fad55d..a65c5f3 100644
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -97,18 +97,31 @@
#define CONFIG_BOOTDELAY 3
/* #define CONFIG_ENV_OVERWRITE 1 */
-#define CONFIG_COMMANDS \
- ((CONFIG_CMD_DFL | CFG_CMD_MII |\
- CFG_CMD_DHCP ) & \
- ~(CFG_CMD_BDI | \
- CFG_CMD_IMI | \
- CFG_CMD_AUTOSCRIPT | \
- CFG_CMD_FPGA | \
- CFG_CMD_MISC | \
- CFG_CMD_LOADS ))
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DHCP
+
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_LOADS
+
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
@@ -150,6 +163,11 @@
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_AT91C_USE_RMII
+/* AC Characteristics */
+/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
+#define DATAFLASH_TCSS (0xC << 16)
+#define DATAFLASH_TCHS (0x1 << 24)
+
#define CONFIG_HAS_DATAFLASH 1
#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
#define CFG_MAX_DATAFLASH_BANKS 2
diff --git a/include/configs/atc.h b/include/configs/atc.h
index bf6c170..3ff4b68 100644
--- a/include/configs/atc.h
+++ b/include/configs/atc.h
@@ -64,9 +64,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- *
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#undef CONFIG_ETHER_NONE /* define if ether on something else */
@@ -124,27 +122,37 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_EEPROM | \
- CFG_CMD_PCI | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_DATE | \
- CFG_CMD_IDE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_DOS_PARTITION
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_IDE
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+#define CONFIG_DOS_PARTITION
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -285,7 +293,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index beaf385..75b153e 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -108,47 +108,29 @@
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
#define CONFIG_NET_MULTI 1
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_SUBNETMASK \
- | CONFIG_BOOTP_GATEWAY)
-
-#define CONFIG_COMMANDS (CFG_CMD_BDI \
- | CFG_CMD_LOADS \
- | CFG_CMD_LOADB \
- | CFG_CMD_IMI \
- /* | CFG_CMD_CACHE */ \
- | CFG_CMD_FLASH \
- | CFG_CMD_MEMORY \
- | CFG_CMD_NET \
- | CFG_CMD_ENV \
- /* | CFG_CMD_IRQ */ \
- | CFG_CMD_BOOTD \
- | CFG_CMD_CONSOLE \
- /* | CFG_CMD_EEPROM */ \
- | CFG_CMD_ASKENV \
- | CFG_CMD_RUN \
- | CFG_CMD_ECHO \
- /* | CFG_CMD_I2C */ \
- | CFG_CMD_REGINFO \
- /* | CFG_CMD_DATE */ \
- | CFG_CMD_DHCP \
- /* | CFG_CMD_AUTOSCRIPT */ \
- /* | CFG_CMD_MII */ \
- | CFG_CMD_MISC \
- /* | CFG_CMD_SDRAM */ \
- /* | CFG_CMD_DIAG */ \
- /* | CFG_CMD_HWFLOW */ \
- /* | CFG_CMD_SAVES */ \
- /* | CFG_CMD_SPI */ \
- /* | CFG_CMD_PING */ \
- | CFG_CMD_MMC \
- | CFG_CMD_FAT \
- | CFG_CMD_IMLS \
- /* | CFG_CMD_ITEST */ \
- | CFG_CMD_EXT2 \
- | CFG_CMD_JFFS2 \
- )
-
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_REGINFO
+
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
#define CONFIG_ATMEL_USART 1
#define CONFIG_MACB 1
@@ -201,10 +183,9 @@
#define CFG_LONGHELP 1
#define CFG_MEMTEST_START \
- ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; })
+ ({ gd->bd->bi_dram[0].start; })
#define CFG_MEMTEST_END \
({ \
- DECLARE_GLOBAL_DATA_PTR; \
gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \
})
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index db58a9f..14c5638 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -32,6 +32,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
#define CONFIG_440EP 1 /* Specific PPC440EP support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
@@ -50,7 +51,7 @@
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
+#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
@@ -73,9 +74,9 @@
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
-#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
+#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (4 << 10)
-#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -104,21 +105,18 @@
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
-/*
- * Define here the location of the environment variables (FLASH or EEPROM).
- * Note: DENX encourages to use redundant environment in FLASH.
- */
-#if 1
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#else
-#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
+#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
+#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
#endif
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
-#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
+#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
+#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
@@ -128,12 +126,12 @@
#define CFG_FLASH_ADDR1 0x2aa
#define CFG_FLASH_WORD_SIZE unsigned char
-#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
-#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
+#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
+#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
-#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
@@ -141,22 +139,91 @@
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */
+/*
+ * IPL (Initial Program Loader, integrated inside CPU)
+ * Will load first 4k from NAND (SPL) into cache and execute it from there.
+ *
+ * SPL (Secondary Program Loader)
+ * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
+ * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
+ * controller and the NAND controller so that the special U-Boot image can be
+ * loaded from NAND to SDRAM.
+ *
+ * NUB (NAND U-Boot)
+ * This NAND U-Boot (NUB) is a special U-Boot version which can be started
+ * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+ *
+ * On 440EPx the SPL is copied to SDRAM before the NAND controller is
+ * set up. While still running from cache, I experienced problems accessing
+ * the NAND controller. sr - 2006-08-25
+ */
+#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
+#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
+#define CFG_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
+#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
+#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
+#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
+
+/*
+ * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
+ */
+#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
+#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
+
+/*
+ * Now the NAND chip has to be defined (no autodetection used!)
+ */
+#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
+#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
+#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
+#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
+#define CFG_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
+
+#define CFG_NAND_ECCSIZE 256
+#define CFG_NAND_ECCBYTES 3
+#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
+#define CFG_NAND_OOBSIZE 16
+#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
+#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
+
+#ifdef CFG_ENV_IS_IN_NAND
+/*
+ * For NAND booting the environment is embedded in the U-Boot image. Please take
+ * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
+ */
+#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
+#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
+#endif
+
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
-#define CFG_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
-#define CFG_NAND_CS 1
+#define CFG_MAX_NAND_DEVICE 2
+#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE
#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE, CFG_NAND_ADDR + 2 }
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CFG_NAND_CS 1
+#else
+#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
+/* Memory Bank 0 (NAND-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x018003c0
+#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000)
+#endif
+
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------------- */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
#undef CONFIG_DDR_ECC /* don't use ECC */
#define CFG_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */
-#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
+#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
+#define CFG_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */
+#define CONFIG_PROG_SDRAM_TLB
+#undef CFG_DRAM_TEST
/*-----------------------------------------------------------------------
* I2C
@@ -251,45 +318,55 @@
#define USB_2_0_DEVICE
#endif /*CONFIG_440EP*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_SNTP
+
#ifdef CONFIG_BAMBOO_NAND
-#define _CFG_CMD_NAND CFG_CMD_NAND
-#else
-#define _CFG_CMD_NAND 0
-#endif /* CONFIG_BAMBOO_NAND */
+#define CONFIG_CMD_NAND
+#endif
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_USB | \
- CFG_CMD_FAT | \
- CFG_CMD_EXT2 | \
- _CFG_CMD_NAND | \
- CFG_CMD_SNTP )
#define CONFIG_SUPPORT_VFAT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -324,7 +401,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
@@ -343,7 +419,7 @@
*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -355,7 +431,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/barco.h b/include/configs/barco.h
index 624fa1d..0bb446f 100644
--- a/include/configs/barco.h
+++ b/include/configs/barco.h
@@ -70,22 +70,30 @@
#define CONFIG_BOOTARGS "mem=32M"
-/* Add support for a few extra bootp options like:
- * - File size
- * - DNS
+
+/*
+ * BOOTP options
*/
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE | \
- CONFIG_BOOTP_DNS)
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_PCI
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_PCI )
+#undef CONFIG_CMD_NET
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_HUSH_PARSER 1 /* use "hush" command parser */
#define CONFIG_BOOTDELAY 1
@@ -110,7 +118,6 @@
*/
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP
-#undef CFG_CMD_NET
#define PCI_ENET0_IOADDR 0x80000000
#define PCI_ENET0_MEMADDR 0x80000000
@@ -340,7 +347,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
index 65dfc81..6cb6bc4 100644
--- a/include/configs/bf533-ezkit.h
+++ b/include/configs/bf533-ezkit.h
@@ -97,19 +97,31 @@
#define CONFIG_LOADS_ECHO 1
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PING | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_DATE)
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600"
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_DATE
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600"
#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index 79a1404..cce6ef7 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -240,23 +240,6 @@
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
-#if (CONFIG_DRIVER_SMC91111)
-#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \
- CFG_CMD_PING | \
- CFG_CMD_ELF | \
- CFG_CMD_CACHE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_EEPROM | \
- CFG_CMD_DATE)
-
-#else
-#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \
- CFG_CMD_ELF | \
- CFG_CMD_CACHE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_EEPROM | \
- CFG_CMD_DATE)
-#endif
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#if (CONFIG_DRIVER_SMC91111)
@@ -305,20 +288,39 @@
#endif
#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DATE
+
+#if (CONFIG_DRIVER_SMC91111)
+#define CONFIG_CMD_PING
+#endif
+
#if (CONFIG_SOFT_I2C)
-#define CONFIG_COMMANDS2 CFG_CMD_I2C
-#else
-#define CONFIG_COMMANDS2 0
-#endif /* CONFIG_SOFT_I2C */
+#define CONFIG_CMD_I2C
+#endif
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
-#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2 | CFG_CMD_DHCP)
-#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
-#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2)
+#define CONFIG_CMD_DHCP
#endif
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Console settings
@@ -345,7 +347,7 @@
#endif
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -395,7 +397,7 @@
/* Enabled below option for CF support */
/* #define CONFIG_STAMP_CF 1 */
-#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(CONFIG_STAMP_CF) && defined(CONFIG_CMD_IDE)
#define CONFIG_MISC_INIT_R 1
#define CONFIG_DOS_PARTITION 1
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index f6755ac..b9a9e3c 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -144,11 +144,8 @@
#endif
#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
-#else
-#define CFG_CMD_POST_DIAG 0
#endif
/* CF-CARD IDE-HDD Support */
@@ -159,51 +156,65 @@
#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
# define CONFIG_BFIN_IDE 1
-# define ADD_IDE_CMD CFG_CMD_IDE
-#else
-# define ADD_IDE_CMD 0
#endif
/*#define CONFIG_BF537_NAND */ /* Add nand flash support */
-#ifdef CONFIG_BF537_NAND
-# define ADD_NAND_CMD CFG_CMD_NAND
-#else
-# define ADD_NAND_CMD 0
-#endif
-
#define CONFIG_NETCONSOLE 1
#define CONFIG_NET_MULTI 1
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DATE
+
#if (BFIN_CPU == ADSP_BF534)
-#define CONFIG_BFIN_CMD (CONFIG_CMD_DFL & ~CFG_CMD_NET)
+#undef CONFIG_CMD_NET
#else
-#define CONFIG_BFIN_CMD (CONFIG_CMD_DFL | CFG_CMD_PING)
+#define CONFIG_CMD_PING
+#endif
+
+#if defined(CONFIG_BFIN_CF_IDE) \
+ || defined(CONFIG_BFIN_HDD_IDE) \
+ || defined(CONFIG_BFIN_TRUE_IDE)
+#define CONFIG_CMD_IDE
+#endif
+
#endif
#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
-#define CONFIG_COMMANDS (CONFIG_BFIN_CMD| \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_CACHE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_EEPROM | \
- CFG_CMD_DHCP | \
- ADD_IDE_CMD | \
- ADD_NAND_CMD | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_DATE)
-#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
-#define CONFIG_COMMANDS (CONFIG_BFIN_CMD| \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_CACHE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_EEPROM | \
- ADD_IDE_CMD | \
- CFG_CMD_DATE)
+
+#define CONFIG_CMD_DHCP
+
+#if defined(CONFIG_POST)
+#define CONFIG_CMD_DIAG
#endif
+#ifdef CONFIG_BF537_NAND
+#define CONFIG_CMD_NAND
+#endif
+
+#endif
+
+
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
#define CONFIG_LOADADDR 0x1000000
@@ -256,9 +267,6 @@
#endif
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
#if (BFIN_CPU == ADSP_BF534)
#define CFG_PROMPT "serial_bf534> " /* Monitor Command Prompt */
@@ -277,7 +285,7 @@
#endif
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 8d826fa..2966260 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -164,12 +164,6 @@
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
#if (CONFIG_DRIVER_SMC91111)
-#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \
- CFG_CMD_PING | \
- CFG_CMD_ELF | \
- CFG_CMD_CACHE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_DHCP)
#define CONFIG_EXTRA_ENV_SETTINGS \
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
@@ -186,20 +180,36 @@
"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
""
#else
-#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \
- CFG_CMD_ELF | \
- CFG_CMD_CACHE | \
- CFG_CMD_JFFS2)
#define CONFIG_EXTRA_ENV_SETTINGS \
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
"flashboot=bootm 0x20100000\0" \
""
#endif
-#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2 )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_JFFS2
+
+#if defined(CONFIG_DRIVER_SMC91111)
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#endif
+
/*
* Console settings
@@ -208,7 +218,7 @@
#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
index 10c4814..7736a1e 100644
--- a/include/configs/bubinga.h
+++ b/include/configs/bubinga.h
@@ -137,25 +137,37 @@
#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_CACHE | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -166,7 +178,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -219,7 +231,7 @@
#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
-#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
+#if defined(CONFIG_CMD_EEPROM)
#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
#endif
@@ -314,7 +326,7 @@
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EP CPU */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -426,7 +438,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h
index ae75539..a9a5254 100644
--- a/include/configs/c2mon.h
+++ b/include/configs/c2mon.h
@@ -68,7 +68,15 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -77,15 +85,18 @@
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
@@ -98,7 +109,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -174,7 +185,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
index 2c160a4..d577b95 100644
--- a/include/configs/canmb.h
+++ b/include/configs/canmb.h
@@ -38,11 +38,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
#define CONFIG_BOARD_EARLY_INIT_R
/*
@@ -52,21 +47,30 @@
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
/*
- * Supported commands
+ * BOOTP options
*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IMMAP | \
- CFG_CMD_MII | \
- CFG_CMD_NFS | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+
/*
* MUST be low boot - HIGHBOOT is not supported anymore
@@ -111,7 +115,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* Flash configuration, expect one 16 Megabyte Bank at most
@@ -181,7 +185,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -199,6 +203,11 @@
#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h
index 6997c7a..e06735d 100644
--- a/include/configs/cerf250.h
+++ b/include/configs/cerf250.h
@@ -61,10 +61,21 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_ETHADDR 00:D0:CA:F1:3C:D2
@@ -75,7 +86,7 @@
#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,38400"
#define CONFIG_CMDLINE_TAG
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h
index 5947c2a..ae40b35 100644
--- a/include/configs/cm4008.h
+++ b/include/configs/cm4008.h
@@ -58,10 +58,23 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-#undef CONFIG_COMMANDS
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~(CFG_CMD_NONSTD | CFG_CMD_ENV))
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_ENV
+
#define CONFIG_BOOTDELAY 0
#define CONFIG_BOOTARGS "mem=16M console=ttyAM0,115200"
diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h
index e62fc06..c1dd33d 100644
--- a/include/configs/cm41xx.h
+++ b/include/configs/cm41xx.h
@@ -58,10 +58,23 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-#undef CONFIG_COMMANDS
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~(CFG_CMD_NONSTD | CFG_CMD_ENV))
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_ENV
+
#define CONFIG_BOOTDELAY 0
#define CONFIG_BOOTARGS "mem=32M console=ttyAM0,115200"
diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h
new file mode 100644
index 0000000..d554348
--- /dev/null
+++ b/include/configs/cm5200.h
@@ -0,0 +1,338 @@
+/*
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_CM5200 1 /* ... on CM5200 platform */
+
+/*
+ * Supported commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
+#define CONFIG_BAUDRATE 57600 /* ... at 57600 bps */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SILENT_CONSOLE 1 /* needed to silence i2c_init() */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_PHY_ADDR 0x00
+#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */
+/* use misc_init_r() to read ethaddr from I2C EEPROM (see CFG_I2C_EEPROM) */
+#define CONFIG_MISC_INIT_R 1
+#define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */
+
+/*
+ * POST support
+ */
+#define CONFIG_POST (CFG_POST_MEMORY | CFG_POST_CPU | CFG_POST_I2C)
+#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
+/* List of I2C addresses to be verified by POST */
+#define I2C_ADDR_LIST { CFG_I2C_SLAVE, CFG_I2C_IO, CFG_I2C_EEPROM }
+
+/* display image timestamps */
+#define CONFIG_TIMESTAMP 1
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
+ "echo"
+#undef CONFIG_BOOTARGS
+
+/*
+ * Default environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "netmask=255.255.0.0\0" \
+ "ipaddr=192.168.160.33\0" \
+ "serverip=192.168.1.1\0" \
+ "gatewayip=192.168.1.1\0" \
+ "console=ttyPSC0\0" \
+ "u-boot_addr=100000\0" \
+ "kernel_addr=200000\0" \
+ "kernel_addr_flash=fc0c0000\0" \
+ "fdt_addr=400000\0" \
+ "fdt_addr_flash=fc0a0000\0" \
+ "ramdisk_addr=500000\0" \
+ "rootpath=/opt/eldk-4.1/ppc_6xx\0" \
+ "u-boot=/tftpboot/cm5200/u-boot.bin\0" \
+ "bootfile_fdt=/tftpboot/cm5200/uImage\0" \
+ "fdt_file=/tftpboot/cm5200/cm5200.dtb\0" \
+ "load=tftp ${u-boot_addr} ${u-boot}\0" \
+ "update=prot off fc000000 +${filesize}; " \
+ "era fc000000 +${filesize}; " \
+ "cp.b ${u-boot_addr} fc000000 ${filesize}; " \
+ "prot on fc000000 +${filesize}\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \
+ "addcons=setenv bootargs ${bootargs} " \
+ "console=${console},${baudrate}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:${netdev}:off panic=1\0" \
+ "flash_flash=run flashargs addinit addip addcons;" \
+ "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \
+ "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \
+ "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \
+ "addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_flash"
+
+/*
+ * Low level configuration
+ */
+
+/*
+ * Clock configuration
+ */
+#define CFG_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */
+#define CFG_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR 0xF0000000
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_DEFAULT_MBAR 0x80000000
+
+#define CFG_LOWBOOT 1
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
+#else
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#endif
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_BOARD_TYPES 1 /* we use board_type */
+
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
+#define CFG_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */
+#define CFG_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#define CFG_FLASH_BASE 0xfc000000
+/* we need these despite using CFI */
+#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
+#define CFG_MAX_FLASH_SECT 256 /* max num of sectors on one chip */
+#define CFG_FLASH_SIZE 0x02000000 /* 32 MiB */
+
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT 1
+#undef CFG_LOWBOOT
+#endif
+
+
+/*
+ * Chip selects configuration
+ */
+/* Boot Chipselect */
+#define CFG_BOOTCS_START CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */
+/* use board_early_init_r to enable flash write in CS_BOOT */
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/* Flash memory addressing */
+#define CFG_CS0_START CFG_FLASH_BASE
+#define CFG_CS0_SIZE CFG_FLASH_SIZE
+
+/* No burst, dead cycle = 1 for CS0 (Flash) */
+#define CFG_CS_BURST 0x00000000
+#define CFG_CS_DEADCYCLE 0x00000001
+
+/*
+ * SDRAM configuration
+ * settings for k4s561632E-xx75, assuming XLB = 132 MHz
+ */
+#define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */
+#define SDRAM_CONTROL 0x514F0000
+#define SDRAM_CONFIG1 0xE2333900
+#define SDRAM_CONFIG2 0x8EE70000
+
+/*
+ * MTD configuration
+ */
+#define CONFIG_JFFS2_CMDLINE 1
+#define MTDIDS_DEFAULT "nor0=cm5200-0"
+#define MTDPARTS_DEFAULT "mtdparts=cm5200-0:" \
+ "384k(uboot),128k(env)," \
+ "128k(redund_env),128k(dtb)," \
+ "2m(kernel),27904k(rootfs)," \
+ "-(config)"
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CFG_I2C_MODULE 2 /* Select I2C module #2 */
+#define CFG_I2C_SPEED 40000 /* 40 kHz */
+#define CFG_I2C_SLAVE 0x0
+#define CFG_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */
+#define CFG_I2C_EEPROM 0x53 /* I2C EEPROM device address */
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
+
+/*
+ * USB configuration
+ */
+#define CONFIG_USB_OHCI 1
+#define CONFIG_USB_STORAGE 1
+#define CONFIG_USB_CLOCK 0x0001BBBB
+#define CONFIG_USB_CONFIG 0x00001000
+/* Partitions (for USB) */
+#define CONFIG_MAC_PARTITION 1
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_ISO_PARTITION 1
+
+/*
+ * Invoke our last_stage_init function - needed by fwupdate
+ */
+#define CONFIG_LAST_STAGE_INIT 1
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 0x10000
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
+/* Configuration of redundant environment */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+/*
+ * Pin multiplexing configuration
+ */
+
+/*
+ * CS1/GPIO_WKUP_6: GPIO (default)
+ * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1
+ * IRDA/PSC6: UART
+ * Ether: Ethernet 100Mbit with MD
+ * PCI_DIS: PCI controller disabled
+ * USB: USB
+ * PSC3: SPI with UART3
+ * PSC2: UART
+ * PSC1: UART
+ */
+#define CFG_GPS_PORT_CONFIG 0x10559C44
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP 1 /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_ALT_MEMTEST 1
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */
+
+#define CONFIG_LOOPW 1
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL HID0_ICE
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_XLB_PIPELINING 1 /* enable transaction pipeling */
+
+/*
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#ifdef CONFIG_CMD_KGDB
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Flat Device Tree support
+ */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define OF_CPU "PowerPC,5200@0"
+#define OF_SOC "soc5200@f0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index 572a70f..f32c8c2 100644
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -104,35 +104,44 @@
#define CFG_I2C_EEPROM_ADDR 0x50
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_I2C_EEPROM_ADDR_OVERFLOW
+#else
+#define CONFIG_TIMESTAMP
#endif
/* still about 20 kB free with this defined */
#define CFG_LONGHELP
#define CONFIG_BOOTDELAY 1
-#ifdef CONFIG_HARD_I2C
-#define CONFIG_COMMANDS \
- ((CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP ) & \
- ~(CFG_CMD_FPGA | CFG_CMD_MISC) )
-#else
-#define CONFIG_COMMANDS \
- ((CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP ) & \
- ~(CFG_CMD_FPGA | CFG_CMD_MISC) )
-#define CONFIG_TIMESTAMP
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+
+#if defined(CONFIG_HARD_I2C)
+ #define CONFIG_CMD_DATE
+ #define CONFIG_CMD_EEPROM
+ #define CONFIG_CMD_I2C
#endif
-#define CFG_LONGHELP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+#define CFG_LONGHELP
#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h
index e459919..a869364 100644
--- a/include/configs/cmi_mpc5xx.h
+++ b/include/configs/cmi_mpc5xx.h
@@ -44,13 +44,35 @@
#define CONFIG_BAUDRATE 57600
-#define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | \
- CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ASKENV | \
- CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_ENV | CFG_CMD_RUN | \
- CFG_CMD_IMI)
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_NET /* disabeled - causes compile errors */
+
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_IMI
+
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
@@ -73,7 +95,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -149,8 +171,9 @@
#define CFG_ENV_IS_IN_FLASH 1
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */
-#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */
+#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */
+#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#endif
/*-----------------------------------------------------------------------
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 9033fa8..104d94e 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -65,8 +65,10 @@
* Enable use of Ethernet
* ---
*/
+#define CONFIG_MCFFEC
-#define FEC_ENET
+/* Enable Dma Timer */
+#define CONFIG_MCFTMR
/* ---
* Define baudrate for UART1 (console output, tftp, ...)
@@ -76,6 +78,8 @@
* ---
*/
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
@@ -130,16 +134,47 @@
#define CFG_ENV_IS_IN_FLASH 1
#endif
-/* ---
- * Define which commmands should be available at u-boot command prompt
- * ---
+
+/*
+ * BOOTP options
*/
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | CFG_CMD_PING & ~(CFG_CMD_LOADS | \
-CFG_CMD_LOADB) | CFG_CMD_MII)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_MII
+
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
/*
*-----------------------------------------------------------------------------
@@ -184,7 +219,7 @@ from which user programs will be started */
#define CFG_LONGHELP /* undef to save memory */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/cogent_mpc8260.h b/include/configs/cogent_mpc8260.h
index aea2e64..84d50c7 100644
--- a/include/configs/cogent_mpc8260.h
+++ b/include/configs/cogent_mpc8260.h
@@ -71,8 +71,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
@@ -88,10 +87,25 @@
#define CONFIG_BAUDRATE 9600
#endif
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL|CFG_CMD_KGDB)&~CFG_CMD_NET)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_KGDB
+
+#undef CONFIG_CMD_NET
+
#ifdef DEBUG
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
@@ -102,7 +116,7 @@
#define CONFIG_BOOTARGS "root=/dev/ram rw"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -124,7 +138,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -256,7 +270,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
#endif
diff --git a/include/configs/cogent_mpc8xx.h b/include/configs/cogent_mpc8xx.h
index 80962d3..ce38af1 100644
--- a/include/configs/cogent_mpc8xx.h
+++ b/include/configs/cogent_mpc8xx.h
@@ -59,10 +59,25 @@
#define CFG_I2C_SLAVE 0x7F
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_KGDB | CFG_CMD_I2C) & ~CFG_CMD_NET)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_KGDB
+#define CONFIG_CMD_I2C
+
+#undef CONFIG_CMD_NET
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
@@ -73,7 +88,7 @@
#define CONFIG_BOOTARGS "root=/dev/ram rw"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#define CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -88,7 +103,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -200,7 +215,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h
index f9586fb..ce4ea1f 100644
--- a/include/configs/cpci5200.h
+++ b/include/configs/cpci5200.h
@@ -50,11 +50,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -92,12 +87,6 @@
#define CONFIG_NS8382X 1
#endif
-#define ADD_PCI_CMD CFG_CMD_PCI
-
-#else /* MPC5100 */
-
-#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
-
#endif
/* Partitions */
@@ -107,28 +96,35 @@
/* USB */
#if 0
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD 0
#endif
/*
- * Supported commands
+ * BOOTP options
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_EEPROM | \
- CFG_CMD_FAT | \
- CFG_CMD_IDE | \
- CFG_CMD_I2C | \
- CFG_CMD_BSP | \
- CFG_CMD_ELF | \
- CFG_CMD_EXT2 | \
- CFG_CMD_DATE | \
- ADD_PCI_CMD )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_DATE
#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CFG_LOWBOOT 1
@@ -179,7 +175,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*
* I2C configuration
@@ -277,7 +273,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -295,6 +291,11 @@
#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/cradle.h b/include/configs/cradle.h
index 776e1d2..eb93a8f 100644
--- a/include/configs/cradle.h
+++ b/include/configs/cradle.h
@@ -61,10 +61,21 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 console=ttyS0,115200"
diff --git a/include/configs/csb226.h b/include/configs/csb226.h
index f04102e..0be0f21 100644
--- a/include/configs/csb226.h
+++ b/include/configs/csb226.h
@@ -57,10 +57,34 @@
#define CONFIG_BAUDRATE 19200
#undef CONFIG_MISC_INIT_R /* not used yet */
-#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_DHCP|CFG_CMD_CACHE)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_CACHE
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0"
@@ -73,7 +97,7 @@
#define CONFIG_CMDLINE_TAG 1
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/csb272.h b/include/configs/csb272.h
index 27d64c1..c43b497 100644
--- a/include/configs/csb272.h
+++ b/include/configs/csb272.h
@@ -73,30 +73,32 @@
#endif
/*
- * BOOTP/DHCP protocol configuration
- *
+ * BOOTP options
*/
-#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_BOOTFILESIZE )
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS2
+
+
/*
- * U-Boot Monitor Command Line Functions Configuration
- *
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_ELF | \
- CFG_CMD_IRQ | \
- CFG_CMD_I2C | \
- CFG_CMD_PCI | \
- CFG_CMD_DATE | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_DHCP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
/*
* Serial download configuration
@@ -109,7 +111,7 @@
* KGDB Configuration
*
*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -125,7 +127,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/csb472.h b/include/configs/csb472.h
index 09d52de..a7120aa 100644
--- a/include/configs/csb472.h
+++ b/include/configs/csb472.h
@@ -73,30 +73,31 @@
#endif
/*
- * BOOTP/DHCP protocol configuration
- *
+ * BOOTP options
*/
-#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_BOOTFILESIZE )
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS2
+
+
/*
- * U-Boot Monitor Command Line Functions Configuration
- *
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_ELF | \
- CFG_CMD_IRQ | \
- CFG_CMD_I2C | \
- CFG_CMD_PCI | \
- CFG_CMD_DATE | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_DHCP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
/*
* Serial download configuration
@@ -109,7 +110,7 @@
* KGDB Configuration
*
*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -125,7 +126,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/csb637.h b/include/configs/csb637.h
index 071d5b7..976dae3 100644
--- a/include/configs/csb637.h
+++ b/include/configs/csb637.h
@@ -99,20 +99,32 @@
#define CONFIG_BOOTDELAY 3
/* #define CONFIG_ENV_OVERWRITE 1 */
-#define CONFIG_COMMANDS \
- ((CONFIG_CMD_DFL | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING ) & \
- ~(CFG_CMD_BDI | \
- CFG_CMD_IMI | \
- CFG_CMD_AUTOSCRIPT | \
- CFG_CMD_FPGA | \
- CFG_CMD_MISC | \
- CFG_CMD_LOADS ))
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_LOADS
+
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
new file mode 100644
index 0000000..8ecd059
--- /dev/null
+++ b/include/configs/davinci_dvevm.h
@@ -0,0 +1,214 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * Define this to make U-Boot skip low level initialization when loaded
+ * by initial bootloader. Not required by NAND U-Boot version but IS
+ * required for a NOR version used to burn the real NOR U-Boot into
+ * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
+ * so it is NOT possible to build a U-Boot with both NAND and NOR routines.
+ * NOR U-Boot is loaded directly from Flash so it must perform all the
+ * low level initialization itself. NAND version is loaded by an initial
+ * bootloader (UBL in TI-ese) that performs such an initialization so it's
+ * skipped in NAND version. The third DaVinci boot mode loads a bootloader
+ * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
+ * performing low level init prior to loading. All that means we can NOT use
+ * NAND version to put U-Boot into NOR because it doesn't have NOR support and
+ * we can NOT use NOR version because it performs low level initialization
+ * effectively destroying itself in DDR memory. That's why a separate NOR
+ * version with this define is needed. It is loaded via UART, then one uses
+ * it to somehow download a proper NOR version built WITHOUT this define to
+ * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
+ * NOR support into the initial bootloader so it won't be needed but DaVinci
+ * static RAM might be too small for this (I have something like 2Kbytes left
+ * as of now, without NOR support) so this might've not happened...
+ *
+#define CONFIG_NOR_UART_BOOT
+ */
+
+/*=======*/
+/* Board */
+/*=======*/
+#define DV_EVM
+#define CFG_NAND_SMALLPAGE
+#define CFG_USE_NOR
+/*===================*/
+/* SoC Configuration */
+/*===================*/
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */
+#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
+#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
+#define CFG_HZ 1000
+/*====================================================*/
+/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
+/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
+/*====================================================*/
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_EEPROM_PAGE_WRITE_BITS 6
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+/*=============*/
+/* Memory Info */
+/*=============*/
+#define CFG_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
+#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */
+#define CFG_MEMTEST_START 0x80000000 /* memtest start address */
+#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
+#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */
+#define DDR_8BANKS /* 8-bank DDR2 (256MB) */
+/*====================*/
+/* Serial Driver info */
+/*====================*/
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */
+#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */
+#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+/*===================*/
+/* I2C Configuration */
+/*===================*/
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
+#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+/*==================================*/
+/* Network & Ethernet Configuration */
+/*==================================*/
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#ifdef CFG_USE_NAND
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_NO_FLASH
+#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
+#ifdef CFG_NAND_SMALLPAGE
+#define CFG_ENV_SECT_SIZE 512 /* Env sector Size */
+#define CFG_ENV_SIZE SZ_16K
+#else
+#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */
+#define CFG_ENV_SIZE SZ_128K
+#endif
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
+#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
+#define CFG_NAND_BASE 0x02000000
+#define CFG_NAND_HW_ECC
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
+#define DEF_BOOTM ""
+#elif defined(CFG_USE_NOR)
+#ifdef CONFIG_NOR_UART_BOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
+#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
+#else
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+#endif
+#define CFG_ENV_IS_IN_FLASH
+#undef CFG_NO_FLASH
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */
+#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */
+#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*3)
+#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
+#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
+#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
+#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
+#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */
+#endif
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#define CONFIG_MISC_INIT_R
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CFG_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+/*===================*/
+/* Linux Information */
+/*===================*/
+#define LINUX_BOOT_PARAM_ADDR 0x80000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS "mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2050000"
+/*=================*/
+/* U-Boot commands */
+/*=================*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#ifdef CFG_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#elif defined(CFG_USE_NOR)
+#define CONFIG_CMD_JFFS2
+#else
+#error "Either CFG_USE_NAND or CFG_USE_NOR _MUST_ be defined !!!"
+#endif
+/*=======================*/
+/* KGDB support (if any) */
+/*=======================*/
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
new file mode 100644
index 0000000..96c9a30
--- /dev/null
+++ b/include/configs/davinci_schmoogie.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*=======*/
+/* Board */
+/*=======*/
+#define SCHMOOGIE
+#define CFG_NAND_LARGEPAGE
+#define CFG_USE_NAND
+/*===================*/
+/* SoC Configuration */
+/*===================*/
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */
+#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
+#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
+#define CFG_HZ 1000
+/*=============*/
+/* Memory Info */
+/*=============*/
+#define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
+#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */
+#define CFG_MEMTEST_START 0x80000000 /* memtest start address */
+#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
+#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
+/*====================*/
+/* Serial Driver info */
+/*====================*/
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */
+#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */
+#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+/*===================*/
+/* I2C Configuration */
+/*===================*/
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
+#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+/*==================================*/
+/* Network & Ethernet Configuration */
+/*==================================*/
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_NO_FLASH
+#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
+#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */
+#define CFG_ENV_SIZE SZ_128K
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
+#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
+#define CFG_NAND_BASE 0x02000000
+#define CFG_NAND_HW_ECC
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
+/*=====================*/
+/* Board related stuff */
+/*=====================*/
+#define CONFIG_RTC_DS1307 /* RTC chip on SCHMOOGIE */
+#define CFG_I2C_RTC_ADDR 0x6f /* RTC chip I2C address */
+#define CONFIG_HAS_UID
+#define CONFIG_UID_DS28CM00 /* Unique ID on SCHMOOGIE */
+#define CFG_UID_ADDR 0x50 /* UID chip I2C address */
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#define CONFIG_MISC_INIT_R
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CFG_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+/*===================*/
+/* Linux Information */
+/*===================*/
+#define LINUX_BOOT_PARAM_ADDR 0x80000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot"
+/*=================*/
+/* U-Boot commands */
+/*=================*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_NAND
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+/*=======================*/
+/* KGDB support (if any) */
+/*=======================*/
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
new file mode 100644
index 0000000..de8c4fa
--- /dev/null
+++ b/include/configs/davinci_sonata.h
@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * Define this to make U-Boot skip low level initialization when loaded
+ * by initial bootloader. Not required by NAND U-Boot version but IS
+ * required for a NOR version used to burn the real NOR U-Boot into
+ * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
+ * so it is NOT possible to build a U-Boot with both NAND and NOR routines.
+ * NOR U-Boot is loaded directly from Flash so it must perform all the
+ * low level initialization itself. NAND version is loaded by an initial
+ * bootloader (UBL in TI-ese) that performs such an initialization so it's
+ * skipped in NAND version. The third DaVinci boot mode loads a bootloader
+ * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
+ * performing low level init prior to loading. All that means we can NOT use
+ * NAND version to put U-Boot into NOR because it doesn't have NOR support and
+ * we can NOT use NOR version because it performs low level initialization
+ * effectively destroying itself in DDR memory. That's why a separate NOR
+ * version with this define is needed. It is loaded via UART, then one uses
+ * it to somehow download a proper NOR version built WITHOUT this define to
+ * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
+ * NOR support into the initial bootloader so it won't be needed but DaVinci
+ * static RAM might be too small for this (I have something like 2Kbytes left
+ * as of now, without NOR support) so this might've not happened...
+ *
+#define CONFIG_NOR_UART_BOOT
+ */
+
+/*=======*/
+/* Board */
+/*=======*/
+#define SONATA_BOARD
+#define CFG_NAND_SMALLPAGE
+#define CFG_USE_NOR
+/*===================*/
+/* SoC Configuration */
+/*===================*/
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */
+#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
+#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
+#define CFG_HZ 1000
+/*====================================================*/
+/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
+/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
+/*====================================================*/
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_EEPROM_PAGE_WRITE_BITS 6
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+/*=============*/
+/* Memory Info */
+/*=============*/
+#define CFG_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
+#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */
+#define CFG_MEMTEST_START 0x80000000 /* memtest start address */
+#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
+#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
+/*====================*/
+/* Serial Driver info */
+/*====================*/
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */
+#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */
+#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+/*===================*/
+/* I2C Configuration */
+/*===================*/
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
+#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+/*==================================*/
+/* Network & Ethernet Configuration */
+/*==================================*/
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#ifdef CFG_USE_NAND
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_NO_FLASH
+#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
+#define CFG_ENV_SECT_SIZE 512 /* Env sector Size */
+#define CFG_ENV_SIZE SZ_16K
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
+#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
+#define CFG_NAND_BASE 0x02000000
+#define CFG_NAND_HW_ECC
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
+#define DEF_BOOTM ""
+#elif defined(CFG_USE_NOR)
+#ifdef CONFIG_NOR_UART_BOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
+#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
+#else
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+#endif
+#define CFG_ENV_IS_IN_FLASH
+#undef CFG_NO_FLASH
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */
+#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */
+#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*2)
+#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
+#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
+#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
+#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
+#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */
+#endif
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#define CONFIG_MISC_INIT_R
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CFG_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+/*===================*/
+/* Linux Information */
+/*===================*/
+#define LINUX_BOOT_PARAM_ADDR 0x80000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2060000"
+/*=================*/
+/* U-Boot commands */
+/*=================*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#ifdef CFG_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#elif defined(CFG_USE_NOR)
+#define CONFIG_CMD_JFFS2
+#else
+#error "Either CFG_USE_NAND or CFG_USE_NOR _MUST_ be defined !!!"
+#endif
+/*=======================*/
+/* KGDB support (if any) */
+/*=======================*/
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index 4cc5085..b2f606f 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -75,21 +75,57 @@
#ifdef CONFIG_DBAU1550
/* Boot from flash by default, revert to bootp */
#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
-
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_NET) & \
- ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FPGA | CFG_CMD_IDE | \
- CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_BDI | CFG_CMD_BEDBUG | \
- CFG_CMD_NFS | CFG_CMD_ELF | CFG_CMD_PCMCIA | CFG_CMD_I2C))
#else /* CONFIG_DBAU1550 */
#define CONFIG_BOOTCOMMAND "bootp;bootm"
-
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP | CFG_CMD_ELF) & \
- ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
- CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | \
- CFG_CMD_ELF | CFG_CMD_BDI | CFG_CMD_BEDBUG))
#endif /* CONFIG_DBAU1550 */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_FAT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_RUN
+
+
+#ifdef CONFIG_DBAU1550
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_NET
+
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_PCMCIA
+
+#else
+
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DHCP
+
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+#endif
+
/*
* Miscellaneous configurable options
diff --git a/include/configs/debris.h b/include/configs/debris.h
index 8ff963f..7667e5e 100644
--- a/include/configs/debris.h
+++ b/include/configs/debris.h
@@ -122,23 +122,35 @@
#define CONFIG_BAUDRATE 9600
#define CONFIG_DRAM_SPEED 100 /* MHz */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_CACHE | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_KGBD | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_SAVES | \
- CFG_CMD_SDRAM)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_KGBD
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
/*
@@ -435,7 +447,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/delta.h b/include/configs/delta.h
index 1568120..09667ed 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -87,22 +87,49 @@
#define CONFIG_BAUDRATE 115200
-/* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#ifdef TURN_ON_ETHERNET
-# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
+
+#define CONFIG_CMD_PING
+
#else
-# define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_ENV \
- | CFG_CMD_NAND \
- | CFG_CMD_I2C) \
- & ~(CFG_CMD_NET \
- | CFG_CMD_FLASH \
- | CFG_CMD_IMLS))
+
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_I2C
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+
#endif
+/* USB */
+#define CONFIG_USB_OHCI_NEW 1
+#define CONFIG_USB_STORAGE 1
+#define CONFIG_DOS_PARTITION 1
+
+#undef CFG_USB_OHCI_BOARD_INIT
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE OHCI_REGS_BASE
+#define CFG_USB_OHCI_SLOT_NAME "delta"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 3
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define LITTLEENDIAN 1 /* used by usb_ohci.c */
#define CONFIG_BOOTDELAY -1
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
@@ -114,7 +141,7 @@
#define CONFIG_CMDLINE_TAG
#define CONFIG_TIMESTAMP
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h
index 9ac2856..d32e046 100644
--- a/include/configs/dnp1110.h
+++ b/include/configs/dnp1110.h
@@ -66,10 +66,21 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200"
@@ -80,7 +91,7 @@
#define CONFIG_BOOTFILE "dnp1110"
#define CONFIG_BOOTCOMMAND "tftp; bootm"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h
index a014c7c..f8e2c88 100644
--- a/include/configs/eXalion.h
+++ b/include/configs/eXalion.h
@@ -58,17 +58,27 @@
/*#define CONFIG_DRAM_SPEED 66 */ /* MHz */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_FLASH | \
- CFG_CMD_SDRAM | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_ENV | \
- CFG_CMD_PCI )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_PCI
/*-----------------------------------------------------------------------
@@ -398,7 +408,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ebony.h b/include/configs/ebony.h
index a42319b..2c626a0 100644
--- a/include/configs/ebony.h
+++ b/include/configs/ebony.h
@@ -32,6 +32,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_EBONY 1 /* Board is ebony */
#define CONFIG_440GP 1 /* Specifc GP support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
@@ -121,7 +122,7 @@
#define CFG_FLASH_WORD_SIZE unsigned char
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
@@ -207,26 +208,38 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -235,7 +248,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -269,7 +282,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
@@ -286,7 +298,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -298,7 +310,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/ep7312.h b/include/configs/ep7312.h
index bdda629..f5cf477 100644
--- a/include/configs/ep7312.h
+++ b/include/configs/ep7312.h
@@ -62,12 +62,23 @@
#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_JFFS2)
+#define CONFIG_CMD_JFFS2
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600"
@@ -78,7 +89,7 @@
/*#define CONFIG_BOOTFILE "impa7" */
#define CONFIG_BOOTCOMMAND "bootp;bootm"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h
index 04147a5..85ad70a 100644
--- a/include/configs/ep8248.h
+++ b/include/configs/ep8248.h
@@ -60,8 +60,8 @@
* SCC, 1-3 for FCC)
*
* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
- * must be defined elsewhere (as for the console), or CFG_CMD_NET must
- * be removed from CONFIG_COMMANDS to remove support for networking.
+ * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
+ * must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
@@ -123,23 +123,34 @@
#define CONFIG_BAUDRATE 38400
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_DHCP \
- | CFG_CMD_ECHO \
- | CFG_CMD_I2C \
- | CFG_CMD_IMMAP \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -157,7 +168,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -183,20 +194,20 @@
#define CFG_DIRECT_FLASH_TFTP
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#if defined(CONFIG_CMD_JFFS2)
#define CFG_JFFS2_FIRST_BANK 0
#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS
#define CFG_JFFS2_FIRST_SECTOR 0
#define CFG_JFFS2_LAST_SECTOR 62
#define CFG_JFFS2_SORT_FRAGMENTS
#define CFG_JFFS_CUSTOM_PART
-#endif /* CFG_CMD_JFFS2 */
+#endif
-#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#if defined(CONFIG_CMD_I2C)
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
#define CFG_I2C_SPEED 100000 /* I2C speed */
#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
-#endif /* CFG_CMD_I2C */
+#endif
#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
@@ -240,7 +251,7 @@
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h
index 6862519..025c249 100644
--- a/include/configs/ep8260.h
+++ b/include/configs/ep8260.h
@@ -183,8 +183,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
@@ -291,37 +290,49 @@
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
-/* What U-Boot subsytems do you want enabled? */
+
/*
-*/
-#define CONFIG_COMMANDS ( CFG_CMD_ALL & \
- ~( CFG_CMD_BMP | \
- CFG_CMD_BSP | \
- CFG_CMD_DCR | \
- CFG_CMD_DHCP | \
- CFG_CMD_DISPLAY | \
- CFG_CMD_DOC | \
- CFG_CMD_DTT | \
- CFG_CMD_EEPROM | \
- CFG_CMD_EXT2 | \
- CFG_CMD_FDC | \
- CFG_CMD_FDOS | \
- CFG_CMD_HWFLOW | \
- CFG_CMD_IDE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_KGDB | \
- CFG_CMD_MII | \
- CFG_CMD_MMC | \
- CFG_CMD_NAND | \
- CFG_CMD_PCI | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_REISER | \
- CFG_CMD_SCSI | \
- CFG_CMD_SPI | \
- CFG_CMD_UNIVERSE| \
- CFG_CMD_USB | \
- CFG_CMD_VFD | \
- CFG_CMD_XIMG ) )
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_BMP
+#undef CONFIG_CMD_BSP
+#undef CONFIG_CMD_DCR
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DISPLAY
+#undef CONFIG_CMD_DOC
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_EXT2
+#undef CONFIG_CMD_FDC
+#undef CONFIG_CMD_FDOS
+#undef CONFIG_CMD_HWFLOW
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_KGDB
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_MFSL
+#undef CONFIG_CMD_MMC
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_PCI
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_REISER
+#undef CONFIG_CMD_SCSI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_UNIVERSE
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_VFD
+#undef CONFIG_CMD_XIMG
/* Where do the internal registers live? */
@@ -342,13 +353,10 @@
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -496,7 +504,7 @@
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h
index a77ccef..4febd32 100644
--- a/include/configs/ep82xxm.h
+++ b/include/configs/ep82xxm.h
@@ -60,8 +60,8 @@
* SCC, 1-3 for FCC)
*
* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
- * must be defined elsewhere (as for the console), or CFG_CMD_NET must
- * be removed from CONFIG_COMMANDS to remove support for networking.
+ * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
+ * must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
@@ -108,22 +108,34 @@
#define CFG_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_DHCP \
- | CFG_CMD_ECHO \
- | CFG_CMD_I2C \
- | CFG_CMD_IMMAP \
- | CFG_CMD_MII \
- | CFG_CMD_PING \
- | CFG_CMD_DATE \
- | CFG_CMD_DTT \
- | CFG_CMD_EEPROM \
- | CFG_CMD_PCI \
- | CFG_CMD_DIAG \
- )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_DIAG
+
#define CONFIG_ETHADDR 00:10:EC:00:88:65
#define CONFIG_HAS_ETH1
@@ -138,7 +150,7 @@
#define CONFIG_AUTO_COMPLETE 1
#define CONFIG_EXTRA_ENV_SETTINGS "ethprime=FCC3 ETHERNET"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -156,7 +168,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "ep82xxm=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -308,20 +320,20 @@
#define CFG_DIRECT_FLASH_TFTP
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#if defined(CONFIG_CMD_JFFS2)
#define CFG_JFFS2_FIRST_BANK 0
#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS
#define CFG_JFFS2_FIRST_SECTOR 0
#define CFG_JFFS2_LAST_SECTOR 62
#define CFG_JFFS2_SORT_FRAGMENTS
#define CFG_JFFS_CUSTOM_PART
-#endif /* CFG_CMD_JFFS2 */
+#endif
-#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#if defined(CONFIG_CMD_I2C)
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
#define CFG_I2C_SPEED 100000 /* I2C speed */
#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
-#endif /* CFG_CMD_I2C */
+#endif
#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
@@ -358,7 +370,7 @@
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h
index 88c2c74..66500c2 100644
--- a/include/configs/evb4510.h
+++ b/include/configs/evb4510.h
@@ -72,12 +72,23 @@
#define CONFIG_BAUDRATE 19200
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
+#define CONFIG_CMD_PING
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_ETHADDR 00:40:95:36:35:33
#define CONFIG_NETMASK 255.255.255.0
@@ -89,7 +100,7 @@
#define CONFIG_BOOTCOMMAND "tftp 100000 uImage"
/* #define CONFIG_BOOTARGS "console=ttyS0,19200 initrd=0x100a0040,530K root=/dev/ram keepinitrd" */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h
index b68a2dc..e11ce4c 100644
--- a/include/configs/gcplus.h
+++ b/include/configs/gcplus.h
@@ -79,18 +79,30 @@
#define CONFIG_BAUDRATE 38400
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySA0,38400n8 mtdparts=sa1100-flash:1m@0(zImage),3m@1m(ramdisk.gz),12m@4m(userfs) root=/dev/nfs ip=bootp"
#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
#define CFG_AUTOLOAD "n" /* No autoload */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 38400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/gth2.h b/include/configs/gth2.h
index a49ed3b..c2a50c1 100644
--- a/include/configs/gth2.h
+++ b/include/configs/gth2.h
@@ -71,12 +71,37 @@
/* Boot from Compact flash partition 2 as default */
#define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;run addmisc;bootm"
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP ) & \
- ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
- CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_LOADB | CFG_CMD_ELF | \
- CFG_CMD_BDI | CFG_CMD_BEDBUG | CFG_CMD_NFS | CFG_CMD_AUTOSCRIPT ))
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DHCP
+
+#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_FAT
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_AUTOSCRIPT
+
/*
* Miscellaneous configurable options
diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h
index 4f83b19..ff57240 100644
--- a/include/configs/gw8260.h
+++ b/include/configs/gw8260.h
@@ -194,8 +194,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC
@@ -286,13 +285,16 @@
#undef CONFIG_AUTOBOOT_DELAY_STR
#define DEBUG_BOOTKEYS 0
-/* Add support for a few extra bootp options like:
- * - File size
- * - DNS
+/*
+ * BOOTP options
*/
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE | \
- CONFIG_BOOTP_DNS)
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
/* undef this to save memory */
#define CFG_LONGHELP
@@ -300,14 +302,21 @@
/* Monitor Command Prompt */
#define CFG_PROMPT "=> "
-/* What U-Boot subsytems do you want enabled? */
-#define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_ELF | \
- CFG_CMD_ASKENV | \
- CFG_CMD_REGINFO | \
- CFG_CMD_IMMAP | \
- CFG_CMD_MII)
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+
+#undef CONFIG_CMD_KGDB
+
/* Where do the internal registers live? */
#define CFG_IMMR 0xf0000000
@@ -331,13 +340,10 @@
#define CONFIG_GW8260 1 /* on an GW8260 Board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -473,7 +479,7 @@
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h
new file mode 100644
index 0000000..577f459
--- /dev/null
+++ b/include/configs/hcu4.h
@@ -0,0 +1,348 @@
+/*
+ *(C) Copyright 2005-2007 Netstal Maschinen AG
+ * Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * hcu4.h - configuration for HCU4 board (similar to hcu5.h)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_HCU4 1 /* Board is HCU4 */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_405GPr 1 /* HCU4 has a 405GPr */
+#define CONFIG_405GP 1
+#define CONFIG_4xx 1
+
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+*----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+
+
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+
+/* ... with on-chip memory here (4KBytes) */
+#define CFG_OCM_DATA_ADDR 0xF4000000
+#define CFG_OCM_DATA_SIZE 0x00001000
+/* Do not set up locked dcache as init ram. */
+#undef CFG_INIT_DCACHE_CS
+
+/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
+#define CFG_TEMP_STACK_OCM 1
+
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* OCM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+/*
+ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ * baseBaud = cpuClock/(uartDivisor*16)
+ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#undef CONFIG_SERIAL_MULTI /* needed to be able to define
+ CONFIG_SERIAL_SOFTWARE_FIFO */
+#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD 691200
+
+/* Size (bytes) of interrupt driven serial port buffer.
+ * Set to 0 to use polling instead of interrupts.
+ * Setting to 0 will also disable RTS/CTS handshaking.
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+
+/* Set console baudrate to 9600 */
+#define CONFIG_BAUDRATE 9600
+
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_IS_IN_EEPROM
+#undef CFG_ENV_IS_NOWHERE
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+/* Put the environment after the SDRAM configuration */
+#define PROM_SIZE 2048
+#define CFG_ENV_OFFSET 512
+#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET)
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+/* Put the environment in Flash */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
+ * the first internal I2C controller of the PPC440EPx
+ *----------------------------------------------------------------------*/
+#define CFG_SPD_BUS_NUM 0
+
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+/* This is the 7bit address of the device, not including P. */
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+
+/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#undef CFG_I2C_MULTI_EEPROMS
+
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+/* Setup some board specific values for the default environment variables */
+#define CONFIG_HOSTNAME hcu4
+#define CONFIG_IPADDR 172.25.1.42
+#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_SERVERIP 172.25.1.3
+
+#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=0x01000000\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/home/diagnose/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/hcu4/uImage\0" \
+ "load=tftp 100000 hcu4/u-boot.bin\0" \
+ "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \
+ "cp.b 100000 FFFa0000 60000\0" \
+ "upd=run load;run update\0" \
+ "vx=tftp ${loadaddr} hcu4_vx_rom;" \
+ "setenv bootargs emac(0,0)hcu4_vx_rom e=${ipaddr} " \
+ " h=${serverip} u=dpu pw=netstal8752 tn=hcu4 f=0x3008;" \
+ "bootvx ${loadaddr}\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run vx"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 1 /* PHY address */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+/* SPD EEPROM (sdram speed config) disabled */
+#define CONFIG_SPD_EEPROM 1
+#define SPD_EEPROM_ADDRESS 0x50
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization */
+#define CFG_EBC_PB0AP 0x02005400
+#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
+
+#define CFG_EBC_PB1AP 0x03041200
+#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+
+#define CFG_EBC_PB2AP 0x02054500
+#define CFG_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+
+#define CFG_EBC_PB3AP 0x01840300
+#define CFG_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+
+#define CFG_EBC_PB4AP 0x01800300
+#define CFG_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+
+#define CFG_GPIO0_TCR 0x7ffe0000 /* GPIO value */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+/* Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
+
+
+/* Configuration Port location */
+#define CONFIG_PORT_ADDR 0xF0000500
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ *----------------------------------------------------------------------*/
+#define CFG_DCACHE_SIZE 16384 /* For IBM 405GPr CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_HUSH_PARSER /* use "hush" command parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h
new file mode 100644
index 0000000..9085881
--- /dev/null
+++ b/include/configs/hcu5.h
@@ -0,0 +1,391 @@
+/*
+ * (C) Copyright 2007 Netstal Maschinen AG
+ * Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * hcu5.h - configuration for HCU5 board (derived from sequoia.h)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_HCU5 1 /* Board is HCU5 */
+#define CONFIG_440EPX 1 /* Specific PPC440EPx */
+#define CONFIG_440 1 /* ... PPC440 family */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+
+#define CFG_BOOT_BASE_ADDR 0xfff00000
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_OCM_BASE 0xe0010000 /* ocm */
+#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
+
+/* Don't change either of these */
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
+
+#define CFG_USB2D0_BASE 0xe0000100
+#define CFG_USB_DEVICE 0xe0000000
+#define CFG_USB_HOST 0xe0000400
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
+#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
+
+#define CFG_INIT_RAM_END (4 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#define CONFIG_BAUDRATE 9600
+#undef CONFIG_SERIAL_MULTI /* needed to be able to define
+ CONFIG_SERIAL_SOFTWARE_FIFO, but
+ CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */
+/* Size (bytes) of interrupt driven serial port buffer.
+ * Set to 0 to use polling instead of interrupts.
+ * Setting to 0 will also disable RTS/CTS handshaking.
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_IS_IN_EEPROM
+#undef CFG_ENV_IS_NOWHERE
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+/* Put the environment after the SDRAM and bootstrap configuration */
+#define PROM_SIZE 2048
+#define CFG_BOOSTRAP_OPTION_OFFSET 512
+#define CFG_ENV_OFFSET (CFG_BOOSTRAP_OPTION_OFFSET + 0x10)
+#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET)
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+/* Put the environment in Flash */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */
+#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
+#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */
+#define CONFIG_DDR_ECC 1 /* enable ECC */
+
+/*-----------------------------------------------------------------------
+ * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
+ * the second internal I2C controller of the PPC440EPx
+ *----------------------------------------------------------------------*/
+#define CFG_SPD_BUS_NUM 1
+
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+/* This is the 7bit address of the device, not including P. */
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+
+/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#undef CFG_I2C_MULTI_EEPROMS
+
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run nfs\" to mount Linux root filesystem over NFS;"\
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+/* Setup some board specific values for the default environment variables */
+#define CONFIG_HOSTNAME hcu5
+#define CONFIG_IPADDR 172.25.1.42
+#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_SERVERIP 172.25.1.3
+
+#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=0x01000000\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "bootfile=hcu5/uImage\0" \
+ "rootpath=/home/hcu/eldk/ppc_4xxFP\0" \
+ "load=tftp 100000 hcu5/u-boot.bin\0" \
+ "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \
+ "cp.b 100000 FFFa0000 60000\0" \
+ "upd=run load;run update\0" \
+ "vx=tftp ${loadaddr} hcu5/hcu5_vx_rom;" \
+ "setenv bootargs emac(0,0)hcu5_vx_rom e=${ipaddr} " \
+ " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008;" \
+ "bootvx ${loadaddr}\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run vx"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_M88E1111_PHY 1
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR 1
+
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_USB
+
+#define CONFIG_SUPPORT_VFAT
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH CFG_FLASH_BASE
+#define CFG_CS_1 0xC8000000 /* CAN */
+#define CFG_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */
+#define CFG_CPLD CFG_CS_2
+#define CFG_CS_3 0xCD000000 /* CPLD and IMC-Bus Fast */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ * Memory Bank 0 (BOOT-FLASH) initialization
+ */
+#define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */
+#define CFG_EBC_PB0AP 0x02005400
+#define CFG_EBC_PB0CR 0xFFF18000 /* (CFG_FLASH | 0xda000) */
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
+
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+/* Memory Bank 1 CAN-Chips initialization */
+#define CFG_EBC_PB1AP 0x02054500
+#define CFG_EBC_PB1CR 0xC8018000
+
+/* Memory Bank 2 CPLD/IMC-Bus standard initialization */
+#define CFG_EBC_PB2AP 0x01840300
+#define CFG_EBC_PB2CR 0xCC0BA000
+
+/* Memory Bank 3 IMC-Bus fast mode initialization */
+#define CFG_EBC_PB3AP 0x01800300
+#define CFG_EBC_PB3CR 0xCE0BA000
+
+/* Memory Bank 4 (not used) initialization */
+#undef CFG_EBC_PB4AP
+#undef CFG_EBC_PB4CR
+
+/* Memory Bank 5 (not used) initialization */
+#undef CFG_EBC_PB5AP
+#undef CFG_EBC_PB5CR
+
+#define HCU_CPLD_VERSION_REGISTER ( CFG_CPLD + 0x0F00000 )
+#define HCU_HW_VERSION_REGISTER ( CFG_CPLD + 0x1400000 )
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ *----------------------------------------------------------------------*/
+#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_HUSH_PARSER /* use "hush" command parser */
+#ifdef CFG_HUSH_PARSER
+ #define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
diff --git a/include/configs/hermes.h b/include/configs/hermes.h
index 91117ba..e3a2ed2 100644
--- a/include/configs/hermes.h
+++ b/include/configs/hermes.h
@@ -64,23 +64,28 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_COMMANDS CONFIG_CMD_DFL
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-/*----------------------------------------------------------------------*/
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
-/*----------------------------------------------------------------------*/
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -157,7 +162,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h
index 095b5f6..6c15b4e 100644
--- a/include/configs/hmi1001.h
+++ b/include/configs/hmi1001.h
@@ -38,11 +38,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
#define CONFIG_BOARD_EARLY_INIT_R
/*
@@ -55,22 +50,31 @@
/* Partitions */
#define CONFIG_DOS_PARTITION
+
/*
- * Supported commands
+ * BOOTP options
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DISPLAY | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DISPLAY
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SNTP
+
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
@@ -110,7 +114,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration
@@ -222,7 +226,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -231,6 +235,11 @@
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/* Enable an alternate, more extensive memory test */
#define CFG_ALT_MEMTEST
@@ -242,8 +251,7 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
diff --git a/include/configs/hymod.h b/include/configs/hymod.h
index 8cad98d..2547afb 100644
--- a/include/configs/hymod.h
+++ b/include/configs/hymod.h
@@ -69,8 +69,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
@@ -174,32 +173,44 @@
#define CONFIG_LAST_STAGE_INIT
-#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
- CFG_CMD_BEDBUG | \
- CFG_CMD_BMP | \
- CFG_CMD_DISPLAY | \
- CFG_CMD_DOC | \
- CFG_CMD_EXT2 | \
- CFG_CMD_FDC | \
- CFG_CMD_FDOS | \
- CFG_CMD_FPGA | \
- CFG_CMD_HWFLOW | \
- CFG_CMD_IDE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_NAND | \
- CFG_CMD_MMC | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_PCI | \
- CFG_CMD_USB | \
- CFG_CMD_REISER | \
- CFG_CMD_SCSI | \
- CFG_CMD_SPI | \
- CFG_CMD_UNIVERSE| \
- CFG_CMD_VFD | \
- CFG_CMD_XIMG ) )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_BMP
+#undef CONFIG_CMD_DISPLAY
+#undef CONFIG_CMD_DOC
+#undef CONFIG_CMD_EXT2
+#undef CONFIG_CMD_FDC
+#undef CONFIG_CMD_FDOS
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_HWFLOW
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_MFSL
+#undef CONFIG_CMD_MMC
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_PCI
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_REISER
+#undef CONFIG_CMD_SCSI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_UNIVERSE
+#undef CONFIG_CMD_VFD
+#undef CONFIG_CMD_XIMG
+
#ifdef DEBUG
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
@@ -218,7 +229,7 @@
#define DEBUG_BOOTKEYS 0
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
@@ -247,7 +258,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -395,12 +406,13 @@
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
#endif
diff --git a/include/configs/idmr.h b/include/configs/idmr.h
index b1dbe2c..3821ebc 100644
--- a/include/configs/idmr.h
+++ b/include/configs/idmr.h
@@ -44,6 +44,8 @@
*/
#define CONFIG_BOOTCOMMAND "run net_nfs"
#define CONFIG_BOOTDELAY 5
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#define CONFIG_ETHADDR 00:06:3b:01:41:55
@@ -58,6 +60,8 @@
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root " \
"filesystem over NFS; echo"
+#define CONFIG_MCFTMR
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
@@ -78,18 +82,27 @@
"u-boot=/tftpboot/idmr/u-boot.bin\0" \
""
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Commands' definition
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
- CFG_CMD_PING | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_NET) & \
- ~(CFG_CMD_LOADS | \
- CFG_CMD_LOADB))
+#include <config_cmd_default.h>
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NET
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
/*
@@ -112,14 +125,16 @@
#define CFG_ENV_IS_IN_FLASH
#endif /* !CONFIG_MONITOR_IS_IN_RAM */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
#define CFG_PROMPT "=> "
#define CFG_LONGHELP /* undef to save memory */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else /* !(CONFIG_COMMANDS & CFG_CMD_KGDB) */
+#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif /* (CONFIG_COMMANDS & CFG_CMD_KGDB) */
+#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
@@ -138,11 +153,27 @@
/*
* Ethernet
*/
-#define FEC_ENET
-#define CONFIG_NET_RETRY_COUNT 5
-#define CFG_ENET_BD_BASE 0x480000
-#define CFG_DISCOVER_PHY 1
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
#define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
/*
* Definitions for initial stack pointer and data area (in DPRAM)
@@ -177,7 +208,7 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/* FLASH organization */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
@@ -206,8 +237,8 @@
"2m(rootfs)," \
"-(user)";
-#if (CONFIG_COMMANDS & CFG_CMD_MII)
-#error MII commands don't work on iDMR board and sholud not be enabled.
-#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) */
+#if defined(CONFIG_CMD_MII)
+#error "MII commands don't work on iDMR board and should not be enabled."
+#endif
#endif /* _IDMR_H */
diff --git a/include/configs/impa7.h b/include/configs/impa7.h
index 8b841ff..0e52ffe 100644
--- a/include/configs/impa7.h
+++ b/include/configs/impa7.h
@@ -61,12 +61,23 @@
#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_JFFS2)
+#define CONFIG_CMD_JFFS2
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600"
@@ -77,7 +88,7 @@
/*#define CONFIG_BOOTFILE "impa7" */
#define CONFIG_BOOTCOMMAND "bootp;bootm"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/incaip.h b/include/configs/incaip.h
index 1c6216b..4caf54e 100644
--- a/include/configs/incaip.h
+++ b/include/configs/incaip.h
@@ -81,15 +81,29 @@
""
#define CONFIG_BOOTCOMMAND "run flash_self"
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_SNTP )
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+
/*
* Miscellaneous configurable options
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index 773d5d2..0fac28f 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -40,11 +40,6 @@
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -76,21 +71,30 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
+
/*
- * Supported commands
+ * BOOTP options
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_EXT2 | \
- CFG_CMD_FAT | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_SNTP | \
- CFG_CMD_USB )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
@@ -147,7 +151,7 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* Flash configuration
@@ -239,7 +243,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -248,6 +252,11 @@
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/* Enable an alternate, more extensive memory test */
#define CFG_ALT_MEMTEST
@@ -259,8 +268,7 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
diff --git a/include/configs/innokom.h b/include/configs/innokom.h
index 3cb9ebc..5310e0d 100644
--- a/include/configs/innokom.h
+++ b/include/configs/innokom.h
@@ -54,10 +54,34 @@
#define CONFIG_BAUDRATE 19200
#define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */
-#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_I2C|CFG_CMD_DHCP|CFG_CMD_CACHE)
-/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_RUN
+
#define CONFIG_BOOTDELAY 3
/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
index 2f6e399..1452bf2 100644
--- a/include/configs/integratorap.h
+++ b/include/configs/integratorap.h
@@ -66,15 +66,26 @@
#define CFG_SERIAL0 0x16000000
#define CFG_SERIAL1 0x17000000
-/*#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */
/*#define CONFIG_NET_MULTI */
-/*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */
-#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_MEMORY
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 2
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty"
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
index 4189f9c..69310d4 100644
--- a/include/configs/integratorcp.h
+++ b/include/configs/integratorcp.h
@@ -70,17 +70,28 @@
#define CFG_SERIAL0 0x16000000
#define CFG_SERIAL1 0x17000000
+
/*
-#define CONFIG_COMMANDS (CFG_CMD_DFL | CFG_CMD_PCI)
-*/
-#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | \
- CFG_CMD_BDI | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_ENV \
- )
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-/* #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+
#if 0
#define CONFIG_BOOTDELAY 2
diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h
index 9f9fdb2..bc5f9e1 100644
--- a/include/configs/ixdp425.h
+++ b/include/configs/ixdp425.h
@@ -53,14 +53,28 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF | CFG_CMD_PCI)
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_PCI
+
#define CONFIG_PCI
#define CONFIG_NET_MULTI
#define CONFIG_EEPRO100
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-/* These are u-boot generic parameters */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 3
/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b*/
@@ -71,7 +85,7 @@
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
#define CONFIG_CMDLINE_TAG
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h
index af4ecf6..da59230 100644
--- a/include/configs/ixdpg425.h
+++ b/include/configs/ixdpg425.h
@@ -75,16 +75,27 @@
#define CONFIG_BAUDRATE 115200
#define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_NET | \
- CFG_CMD_MII | \
- CFG_CMD_PING)
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-/* These are u-boot generic parameters */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
index 5b97526..b7100e9 100644
--- a/include/configs/jupiter.h
+++ b/include/configs/jupiter.h
@@ -41,11 +41,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -71,7 +66,6 @@
#define CONFIG_PCI_IO_BUS 0x50000000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
-#define ADD_PCI_CMD CFG_CMD_PCI
#endif
#define CFG_XLB_PIPELINING 1
@@ -87,15 +81,28 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP)
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+#if defined(CONFIG_PCI)
+#define CODFIG_CMD_PCI
+#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Autobooting
@@ -138,12 +145,9 @@
#if 0
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,5200@0"
#define OF_SOC "soc5200@f0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -254,7 +258,7 @@
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -271,6 +275,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index cc47a16..7908e5a 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -42,7 +42,6 @@
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
-#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
#undef CONFIG_SHOW_BOOT_PROGRESS
/*-----------------------------------------------------------------------
@@ -67,11 +66,11 @@
#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
#define CFG_PCIE0_CFGBASE 0xc0000000
-#define CFG_PCIE0_XCFGBASE 0xc0000400
-#define CFG_PCIE1_CFGBASE 0xc0001000
-#define CFG_PCIE1_XCFGBASE 0xc0001400
-#define CFG_PCIE2_CFGBASE 0xc0002000
-#define CFG_PCIE2_XCFGBASE 0xc0002400
+#define CFG_PCIE1_CFGBASE 0xc1000000
+#define CFG_PCIE2_CFGBASE 0xc2000000
+#define CFG_PCIE0_XCFGBASE 0xc3000000
+#define CFG_PCIE1_XCFGBASE 0xc3001000
+#define CFG_PCIE2_XCFGBASE 0xc3002000
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
@@ -202,6 +201,7 @@
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
"kozio=bootm ffc60000\0" \
+ "pciconfighost=1\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -210,28 +210,40 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_EEPROM | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_DTT | \
- CFG_CMD_ELF | \
- CFG_CMD_EXT2 | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
#define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */
#define CONFIG_MII 1 /* MII PHY management */
@@ -254,7 +266,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -311,10 +323,9 @@
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
-#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#undef CFG_PCI_MASTER_INIT
@@ -421,7 +432,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -433,7 +444,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h
index 6590f6f..75d9c3b 100644
--- a/include/configs/kb9202.h
+++ b/include/configs/kb9202.h
@@ -78,17 +78,29 @@
#define CONFIG_BOOTDELAY 3
#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_COMMANDS \
- ((CONFIG_CMD_DFL | \
- CFG_CMD_I2C | \
- CFG_CMD_PING | \
- CFG_CMD_DHCP ) & \
- ~(CFG_CMD_BDI | \
- CFG_CMD_FPGA | \
- CFG_CMD_MISC))
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
diff --git a/include/configs/kvme080.h b/include/configs/kvme080.h
index 61cf705..569800a 100644
--- a/include/configs/kvme080.h
+++ b/include/configs/kvme080.h
@@ -60,32 +60,44 @@
#undef CONFIG_WATCHDOG
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_DS164x
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_CACHE | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP)
-#define CONFIG_NETCONSOLE
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
-#include <cmd_confdefs.h>
+
+#define CONFIG_NETCONSOLE
#define CFG_LONGHELP
#define CFG_PROMPT "=> "
@@ -178,7 +190,7 @@
#define CONFIG_SYS_CLK_FREQ 33333333
#define CFG_CACHELINE_SIZE 32
-#if CONFIG_COMMANDS & CFG_CMD_KGDB
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5
#endif
diff --git a/include/configs/lart.h b/include/configs/lart.h
index a00640b..8f18c9f 100644
--- a/include/configs/lart.h
+++ b/include/configs/lart.h
@@ -59,10 +59,21 @@
#define CONFIG_BAUDRATE 9600
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600"
@@ -73,7 +84,7 @@
#define CONFIG_BOOTFILE "elinos-lart"
#define CONFIG_BOOTCOMMAND "tftp; bootm"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/logodl.h b/include/configs/logodl.h
index 715ed74..2b2d377 100644
--- a/include/configs/logodl.h
+++ b/include/configs/logodl.h
@@ -54,10 +54,26 @@
#define CONFIG_BAUDRATE 19200
#undef CONFIG_MISC_INIT_R /* FIXME: misc_init_r() missing */
-#define CONFIG_COMMANDS (CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO)
-/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_RUN
+
#define CONFIG_BOOTDELAY 3
/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h
index 7e51523..e3fef5e 100644
--- a/include/configs/lpc2292sodimm.h
+++ b/include/configs/lpc2292sodimm.h
@@ -1,12 +1,8 @@
/*
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Configuation settings for the EP7312 board.
- *
- * Modified to work on Armadillo HT1070 ARM720T board
- * (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com
+ * Configuation settings for the LPC2292SODIMM board from Embedded Artists.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -31,7 +27,7 @@
#define __CONFIG_H
/*
- * If we are developing, we might want to start armboot from ram
+ * If we are developing, we might want to start u-boot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
#undef CONFIG_INIT_CRITICAL /* undef for developing */
@@ -46,7 +42,7 @@
#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */
#define CONFIG_LPC2292
-#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
+#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
#undef CONFIG_USE_IRQ /* don't need them anymore */
@@ -70,24 +66,31 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_FAT | \
- CFG_CMD_MMC | \
- CFG_CMD_NET | \
- CFG_CMD_PING)
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#define CONFIG_BOOTDELAY 5
/*
@@ -103,11 +106,12 @@
#define CFG_MEMTEST_START 0x40000000 /* memtest works on */
#define CFG_MEMTEST_END 0x40000000 /* 4 ... 8 MB in DRAM */
-#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
-#define CFG_LOAD_ADDR 0x00040000 /* default load address for armadillo: kernel img is here*/
+#define CFG_LOAD_ADDR 0x00040000 /* default load address for */
+ /* armadillo: kernel img is here*/
-#define CFG_SYS_CLK_FREQ 58982400 /* Hz */
+#define CFG_SYS_CLK_FREQ 58982400 /* Hz */
#define CFG_HZ 2048 /* decrementer freq in Hz */
/* valid baudrates */
@@ -154,5 +158,7 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_MMC 1
+/* we use this ethernet chip */
+#define CONFIG_ENC28J60
#endif /* __CONFIG_H */
diff --git a/include/configs/lpd7a400.h b/include/configs/lpd7a400.h
index d7d0460..0414889 100644
--- a/include/configs/lpd7a400.h
+++ b/include/configs/lpd7a400.h
@@ -55,19 +55,32 @@
#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#ifndef USE_920T_MMU
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING) & ~(CFG_CMD_CACHE))
+ #define CONFIG_CMD_PING
+ #undef CONFIG_CMD_CACHE
#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE)
+ #define CONFIG_CMD_DATE
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#define CONFIG_BOOTDELAY 3
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
diff --git a/include/configs/lpd7a404.h b/include/configs/lpd7a404.h
index 4002e68..11ede96 100644
--- a/include/configs/lpd7a404.h
+++ b/include/configs/lpd7a404.h
@@ -55,19 +55,32 @@
#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#ifndef USE_920T_MMU
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING) & ~(CFG_CMD_CACHE))
+ #define CONFIG_CMD_PING)
+ #undef CONFIG_CMD_CACHE
#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE)
+ #define CONFIG_CMD_DATE
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#define CONFIG_BOOTDELAY 3
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
diff --git a/include/configs/luan.h b/include/configs/luan.h
index 9c8769b..a09dd74 100644
--- a/include/configs/luan.h
+++ b/include/configs/luan.h
@@ -39,7 +39,6 @@
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
@@ -135,7 +134,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/
-#undef CONFIG_DDR_ECC /* no ECC support for now */
+#define CONFIG_DDR_ECC 1 /* with ECC support */
/*-----------------------------------------------------------------------
* I2C
@@ -212,31 +211,38 @@
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- 0)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -264,7 +270,7 @@
* PCI stuff
*-----------------------------------------------------------------------
*/
-#if (CONFIG_COMMANDS & CFG_CMD_PCI)
+#if defined(CONFIG_CMD_PCI)
/* General PCI */
#define CONFIG_PCI /* include pci support */
@@ -272,14 +278,13 @@
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#undef CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */
-#endif /* CONFIG_COMMANDS & CFG_CMD_PCI */
+#endif
/*
* For booting Linux, the board info and command line data
@@ -293,7 +298,7 @@
*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -305,7 +310,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h
index ad1035b..4adf254 100644
--- a/include/configs/lubbock.h
+++ b/include/configs/lubbock.h
@@ -67,10 +67,24 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
@@ -82,7 +96,7 @@
#define CONFIG_CMDLINE_TAG
#define CONFIG_TIMESTAMP
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h
index 9b4c004..8a82702 100644
--- a/include/configs/lwmon.h
+++ b/include/configs/lwmon.h
@@ -170,34 +170,41 @@
#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
-#else
-#define CFG_CMD_POST_DIAG 0
+#define CONFIG_CMD_DIAG
#endif
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BMP | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_SNTP )
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-/*----------------------------------------------------------------------*/
/*
* Miscellaneous configurable options
@@ -210,7 +217,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -276,7 +283,7 @@
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0x40000000
-#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
@@ -370,7 +377,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
new file mode 100644
index 0000000..be48324
--- /dev/null
+++ b/include/configs/lwmon5.h
@@ -0,0 +1,505 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * lwmon5.h - configuration for lwmon5 board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_LWMON5 1 /* Board is lwmon5 */
+#define CONFIG_440EPX 1 /* Specific PPC440EPx */
+#define CONFIG_440 1 /* ... PPC440 family */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
+#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
+
+#define CFG_BOOT_BASE_ADDR 0xf0000000
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_LIME_BASE_0 0xc0000000
+#define CFG_LIME_BASE_1 0xc1000000
+#define CFG_LIME_BASE_2 0xc2000000
+#define CFG_LIME_BASE_3 0xc3000000
+#define CFG_FPGA_BASE_0 0xc4000000
+#define CFG_FPGA_BASE_1 0xc4200000
+#define CFG_OCM_BASE 0xe0010000 /* ocm */
+#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
+
+/* Don't change either of these */
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
+
+#define CFG_USB2D0_BASE 0xe0000100
+#define CFG_USB_DEVICE 0xe0000000
+#define CFG_USB_HOST 0xe0000400
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
+#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
+#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
+
+#define CFG_INIT_RAM_END (4 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK /* no external clock provided */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI 1
+/* define this if you want console on UART1 */
+#define CONFIG_UART1_CONSOLE 1 /* use UART1 as console */
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CFG_FLASH0 0xFC000000
+#define CFG_FLASH1 0xF8000000
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
+
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+
+#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CFG_MBYTES_SDRAM (256) /* 256MB */
+#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
+#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
+#if 0 /* test-only: disable ECC for now */
+#define CONFIG_DDR_ECC 1 /* enable ECC */
+#define CFG_POST_ECC_ON CFG_POST_ECC
+#else
+#define CFG_POST_ECC_ON 0
+#endif
+
+/* POST support */
+#define CONFIG_POST (CFG_POST_CACHE | \
+ CFG_POST_CPU | \
+ CFG_POST_ECC_ON | \
+ CFG_POST_ETHER | \
+ CFG_POST_FPU | \
+ CFG_POST_I2C | \
+ CFG_POST_MEMORY | \
+ CFG_POST_RTC | \
+ CFG_POST_SPR | \
+ CFG_POST_UART)
+
+#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */
+#define CONFIG_LOGBUFFER
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
+ /* 64 byte page write mode using*/
+ /* last 6 bits of the address */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+#define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */
+#define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
+#define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
+
+#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
+#if 0
+#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */
+#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
+#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */
+#endif
+
+#define CONFIG_PREBOOT "setenv bootdelay 15"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hostname=lwmon5\0" \
+ "netdev=eth0\0" \
+ "unlock=yes\0" \
+ "logversion=2\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xxFP\0" \
+ "bootfile=/tftpboot/lwmon5/uImage\0" \
+ "kernel_addr=FC000000\0" \
+ "ramdisk_addr=FC180000\0" \
+ "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
+ "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
+ "cp.b 200000 FFF80000 80000\0" \
+ "upd=run load;run update\0" \
+ "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
+ "autoscr 200000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_RESET_DELAY 300
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR 1
+
+/* USB */
+#ifdef CONFIG_440EPX
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+#endif /* CONFIG_440EPX */
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+#ifdef CONFIG_440EPX
+#define CONFIG_CMD_USB
+#endif
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CONFIG_SUPPORT_VFAT
+
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
+
+#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH CFG_FLASH_BASE
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x03050200
+#define CFG_EBC_PB0CR (CFG_FLASH | 0xfc000)
+
+/* Memory Bank 1 (Lime) initialization */
+#define CFG_EBC_PB1AP 0x01004380
+#define CFG_EBC_PB1CR (CFG_LIME_BASE_0 | 0xdc000)
+
+/* Memory Bank 2 (FPGA) initialization */
+#define CFG_EBC_PB2AP 0x01004400
+#define CFG_EBC_PB2CR (CFG_FPGA_BASE_0 | 0x1c000)
+
+/* Memory Bank 3 (FPGA2) initialization */
+#define CFG_EBC_PB3AP 0x01004400
+#define CFG_EBC_PB3CR (CFG_FPGA_BASE_1 | 0x1c000)
+
+#define CFG_EBC_CFG 0xb8400000
+
+/*-----------------------------------------------------------------------
+ * Graphics (Fujitsu Lime)
+ *----------------------------------------------------------------------*/
+/* SDRAM Clock frequency adjustment register */
+#define CFG_LIME_SDRAM_CLOCK 0xC1FC0038
+/* Lime Clock frequency is to set 100MHz */
+#define CFG_LIME_CLOCK_100MHZ 0x00000
+#if 0
+/* Lime Clock frequency for 133MHz */
+#define CFG_LIME_CLOCK_133MHZ 0x10000
+#endif
+
+/* SDRAM Parameter register */
+#define CFG_LIME_MMR 0xC1FCFFFC
+/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
+ and pixel flare on display when 133MHz was configured. According to
+ SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
+#ifdef CFG_LIME_CLOCK_133MHZ
+#define CFG_LIME_MMR_VALUE 0x414FB7F3
+#else
+#define CFG_LIME_MMR_VALUE 0x414FB7F2
+#endif
+
+/*-----------------------------------------------------------------------
+ * GPIO Setup
+ *----------------------------------------------------------------------*/
+#define CFG_GPIO_PHY1_RST 12
+#define CFG_GPIO_FLASH_WP 14
+#define CFG_GPIO_PHY0_RST 22
+#define CFG_GPIO_EEPROM_EXT_WP 55
+#define CFG_GPIO_EEPROM_INT_WP 57
+#define CFG_GPIO_LIME_S 59
+#define CFG_GPIO_LIME_RST 60
+#define CFG_GPIO_WATCHDOG 63
+
+/*-----------------------------------------------------------------------
+ * PPC440 GPIO Configuration
+ */
+#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
+{ \
+/* GPIO Core 0 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
+}, \
+{ \
+/* GPIO Core 1 */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO58 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
+} \
+}
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ *----------------------------------------------------------------------*/
+#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index 621a81c..cc2dbcd 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -40,11 +40,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*
@@ -92,27 +87,37 @@
/* USB */
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
/* automatic software updates (see board/mcc200/auto_update.c) */
#define CONFIG_AUTO_UPDATE 1
+
/*
- * Supported commands
+ * BOOTP options
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- ADD_USB_CMD | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C)
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_USB
+
+#undef CONFIG_CMD_NET
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Autobooting
*/
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
@@ -128,20 +133,30 @@
# define CFG__LINUX_CONSOLE "ttyS0"
#else
# define CFG__BOARDNAME "mcc200"
-# define CFG__LINUX_CONSOLE "ttyEU7"
+# define CFG__LINUX_CONSOLE "ttyEU5"
#endif
+/* Network */
+#define CONFIG_ETHADDR 00:17:17:ff:00:00
+#define CONFIG_IPADDR 10.76.9.29
+#define CONFIG_SERVERIP 10.76.9.1
+
+#include <version.h> /* For U-Boot version */
+
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "ubootver=" U_BOOT_VERSION "\0" \
"netdev=eth0\0" \
"hostname=" CFG__BOARDNAME "\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "ramargs=setenv bootargs root=/dev/mtdblock2 " \
+ "rootfstype=cramfs\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addcons=setenv bootargs ${bootargs} " \
- "console=${console},${baudrate}\0" \
+ "console=${console},${baudrate} " \
+ "ubootver=${ubootver} board=${board}\0" \
"flash_nfs=run nfsargs addip addcons;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addcons;" \
@@ -153,6 +168,7 @@
"bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0" \
"load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0" \
"text_base=" MK_STR(TEXT_BASE) "\0" \
+ "kernel_addr=0xFC0C0000\0" \
"update=protect off ${text_base} +${filesize};" \
"era ${text_base} +${filesize};" \
"cp.b 200000 ${text_base} ${filesize}\0" \
@@ -169,7 +185,7 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration
@@ -253,7 +269,7 @@
/*
* Ethernet configuration
*/
-#define CONFIG_MPC5xxx_FEC 1
+/*#define CONFIG_MPC5xxx_FEC 1*/
/*
* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
*/
@@ -291,7 +307,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -307,6 +323,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
@@ -329,6 +350,13 @@
#define CFG_CS1_SIZE 0x00001000
#define CFG_CS1_CFG 0x1d300
+/* Leica - build revision resistors */
+/*
+#define CFG_CS3_START 0x80020000
+#define CFG_CS3_SIZE 0x00000004
+#define CFG_CS3_CFG 0x1d300
+*/
+
/*
* Select one of quarts as a default
* console. If undefined - PSC console
@@ -384,4 +412,8 @@
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00005000
+#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR "432"
+#define CONFIG_SILENT_CONSOLE 1
+
#endif /* __CONFIG_H */
diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h
index 0c10294..49919fb 100644
--- a/include/configs/mecp5200.h
+++ b/include/configs/mecp5200.h
@@ -50,11 +50,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -88,26 +83,32 @@
/* USB */
#if 0
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD 0
#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_EEPROM | \
- CFG_CMD_FAT | \
- CFG_CMD_EXT2 | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_BSP | \
- CFG_CMD_ELF)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_ELF
+
#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CFG_LOWBOOT 1
@@ -258,7 +259,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -276,6 +277,11 @@
#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/ml300.h b/include/configs/ml300.h
index 6762cd6..0183041 100644
--- a/include/configs/ml300.h
+++ b/include/configs/ml300.h
@@ -87,13 +87,28 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define REMOVE_COMMANDS (CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_FAT | \
- CFG_CMD_IMLS )
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_NET) \
- & ~REMOVE_COMMANDS)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NET
+
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_FAT
+#undef CONFIG_CMD_IMLS
+
/* #define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ */
/* 300000000 */
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index cb159e7..7eeae70 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -28,6 +28,7 @@
#include "../board/xilinx/ml401/xparameters.h"
#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
+#define MICROBLAZE_V5 1
#define CONFIG_ML401 1 /* ML401 Board */
/* uart */
@@ -36,11 +37,11 @@
#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
/* setting reset address */
-#define CFG_RESET_ADDRESS TEXT_BASE
+/*#define CFG_RESET_ADDRESS TEXT_BASE*/
/* ethernet */
#define CONFIG_EMACLITE 1
-#define XPAR_EMAC_0_DEVICE_ID XPAR_XEMAC_NUM_INSTANCES
+#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
/* gpio */
#define CFG_GPIO_0 1
@@ -58,6 +59,10 @@
#define FREQUENCE XILINX_CLOCK_FREQ
#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
+/* FSL */
+#define CFG_FSL_2
+#define FSL_INTR_2 1
+
/*
* memory layout - Example
* TEXT_BASE = 0x1200_0000;
@@ -93,7 +98,8 @@
/* global pointer */
#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
-#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */
+/* start of global data */
+#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
/* monitor code */
#define SIZE 0x40000
@@ -117,6 +123,7 @@
#define CFG_FLASH_EMPTY_INFO 1 /* ?empty sector */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+ #define CFG_FLASH_PROTECTION /* hardware flash protection */
#ifdef RAMENV
#define CFG_ENV_IS_NOWHERE 1
@@ -135,69 +142,62 @@
#define CFG_ENV_IS_NOWHERE 1
#define CFG_ENV_SIZE 0x1000
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
+ #define CFG_FLASH_PROTECTION /* hardware flash protection */
#endif /* !FLASH */
-#ifdef FLASH
- #ifdef RAMENV
- #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
- CFG_CMD_MEMORY |\
- CFG_CMD_MISC |\
- CFG_CMD_AUTOSCRIPT |\
- CFG_CMD_IRQ |\
- CFG_CMD_ASKENV |\
- CFG_CMD_BDI |\
- CFG_CMD_RUN |\
- CFG_CMD_LOADS |\
- CFG_CMD_LOADB |\
- CFG_CMD_IMI |\
- CFG_CMD_NET |\
- CFG_CMD_CACHE |\
- CFG_CMD_IMLS |\
- CFG_CMD_FLASH |\
- CFG_CMD_PING \
- )
- #else /* !RAMENV */
- #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
- CFG_CMD_MEMORY |\
- CFG_CMD_MISC |\
- CFG_CMD_AUTOSCRIPT |\
- CFG_CMD_IRQ |\
- CFG_CMD_ASKENV |\
- CFG_CMD_BDI |\
- CFG_CMD_RUN |\
- CFG_CMD_LOADS |\
- CFG_CMD_LOADB |\
- CFG_CMD_IMI |\
- CFG_CMD_NET |\
- CFG_CMD_CACHE |\
- CFG_CMD_IMLS |\
- CFG_CMD_FLASH |\
- CFG_CMD_PING |\
- CFG_CMD_ENV |\
- CFG_CMD_SAVES \
- )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MFSL
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+
+#if defined(FLASH)
+ #define CONFIG_CMD_ECHO
+ #define CONFIG_CMD_FLASH
+ #define CONFIG_CMD_IMLS
+ #define CONFIG_CMD_JFFS2
+
+ #if !defined(RAMENV)
+ #define CONFIG_CMD_ENV
+ #define CONFIG_CMD_SAVES
#endif
+#endif
+
+#if defined(CONFIG_CMD_JFFS2)
+/* JFFS2 partitions */
+#define CONFIG_JFFS2_CMDLINE /* mtdparts command line support */
+#define MTDIDS_DEFAULT "nor0=ml401-0"
-#else /* !FLASH */
- #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
- CFG_CMD_MEMORY |\
- CFG_CMD_MISC |\
- CFG_CMD_AUTOSCRIPT |\
- CFG_CMD_IRQ |\
- CFG_CMD_ASKENV |\
- CFG_CMD_BDI |\
- CFG_CMD_RUN |\
- CFG_CMD_LOADS |\
- CFG_CMD_LOADB |\
- CFG_CMD_IMI |\
- CFG_CMD_NET |\
- CFG_CMD_CACHE |\
- CFG_CMD_PING \
- )
-#endif /* !FLASH */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/* default mtd partition table */
+#define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\
+ "256k(env),3m(kernel),1m(romfs),"\
+ "1m(cramfs),-(jffs2)"
+#endif
/* Miscellaneous configurable options */
#define CFG_PROMPT "U-Boot-mONStR> "
@@ -207,7 +207,7 @@
#define CFG_LONGHELP
#define CFG_LOAD_ADDR 0x12000000 /* default load address */
-#define CONFIG_BOOTDELAY 30
+#define CONFIG_BOOTDELAY 30
#define CONFIG_BOOTARGS "root=romfs"
#define CONFIG_HOSTNAME "ml401"
#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
@@ -221,10 +221,19 @@
#define CFG_HZ 1000
/* system ace */
-/*#define CONFIG_SYSTEMACE
-#define DEBUG_SYSTEMACE
-#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
-#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
-#define CONFIG_DOS_PARTITION
-*/
+#define CONFIG_SYSTEMACE
+/* #define DEBUG_SYSTEMACE */
+#define SYSTEMACE_CONFIG_FPGA
+#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
+#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo"
+
+#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\
+ "nor0=ml401-0\0"\
+ "mtdparts=mtdparts=ml401-0:"\
+ "256k(u-boot),256k(env),3m(kernel),"\
+ "1m(romfs),1m(cramfs),-(jffs2)\0"
+
#endif /* __CONFIG_H */
diff --git a/include/configs/modnet50.h b/include/configs/modnet50.h
index 2028767..4461bdf 100644
--- a/include/configs/modnet50.h
+++ b/include/configs/modnet50.h
@@ -63,12 +63,23 @@
#define CONFIG_BAUDRATE 38400
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_JFFS2))
+#define CONFIG_CMD_JFFS2
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.30.2
@@ -81,7 +92,7 @@
#define CONFIG_BOOTCOMMAND "bootm 0x10020000 0x100a0000"
#define CONFIG_BOOTARGS "console=ttyS0,38400 initrd=0x100a0040,530K root=/dev/ram keepinitrd"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 5328e8d..9a21632 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -26,12 +26,10 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-
/*
* High Level Configuration Options
*/
-
/* CPU and board */
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
@@ -39,21 +37,35 @@
/*
- * Supported commands
+ * BOOTP options
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_REGINFO | \
- CFG_CMD_IMMAP | \
- CFG_CMD_ELF | \
- CFG_CMD_MII | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_NET | \
- CFG_CMD_PING)
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DTT
/*
@@ -71,7 +83,7 @@
#define CONFIG_MPC5xxx_FEC 1
#define CONFIG_PHY_ADDR 0x2
#define CONFIG_PHY_TYPE 0x79c874
-
+#define CONFIG_RESET_PHY_R 1
/*
* Autobooting
@@ -94,42 +106,51 @@
* Default environment settings
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
- "sdram_test=0\0" \
"netdev=eth0\0" \
"hostname=motionpro\0" \
"netmask=255.255.0.0\0" \
"ipaddr=192.168.160.22\0" \
"serverip=192.168.1.1\0" \
"gatewayip=192.168.1.1\0" \
- "kernel_addr=200000\0" \
+ "console=ttyPSC0,115200\0" \
"u-boot_addr=100000\0" \
- "kernel_sector=20\0" \
- "kernel_size=1000\0" \
- "console=ttyS0,115200\0" \
+ "kernel_addr=200000\0" \
+ "fdt_addr=400000\0" \
+ "ramdisk_addr=500000\0" \
+ "multi_image_addr=800000\0" \
"rootpath=/opt/eldk-4.1/ppc_6xx\0" \
- "bootfile=/tftpboot/motionpro/uImage\0" \
"u-boot=/tftpboot/motionpro/u-boot.bin\0" \
- "load=tftp $(u-boot_addr) $(u-boot)\0" \
+ "bootfile=/tftpboot/motionpro/uImage\0" \
+ "fdt_file=/tftpboot/motionpro/motionpro.dtb\0" \
+ "ramdisk_file=/tftpboot/motionpro/uRamdisk\0" \
+ "multi_image_file=kernel+initrd+dtb.img\0" \
+ "load=tftp ${u-boot_addr} ${u-boot}\0" \
"update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; " \
- "cp.b $(u-boot_addr) fff00000 $(filesize);" \
+ "cp.b ${u-boot_addr} fff00000 ${filesize};" \
"prot on fff00000 fff3ffff\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $(bootargs) console=$(console) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):" \
- "$(netmask):$(hostname):$(netdev):off panic=1\0" \
- "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
- "flash_self=run ramargs addip;bootm $(kernel_addr) " \
- "$(ramdisk_addr)\0" \
- "net_nfs=tftp $(kernel_addr) $(bootfile); run nfsargs addip; " \
- "bootm $(kernel_addr)\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
- "fstype=ext3\0" \
- "fatargs=setenv bootargs init=/linuxrc rw\0" \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "fat_args=setenv bootargs rw\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:${netdev}:off panic=1 " \
+ "console=${console}\0" \
+ "net_nfs=tftp ${kernel_addr} ${bootfile}; " \
+ "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip; " \
+ "bootm ${kernel_addr} - ${fdt_addr}\0" \
+ "net_self=tftp ${kernel_addr} ${bootfile}; " \
+ "tftp ${fdt_addr} ${fdt_file}; " \
+ "tftp ${ramdisk_addr} ${ramdisk_file}; " \
+ "run ramargs addip; " \
+ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
+ "fat_multi=run fat_args addip; fatload ide 0:1 " \
+ "${multi_image_addr} ${multi_image_file}; " \
+ "bootm ${multi_image_addr}\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
-
/*
* do board-specific init
*/
@@ -148,6 +169,12 @@
/*
+ * Set IPB speed to 100MHz
+ */
+#define CFG_IPBCLK_EQUALS_XLBCLK
+
+
+/*
* Memory map
*/
/*
@@ -243,6 +270,84 @@
#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
#define CONFIG_FLASH_16BIT /* Flash is 16-bit */
+/*
+ * MTD configuration
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=motionpro-0"
+#define MTDPARTS_DEFAULT "mtdparts=motionpro-0:" \
+ "13m(fs),2m(kernel),256k(uboot)," \
+ "64k(env),64k(redund_env),64k(dtb)," \
+ "-(user_data)"
+
+/*
+ * IDE/ATA configuration
+ */
+#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
+#define CFG_IDE_MAXBUS 1
+#define CFG_IDE_MAXDEVICE 1
+#define CONFIG_IDE_PREINIT
+
+#define CFG_ATA_DATA_OFFSET 0x0060
+#define CFG_ATA_REG_OFFSET CFG_ATA_DATA_OFFSET
+#define CFG_ATA_STRIDE 4
+#define CONFIG_DOS_PARTITION
+
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CFG_I2C_MODULE 2 /* select I2C module #2 */
+#define CFG_I2C_SPEED 100000 /* 100 kHz */
+#define CFG_I2C_SLAVE 0x7F
+
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* DTT driver needs this */
+#define CFG_EEPROM_PAGE_WRITE_BITS 1 /* 2 bytes per write cycle */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 5 /* 2ms/cycle + 3ms extra */
+#define CFG_I2C_MULTI_EEPROMS 1 /* 2 EEPROMs (addr:50,52) */
+
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_DS1337 1
+#define CFG_I2C_RTC_ADDR 0x68
+
+
+/*
+ * Status LED configuration
+ */
+#define CONFIG_STATUS_LED /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED
+
+#define ENABLE_GPIO_OUT 0x00000024
+#define LED_ON 0x00000010
+
+#ifndef __ASSEMBLY__
+/*
+ * In case of Motion-PRO, a LED is identified by its corresponding
+ * GPT Enable and Mode Select Register.
+ */
+typedef volatile unsigned long * led_id_t;
+
+extern void __led_init(led_id_t id, int state);
+extern void __led_toggle(led_id_t id);
+extern void __led_set(led_id_t id, int state);
+#endif /* __ASSEMBLY__ */
+
+
+/*
+ * Temperature sensor
+ */
+#define CONFIG_DTT_LM75 1
+#define CONFIG_DTT_SENSORS { 0x49 }
+
/*
* Environment settings
@@ -253,6 +358,9 @@
#define CFG_ENV_SIZE 0x1000
#define CFG_ENV_SECT_SIZE 0x10000
+/* Configuration of redundant environment */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
/*
* Pin multiplexing configuration
@@ -270,11 +378,17 @@
/*
+ * Motion-PRO's CPLD revision control register
+ */
+#define CPLD_REV_REGISTER (CFG_CS2_START + 0x06)
+
+
+/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
@@ -302,4 +416,13 @@
/* Not needed for MPC 5xxx U-Boot, but used by tools/updater */
#define CFG_RESET_ADDRESS 0xfff00100
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_CPU "PowerPC,5200@0"
+#define OF_SOC "soc5200@f0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
+
#endif /* __CONFIG_H */
diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h
index 04f1f24..ea5a44b 100644
--- a/include/configs/mp2usb.h
+++ b/include/configs/mp2usb.h
@@ -101,12 +101,18 @@
#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
-#define CONFIG_USB_OHCI 1
+#define CONFIG_USB_OHCI_NEW 1
#define CONFIG_USB_KEYBOARD 1
#define CONFIG_USB_STORAGE 1
#define CONFIG_DOS_PARTITION 1
#define CONFIG_AT91C_PQFP_UHPBUG 1
+#undef CFG_USB_OHCI_BOARD_INIT
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
+#define CFG_USB_OHCI_SLOT_NAME "at91rm9200"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+
#undef CONFIG_HARD_I2C
#ifdef CONFIG_HARD_I2C
@@ -123,40 +129,56 @@
#define CONFIG_BOOTDELAY 3
-#ifdef CONFIG_HARD_I2C
-#define CONFIG_COMMANDS \
- ((CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP | \
- CFG_CMD_MISC))
-#else
-#define CONFIG_COMMANDS \
- ((CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP | \
- CFG_CMD_USB | \
- CFG_CMD_CACHE) & \
- ~(CFG_CMD_BDI | \
- CFG_CMD_IMI | \
- CFG_CMD_AUTOSCRIPT | \
- CFG_CMD_FPGA | \
- CFG_CMD_MISC | \
- CFG_CMD_LOADS ))
+#if !defined(CONFIG_HARD_I2C)
#define CONFIG_TIMESTAMP
#endif
-#define CFG_LONGHELP
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+#if defined(CONFIG_HARD_I2C)
+
+ #define CONFIG_CMD_DATE
+ #define CONFIG_CMD_EEPROM
+ #define CONFIG_CMD_I2C
+ #define CONFIG_CMD_MISC
+
+#else
+
+ #define CONFIG_CMD_USB
+ #define CONFIG_CMD_CACHE
+
+ #undef CONFIG_CMD_AUTOSCRIPT
+ #undef CONFIG_CMD_BDI
+ #undef CONFIG_CMD_FPGA
+ #undef CONFIG_CMD_IMI
+ #undef CONFIG_CMD_LOADS
+ #undef CONFIG_CMD_MISC
+
+#endif
+
+
+#define CFG_LONGHELP
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
-#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
+#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
#define CFG_MEMTEST_START PHYS_SDRAM
#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h
index 243a3f6..bd3107a 100644
--- a/include/configs/mpc7448hpc2.h
+++ b/include/configs/mpc7448hpc2.h
@@ -80,9 +80,6 @@
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,7448@0"
#define OF_TSI "tsi108@c0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
@@ -146,25 +143,34 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
-
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_ASKENV \
- | CFG_CMD_CACHE \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C \
- | CFG_CMD_SDRAM \
- | CFG_CMD_EEPROM \
- | CFG_CMD_FLASH \
- | CFG_CMD_ENV \
- | CFG_CMD_BSP \
- | CFG_CMD_DHCP \
- | CFG_CMD_PING \
- | CFG_CMD_DATE)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
+
/*set date in u-boot*/
#define CONFIG_RTC_M48T35A
@@ -182,7 +188,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
#else
@@ -366,9 +372,9 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1/* Flash can be at one of two addresses */
+#define CFG_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */
#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
-#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, /* CFG_FLASH_BASE2 */ }
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
@@ -387,7 +393,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h
index 7f3dfd5..5125b21 100644
--- a/include/configs/mx1ads.h
+++ b/include/configs/mx1ads.h
@@ -78,25 +78,32 @@
#define CONFIG_BAUDRATE 115200
-/***********************************************************
- * Command definition
- ***********************************************************/
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | \
- CFG_CMD_CACHE | \
- CFG_CMD_REGINFO | \
- CFG_CMD_ELF)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_ELF
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "root=/dev/msdk mem=48M"
#define CONFIG_BOOTFILE "mx1ads"
#define CONFIG_BOOTCOMMAND "tftp; bootm"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h
index 9816be8..d527d09 100644
--- a/include/configs/mx1fs2.h
+++ b/include/configs/mx1fs2.h
@@ -34,22 +34,30 @@
#undef _CONFIG_UART4 /* internal uart 4 */
#undef CONFIG_SILENT_CONSOLE /* use this to disable output */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
- * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
- * functionality or size of u-boot code.
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- & ~CFG_CMD_LOADS \
- & ~CFG_CMD_CONSOLE \
- & ~CFG_CMD_AUTOSCRIPT \
- & ~CFG_CMD_NET \
- & ~CFG_CMD_PING \
- & ~CFG_CMD_DHCP \
- | CFG_CMD_JFFS2 \
- )
-
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_JFFS2
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_CONSOLE
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_PING
+#undef CONFIG_CMD_DHCP
+
/*
* Boot options. Setting delay to -1 stops autostart count down.
@@ -160,7 +168,7 @@
* Right now there is no gain for user, but later on booting kernel might be
* possible. Consider using XIP kernel running from flash to save RAM
* footprint.
- * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
*/
/*
diff --git a/include/configs/netstar.h b/include/configs/netstar.h
index 697796a..33159d3 100644
--- a/include/configs/netstar.h
+++ b/include/configs/netstar.h
@@ -140,42 +140,37 @@
#define MTDIDS_DEFAULT "nor0=omapflash.0,nand0=omapnand.0"
#define MTDPARTS_DEFAULT "mtdparts=omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);omapnand.0:48M(rootfs0),48M(rootfs1),-(data)"
-#if 0
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_BOOTD | \
- CFG_CMD_DHCP | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_IMI | \
- CFG_CMD_LOADB | \
- CFG_CMD_NET | \
- CFG_CMD_MEMORY | \
- CFG_CMD_PING | \
- CFG_CMD_RUN)
-#else
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_BOOTD | \
- CFG_CMD_DHCP | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_NAND | \
- CFG_CMD_IMI | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_LOADB | \
- CFG_CMD_NET | \
- CFG_CMD_MEMORY | \
- CFG_CMD_PING | \
- CFG_CMD_RUN)
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
-#endif
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-#define CONFIG_LOOPW
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_LOOPW
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h
index 0b1541d..1d691f9 100644
--- a/include/configs/ns9750dev.h
+++ b/include/configs/ns9750dev.h
@@ -69,33 +69,28 @@
#define CONFIG_BAUDRATE 38400
-/***********************************************************
- * Command definition
- ***********************************************************/
-#if 0 /* @TODO */
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | \
- CFG_CMD_CACHE | \
- /*CFG_CMD_NAND |*/ \
- /*CFG_CMD_EEPROM |*/ \
- /*CFG_CMD_I2C |*/ \
- /*CFG_CMD_USB |*/ \
- CFG_CMD_REGINFO | \
- CFG_CMD_DATE | \
- CFG_CMD_ELF)
-#else
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_BDI | \
- CFG_CMD_NET | \
- CFG_CMD_PING | \
- CFG_CMD_CONSOLE | \
- CFG_CMD_LOADB | \
- CFG_CMD_LOADS | \
- CFG_CMD_MEMORY)
-#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+
#define CONFIG_BOOTDELAY 3
/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
@@ -108,7 +103,7 @@
/*#define CONFIG_BOOTFILE "elinos-lart" */
/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
index 5c05a74..f1d73e4 100644
--- a/include/configs/o2dnt.h
+++ b/include/configs/o2dnt.h
@@ -37,11 +37,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -73,8 +68,6 @@
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
-#define ADD_PCI_CMD CFG_CMD_PCI
-
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -82,20 +75,29 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_EEPROM | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- ADD_PCI_CMD )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PCI
+
#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CFG_LOWBOOT 1
@@ -137,17 +139,17 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
-#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
#endif
@@ -246,7 +248,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -262,6 +264,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
@@ -276,7 +283,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
/*
* For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
*/
diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h
index fe4e638..bc2fd33 100644
--- a/include/configs/ocotea.h
+++ b/include/configs/ocotea.h
@@ -41,6 +41,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_OCOTEA 1 /* Board is ebony */
#define CONFIG_440GX 1 /* Specifc GX support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
@@ -136,7 +137,7 @@
#define CFG_FLASH_WORD_SIZE unsigned char
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
@@ -231,26 +232,38 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -259,7 +272,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -293,7 +306,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
@@ -310,7 +322,7 @@
*/
#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -322,7 +334,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/omap1510inn.h b/include/configs/omap1510inn.h
index 016d3d8..8623ed3 100644
--- a/include/configs/omap1510inn.h
+++ b/include/configs/omap1510inn.h
@@ -86,11 +86,24 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+
#include <configs/omap1510.h>
#define CONFIG_BOOTDELAY 3
@@ -98,7 +111,7 @@
#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
#define CFG_AUTOLOAD "n" /* No autoload */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
diff --git a/include/configs/omap1610h2.h b/include/configs/omap1610h2.h
index c6ca689..74bba05 100644
--- a/include/configs/omap1610h2.h
+++ b/include/configs/omap1610h2.h
@@ -81,11 +81,24 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+
#include <configs/omap1510.h>
#define CONFIG_BOOTDELAY 3
@@ -93,7 +106,7 @@
#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
#define CFG_AUTOLOAD "n" /* No autoload */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
#endif
diff --git a/include/configs/omap1610inn.h b/include/configs/omap1610inn.h
index f28ede0..734f354 100644
--- a/include/configs/omap1610inn.h
+++ b/include/configs/omap1610inn.h
@@ -82,11 +82,24 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+
#include <configs/omap1510.h>
#define CONFIG_BOOTDELAY 3
@@ -98,7 +111,7 @@
#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */
#define CONFIG_BOOTFILE "uImage" /* file to load */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
#endif
diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h
index 5837461..8ae8efe 100644
--- a/include/configs/omap2420h4.h
+++ b/include/configs/omap2420h4.h
@@ -119,15 +119,34 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#ifdef CFG_NAND_BOOT
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_NAND | CFG_CMD_JFFS2)
+ #define CONFIG_CMD_DHCP
+ #define CONFIG_CMD_I2C
+ #define CONFIG_CMD_NAND
+ #define CONFIG_CMD_JFFS2
#else
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT)
+ #define CONFIG_CMD_DHCP
+ #define CONFIG_CMD_I2C
+ #define CONFIG_CMD_JFFS2
+
+ #undef CONFIG_CMD_AUTOSCRIPT
#endif
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
/*
* Board NAND Info.
diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h
index 5db4f52..16ce2f6 100644
--- a/include/configs/omap5912osk.h
+++ b/include/configs/omap5912osk.h
@@ -86,11 +86,24 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+
#include <configs/omap1510.h>
#define CONFIG_BOOTDELAY 3
@@ -102,7 +115,7 @@
#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */
#define CONFIG_BOOTFILE "uImage" /* file to load */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
#endif
diff --git a/include/configs/omap730p2.h b/include/configs/omap730p2.h
index fda55cf..c4d253a 100644
--- a/include/configs/omap730p2.h
+++ b/include/configs/omap730p2.h
@@ -90,14 +90,24 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
/*
- * This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+ * Command line configuration.
*/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
-#include <cmd_confdefs.h>
#include <configs/omap730.h>
#include <configs/h2_p2_dbg_board.h>
@@ -112,7 +122,7 @@
#define CONFIG_SERVERIP 192.150.0.100
#define CONFIG_BOOTFILE "uImage" /* File to load */
-#if defined (CONFIG_COMMANDS) && defined (CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */
#endif
diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h
index 54462f0..bec442d 100644
--- a/include/configs/p3mx.h
+++ b/include/configs/p3mx.h
@@ -60,7 +60,6 @@
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
-#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
@@ -251,26 +250,36 @@
#endif
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_PCI | \
- CFG_CMD_CACHE | \
- CFG_CMD_SDRAM)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_SDRAM
+
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
@@ -280,7 +289,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -421,7 +430,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h
index aa0901f..51f19a1 100644
--- a/include/configs/p3p440.h
+++ b/include/configs/p3p440.h
@@ -35,6 +35,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_P3P440 1 /* Board is P3P440 */
#define CONFIG_440GP 1 /* Specifc GP support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
@@ -167,25 +168,37 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_EEPROM | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_SNTP
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -194,7 +207,7 @@
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -226,7 +239,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/
@@ -285,7 +297,7 @@
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@@ -304,7 +316,7 @@
*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -316,7 +328,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index ed1893f..810e0f0 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -132,11 +132,8 @@
/*---USB -------------------------------------------*/
#if 0
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
-#else
-#define ADD_USB_CMD 0
#endif
/*---ATA PCMCIA ------------------------------------*/
@@ -179,11 +176,36 @@
#define CFG_ICACHE_SIZE 16384
#define CFG_CACHELINE_SIZE 32
-#define CONFIG_COMMANDS \
- (((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_PING) & \
- ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | CFG_CMD_IDE | \
- CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | CFG_CMD_ELF | \
- CFG_CMD_BDI | CFG_CMD_BEDBUG)) | ADD_USB_CMD)
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_FAT
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_RUN
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_BEDBUG
#endif /* __CONFIG_H */
diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h
index 23bdfc8..7653ba1 100644
--- a/include/configs/pcs440ep.h
+++ b/include/configs/pcs440ep.h
@@ -32,6 +32,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_PCS440EP 1 /* Board is PCS440EP */
#define CONFIG_440EP 1 /* Specific PPC440EP support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
@@ -103,21 +104,28 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+#define CONFIG_ENV_OVERWRITE 1
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */
+#define ENV_NAME_REVLEV "revision_level"
+#define ENV_NAME_SOLDER "solder_switch"
+#define ENV_NAME_DIP "dip"
+
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
#undef CONFIG_DDR_ECC /* don't use ECC */
#define SPD_EEPROM_ADDRESS {0x50}
+#define CONFIG_PROG_SDRAM_TLB 1
/*-----------------------------------------------------------------------
* I2C
@@ -142,6 +150,8 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=pcs440ep\0" \
+ "use_eeprom_ethaddr=default\0" \
+ "cs_test=off\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
@@ -172,6 +182,36 @@
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+/* check U-Boot image with SHA1 sum */
+#define CONFIG_SHA1_CHECK_UB_IMG 1
+#define CONFIG_SHA1_START CFG_MONITOR_BASE
+#define CONFIG_SHA1_LEN CFG_MONITOR_LEN
+
+/*-----------------------------------------------------------------------
+ * Definitions for status LED
+ */
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED 1
+
+#define STATUS_LED_BIT 0x08 /* DIAG1 is on GPIO_PPC_1 */
+#define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
+#define STATUS_LED_STATE STATUS_LED_OFF
+#define STATUS_LED_BIT1 0x04 /* DIAG2 is on GPIO_PPC_2 */
+#define STATUS_LED_PERIOD1 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
+#define STATUS_LED_STATE1 STATUS_LED_ON
+#define STATUS_LED_BIT2 0x02 /* DIAG3 is on GPIO_PPC_3 */
+#define STATUS_LED_PERIOD2 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
+#define STATUS_LED_STATE2 STATUS_LED_OFF
+#define STATUS_LED_BIT3 0x01 /* DIAG4 is on GPIO_PPC_4 */
+#define STATUS_LED_PERIOD3 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
+#define STATUS_LED_STATE3 STATUS_LED_OFF
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
@@ -207,37 +247,48 @@
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_EXT2 | \
- CFG_CMD_FAT | \
- CFG_CMD_USB )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_SUPPORT_VFAT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_REISER
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_USB
+
+#define CONFIG_SUPPORT_VFAT
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -266,7 +317,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
@@ -315,76 +365,76 @@
/*-----------------------------------------------------------------------
* PPC440 GPIO Configuration
*/
-#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 Alternate2 Alternate3 */ \
+#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
{ \
/* GPIO Core 0 */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO6 EBC_CS_N(1) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO7 EBC_CS_N(2) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO8 EBC_CS_N(3) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO9 EBC_CS_N(4) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO10 EBC_CS_N(5) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO11 EBC_BUS_ERR */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO12 ZII_p0Rxd(0) */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO13 ZII_p0Rxd(1) */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO14 ZII_p0Rxd(2) */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO15 ZII_p0Rxd(3) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO16 ZII_p0Txd(0) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO17 ZII_p0Txd(1) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO18 ZII_p0Txd(2) */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO19 ZII_p0Txd(3) */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO20 ZII_p0Rx_er */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO21 ZII_p0Rx_dv */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO22 ZII_p0RxCrs */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO23 ZII_p0Tx_er */ \
-{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO24 ZII_p0Tx_en */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO25 ZII_p0Col */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO26 USB2D_RXVALID */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO28 USB2D_TXVALID */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
-{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
-{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6 EBC_CS_N(1) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7 EBC_CS_N(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8 EBC_CS_N(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9 EBC_CS_N(4) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO10 EBC_CS_N(5) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO11 EBC_BUS_ERR */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12 ZII_p0Rxd(0) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13 ZII_p0Rxd(1) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14 ZII_p0Rxd(2) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15 ZII_p0Rxd(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16 ZII_p0Txd(0) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17 ZII_p0Txd(1) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18 ZII_p0Txd(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19 ZII_p0Txd(3) */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20 ZII_p0Rx_er */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21 ZII_p0Rx_dv */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22 ZII_p0RxCrs */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23 ZII_p0Tx_er */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24 ZII_p0Tx_en */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25 ZII_p0Col */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO26 USB2D_RXVALID */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO28 USB2D_TXVALID */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
}, \
{ \
/* GPIO Core 1 */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO32 USB2D_OPMODE0 */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO33 USB2D_OPMODE1 */ \
-{ GPIO1_BASE, GPIO_OUT, GPIO_ALT3 }, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT3 }, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \
-{ GPIO1_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO37 UART0_RTS_N */ \
-{ GPIO1_BASE, GPIO_OUT, GPIO_ALT2 }, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT2 }, /* GPIO39 UART0_RI_N UART1_SIN */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO40 UIC_IRQ(0) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO41 UIC_IRQ(1) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO42 UIC_IRQ(2) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO43 UIC_IRQ(3) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
-{ GPIO1_BASE, GPIO_BI, GPIO_SEL }, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO49 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO50 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO51 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO52 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO53 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO54 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO55 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO56 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO57 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO58 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO59 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO60 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO61 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO62 Unselect via TraceSelect Bit */ \
-{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO63 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO32 USB2D_OPMODE0 */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO33 USB2D_OPMODE1 */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37 UART0_RTS_N */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39 UART0_RI_N UART1_SIN */ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40 UIC_IRQ(0) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41 UIC_IRQ(1) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42 UIC_IRQ(2) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43 UIC_IRQ(3) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
+{GPIO1_BASE, GPIO_BI, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO49 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO50 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO51 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO52 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO53 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO54 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO55 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO56 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO57 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO58 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO59 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO60 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO61 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO62 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO63 Unselect via TraceSelect Bit */ \
} \
}
@@ -393,7 +443,7 @@
*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -405,9 +455,38 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
+
+#define CONFIG_IDE_PREINIT 1
+#define CONFIG_IDE_RESET 1
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR CFG_CF1
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET 0
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET (0x0000)
+
#endif /* __CONFIG_H */
diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h
index 73aa3a8..e3c8843 100644
--- a/include/configs/pcu_e.h
+++ b/include/configs/pcu_e.h
@@ -89,28 +89,34 @@
* ---------------------------------------------------------------- */
#define CFG_SPI_INIT_OFFSET 0xB00
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#define CONFIG_BOOTP_MASK \
- ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-/*----------------------------------------------------------------------*/
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
index 06c6652..5b5b0ef 100644
--- a/include/configs/pdnb3.h
+++ b/include/configs/pdnb3.h
@@ -71,25 +71,33 @@
#define CONFIG_BAUDRATE 115200
#define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
-#if defined(CONFIG_SCPU)
-#define CMD_NAND_ADD 0
-#else
-#define CMD_NAND_ADD CFG_CMD_NAND
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_PING
+
+#if !defined(CONFIG_SCPU)
+#define CONFIG_CMD_NAND
#endif
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE | \
- CFG_CMD_NET | \
- CFG_CMD_MII | \
- CMD_NAND_ADD | \
- CFG_CMD_I2C | \
- CFG_CMD_ELF | \
- CFG_CMD_PING)
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-/* These are u-boot generic parameters */
-#include <cmd_confdefs.h>
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h
index fefdb3c..18d0c87 100644
--- a/include/configs/pf5200.h
+++ b/include/configs/pf5200.h
@@ -49,11 +49,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -90,13 +85,6 @@
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
#endif
-
-#define ADD_PCI_CMD CFG_CMD_PCI
-
-#else /* MPC5100 */
-
-#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
-
#endif
/* Partitions */
@@ -106,26 +94,35 @@
/* USB */
#if 0
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD 0
#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_EEPROM | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_BSP | \
- CFG_CMD_ELF | \
- ADD_PCI_CMD )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+
+#ifdef CONFIG_MPC5200
+#define CONFIG_CMD_PCI
+#endif
+
#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CFG_LOWBOOT 1
@@ -171,7 +168,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*
* I2C configuration
@@ -263,7 +260,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -281,6 +278,11 @@
#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h
index a6c2371..863029d 100644
--- a/include/configs/pleb2.h
+++ b/include/configs/pleb2.h
@@ -66,10 +66,23 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_NET
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
@@ -83,7 +96,7 @@
#define CONFIG_INITRD_TAG
#define CONFIG_SETUP_MEMORY_TAGS
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h
index 072b9dd..fe7de7b 100644
--- a/include/configs/ppmc7xx.h
+++ b/include/configs/ppmc7xx.h
@@ -25,75 +25,91 @@
/*
* Debug
*
- * DEBUG - Define this is you want extra debug info
- * GTREGREAD - Required to build with debug
- * do_bdinfo - Required to build with debug
+ * DEBUG - Define this is you want extra debug info
+ * GTREGREAD - Required to build with debug
+ * do_bdinfo - Required to build with debug
*/
#undef DEBUG
-#define GTREGREAD(x) 0xFFFFFFFF
+#ifdef DEBUG
+#define GTREGREAD(x) 0xFFFFFFFF
#define do_bdinfo(a,b,c,d)
-
+#endif
/*
* CPU type
*
- * CONFIG_7xx - We have a 750 or 755 CPU
- * CONFIG_74xx - We have a 7400 CPU
- * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400)
- * CONFIG_BUS_CLK - System bus clock in Hz
+ * CONFIG_7xx - We have a 750 or 755 CPU
+ * CONFIG_74xx - We have a 7400 CPU
+ * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400)
+ * CONFIG_BUS_CLK - System bus clock in Hz
*/
#define CONFIG_7xx
#undef CONFIG_74xx
#undef CONFIG_ALTIVEC
-#define CONFIG_BUS_CLK 66000000
+#define CONFIG_BUS_CLK 66000000
/*
* Monitor configuration
*
- * CONFIG_COMMANDS - List of command sets to include in shell
+ * List of command sets to include in shell
*
* The following command sets have been tested and known to work:
*
- * CFG_CMD_CACHE - Cache control commands
- * CFG_CMD_MEMORY - Memory display, change and test commands
- * CFG_CMD_FLASH - Erase and program flash
- * CFG_CMD_ENV - Environment commands
- * CFG_CMD_RUN - Run commands stored in env vars
- * CFG_CMD_ELF - Load ELF files
- * CFG_CMD_NET - Networking/file download commands
- * CFG_CMD_PING - ICMP Echo Request command
- * CFG_CMD_PCI - PCI Bus scanning command
+ * CMD_CACHE - Cache control commands
+ * CMD_MEMORY - Memory display, change and test commands
+ * CMD_FLASH - Erase and program flash
+ * CMD_ENV - Environment commands
+ * CMD_RUN - Run commands stored in env vars
+ * CMD_ELF - Load ELF files
+ * CMD_NET - Networking/file download commands
+ * CMD_PIN - ICMP Echo Request command
+ * CMD_PCI - PCI Bus scanning command
*/
-#define CONFIG_COMMANDS ( (CFG_CMD_DFL & ~(CFG_CMD_KGDB)) | \
- CFG_CMD_FLASH | \
- CFG_CMD_ENV | \
- CFG_CMD_RUN | \
- CFG_CMD_ELF | \
- CFG_CMD_NET | \
- CFG_CMD_PING | \
- CFG_CMD_PCI)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PCI
+
+#undef CONFIG_CMD_KGDB
/*
* Serial configuration
*
* CONFIG_CONS_INDEX - Serial console port number (COM1)
- * CONFIG_BAUDRATE - Serial speed
+ * CONFIG_BAUDRATE - Serial speed
*/
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 9600
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 9600
/*
* PCI config
*
- * CONFIG_PCI - Enable PCI bus
- * CONFIG_PCI_PNP - Enable Plug & Play support
+ * CONFIG_PCI - Enable PCI bus
+ * CONFIG_PCI_PNP - Enable Plug & Play support
* CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup
*/
@@ -105,9 +121,9 @@
/*
* Network config
*
- * CONFIG_NET_MULTI - Support for multiple network interfaces
- * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller
- * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
+ * CONFIG_NET_MULTI - Support for multiple network interfaces
+ * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller
+ * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
*/
#define CONFIG_NET_MULTI
@@ -130,7 +146,7 @@
* Boot config
*
* CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot
- * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec)
+ * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec)
*/
#define CONFIG_BOOTCOMMAND \
@@ -149,87 +165,84 @@
*/
-#include <cmd_confdefs.h>
-
-
/*
* Memory map
*
* This board runs in a standard CHRP (Map-B) configuration.
*
- * Type Start End Size Width Chip Sel
+ * Type Start End Size Width Chip Sel
* ----------- ----------- ----------- ------- ------- --------
- * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0
- * User LED's 0x78000000 RCS3
- * UART 0x7C000000 RCS2
- * Mailbox 0xFF000000 RCS1
- * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0
+ * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0
+ * User LED's 0x78000000 RCS3
+ * UART 0x7C000000 RCS2
+ * Mailbox 0xFF000000 RCS1
+ * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0
*
* Flash sectors are laid out as follows.
*
- * Sector Start End Size Comments
+ * Sector Start End Size Comments
* ------- ----------- ----------- ------- -----------
- * 0 0xFFC00000 0xFFC3FFFF 256KB
- * 1 0xFFC40000 0xFFC7FFFF 256KB
- * 2 0xFFC80000 0xFFCBFFFF 256KB
- * 3 0xFFCC0000 0xFFCFFFFF 256KB
- * 4 0xFFD00000 0xFFD3FFFF 256KB
- * 5 0xFFD40000 0xFFD7FFFF 256KB
- * 6 0xFFD80000 0xFFDBFFFF 256KB
- * 7 0xFFDC0000 0xFFDFFFFF 256KB
- * 8 0xFFE00000 0xFFE3FFFF 256KB
- * 9 0xFFE40000 0xFFE7FFFF 256KB
- * 10 0xFFE80000 0xFFEBFFFF 256KB
- * 11 0xFFEC0000 0xFFEFFFFF 256KB
- * 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here
- * 13 0xFFF40000 0xFFF7FFFF 256KB
- * 14 0xFFF80000 0xFFFBFFFF 256KB
- * 15 0xFFFC0000 0xFFFDFFFF 128KB
- * 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here
- * 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here
- * 18 0xFFFF0000 0xFFFFFFFF 64KB
+ * 0 0xFFC00000 0xFFC3FFFF 256KB
+ * 1 0xFFC40000 0xFFC7FFFF 256KB
+ * 2 0xFFC80000 0xFFCBFFFF 256KB
+ * 3 0xFFCC0000 0xFFCFFFFF 256KB
+ * 4 0xFFD00000 0xFFD3FFFF 256KB
+ * 5 0xFFD40000 0xFFD7FFFF 256KB
+ * 6 0xFFD80000 0xFFDBFFFF 256KB
+ * 7 0xFFDC0000 0xFFDFFFFF 256KB
+ * 8 0xFFE00000 0xFFE3FFFF 256KB
+ * 9 0xFFE40000 0xFFE7FFFF 256KB
+ * 10 0xFFE80000 0xFFEBFFFF 256KB
+ * 11 0xFFEC0000 0xFFEFFFFF 256KB
+ * 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here
+ * 13 0xFFF40000 0xFFF7FFFF 256KB
+ * 14 0xFFF80000 0xFFFBFFFF 256KB
+ * 15 0xFFFC0000 0xFFFDFFFF 128KB
+ * 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here
+ * 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here
+ * 18 0xFFFF0000 0xFFFFFFFF 64KB
*/
/*
* SDRAM config - see memory map details above.
*
- * CFG_SDRAM_BASE - Start address of SDRAM, this _must_ be zero!
- * CFG_SDRAM_SIZE - Total size of contiguous SDRAM bank(s)
+ * CFG_SDRAM_BASE - Start address of SDRAM, this _must_ be zero!
+ * CFG_SDRAM_SIZE - Total size of contiguous SDRAM bank(s)
*/
-#define CFG_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_SIZE 0x04000000
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_SIZE 0x04000000
/*
* Flash config - see memory map details above.
*
- * CFG_FLASH_BASE - Start address of flash memory
- * CFG_FLASH_SIZE - Total size of contiguous flash mem
+ * CFG_FLASH_BASE - Start address of flash memory
+ * CFG_FLASH_SIZE - Total size of contiguous flash mem
* CFG_FLASH_ERASE_TOUT - Erase timeout in ms
* CFG_FLASH_WRITE_TOUT - Write timeout in ms
* CFG_MAX_FLASH_BANKS - Number of banks of flash on board
* CFG_MAX_FLASH_SECT - Number of sectors in a bank
*/
-#define CFG_FLASH_BASE 0xFFC00000
-#define CFG_FLASH_SIZE 0x00400000
+#define CFG_FLASH_BASE 0xFFC00000
+#define CFG_FLASH_SIZE 0x00400000
#define CFG_FLASH_ERASE_TOUT 250000
#define CFG_FLASH_WRITE_TOUT 5000
-#define CFG_MAX_FLASH_BANKS 1
-#define CFG_MAX_FLASH_SECT 19
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 19
/*
* Monitor config - see memory map details above
*
- * CFG_MONITOR_BASE - Base address of monitor code
- * CFG_MALLOC_LEN - Size of malloc pool (128KB)
+ * CFG_MONITOR_BASE - Base address of monitor code
+ * CFG_MALLOC_LEN - Size of malloc pool (128KB)
*/
-#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_MALLOC_LEN 0x20000
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MALLOC_LEN 0x20000
/*
@@ -247,16 +260,16 @@
* CFG_PROMPT - Prompt string
*/
-#define CFG_BARGSIZE 1024
-#define CFG_BOOTMAPSZ 0x800000
-#define CFG_CBSIZE 1024
-#define CFG_LOAD_ADDR 0x100000
+#define CFG_BARGSIZE 1024
+#define CFG_BOOTMAPSZ 0x800000
+#define CFG_CBSIZE 1024
+#define CFG_LOAD_ADDR 0x100000
#define CFG_LONGHELP
-#define CFG_MAXARGS 16
-#define CFG_MEMTEST_START 0x00040000
-#define CFG_MEMTEST_END 0x00040100
-#define CFG_PBSIZE 1024
-#define CFG_PROMPT "=> "
+#define CFG_MAXARGS 16
+#define CFG_MEMTEST_START 0x00040000
+#define CFG_MEMTEST_END 0x00040100
+#define CFG_PBSIZE 1024
+#define CFG_PROMPT "=> "
/*
@@ -268,12 +281,12 @@
* CFG_ENV_SECT_SIZE - Size of sector containing env vars (32KB)
*/
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR 0xFFFE0000
-#define CFG_ENV_SIZE 0x1000
-#define CFG_ENV_ADDR_REDUND 0xFFFE8000
-#define CFG_ENV_SIZE_REDUND 0x1000
-#define CFG_ENV_SECT_SIZE 0x8000
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR 0xFFFE0000
+#define CFG_ENV_SIZE 0x1000
+#define CFG_ENV_ADDR_REDUND 0xFFFE8000
+#define CFG_ENV_SIZE_REDUND 0x1000
+#define CFG_ENV_SECT_SIZE 0x8000
/*
@@ -284,15 +297,15 @@
* copied to top of RAM by the init code.
*
* CFG_INIT_RAM_ADDR - Address of Init RAM, above exception vect
- * CFG_INIT_RAM_END - Size of Init RAM
+ * CFG_INIT_RAM_END - Size of Init RAM
* CFG_GBL_DATA_SIZE - Ammount of RAM to reserve for global data
* CFG_GBL_DATA_OFFSET - Start of global data, top of stack
*/
-#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + 0x4000)
-#define CFG_INIT_RAM_END 0x4000
-#define CFG_GBL_DATA_SIZE 128
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + 0x4000)
+#define CFG_INIT_RAM_END 0x4000
+#define CFG_GBL_DATA_SIZE 128
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
/*
@@ -329,71 +342,71 @@
* Cache config
*
* CFG_CACHELINE_SIZE - Size of a cache line (CPU specific)
- * CFG_L2 - L2 cache enabled if defined
- * L2_INIT - L2 cache init flags
- * L2_ENABLE - L2 cache enable flags
+ * CFG_L2 - L2 cache enabled if defined
+ * L2_INIT - L2 cache init flags
+ * L2_ENABLE - L2 cache enable flags
*/
-#define CFG_CACHELINE_SIZE 32
+#define CFG_CACHELINE_SIZE 32
#undef CFG_L2
-#define L2_INIT 0
-#define L2_ENABLE 0
+#define L2_INIT 0
+#define L2_ENABLE 0
/*
* Clocks config
*
- * CFG_BUS_HZ - Bus clock frequency in Hz
- * CFG_BUS_CLK - As above (?)
- * CFG_HZ - Decrementer freq in Hz
+ * CFG_BUS_HZ - Bus clock frequency in Hz
+ * CFG_BUS_CLK - As above (?)
+ * CFG_HZ - Decrementer freq in Hz
*/
-#define CFG_BUS_HZ CONFIG_BUS_CLK
-#define CFG_BUS_CLK CONFIG_BUS_CLK
-#define CFG_HZ 1000
+#define CFG_BUS_HZ CONFIG_BUS_CLK
+#define CFG_BUS_CLK CONFIG_BUS_CLK
+#define CFG_HZ 1000
/*
* Serial port config
*
* CFG_BAUDRATE_TABLE - List of valid baud rates
- * CFG_NS16550 - Include the NS16550 driver
+ * CFG_NS16550 - Include the NS16550 driver
* CFG_NS16550_SERIAL - Include the serial (wrapper) driver
- * CFG_NS16550_CLK - Frequency of reference clock
+ * CFG_NS16550_CLK - Frequency of reference clock
* CFG_NS16550_REG_SIZE - 64-bit accesses to 8-bit port
- * CFG_NS16550_COM1 - Base address of 1st serial port
+ * CFG_NS16550_COM1 - Base address of 1st serial port
*/
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_NS16550
#define CFG_NS16550_SERIAL
-#define CFG_NS16550_CLK 3686400
+#define CFG_NS16550_CLK 3686400
#define CFG_NS16550_REG_SIZE -8
-#define CFG_NS16550_COM1 0x7C000000
+#define CFG_NS16550_COM1 0x7C000000
/*
* PCI Config - Address Map B (CHRP)
*/
-#define CFG_PCI_MEMORY_BUS 0x00000000
-#define CFG_PCI_MEMORY_PHYS 0x00000000
-#define CFG_PCI_MEMORY_SIZE 0x40000000
-#define CFG_PCI_MEM_BUS 0x80000000
-#define CFG_PCI_MEM_PHYS 0x80000000
-#define CFG_PCI_MEM_SIZE 0x7D000000
-#define CFG_ISA_MEM_BUS 0x00000000
-#define CFG_ISA_MEM_PHYS 0xFD000000
-#define CFG_ISA_MEM_SIZE 0x01000000
-#define CFG_PCI_IO_BUS 0x00800000
-#define CFG_PCI_IO_PHYS 0xFE800000
-#define CFG_PCI_IO_SIZE 0x00400000
-#define CFG_ISA_IO_BUS 0x00000000
-#define CFG_ISA_IO_PHYS 0xFE000000
-#define CFG_ISA_IO_SIZE 0x00800000
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x40000000
+#define CFG_PCI_MEM_BUS 0x80000000
+#define CFG_PCI_MEM_PHYS 0x80000000
+#define CFG_PCI_MEM_SIZE 0x7D000000
+#define CFG_ISA_MEM_BUS 0x00000000
+#define CFG_ISA_MEM_PHYS 0xFD000000
+#define CFG_ISA_MEM_SIZE 0x01000000
+#define CFG_PCI_IO_BUS 0x00800000
+#define CFG_PCI_IO_PHYS 0xFE800000
+#define CFG_PCI_IO_SIZE 0x00400000
+#define CFG_ISA_IO_BUS 0x00000000
+#define CFG_ISA_IO_PHYS 0xFE000000
+#define CFG_ISA_IO_SIZE 0x00800000
#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
-#define CFG_ISA_IO CFG_ISA_IO_PHYS
-#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS
+#define CFG_ISA_IO CFG_ISA_IO_PHYS
+#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS
/*
@@ -408,12 +421,12 @@
/*
* Boot flags
*
- * BOOTFLAG_COLD - Indicates a power-on boot
- * BOOTFLAG_WARM - Indicates a software reset
+ * BOOTFLAG_COLD - Indicates a power-on boot
+ * BOOTFLAG_WARM - Indicates a software reset
*/
-#define BOOTFLAG_COLD 0x01
-#define BOOTFLAG_WARM 0x02
+#define BOOTFLAG_COLD 0x01
+#define BOOTFLAG_WARM 0x02
#endif /* __CONFIG_H */
diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h
index d671dcc..fb5ae99 100644
--- a/include/configs/ppmc8260.h
+++ b/include/configs/ppmc8260.h
@@ -169,8 +169,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
@@ -261,13 +260,17 @@
"bootm"
#endif /* CONFIG_BOOT_ROOT_NFS */
-/* Add support for a few extra bootp options like:
- * - File size
- * - DNS
+
+/*
+ * BOOTP options
*/
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE | \
- CONFIG_BOOTP_DNS)
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+
/* undef this to save memory */
#define CFG_LONGHELP
@@ -275,14 +278,20 @@
/* Monitor Command Prompt */
#define CFG_PROMPT "=> "
-/* What U-Boot subsytems do you want enabled? */
-#define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
- CFG_CMD_ELF | \
- CFG_CMD_ASKENV | \
- CFG_CMD_REGINFO | \
- CFG_CMD_MEMTEST | \
- CFG_CMD_MII | \
- CFG_CMD_IMMAP)
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_IMMAP
+
+#undef CONFIG_CMD_KGDB
/* Where do the internal registers live? */
@@ -298,13 +307,10 @@
#define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -477,7 +483,7 @@
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/purple.h b/include/configs/purple.h
index 2ecb7fb..6eb618e 100644
--- a/include/configs/purple.h
+++ b/include/configs/purple.h
@@ -81,8 +81,23 @@
""
#define CONFIG_BOOTCOMMAND "run flash_self"
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF)
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+
#define CFG_SDRAM_BASE 0x80000000
diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
index e5e2772..0e884fc 100644
--- a/include/configs/pxa255_idp.h
+++ b/include/configs/pxa255_idp.h
@@ -102,10 +102,25 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_DHCP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_DHCP
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTCOMMAND "bootm 40000"
@@ -192,7 +207,7 @@
/* "protect off" */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/quantum.h b/include/configs/quantum.h
index 21ec5ac..f49e2b0 100644
--- a/include/configs/quantum.h
+++ b/include/configs/quantum.h
@@ -92,18 +92,28 @@
#define CFG_NVRAM_SIZE 2048
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SNTP )
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
@@ -113,7 +123,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -172,7 +182,7 @@
#endif
/*%%% #define CFG_FLASH_BASE 0xFFF00000 */
-#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
@@ -222,7 +232,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/r5200.h b/include/configs/r5200.h
index e1e406b..fc7658b 100644
--- a/include/configs/r5200.h
+++ b/include/configs/r5200.h
@@ -39,13 +39,10 @@
#define CONFIG_M5271 /* define processor type */
#define CONFIG_R5200 /* define board type */
-#define FEC_ENET
-#define CONFIG_NET_RETRY_COUNT 5
-
-#define CONFIG_IPADDR 192.168.0.172
-#define CONFIG_SERVERIP 192.168.0.148
-#define CONFIG_ETHADDR 00:06:3b:00:44:55
+#define CONFIG_MCFTMR
+#define CONFIG_MCFUART
+#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
@@ -66,10 +63,48 @@
#define CFG_ENV_IS_IN_FLASH 1
#endif
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_NET ) & ~(CFG_CMD_LOADS | CFG_CMD_LOADB))
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NET
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CFG_DISCOVER_PHY
+# define CFG_RX_ETH_BUFFER 8
+# define CFG_FAULT_ECHO_LINK_DOWN
+
+# define CFG_FEC0_PINMUX 0
+# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CFG_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CFG_FAULT_ECHO_LINK_DOWN
+# define CFG_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CFG_DISCOVER_PHY */
+#endif
/* Note: We only copy one sectors worth of application code from location
* 10200000 for speed purposes. Increase the size if necessary */
@@ -79,7 +114,7 @@
#define CFG_PROMPT "u-boot> "
#define CFG_LONGHELP /* undef to save memory */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
diff --git a/include/configs/rmu.h b/include/configs/rmu.h
index b319cf4..2ca60b7 100644
--- a/include/configs/rmu.h
+++ b/include/configs/rmu.h
@@ -87,17 +87,28 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
@@ -108,7 +119,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -152,7 +163,7 @@
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE (0-flash_info[0].size) /* Put flash at end */
-#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
@@ -193,7 +204,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h
index 6c9e392..814082c 100644
--- a/include/configs/rsdproto.h
+++ b/include/configs/rsdproto.h
@@ -64,8 +64,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
@@ -102,7 +101,23 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_KGDB)
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_KGDB
+
/* Define this if you want to boot from 0x00000100. If you don't define
* this, you will need to program the bootloader to 0xfff00000, and
@@ -112,15 +127,12 @@
*/
#define CFG_RSD_BOOT_LOW 1
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#define CONFIG_BOOTDELAY 5
#define CONFIG_BOOTARGS "devfs=mount root=ramfs"
#define CONFIG_ETHADDR 08:00:3e:26:0a:5a
#define CONFIG_NETMASK 255.255.0.0
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -130,7 +142,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -287,7 +299,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index 97b52fa..c474acd 100644
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -159,8 +159,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC
@@ -470,16 +469,18 @@
#define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */
-/* Add support for a few extra bootp options like:
- * - File size
- * - DNS (up to 2 servers)
- * - Send hostname to DHCP server
+/*
+ * BOOTP options
*/
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE | \
- CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME)
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
/* undef this to save memory */
#define CFG_LONGHELP
@@ -502,31 +503,28 @@
*/
#define CONFIG_VERSION_VARIABLE
-/* What U-Boot subsytems do you want enabled? */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_KGDB
+
#ifdef CONFIG_ETHER_ON_FCC
-# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
- CFG_CMD_ELF | \
- CFG_CMD_ASKENV | \
- CFG_CMD_I2C | \
- CFG_CMD_SPI | \
- CFG_CMD_SDRAM | \
- CFG_CMD_REGINFO | \
- CFG_CMD_IMMAP | \
- CFG_CMD_IRQ | \
- CFG_CMD_PING | \
- CFG_CMD_MII )
-#else
-# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
- CFG_CMD_ELF | \
- CFG_CMD_ASKENV | \
- CFG_CMD_I2C | \
- CFG_CMD_SPI | \
- CFG_CMD_SDRAM | \
- CFG_CMD_REGINFO | \
- CFG_CMD_IMMAP | \
- CFG_CMD_IRQ | \
- CFG_CMD_PING )
-#endif /* CONFIG_ETHER_ON_FCC */
+#define CONFIG_CMD_MII
+#endif
+
/* Where do the internal registers live? */
#define CFG_IMMR 0xF0000000
@@ -544,10 +542,6 @@
#define CONFIG_SACSng 1 /* munged for the SACSng */
#define CONFIG_CPM2 1 /* Has a CPM2 */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-
/*
* Miscellaneous configurable options
*/
@@ -589,7 +583,7 @@
#define CFG_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */
/* before it gives up. */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -732,7 +726,7 @@
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h
index 866f7b0..b4a063a 100644
--- a/include/configs/sbc2410x.h
+++ b/include/configs/sbc2410x.h
@@ -82,24 +82,29 @@
#define CONFIG_BAUDRATE 115200
-/***********************************************************
- * Command definition
- ***********************************************************/
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | \
- CFG_CMD_CACHE | \
- /*CFG_CMD_NAND |*/ \
- /*CFG_CMD_EEPROM |*/ \
- /*CFG_CMD_I2C |*/ \
- /*CFG_CMD_USB |*/ \
- CFG_CMD_REGINFO | \
- CFG_CMD_DATE | \
- CFG_CMD_PING | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
@@ -110,7 +115,7 @@
/*#define CONFIG_BOOTFILE "elinos-lart" */
#define CONFIG_BOOTCOMMAND "dhcp; bootm"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
@@ -193,7 +198,7 @@
/*-----------------------------------------------------------------------
* NAND flash settings
*/
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if defined(CONFIG_CMD_NAND)
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
@@ -219,7 +224,7 @@
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)
/* #undef CONFIG_MTD_NAND_VERIFY_WRITE */
-#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */
+#endif /* CONFIG_CMD_NAND */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h
index beff28a..dc906b1 100644
--- a/include/configs/sbc405.h
+++ b/include/configs/sbc405.h
@@ -84,23 +84,33 @@
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BSP | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_SDRAM | \
- 0 )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -123,7 +133,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -229,7 +239,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/sbc8240.h b/include/configs/sbc8240.h
index d891e07..0e878f0 100644
--- a/include/configs/sbc8240.h
+++ b/include/configs/sbc8240.h
@@ -75,24 +75,33 @@
#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BSP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_ENV | \
- CFG_CMD_FLASH | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_SDRAM | \
- 0 )
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+
+/*
+ * Command line configuration.
*/
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
+
/*
* Miscellaneous configurable options
@@ -340,7 +349,7 @@ typedef unsigned int led_id_t;
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h
index 9cf0654..b1d41a6 100644
--- a/include/configs/sbc8260.h
+++ b/include/configs/sbc8260.h
@@ -182,8 +182,7 @@
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC
@@ -412,16 +411,18 @@
"bootm"
#endif /* CONFIG_BOOT_ROOT_NFS */
-/* Add support for a few extra bootp options like:
- * - File size
- * - DNS (up to 2 servers)
- * - Send hostname to DHCP server
+/*
+ * BOOTP options
*/
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE | \
- CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME)
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
/* undef this to save memory */
#define CFG_LONGHELP
@@ -444,27 +445,26 @@
*/
#define CONFIG_VERSION_VARIABLE
-/* What U-Boot subsytems do you want enabled? */
-#ifdef CONFIG_ETHER_ON_FCC
-# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
- CFG_CMD_ASKENV | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IMMAP | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM )
-#else
-# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
- CFG_CMD_ASKENV | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IMMAP | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM )
-#endif /* CONFIG_ETHER_ON_FCC */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+#undef CONFIG_CMD_KGDB
+
+#if defined(CONFIG_ETHER_ON_FCC)
+ #define CONFIG_CMD_CMD_MII
+#endif
+
#undef CONFIG_WATCHDOG /* disable the watchdog */
@@ -481,13 +481,11 @@
#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */
#define CONFIG_CPM2 1 /* Has a CPM2 */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -627,7 +625,7 @@
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 65aac5c..e7d8a5a 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -313,9 +313,6 @@
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,8349@0"
#define OF_SOC "soc8349@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
@@ -328,7 +325,7 @@
#define CONFIG_I2C_CMD_TREE
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CFG_I2C1_OFFSET 0x3000
#define CFG_I2C2_OFFSET 0x3100
#define CFG_I2C_OFFSET CFG_I2C2_OFFSET
@@ -401,15 +398,17 @@
#define CONFIG_NET_MULTI 1
#endif
-#define CONFIG_MPC83XX_TSEC1 1
-#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC83XX_TSEC2 1
-#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_PHY_BCM5421S 1
#define TSEC1_PHY_ADDR 0x19
#define TSEC2_PHY_ADDR 0x1a
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
@@ -439,40 +438,34 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#if defined(CFG_RAMBOOT)
-#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_PCI \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
-#else
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C) \
- & \
- ~(CFG_CMD_ENV \
- | CFG_CMD_LOADS))
-#endif
-#else
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
#if defined(CONFIG_PCI)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PCI \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- )
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_I2C \
- | CFG_CMD_MII \
- )
+ #define CONFG_CMD_PCI
#endif
+
+#if defined(CFG_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -483,7 +476,7 @@
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -504,7 +497,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
@@ -655,7 +648,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
@@ -666,6 +659,7 @@
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:a0:1e:a0:13:8d
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index 6e4fdb2..defc428 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -320,28 +320,37 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+ #define CONFIG_CMD_MII
+#endif
+
#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV | \
- CFG_CMD_LOADS ))
- #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV))
- #endif
-#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_PING | CFG_CMD_I2C)
- #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_PING | CFG_CMD_I2C)
- #endif
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -350,7 +359,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -371,7 +380,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -383,7 +392,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
new file mode 100644
index 0000000..54eac38
--- /dev/null
+++ b/include/configs/sbc8641d.h
@@ -0,0 +1,606 @@
+/*
+ * Copyright 2007 Wind River Systems <www.windriver.com>
+ * Copyright 2007 Embedded Specialties, Inc.
+ * Joe Hamman <joe.hamman@embeddedspecialties.com>
+ *
+ * Copyright 2006 Freescale Semiconductor.
+ *
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * SBC8641D board configuration file
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_MPC86xx 1 /* MPC86xx */
+#define CONFIG_MPC8641 1 /* MPC8641 specific */
+#define CONFIG_SBC8641D 1 /* SBC8641D board specific */
+#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
+#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
+
+#ifdef RUN_DIAG
+#define CFG_DIAG_ADDR 0xff800000
+#endif
+
+#define CFG_RESET_ADDRESS 0xfff00100
+
+#define CONFIG_PCI 1 /* Enable PCIE */
+#define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
+#undef CONFIG_DDR_DLL /* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CACHE_LINE_INTERLEAVING 0x20000000
+#define PAGE_INTERLEAVING 0x21000000
+#define BANK_INTERLEAVING 0x22000000
+#define SUPER_BANK_INTERLEAVING 0x23000000
+
+
+#define CONFIG_ALTIVEC 1
+
+/*
+ * L2CR setup -- make sure this is right for your board!
+ */
+#define CFG_L2
+#define L2_INIT 0
+#define L2_ENABLE (L2CR_L2E)
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00200000 /* memtest region */
+#define CFG_MEMTEST_END 0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+
+#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
+#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
+#define CFG_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+#define CFG_SDRAM_BASE2 CFG_DDR_SDRAM_BASE2
+#define CONFIG_VERY_BIG_RAM
+
+#define MPC86xx_DDR_SDRAM_CLK_CNTL
+
+#if defined(CONFIG_SPD_EEPROM)
+ /*
+ * Determine DDR configuration from I2C interface.
+ */
+ #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */
+
+#else
+ /*
+ * Manually set up DDR1 & DDR2 parameters
+ */
+
+ #define CFG_SDRAM_SIZE 512 /* DDR is 512MB */
+
+ #define CFG_DDR_CS0_BNDS 0x0000000F
+ #define CFG_DDR_CS1_BNDS 0x00000000
+ #define CFG_DDR_CS2_BNDS 0x00000000
+ #define CFG_DDR_CS3_BNDS 0x00000000
+ #define CFG_DDR_CS0_CONFIG 0x80010102
+ #define CFG_DDR_CS1_CONFIG 0x00000000
+ #define CFG_DDR_CS2_CONFIG 0x00000000
+ #define CFG_DDR_CS3_CONFIG 0x00000000
+ #define CFG_DDR_EXT_REFRESH 0x00000000
+ #define CFG_DDR_TIMING_0 0x00220802
+ #define CFG_DDR_TIMING_1 0x38377322
+ #define CFG_DDR_TIMING_2 0x002040c7
+ #define CFG_DDR_CFG_1A 0x43008008
+ #define CFG_DDR_CFG_2 0x24401000
+ #define CFG_DDR_MODE_1 0x23c00542
+ #define CFG_DDR_MODE_2 0x00000000
+ #define CFG_DDR_MODE_CTL 0x00000000
+ #define CFG_DDR_INTERVAL 0x05080100
+ #define CFG_DDR_DATA_INIT 0x00000000
+ #define CFG_DDR_CLK_CTRL 0x03800000
+ #define CFG_DDR_CFG_1B 0xC3008008
+
+ #define CFG_DDR2_CS0_BNDS 0x0010001F
+ #define CFG_DDR2_CS1_BNDS 0x00000000
+ #define CFG_DDR2_CS2_BNDS 0x00000000
+ #define CFG_DDR2_CS3_BNDS 0x00000000
+ #define CFG_DDR2_CS0_CONFIG 0x80010102
+ #define CFG_DDR2_CS1_CONFIG 0x00000000
+ #define CFG_DDR2_CS2_CONFIG 0x00000000
+ #define CFG_DDR2_CS3_CONFIG 0x00000000
+ #define CFG_DDR2_EXT_REFRESH 0x00000000
+ #define CFG_DDR2_TIMING_0 0x00220802
+ #define CFG_DDR2_TIMING_1 0x38377322
+ #define CFG_DDR2_TIMING_2 0x002040c7
+ #define CFG_DDR2_CFG_1A 0x43008008
+ #define CFG_DDR2_CFG_2 0x24401000
+ #define CFG_DDR2_MODE_1 0x23c00542
+ #define CFG_DDR2_MODE_2 0x00000000
+ #define CFG_DDR2_MODE_CTL 0x00000000
+ #define CFG_DDR2_INTERVAL 0x05080100
+ #define CFG_DDR2_DATA_INIT 0x00000000
+ #define CFG_DDR2_CLK_CTRL 0x03800000
+ #define CFG_DDR2_CFG_1B 0xC3008008
+
+
+#endif
+
+/* #define CFG_ID_EEPROM 1
+#define ID_EEPROM_ADDR 0x57 */
+
+/*
+ * The SBC8641D contains 16MB flash space at ff000000.
+ */
+#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
+
+/* Flash */
+#define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */
+#define CFG_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */
+
+/* 64KB EEPROM */
+#define CFG_BR1_PRELIM 0xf0000801 /* port size 16bit */
+#define CFG_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */
+
+/* EPLD - User switches, board id, LEDs */
+#define CFG_BR2_PRELIM 0xf1000801 /* port size 16bit */
+#define CFG_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */
+
+/* Local bus SDRAM 128MB */
+#define CFG_BR3_PRELIM 0xe0001861 /* port size ?bit */
+#define CFG_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */
+#define CFG_BR4_PRELIM 0xe4001861 /* port size ?bit */
+#define CFG_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */
+
+/* Disk on Chip (DOC) 128MB */
+#define CFG_BR5_PRELIM 0xe8001001 /* port size ?bit */
+#define CFG_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */
+
+/* LCD */
+#define CFG_BR6_PRELIM 0xf4000801 /* port size ?bit */
+#define CFG_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
+
+/* Control logic & misc peripherals */
+#define CFG_BR7_PRELIM 0xf2000801 /* port size ?bit */
+#define CFG_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
+
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 131 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_WRITE_SWAPPED_DATA
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_PROTECTION
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#ifndef CFG_INIT_RAM_LOCK
+#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
+#else
+#define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
+#endif
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree to kernel
+ */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_CPU "PowerPC,8641@0"
+#define OF_SOC "soc@f8000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc@f8000000/serial@4500"
+
+#define CFG_64BIT_VSPRINTF 1
+#define CFG_64BIT_STRTOUL 1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3100
+
+/*
+ * RapidIO MMU
+ */
+#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
+#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
+#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0xe2000000
+#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
+
+#define CFG_PCI2_MEM_BASE 0xa0000000
+#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI2_IO_BASE 0xe3000000
+#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
+#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#undef CFG_SCSI_SCAN_BUS_REVERSE
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xe0000000
+ #define PCI_ENET0_MEMADDR 0xe0000000
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#define CONFIG_DOS_PARTITION
+#undef CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CFG_SCSI_MAX_SCSI_ID 4
+#define CFG_SCSI_MAX_LUN 1
+#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
+#endif
+
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+/* #define CONFIG_MII 1 */ /* MII PHY management */
+
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC3"
+#define CONFIG_TSEC4 1
+#define CONFIG_TSEC4_NAME "eTSEC4"
+
+#define TSEC1_PHY_ADDR 0x1F
+#define TSEC2_PHY_ADDR 0x00
+#define TSEC3_PHY_ADDR 0x01
+#define TSEC4_PHY_ADDR 0x02
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC3_PHYIDX 0
+#define TSEC4_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define TSEC3_FLAGS TSEC_GIGABIT
+#define TSEC4_FLAGS TSEC_GIGABIT
+
+#define CFG_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
+
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * BAT0 2G Cacheable, non-guarded
+ * 0x0000_0000 2G DDR
+ */
+#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
+#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
+#define CFG_IBAT0U CFG_DBAT0U
+
+/*
+ * BAT1 1G Cache-inhibited, guarded
+ * 0x8000_0000 512M PCI-Express 1 Memory
+ * 0xa000_0000 512M PCI-Express 2 Memory
+ * Changed it for operating from 0xd0000000
+ */
+#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT1U CFG_DBAT1U
+
+/*
+ * BAT2 512M Cache-inhibited, guarded
+ * 0xc000_0000 512M RapidIO Memory
+ */
+#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U CFG_DBAT2U
+
+/*
+ * BAT3 4M Cache-inhibited, guarded
+ * 0xf800_0000 4M CCSR
+ */
+#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U CFG_DBAT3U
+
+/*
+ * BAT4 32M Cache-inhibited, guarded
+ * 0xe200_0000 16M PCI-Express 1 I/O
+ * 0xe300_0000 16M PCI-Express 2 I/0
+ * Note that this is at 0xe0000000
+ */
+#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT4U CFG_DBAT4U
+
+/*
+ * BAT5 128K Cacheable, non-guarded
+ * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
+ */
+#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_IBAT5L CFG_DBAT5L
+#define CFG_IBAT5U CFG_DBAT5U
+
+/*
+ * BAT6 32M Cache-inhibited, guarded
+ * 0xfe00_0000 32M FLASH
+ */
+#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U CFG_DBAT6U
+
+#define CFG_DBAT7L 0x00000000
+#define CFG_DBAT7U 0x00000000
+#define CFG_IBAT7L 0x00000000
+#define CFG_IBAT7U 0x00000000
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+#define CFG_ENV_SIZE 0x2000
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#include <config_cmd_default.h>
+ #define CONFIG_CMD_PING
+ #define CONFIG_CMD_I2C
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if defined(CONFIG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR 02:E0:0C:00:00:01
+#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
+#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD
+#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD
+#endif
+
+#define CONFIG_HAS_ETH0 1
+#define CONFIG_HAS_ETH1 1
+#define CONFIG_HAS_ETH2 1
+#define CONFIG_HAS_ETH3 1
+
+#define CONFIG_IPADDR 192.168.0.50
+
+#define CONFIG_HOSTNAME sbc8641d
+#define CONFIG_ROOTPATH /opt/eldk/ppc_74xx
+#define CONFIG_BOOTFILE uImage
+
+#define CONFIG_SERVERIP 192.168.0.2
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_NETMASK 255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=uRamdisk\0" \
+ "dtbaddr=400000\0" \
+ "dtbfile=sbc8641d.dtb\0" \
+ "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
+ "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+ "maxcpus=1"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr - $dtbaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr $ramdiskaddr $dtbaddr"
+
+#define CONFIG_FLASHBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "bootm ffd00000 ffb00000 ffa00000"
+
+#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sc3.h b/include/configs/sc3.h
index 6b6acfa..cb22536 100644
--- a/include/configs/sc3.h
+++ b/include/configs/sc3.h
@@ -58,7 +58,7 @@
* 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB)
*/
-#define CONFIG_SOLIDCARD3 1
+#define CONFIG_SC3 1
#define CONFIG_4xx 1
#define CONFIG_405GP 1
@@ -68,8 +68,7 @@
* Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range
* If undefined, IDE access uses a seperat emulation with higher access speed.
* Consider to inform your Linux IDE driver about the different addresses!
- * IDE_USES_ISA_EMULATION is only used if your CONFIG_COMMANDS macro includes
- * the CFG_CMD_IDE macro!
+ * IDE_USES_ISA_EMULATION is only used if you define CONFIG_CMD_IDE!
*/
#define IDE_USES_ISA_EMULATION
@@ -134,7 +133,8 @@
#if 1 /* feel free to disable for development */
#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
#define CONFIG_AUTOBOOT_PROMPT "\nSC3 - booting... stop with ENTER\n"
-#define CONFIG_AUTOBOOT_DELAY_STR "\n" /* 1st "password" */
+#define CONFIG_AUTOBOOT_DELAY_STR "\r" /* 1st "password" */
+#define CONFIG_AUTOBOOT_DELAY_STR2 "\n" /* 1st "password" */
#endif
/*
@@ -168,25 +168,36 @@
#define CONFIG_MII 1 /* add 405GP MII PHY management */
#define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | \
- CFG_CMD_AUTOSCRIPT | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_NET | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_NAND | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_CACHE | \
- CFG_CMD_ELF )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_ELF
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -276,7 +287,7 @@
* External peripheral base address
*-----------------------------------------------------------------------
*/
-#if !(CONFIG_COMMANDS & CFG_CMD_IDE)
+#if !defined(CONFIG_CMD_IDE)
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
@@ -285,7 +296,7 @@
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
-#else /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */
+#else
#define CONFIG_START_IDE 1 /* check, if use IDE */
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
@@ -345,7 +356,7 @@
#endif /* IDE_USES_ISA_EMULATION */
-#endif /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */
+#endif
/*
#define CFG_KEY_REG_BASE_ADDR 0xF0100000
@@ -436,7 +447,7 @@ extern unsigned long offsetOfEnvironment;
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h
index d7d07a6..8491d97 100644
--- a/include/configs/sc520_cdp.h
+++ b/include/configs/sc520_cdp.h
@@ -64,24 +64,37 @@
*/
#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024)
-
#define CONFIG_BAUDRATE 9600
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET | CFG_CMD_EEPROM)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_EEPROM
#define CONFIG_BOOTDELAY 15
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
-
/*
* Miscellaneous configurable options
*/
@@ -104,7 +117,6 @@
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
@@ -113,8 +125,6 @@
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
-
-
#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
@@ -125,11 +135,9 @@
#define CONFIG_SPI_EEPROM /* Support for SPI EEPROMs (AT25128) */
#define CONFIG_MW_EEPROM /* Support for MicroWire EEPROMs (AT93LC46) */
-
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-
/* Environment in EEPROM */
#define CFG_ENV_IS_IN_EEPROM 1
#define CONFIG_SPI
@@ -182,6 +190,15 @@
#undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */
/************************************************************
+*SATA/Native Stuff
+************************************************************/
+#define CFG_SATA_SUPPORTED 1
+#define CFG_SATA_MAXBUS 2 /*Max Sata buses supported */
+#define CFG_SATA_DEVS_PER_BUS 2 /*Max no. of devices per bus/port */
+#define CFG_SATA_MAXDEVICES (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS)
+#define CFG_ATA_PIIX 1 /*Supports ata_piix driver */
+
+/************************************************************
* ATAPI support (experimental)
************************************************************/
#define CONFIG_ATAPI /* enable ATAPI Support */
@@ -200,7 +217,6 @@
#define CONFIG_I8042_KBD
#define CFG_ISA_IO 0
-
/************************************************************
* RTC
***********************************************************/
diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h
index a8e3555..c6f7f15 100644
--- a/include/configs/sc520_spunk.h
+++ b/include/configs/sc520_spunk.h
@@ -64,16 +64,34 @@
#define CONFIG_BAUDRATE 9600
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET | CFG_CMD_PCMCIA | CFG_CMD_EEPROM)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_EEPROM
+
#define CONFIG_BOOTDELAY 15
#define CONFIG_BOOTARGS "root=/dev/mtdblock1 console=ttyS0,9600 mtdparts=phys:7936k(root),256k(uboot) "
#define CONFIG_BOOTCOMMAND "setenv bootargs root=/dev/nfs ip=autoconf console=ttyS0,9600 mtdparts=phys:7808k(root),128k(env),256k(uboot); bootp; bootm"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h
index a4249c4..d140241 100644
--- a/include/configs/scb9328.h
+++ b/include/configs/scb9328.h
@@ -36,20 +36,27 @@
/*
- * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
- * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
- * functionality or size of u-boot code.
+ * BOOTP options
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- & ~CFG_CMD_LOADS \
- & ~CFG_CMD_CONSOLE \
- & ~CFG_CMD_AUTOSCRIPT \
- | CFG_CMD_NET \
- | CFG_CMD_PING \
- | CFG_CMD_DHCP \
- )
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_CONSOLE
+#undef CONFIG_CMD_AUTOSCRIPT
-#include <cmd_confdefs.h>
/*
* Boot options. Setting delay to -1 stops autostart count down.
@@ -182,7 +189,7 @@
* Right now there is no gain for user, but later on booting kernel might be
* possible. Consider using XIP kernel running from flash to save RAM
* footprint.
- * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
*/
#define CFG_JFFS2_FIRST_BANK 0
#define CFG_JFFS2_FIRST_SECTOR 5
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index b7f79c2..c2e1386 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -37,10 +37,11 @@
#else
#define CONFIG_440GRX 1 /* Specific PPC440GRx */
#endif
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
/* Detect Sequoia PLL input clock automatically via CPLD bit */
#define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
- 3333333 : 33000000)
+ 33333333 : 33000000)
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
@@ -58,6 +59,7 @@
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
#define CFG_OCM_BASE 0xe0010000 /* ocm */
+#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
@@ -80,7 +82,7 @@
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
/*-----------------------------------------------------------------------
* Serial Port
@@ -125,7 +127,7 @@
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@@ -168,12 +170,19 @@
/*
* Now the NAND chip has to be defined (no autodetection used!)
*/
-#define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */
+#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
-#define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */
-#define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */
+#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
+#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
+#define CFG_NAND_ECCSIZE 256
+#define CFG_NAND_ECCBYTES 3
+#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
+#define CFG_NAND_OOBSIZE 16
+#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
+#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
+
#ifdef CFG_ENV_IS_IN_NAND
/*
* For NAND booting the environment is embedded in the U-Boot image. Please take
@@ -290,9 +299,6 @@
/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE
-#define CMD_USB CFG_CMD_USB
-#else
-#define CMD_USB 0 /* no USB on 440GRx */
#endif /* CONFIG_440EPX */
/* Partitions */
@@ -300,37 +306,73 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_DTT | \
- CFG_CMD_DIAG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NAND | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CMD_USB)
-#define CONFIG_SUPPORT_VFAT
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+#ifdef CONFIG_440EPX
+#define CONFIG_CMD_USB
+#endif
+
+#ifndef CONFIG_RAINIER
+#define CFG_POST_FPU_ON CFG_POST_FPU
+#else
+#define CFG_POST_FPU_ON 0
+#endif
+
+/* POST support */
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CPU | \
+ CFG_POST_UART | \
+ CFG_POST_I2C | \
+ CFG_POST_CACHE | \
+ CFG_POST_FPU_ON | \
+ CFG_POST_ETHER | \
+ CFG_POST_SPR)
+
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_LOGBUFFER
+#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
+#define CONFIG_SUPPORT_VFAT
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -358,12 +400,12 @@
*----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
-#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
@@ -421,7 +463,7 @@
*----------------------------------------------------------------------*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -433,7 +475,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/shannon.h b/include/configs/shannon.h
index 572985b..c1fa53f 100644
--- a/include/configs/shannon.h
+++ b/include/configs/shannon.h
@@ -66,21 +66,28 @@
#define CONFIG_BAUDRATE 115200
-#if 0 /* XXX - cannot test IDE anyway, so disabled for now - wd */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_IDE)
-#endif /* 0 */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200"
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_BOOTCOMMAND "help"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h
index a137f9d..05f6053 100644
--- a/include/configs/smdk2400.h
+++ b/include/configs/smdk2400.h
@@ -86,24 +86,32 @@
/* Use s3c2400's RTC */
#define CONFIG_RTC_S3C24X0 1
-#ifndef USE_920T_MMU
-#define CONFIG_COMMANDS_tmp ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \
- CFG_CMD_DATE | \
- CFG_CMD_SNTP )
-#else
-#define CONFIG_COMMANDS_tmp (CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_SNTP )
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_SNTP
+
+#if defined(CONFIG_HWFLOW)
+ #define CONFIG_CONFIG_HWFLOW
#endif
-#ifdef CONFIG_HWFLOW
-#define CONFIG_COMMANDS (CONFIG_COMMANDS_tmp | CFG_CMD_HWFLOW)
-#else
-#define CONFIG_COMMANDS CONFIG_COMMANDS_tmp
+#if !defined(USE_920T_MMU)
+ #undef CONFIG_CMD_CACHE
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 3
#if 0
@@ -118,7 +126,7 @@
#define CONFIG_BOOTCOMMAND "tftp; bootm"
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index 7edec0d..ca404ff 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -72,22 +72,26 @@
#define CONFIG_BAUDRATE 115200
-/***********************************************************
- * Command definition
- ***********************************************************/
-#define CONFIG_COMMANDS \
- (CONFIG_CMD_DFL | \
- CFG_CMD_CACHE | \
- /*CFG_CMD_NAND |*/ \
- /*CFG_CMD_EEPROM |*/ \
- /*CFG_CMD_I2C |*/ \
- /*CFG_CMD_USB |*/ \
- CFG_CMD_REGINFO | \
- CFG_CMD_DATE | \
- CFG_CMD_ELF)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+
#define CONFIG_BOOTDELAY 3
/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
@@ -98,7 +102,7 @@
/*#define CONFIG_BOOTFILE "elinos-lart" */
/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h
index e106b3b..ad68c75 100644
--- a/include/configs/smmaco4.h
+++ b/include/configs/smmaco4.h
@@ -42,11 +42,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -65,33 +60,41 @@
CFG_POST_I2C)
#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#else
-#define CFG_CMD_POST_DIAG 0
#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+
+#ifdef CONFIG_POST
+#define CONFIG_CMD_DIAG
+#endif
+
#define CONFIG_TIMESTAMP /* display image timestamps */
@@ -138,17 +141,17 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
-#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@@ -319,7 +322,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -338,9 +341,13 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
@@ -357,7 +364,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h
index 4937638..fe014ea 100644
--- a/include/configs/sorcery.h
+++ b/include/configs/sorcery.h
@@ -39,12 +39,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -69,30 +63,35 @@
#define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS
#define CONFIG_PCI_CFG_SIZE 0x01000000
+
/*
- * Supported commands
+ * BOOTP options
*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BOOTD | \
- CFG_CMD_CACHE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP | \
- 0)
-
-/* CFG_CMD_MII | \ */
-/* CFG_CMD_USB | \ */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
/*
* Default Environment
@@ -268,7 +267,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -284,6 +283,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h
index 09bbebd..2efc8f1 100644
--- a/include/configs/spc1920.h
+++ b/include/configs/spc1920.h
@@ -31,14 +31,9 @@
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_MII
-/* #define MII_DEBUG */
-/* #define CONFIG_FEC_ENET */
#undef CONFIG_ETHER_ON_FEC1
#define CONFIG_ETHER_ON_FEC2
#define FEC_ENET
-/* #define CONFIG_FEC2_PHY_NORXERR */
-/* #define CFG_DISCOVER_PHY */
-/* #define CONFIG_PHY_ADDR 0x1 */
#define CONFIG_FEC2_PHY 1
#define CONFIG_BAUDRATE 19200
@@ -80,24 +75,31 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
-#ifndef CONFIG_COMMANDS
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_ASKENV \
- | CFG_CMD_DATE \
- | CFG_CMD_ECHO \
- | CFG_CMD_IMMAP \
- | CFG_CMD_JFFS2 \
- | CFG_CMD_PING \
- | CFG_CMD_DHCP \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
- /* & ~( CFG_CMD_NET)) */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#endif /* !CONFIG_COMMANDS */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
/*
* Miscellaneous configurable options
@@ -107,7 +109,7 @@
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -194,7 +196,7 @@
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#ifdef CFG_CMD_DATE
+#ifdef CONFIG_CMD_DATE
# define CONFIG_RTC_DS3231
# define CFG_I2C_RTC_ADDR 0x68
#endif
@@ -202,7 +204,7 @@
/*-----------------------------------------------------------------------
* I2C configuration
*/
-#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#if defined(CONFIG_CMD_I2C)
/* enable I2C and select the hardware/software driver */
#undef CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
diff --git a/include/configs/spieval.h b/include/configs/spieval.h
index f40dde2..4b618f3 100644
--- a/include/configs/spieval.h
+++ b/include/configs/spieval.h
@@ -44,11 +44,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -88,12 +83,6 @@
#define CONFIG_NS8382X 1
#endif /* CONFIG_STK52XX */
-#ifdef CONFIG_PCI
-#define ADD_PCI_CMD CFG_CMD_PCI
-#else
-#define ADD_PCI_CMD 0
-#endif
-
/*
* Video console
*/
@@ -110,12 +99,6 @@
#define CFG_CONSOLE_IS_IN_ENV
#endif
-#ifdef CONFIG_VIDEO
-#define ADD_BMP_CMD CFG_CMD_BMP
-#else
-#define ADD_BMP_CMD 0
-#endif
-
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -124,10 +107,7 @@
/* USB */
#ifdef CONFIG_STK52XX
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
-#else
-#define ADD_USB_CMD 0
#endif
/* POST support */
@@ -136,43 +116,60 @@
CFG_POST_I2C)
#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#else
-#define CFG_CMD_POST_DIAG 0
#endif
-/* IDE */
-#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX)
-#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
-#else
-#define ADD_IDE_CMD 0
-#endif
/*
- * Supported commands
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- ADD_BMP_CMD | \
- ADD_IDE_CMD | \
- ADD_PCI_CMD | \
- ADD_USB_CMD | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_ECHO | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+
+#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
+ #define CONFIG_CMD_IDE
+ #define CONFIG_CMD_FAT
+ #define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_STK52XX
+ #define CONFIG_CMD_USB
+ #define CONFIG_CMD_FAT
+#endif
+
+#ifdef CONFIG_VIDEO
+ #define CONFIG_CMD_BMP
+#endif
+
+#ifdef CONFIG_PCI
+ #define CONFIG_CMD_PCI
+#endif
+
+#ifdef CONFIG_POST
+#define CONFIG_CMD_DIAG
+#endif
+
#define CONFIG_TIMESTAMP /* display image timestamps */
@@ -219,17 +216,17 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
-#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@@ -406,7 +403,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -425,9 +422,13 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
@@ -444,7 +445,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 625cf20..c5ae0cd 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -230,16 +230,17 @@
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
-#undef CONFIG_MPS85XX_FEC
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 4
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#define CONFIG_ETHPRIME "TSEC0"
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
@@ -298,34 +299,38 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+
#if defined(CFG_RAMBOOT)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV | \
- CFG_CMD_LOADS ))
- #elif defined(CONFIG_TSEC_ENET)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \
- CFG_CMD_MII | CFG_CMD_I2C ) & \
- ~(CFG_CMD_ENV))
- #elif defined(CONFIG_ETHER_ON_FCC)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV))
- #endif
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
- #elif defined(CONFIG_TSEC_ENET)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \
- CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C)
- #elif defined(CONFIG_ETHER_ON_FCC)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
- #endif
+ #define CONFIG_CMD_ELF
+#endif
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
#endif
-#include <cmd_confdefs.h>
+
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+ #define CONFIG_CMD_MII
+#endif
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -334,7 +339,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "GPPP=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -355,7 +360,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -367,13 +372,14 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*Note: change below for your network setting!!! */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index 8624f4b..b41dafa 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -42,20 +42,20 @@
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
-#undef CONFIG_PCI /* pci ethernet support */
-#define CONFIG_TSEC_ENET /* tsec ethernet support*/
-#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
+#define CONFIG_PCI /* PCI ethernet support */
+#define CONFIG_TSEC_ENET /* tsec ethernet support*/
+#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#undef CONFIG_DDR_DLL /* possible DLL fix needed */
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+#undef CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
/* sysclk for MPC85xx
*/
-#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
+#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
/* Blinkin' LEDs for Robert :-)
*/
@@ -64,36 +64,40 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#undef CFG_DRAM_TEST /* memory test, takes time */
-#define CFG_MEMTEST_START 0x00200000 /* memtest region */
-#define CFG_MEMTEST_END 0x00400000
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00200000 /* memtest region */
+#define CFG_MEMTEST_END 0x00400000
-/* Localbus connector. There are many options that can be
+/* Localbus connector. There are many options that can be
* connected here, including sdram or lots of flash.
* This address, however, is used to configure a 256M local bus
* window that includes the Config latch below.
*/
-#define CFG_LBC_OPTION_BASE 0xf0000000 /* Localbus Extension */
+#define CFG_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
#define CFG_LBC_OPTION_SIZE 256 /* 256MB */
/* There are various flash options used, we configure for the largest,
* which is 64Mbytes. The CFI works fine and will discover the proper
* sizes.
*/
-#define CFG_FLASH_BASE 0xFC000000 /* start of FLASH 64M */
-#define CFG_BR0_PRELIM 0xFC001801 /* port size 32bit */
-#define CFG_OR0_PRELIM 0xFC000FF7 /* 64 MB Flash */
+#ifdef CONFIG_STXSSA_4M
+#define CFG_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
+#else
+#define CFG_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
+#endif
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x1801) /* port size 32bit */
+#define CFG_OR0_PRELIM (CFG_FLASH_BASE | 0x0FF7)
#define CFG_FLASH_CFI 1
#define CFG_FLASH_CFI_DRIVER 1
-#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
+#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
@@ -104,24 +108,24 @@
/* The configuration latch is Chip Select 1.
* It's an 8-bit latch in the lower 8 bits of the word.
*/
-#define CFG_LBC_CFGLATCH_BASE 0xfb000000 /* Base of config latch */
-#define CFG_BR1_PRELIM 0xfb001801 /* 32-bit port */
-#define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
+#define CFG_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
+#define CFG_BR1_PRELIM 0xFB001801 /* 32-bit port */
+#define CFG_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
-#undef CFG_RAMBOOT
+#undef CFG_RAMBOOT
#endif
#ifdef CFG_RAMBOOT
-#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
+#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
#else
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#endif
-#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
+#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
@@ -136,14 +140,14 @@
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
-#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
+#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
#undef CONFIG_CLOCKS_IN_MHZ
/* local bus definitions */
-#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
+#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
#define CFG_OR2_PRELIM 0xfc006901
-#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
+#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
#define CFG_LBC_LBCR 0x00000000
#define CFG_LBC_LSRT 0x20000000
#define CFG_LBC_MRTPR 0x20000000
@@ -154,52 +158,52 @@
#define CFG_LBC_LSDMR_5 0x4061b723
#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
-#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 2
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
-#ifdef CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* I2C */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#if 0
-#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */
+#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */
#else
/* I did the 'if 0' so we could keep the syntax above if ever needed. */
#undef CFG_I2C_NOPROBES
#endif
#define CFG_I2C_OFFSET 0x3000
-/* I2C EEPROM. AT24C32, we keep our environment in here.
+/* I2C EEPROM. AT24C32, we keep our environment in here.
*/
#define CFG_I2C_EEPROM_ADDR 0x51 /* 1010001x */
#define CFG_I2C_EEPROM_ADDR_LEN 2
@@ -226,49 +230,50 @@
#define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */
#if defined(CONFIG_PCI) /* PCI Ethernet card */
-
+#define CONFIG_MPC85XX_PCI2 1
#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
+#define CONFIG_EEPRO100
+#define CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xe0000000
- #define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+ #define PCI_ENET0_IOADDR 0xe0000000
+ #define PCI_ENET0_MEMADDR 0xe0000000
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
-#undef CONFIG_PCI_SCAN_SHOW
-#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+#define CONFIG_PCI_SCAN_SHOW
+#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1 1
-#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC85XX_TSEC2 1
-#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
-#undef CONFIG_MPS85XX_FEC
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 4
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#define CONFIG_ETHPRIME "TSEC0"
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
-#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
+#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
+#undef CONFIG_ETHER_NONE /* define if ether on something else */
+#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
#if (CONFIG_ETHER_INDEX == 2)
/*
@@ -277,19 +282,19 @@
* - Select bus for bd/buffers
* - Full duplex
*/
- #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
- #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
- #define CFG_CPMFCR_RAMTYPE 0
+ #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+ #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+ #define CFG_CPMFCR_RAMTYPE 0
#if 0
- #define CFG_FCC_PSMR (FCC_PSMR_FDE)
+ #define CFG_FCC_PSMR (FCC_PSMR_FDE)
#else
- #define CFG_FCC_PSMR 0
+ #define CFG_FCC_PSMR 0
#endif
#define FETH2_RST 0x01
#elif (CONFIG_ETHER_INDEX == 3)
/* need more definitions here for FE3 */
#define FETH3_RST 0x80
-#endif /* CONFIG_ETHER_INDEX */
+#endif /* CONFIG_ETHER_INDEX */
/* MDIO is done through the TSEC0 control.
*/
@@ -300,17 +305,20 @@
/* Environment - default config is in flash, see below */
#if 0 /* in EEPROM */
-#define CFG_ENV_IS_IN_EEPROM 1
-#define CFG_ENV_OFFSET 0
-#define CFG_ENV_SIZE 2048
+# define CFG_ENV_IS_IN_EEPROM 1
+# define CFG_ENV_OFFSET 0
+# define CFG_ENV_SIZE 2048
#else /* in flash */
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_SECT_SIZE 0x40000
-
-#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE 0x4000
-#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+# define CFG_ENV_IS_IN_FLASH 1
+# ifdef CONFIG_STXSSA_4M
+# define CFG_ENV_SECT_SIZE 0x20000
+# else /* default configuration - 64 MiB flash */
+# define CFG_ENV_SECT_SIZE 0x40000
+# endif
+# define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
+# define CFG_ENV_SIZE 0x4000
+# define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
+# define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
@@ -318,34 +326,39 @@
#define CONFIG_TIMESTAMP /* Print image info with ts */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+ #define CONFIG_CMD_MII
+#endif
+
#if defined(CFG_RAMBOOT)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV | \
- CFG_CMD_LOADS ))
- #elif defined(CONFIG_TSEC_ENET)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \
- CFG_CMD_MII | CFG_CMD_I2C ) & \
- ~(CFG_CMD_ENV))
- #elif defined(CONFIG_ETHER_ON_FCC)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV))
- #endif
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
- #elif defined(CONFIG_TSEC_ENET)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \
- CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C)
- #elif defined(CONFIG_ETHER_ON_FCC)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
- #endif
+ #define CONFIG_CMD_ELF
#endif
-#include <cmd_confdefs.h>
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -354,7 +367,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "SSA=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -375,7 +388,7 @@
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -387,13 +400,14 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*Note: change below for your network setting!!! */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
@@ -408,13 +422,13 @@
*/
#ifdef CFG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */
-#define CONFIG_BAUDRATE 38400
+#define CONFIG_BAUDRATE 38400
#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
#define CONFIG_SERVERIP 192.168.85.1
-#define CONFIG_IPADDR 192.168.85.60
+#define CONFIG_IPADDR 192.168.85.60
#define CONFIG_GATEWAYIP 192.168.85.1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_HOSTNAME STX_SSA
@@ -424,7 +438,7 @@
#else /* ENV IS IN FLASH -- use a full-blown envionment */
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
index 614a046..b035857 100644
--- a/include/configs/stxxtc.h
+++ b/include/configs/stxxtc.h
@@ -77,7 +77,16 @@
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
+
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
@@ -100,19 +109,22 @@
#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_NAND | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_MII | \
- CFG_CMD_NFS)
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
@@ -122,7 +134,7 @@
#define CFG_HUSH_PARSER 1
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -213,7 +225,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
@@ -580,9 +592,6 @@ typedef unsigned int led_id_t;
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
#define OF_CPU "PowerPC,MPC870@0"
#define OF_TBCLK (MPC8XX_HZ / 16)
#define CONFIG_OF_HAS_BD_T 1
diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h
index 8224555..08ac9cb 100644
--- a/include/configs/suzaku.h
+++ b/include/configs/suzaku.h
@@ -55,10 +55,21 @@
#define MICROBLAZE_SYSREG_BASE_ADDR 0xFFFFA000
#define MICROBLAZE_SYSREG_RECONFIGURE (1 << 0)
-#define CONFIG_COMMANDS (CONFIG__CMD_DFL)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#define CFG_UART1_BASE (0xFFFF2000)
#define CONFIG_SERIAL_BASE CFG_UART1_BASE
diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h
index 92ee8cb..3b90f3c 100644
--- a/include/configs/svm_sc8xx.h
+++ b/include/configs/svm_sc8xx.h
@@ -125,22 +125,32 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_DOC | \
-/* CFG_CMD_IDE |*/ \
- CFG_CMD_DATE )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_DATE
+
+
#define CFG_NAND_LEGACY
/*
@@ -153,7 +163,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -246,7 +256,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/taihu.h b/include/configs/taihu.h
new file mode 100644
index 0000000..d623e56
--- /dev/null
+++ b/include/configs/taihu.h
@@ -0,0 +1,476 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2005-2007
+ * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+#define CONFIG_405EP 1 /* this is a PPC405 CPU */
+#define CONFIG_4xx 1 /* member of PPC4xx family */
+#define CONFIG_TAIHU 1 /* on a taihu board */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */
+
+#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
+
+#define CONFIG_NO_SERIAL_EEPROM
+
+/*----------------------------------------------------------------------------*/
+#ifdef CONFIG_NO_SERIAL_EEPROM
+
+/*
+!-------------------------------------------------------------------------------
+! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI,
+! assuming a 33MHz input clock to the 405EP from the C9531.
+!-------------------------------------------------------------------------------
+*/
+#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_3)
+#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_1)
+#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+
+#define PLLMR0_DEFAULT PLLMR0_333_111_55_37
+#define PLLMR1_DEFAULT PLLMR1_333_111_55_37
+#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111
+#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111
+
+#endif
+/*----------------------------------------------------------------------------*/
+
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootfile=/tftpboot/taihu/uImage\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "kernel_addr=FC000000\0" \
+ "ramdisk_addr=FC180000\0" \
+ "load=tftp 200000 /tftpboot/taihu/u-boot.bin\0" \
+ "update=protect off FFFC0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \
+ "cp.b 200000 FFFC0000 40000\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0x14 /* PHY address */
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */
+#define CONFIG_NET_MULTI 1
+#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_PHY_RESET 1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SPI
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */
+#define CFG_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
+#define CFG_SDRAM_BANKS 2
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
+
+/* SDRAM timings used in datasheet */
+#define CFG_SDRAM_CL 3 /* CAS latency */
+#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */
+#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
+#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
+#define CFG_SDRAM_tRFC 66 /* Auto refresh period */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+/*
+ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ * baseBaud = cpuClock/(uartDivisor*16)
+ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD 691200
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_UART1_CONSOLE 1
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * I2C stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
+
+#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+
+#define CONFIG_SOFT_SPI
+#define SPI_SCL spi_scl
+#define SPI_SDA spi_sda
+#define SPI_READ spi_read()
+#define SPI_DELAY udelay(2)
+#ifndef __ASSEMBLY__
+void spi_scl(int);
+void spi_sda(int);
+unsigned char spi_read(void);
+#endif
+
+/* standard dtt sensor configuration */
+#define CONFIG_DTT_DS1775 1
+#define CONFIG_DTT_SENSORS { 0 }
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
+#define PCI_HOST_FORCE 1 /* configure as pci host */
+#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
+
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+ /* resource configuration */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
+#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
+#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
+#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
+#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
+#define CONFIG_EEPRO100 1
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFFE00000
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_ADDR0 0x555
+#define CFG_FLASH_ADDR1 0x2aa
+#define CFG_FLASH_WORD_SIZE unsigned short
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
+#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
+
+#ifdef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
+#define CFG_ENV_ADDR \
+ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * PPC405 GPIO Configuration
+ */
+#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 */ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \
+} \
+}
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
+#define CFG_CACHELINE_SIZE 32
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR 0xF8000000
+#define CFG_OCM_DATA_SIZE 0x1000
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash/SRAM) initialization */
+#define CFG_EBC_PB0AP 0x03815600
+#define CFG_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (NVRAM/RTC) initialization */
+#define CFG_EBC_PB1AP 0x05815600
+#define CFG_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (USB device) initialization */
+#define CFG_EBC_PB2AP 0x03016600
+#define CFG_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 3 (LCM and D-flip-flop) initialization */
+#define CFG_EBC_PB3AP 0x158FF600
+#define CFG_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 4 (not install) initialization */
+#define CFG_EBC_PB4AP 0x158FF600
+#define CFG_EBC_PB4CR 0x5021A000
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0] - External Bus Controller BLAST output
+ * GPIO0[1-9] - Instruction trace outputs
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CFG_GPIO0_OSRH 0x15555550 /* output select high/low */
+#define CFG_GPIO0_OSRL 0x00000110
+#define CFG_GPIO0_ISR1H 0x00000001 /* input select high/low */
+#define CFG_GPIO0_ISR1L 0x15545440
+#define CFG_GPIO0_TSRH 0x00000000 /* three-state select high/low */
+#define CFG_GPIO0_TSRL 0x00000000
+#define CFG_GPIO0_TCR 0xFFFE8117 /* three-state control */
+#define CFG_GPIO0_ODR 0x00000000 /* open drain */
+
+#define GPIO0 0 /* GPIO controller 0 */
+
+/* the GPIO macros in include/ppc405.h for High/Low registers are backwards */
+
+#define GPIOx_OSL (GPIO0_OSRH-GPIO_BASE)
+#define GPIOx_TSL (GPIO0_TSRH-GPIO_BASE)
+#define GPIOx_IS1L (GPIO0_ISR1H-GPIO_BASE)
+#define GPIOx_IS2L (GPIO0_ISR1H-GPIO_BASE)
+#define GPIOx_IS3L (GPIO0_ISR1H-GPIO_BASE)
+
+#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO output select */
+#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO three-state select */
+#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO input select */
+#define GPIO_IS2(x) (x+GPIOx_IS1L)
+#define GPIO_IS3(x) (x+GPIOx_IS1L)
+
+#define CPLD_REG0_ADDR 0x50100000
+#define CPLD_REG1_ADDR 0x50100001
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/taishan.h b/include/configs/taishan.h
index 2b28f93..baa4fbd 100644
--- a/include/configs/taishan.h
+++ b/include/configs/taishan.h
@@ -30,6 +30,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_TAISHAN 1 /* Board is taishan */
#define CONFIG_440GX 1 /* Specifc GX support */
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
@@ -217,8 +218,8 @@
#define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1
-#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
-#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
+#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
+#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
#define CONFIG_PHY2_ADDR 0x1
#define CONFIG_PHY3_ADDR 0x3
#define CONFIG_ET1011C_PHY 1
@@ -233,27 +234,36 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
-/*-----------------------------------------------------------------------
- * Console/Commands/Parser
- *----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_DTT | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -262,7 +272,7 @@
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -297,7 +307,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
@@ -315,7 +324,7 @@
*----------------------------------------------------------------------*/
#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -327,7 +336,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h
index dac1eb7..a21af21 100644
--- a/include/configs/tb0229.h
+++ b/include/configs/tb0229.h
@@ -87,13 +87,27 @@
/*#define CONFIG_BOOTCOMMAND "run flash_local" */
#define CONFIG_BOOTCOMMAND "run netboot"
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_PCI | \
- CFG_CMD_ELF )
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_ELF
+
/*
* Miscellaneous configurable options
diff --git a/include/configs/trab.h b/include/configs/trab.h
index a2dc8e7..b9088a8 100644
--- a/include/configs/trab.h
+++ b/include/configs/trab.h
@@ -80,10 +80,17 @@
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
/* USB stuff */
-#define CONFIG_USB_OHCI 1
+#define CONFIG_USB_OHCI_NEW 1
#define CONFIG_USB_STORAGE 1
#define CONFIG_DOS_PARTITION 1
+#undef CFG_USB_OHCI_BOARD_INIT
+#define CFG_USB_OHCI_CPU_INIT 1
+
+#define CFG_USB_OHCI_REGS_BASE 0x14200000
+#define CFG_USB_OHCI_SLOT_NAME "s3c2400"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+
/*
* Size of malloc() pool
*/
@@ -130,60 +137,50 @@
/* Use s3c2400's RTC */
#define CONFIG_RTC_S3C24X0 1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
#ifdef CONFIG_HWFLOW
-#define CONFIG_COMMANDS_ADD_HWFLOW CFG_CMD_HWFLOW
-#else
-#define CONFIG_COMMANDS_ADD_HWFLOW 0
+ #define CONFIG_CMD_HWFLOW
#endif
#ifdef CONFIG_VFD
-#define CONFIG_COMMANDS_ADD_VFD CFG_CMD_VFD
-#else
-#define CONFIG_COMMANDS_ADD_VFD 0
+ #define CONFIG_CMD_VFD
#endif
#ifdef CONFIG_DRIVER_S3C24X0_I2C
-#define CONFIG_COMMANDS_ADD_EEPROM CFG_CMD_EEPROM
-#define CONFIG_COMMANDS_I2C CFG_CMD_I2C
-#else
-#define CONFIG_COMMANDS_ADD_EEPROM 0
-#define CONFIG_COMMANDS_I2C 0
+ #define CONFIG_CMD_EEPROM
+ #define CONFIG_CMD_I2C
#endif
#ifndef USE_920T_MMU
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \
- CONFIG_COMMANDS_ADD_HWFLOW | \
- CONFIG_COMMANDS_ADD_VFD | \
- CONFIG_COMMANDS_ADD_EEPROM | \
- CONFIG_COMMANDS_I2C | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_FAT | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP | \
- CFG_CMD_USB )
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CONFIG_COMMANDS_ADD_HWFLOW | \
- CONFIG_COMMANDS_ADD_VFD | \
- CONFIG_COMMANDS_ADD_EEPROM | \
- CONFIG_COMMANDS_I2C | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_FAT | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP | \
- CFG_CMD_USB )
+ #undef CONFIG_CMD_CACHE
#endif
+
/* moved up */
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#define CONFIG_BOOTDELAY 5
#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
#define CONFIG_PREBOOT "echo;echo *** booting ***;echo"
@@ -296,7 +293,7 @@
#define CONFIG_AUTOBOOT_DELAY_STR "R" /* 1st "password" */
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
@@ -422,6 +419,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/* Initial value of the on-board touch screen brightness */
#define CFG_BRIGHTNESS 0x20
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
new file mode 100644
index 0000000..84998d4
--- /dev/null
+++ b/include/configs/trizepsiv.h
@@ -0,0 +1,325 @@
+/*
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Gmbh, sbabic@denx.de
+ *
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the LUBBOCK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */
+
+#define LITTLEENDIAN 1 /* used by usb_ohci.c */
+
+#define CONFIG_MMC 1
+#define BOARD_LATE_INIT 1
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define RTC
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_FFUART 1 /* we use FFUART on Conxs */
+#define CONFIG_BTUART 1 /* we use BTUART on Conxs */
+#define CONFIG_STUART 1 /* we use STUART on Conxs */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 38400
+
+#define CONFIG_DOS_PARTITION 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IMLS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_SERVERIP 192.168.1.99
+#define CONFIG_BOOTCOMMAND "run boot_flash"
+#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\
+ " rw root=/dev/ram initrd=0xa0800000,5m"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "program_boot_mmc=" \
+ "mw.b 0xa0010000 0xff 0x20000; " \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa0010000 u-boot.bin; " \
+ "then " \
+ "protect off 0x0 0x1ffff; " \
+ "erase 0x0 0x1ffff; " \
+ "cp.b 0xa0010000 0x0 0x20000; " \
+ "fi\0" \
+ "program_uzImage_mmc=" \
+ "mw.b 0xa0010000 0xff 0x180000; " \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa0010000 uzImage; " \
+ "then " \
+ "protect off 0x40000 0x1bffff; " \
+ "erase 0x40000 0x1bffff; " \
+ "cp.b 0xa0010000 0x40000 0x180000; " \
+ "fi\0" \
+ "program_ramdisk_mmc=" \
+ "mw.b 0xa0010000 0xff 0x500000; " \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa0010000 ramdisk.gz; " \
+ "then " \
+ "protect off 0x1c0000 0x6bffff; " \
+ "erase 0x1c0000 0x6bffff; " \
+ "cp.b 0xa0010000 0x1c0000 0x500000; " \
+ "fi\0" \
+ "boot_mmc=" \
+ "if mmcinit && " \
+ "fatload mmc 0 0xa0030000 uzImage && " \
+ "fatload mmc 0 0xa0800000 ramdisk.gz; " \
+ "then " \
+ "bootm 0xa0030000; " \
+ "fi\0" \
+ "boot_flash=" \
+ "cp.b 0x1c0000 0xa0800000 0x500000; " \
+ "bootm 0x40000\0" \
+
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+/* #define CONFIG_INITRD_TAG 1 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER 1
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#define CFG_LONGHELP /* undef to save memory */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT "$ " /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_DEVICE_NULLDEV 1
+
+#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0xa1000000 /* default load address */
+
+#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
+
+ /* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_MMC_BASE 0xF0000000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+
+#define CFG_DRAM_BASE 0xa0000000
+#define CFG_DRAM_SIZE 0x04000000
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+
+/*
+ * GPIO settings
+ */
+#define CFG_GPSR0_VAL 0x00018000
+#define CFG_GPSR1_VAL 0x00000000
+#define CFG_GPSR2_VAL 0x400dc000
+#define CFG_GPSR3_VAL 0x00000000
+#define CFG_GPCR0_VAL 0x00000000
+#define CFG_GPCR1_VAL 0x00000000
+#define CFG_GPCR2_VAL 0x00000000
+#define CFG_GPCR3_VAL 0x00000000
+#define CFG_GPDR0_VAL 0x00018000
+#define CFG_GPDR1_VAL 0x00028801
+#define CFG_GPDR2_VAL 0x520dc000
+#define CFG_GPDR3_VAL 0x0001E000
+#define CFG_GAFR0_L_VAL 0x801c0000
+#define CFG_GAFR0_U_VAL 0x00000013
+#define CFG_GAFR1_L_VAL 0x6990100A
+#define CFG_GAFR1_U_VAL 0x00000008
+#define CFG_GAFR2_L_VAL 0xA0000000
+#define CFG_GAFR2_U_VAL 0x010900F2
+#define CFG_GAFR3_L_VAL 0x54000003
+#define CFG_GAFR3_U_VAL 0x00002401
+#define CFG_GRER0_VAL 0x00000000
+#define CFG_GRER1_VAL 0x00000000
+#define CFG_GRER2_VAL 0x00000000
+#define CFG_GRER3_VAL 0x00000000
+#define CFG_GFER0_VAL 0x00000000
+#define CFG_GFER1_VAL 0x00000000
+#define CFG_GFER2_VAL 0x00000000
+#define CFG_GFER3_VAL 0x00000020
+
+
+#define CFG_PSSR_VAL 0x20 /* CHECK */
+
+/*
+ * Clock settings
+ */
+#define CFG_CKEN 0x01FFFFFF /* CHECK */
+#define CFG_CCCR 0x02000290 /* 520Mhz */
+
+/*
+ * Memory settings
+ */
+
+#define CFG_MSC0_VAL 0x4df84df0
+#define CFG_MSC1_VAL 0x7ff87ff4
+#define CFG_MSC2_VAL 0xa26936d4
+#define CFG_MDCNFG_VAL 0x880009C9
+#define CFG_MDREFR_VAL 0x20ca201e
+#define CFG_MDMRS_VAL 0x00220022
+
+#define CFG_FLYCNFG_VAL 0x00000000
+#define CFG_SXCNFG_VAL 0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL 0x00000001
+#define CFG_MCMEM0_VAL 0x00004204
+#define CFG_MCMEM1_VAL 0x00010204
+#define CFG_MCATT0_VAL 0x00010504
+#define CFG_MCATT1_VAL 0x00010504
+#define CFG_MCIO0_VAL 0x00008407
+#define CFG_MCIO1_VAL 0x0000c108
+
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DM9000_BASE 0x08000000
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004)
+/* #define CONFIG_DM9000_USE_8BIT */
+/* #define CONFIG_DM9000_USE_16BIT */
+#define CONFIG_DM9000_USE_32BIT
+
+#define CONFIG_USB_OHCI_NEW 1
+#define CFG_USB_OHCI_BOARD_INIT 1
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 3
+#define CFG_USB_OHCI_REGS_BASE 0x4C000000
+#define CFG_USB_OHCI_SLOT_NAME "trizepsiv"
+#define CONFIG_USB_STORAGE 1
+#define CFG_USB_OHCI_CPU_INIT 1
+
+/*
+ * FLASH and environment organization
+ */
+
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER 1
+
+#define CFG_MONITOR_BASE 0
+#define CFG_MONITOR_LEN 0x40000
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
+
+/* write flash less slowly */
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+
+/* Flash environment locations */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */
+#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment */
+#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/uc100.h b/include/configs/uc100.h
index c4e629a..92148e2 100644
--- a/include/configs/uc100.h
+++ b/include/configs/uc100.h
@@ -98,7 +98,15 @@
#undef CONFIG_STATUS_LED /* no status-led */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -117,32 +125,32 @@
CFG_POST_SPR )
#undef CONFIG_POST
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+
#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
-#else
-#define CFG_CMD_POST_DIAG 0
+#define CONFIG_CMD_DIAG
#endif
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_MII | \
- CFG_CMD_NFS | \
- CFG_CMD_PING | \
- CFG_CMD_POST_DIAG | \
- CFG_CMD_SNTP )
#define CONFIG_NETCONSOLE
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
@@ -156,7 +164,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -246,7 +254,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/uc101.h b/include/configs/uc101.h
index 8cd8e9b..aed80ec 100644
--- a/include/configs/uc101.h
+++ b/include/configs/uc101.h
@@ -38,11 +38,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
#define CONFIG_BOARD_EARLY_INIT_R
/*
@@ -55,25 +50,34 @@
/* Partitions */
#define CONFIG_DOS_PARTITION
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
/*
- * Supported commands
+ * Command line configuration.
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DISPLAY | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_DTT | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_NFS | \
- CFG_CMD_MII | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DISPLAY
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_SNTP
+
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
@@ -114,7 +118,7 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration
@@ -245,7 +249,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -264,9 +268,13 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
- * which is normally part of the default commands (CFV_CMD_DFL)
+ * Enable loopw command.
*/
#define CONFIG_LOOPW
@@ -324,7 +332,6 @@
#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
#define CONFIG_IDE_PREINIT 1
-/* #define CONFIG_IDE_RESET 1 beispile siehe tqm5200.c */
#define CFG_ATA_IDE0_OFFSET 0x0000
diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h
index e5d4397..cd00c49 100644
--- a/include/configs/utx8245.h
+++ b/include/configs/utx8245.h
@@ -86,18 +86,36 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_COMMANDS (CFG_CMD_DFL | CFG_CMD_BDI | CFG_CMD_PCI \
- | CFG_CMD_FLASH | CFG_CMD_MEMORY \
- | CFG_CMD_ENV | CFG_CMD_CONSOLE \
- | CFG_CMD_LOADS | CFG_CMD_LOADB \
- | CFG_CMD_IMI | CFG_CMD_CACHE \
- | CFG_CMD_REGINFO | CFG_CMD_NET\
- | CFG_CMD_DHCP | CFG_CMD_I2C \
- | CFG_CMD_DATE)
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
*/
-#include <cmd_confdefs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
/*
@@ -403,7 +421,7 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/v37.h b/include/configs/v37.h
index a2e99b5..0407253 100644
--- a/include/configs/v37.h
+++ b/include/configs/v37.h
@@ -76,16 +76,30 @@
#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_DATE )
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_DATE
+
/*
* JFFS2 partitions
@@ -105,15 +119,12 @@
#define MTDPARTS_DEFAULT "mtdparts=v37-1:-(jffs2)"
*/
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -194,7 +205,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index e19591d..c0b1a15 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -46,11 +46,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Serial console configuration
*/
@@ -89,28 +84,37 @@
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00001000
+
/*
- * Supported commands
+ * BOOTP options
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_PING | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_IRQ | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_SDRAM | \
- CFG_CMD_DATE | \
- CFG_CMD_USB | \
- CFG_CMD_FAT)
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/*
* Boot low with 16 MB Flash
@@ -167,7 +171,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*
@@ -254,7 +258,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -270,6 +274,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
/*
* Various low-level settings
*/
diff --git a/include/configs/versatile.h b/include/configs/versatile.h
index 16db43b..d250150 100644
--- a/include/configs/versatile.h
+++ b/include/configs/versatile.h
@@ -96,14 +96,29 @@
#define CFG_SERIAL0 0x101F1000
#define CFG_SERIAL1 0x101F2000
-#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_ENV)
-/*#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) */
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_ENV
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
#define CONFIG_BOOTDELAY 2
#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=25,0,0xf1010000,0xf1010010,eth0"
diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h
index 06d8536..edae6f4 100644
--- a/include/configs/virtlab2.h
+++ b/include/configs/virtlab2.h
@@ -89,34 +89,38 @@
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#ifdef CONFIG_SPLASH_SCREEN
-# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BMP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
-#else
-# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_IDE | \
- CFG_CMD_NFS | \
- CFG_CMD_SNTP )
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+#if defined(CONFIG_SPLASH_SCREEN)
+ #define CONFIG_CMD_BMP
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
@@ -131,7 +135,7 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -203,6 +207,8 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
@@ -214,7 +220,7 @@
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h
index 4e97b01..7cab31d 100644
--- a/include/configs/voiceblue.h
+++ b/include/configs/voiceblue.h
@@ -131,33 +131,38 @@
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#ifdef VOICEBLUE_SMALL_FLASH
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_LOADB | \
- CFG_CMD_IMI | \
- CFG_CMD_FLASH | \
- CFG_CMD_MEMORY | \
- CFG_CMD_NET | \
- CFG_CMD_BOOTD | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_RUN)
-#else
-#define CONFIG_COMMANDS (CFG_CMD_BDI | \
- CFG_CMD_LOADB | \
- CFG_CMD_IMI | \
- CFG_CMD_FLASH | \
- CFG_CMD_MEMORY | \
- CFG_CMD_NET | \
- CFG_CMD_ENV | \
- CFG_CMD_BOOTD | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_RUN | \
- CFG_CMD_JFFS2)
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+
+#if !defined(VOICEBLUE_SMALL_FLASH)
+ #define CONFIG_CMD_ENV
+ #define CONFIG_CMD_JFFS2
#endif
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+
#define CONFIG_LOOPW
#ifdef VOICEBLUE_SMALL_FLASH
@@ -220,8 +225,6 @@
#endif /* VOICEBLUE_SMALL_FLASH */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
diff --git a/include/configs/walnut.h b/include/configs/walnut.h
index b34dc71..180549e 100644
--- a/include/configs/walnut.h
+++ b/include/configs/walnut.h
@@ -98,26 +98,38 @@
#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -128,7 +140,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -283,7 +295,7 @@
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -340,7 +352,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h
index 47251bb..c67b301 100644
--- a/include/configs/wepep250.h
+++ b/include/configs/wepep250.h
@@ -36,18 +36,24 @@
/*
- * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
- * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
- * functionality or size of u-boot code.
+ * BOOTP options
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- & ~CFG_CMD_NET \
- & ~CFG_CMD_LOADS \
- & ~CFG_CMD_CONSOLE \
- & ~CFG_CMD_AUTOSCRIPT \
-/* | CFG_CMD_JFFS2 */ \
- )
-#include <cmd_confdefs.h>
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_CONSOLE
+#undef CONFIG_CMD_AUTOSCRIPT
+
/*
* Boot options. Setting delay to -1 stops autostart count down.
@@ -152,7 +158,7 @@
* Right now there is no gain for user, but later on booting kernel might be
* possible. Consider using XIP kernel running from flash to save RAM
* footprint.
- * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
*/
#define CFG_JFFS2_FIRST_BANK 0
#define CFG_JFFS2_FIRST_SECTOR 5
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
index 1039762..7418986 100644
--- a/include/configs/xaeniax.h
+++ b/include/configs/xaeniax.h
@@ -64,15 +64,29 @@
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_DTT) | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_NFS | \
- CFG_CMD_SDRAM | \
- CFG_CMD_SNTP )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
+#undef CONFIG_CMD_DTT
+
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
#define CONFIG_NETMASK 255.255.255.0
@@ -86,7 +100,7 @@
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
#endif
diff --git a/include/configs/xm250.h b/include/configs/xm250.h
index 825bfd1..bcd16ec 100644
--- a/include/configs/xm250.h
+++ b/include/configs/xm250.h
@@ -81,14 +81,26 @@
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+
#define CONFIG_BOOTDELAY 3
diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h
index dc702cf..5733933 100644
--- a/include/configs/xsengine.h
+++ b/include/configs/xsengine.h
@@ -102,10 +102,26 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_PING | CFG_CMD_JFFS2)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_JFFS2
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h
index a2f4810..35001d7 100644
--- a/include/configs/xupv2p.h
+++ b/include/configs/xupv2p.h
@@ -118,25 +118,39 @@
#define CFG_ENV_IS_NOWHERE 1
#define CFG_ENV_SIZE 0x1000
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
-#define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
- CFG_CMD_MEMORY |\
- CFG_CMD_IRQ |\
- CFG_CMD_BDI |\
- CFG_CMD_NET |\
- CFG_CMD_IMI |\
- CFG_CMD_ECHO |\
- CFG_CMD_CACHE |\
- CFG_CMD_RUN |\
- CFG_CMD_AUTOSCRIPT |\
- CFG_CMD_ASKENV |\
- CFG_CMD_LOADS |\
- CFG_CMD_LOADB |\
- CFG_CMD_MISC |\
- CFG_CMD_PING \
- )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_PING
+
/* Miscellaneous configurable options */
#define CFG_PROMPT "U-Boot-mONStR> "
@@ -163,12 +177,12 @@
"base 0;" \
"echo"
-
/* system ace */
-/*#define CONFIG_SYSTEMACE
-#define DEBUG_SYSTEMACE
-#define CFG_SYSTEMACE_BASE 0xCF000000
-#define CFG_SYSTEMACE_WIDTH 16
-#define CONFIG_DOS_PARTITION*/
+#define CONFIG_SYSTEMACE
+/* #define DEBUG_SYSTEMACE */
+#define SYSTEMACE_CONFIG_FPGA
+#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
+#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
+#define CONFIG_DOS_PARTITION
#endif /* __CONFIG_H */
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index b68ae54..6a5b7f1 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -38,6 +38,7 @@
#define CONFIG_440GR 1 /* Specific PPC440GR support */
#define CONFIG_HOSTNAME yellowstone
#endif
+#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
@@ -122,7 +123,7 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@@ -232,17 +233,20 @@
#ifdef CONFIG_440EP
/* USB */
-#define CONFIG_USB_OHCI
+#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
+#define CFG_OHCI_BE_CONTROLLER
+
+#undef CFG_USB_OHCI_BOARD_INIT
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE (CFG_PERIPHERAL_BASE | 0x1000)
+#define CFG_USB_OHCI_SLOT_NAME "ppc440"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE
-#define CMD_USB (CFG_CMD_USB | CFG_CMD_FAT | CFG_CMD_EXT2)
-
#define CONFIG_SUPPORT_VFAT
-#else
-#define CMD_USB 0 /* no USB on 440GR */
#endif /* CONFIG_440EP */
#ifdef DEBUG
@@ -251,32 +255,49 @@
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CMD_USB)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+#ifdef CONFIG_440EP
+ #define CONFIG_CMD_USB
+ #define CONFIG_CMD_FAT
+ #define CONFIG_CMD_EXT2
+#endif
+
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -311,7 +332,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
@@ -344,7 +364,7 @@
*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -356,7 +376,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index 7f8b022..74033b4 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -46,7 +46,6 @@
#define EXTCLK_83 83333333
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
-#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
#undef CONFIG_SHOW_BOOT_PROGRESS
#undef CONFIG_STRESS
@@ -69,11 +68,11 @@
#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
#define CFG_PCIE0_CFGBASE 0xc0000000
-#define CFG_PCIE0_XCFGBASE 0xc0000400
-#define CFG_PCIE1_CFGBASE 0xc0001000
-#define CFG_PCIE1_XCFGBASE 0xc0001400
-#define CFG_PCIE2_CFGBASE 0xc0002000
-#define CFG_PCIE2_XCFGBASE 0xc0002400
+#define CFG_PCIE1_CFGBASE 0xc1000000
+#define CFG_PCIE2_CFGBASE 0xc2000000
+#define CFG_PCIE0_XCFGBASE 0xc3000000
+#define CFG_PCIE1_XCFGBASE 0xc3001000
+#define CFG_PCIE2_XCFGBASE 0xc3002000
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
@@ -136,7 +135,7 @@
/* Don't probe these addrs */
#define CFG_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54}
-/* #if (CONFIG_COMMANDS & CFG_CMD_EEPROM) */
+/* #if defined(CONFIG_CMD_EEPROM) */
/* #define CFG_I2C_EEPROM_ADDR 0x50 */ /* I2C boot EEPROM */
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
/* #endif */
@@ -183,6 +182,7 @@
"cp.b ${fileaddr} FFFB0000 ${filesize};" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
+ "pciconfighost=1\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -191,24 +191,36 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_EEPROM | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
#define CONFIG_IBM_EMAC4_V4 1
#define CONFIG_MII 1 /* MII PHY management */
@@ -232,7 +244,7 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -286,10 +298,9 @@
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
-#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#undef CFG_PCI_MASTER_INIT
@@ -314,7 +325,7 @@
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -326,7 +337,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/zeus.h b/include/configs/zeus.h
new file mode 100644
index 0000000..605755a
--- /dev/null
+++ b/include/configs/zeus.h
@@ -0,0 +1,382 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * zeus.h - configuration for Zeus board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_ZEUS 1 /* Board is Zeus */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_405EP 1 /* Specifc 405EP support*/
+
+#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+#define PLLMR0_DEFAULT PLLMR0_333_111_55_111
+#define PLLMR1_DEFAULT PLLMR1_333_111_55_111
+
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+
+#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0x01 /* PHY address */
+#define CONFIG_HAS_ETH1 1
+#define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */
+#define CONFIG_NET_MULTI 1
+#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_PHY_RESET 1
+#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+/* POST support */
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CPU | \
+ CFG_POST_CACHE | \
+ CFG_POST_UART | \
+ CFG_POST_ETHER)
+
+#define CFG_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */
+
+/* Define here the base-addresses of the UARTs to test in POST */
+#define CFG_POST_UART_TABLE {UART0_BASE}
+
+#define CONFIG_LOGBUFFER
+#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
+
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*-----------------------------------------------------------------------
+ * SDRAM
+ *----------------------------------------------------------------------*/
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
+
+/* SDRAM timings used in datasheet */
+#define CFG_SDRAM_CL 3 /* CAS latency */
+#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */
+#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
+#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
+#define CFG_SDRAM_tRFC 66 /* Auto refresh period */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#define CFG_BASE_BAUD 691200
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+/* these are for the ST M24C02 2kbit serial i2c eeprom */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
+
+#define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* write eeprom in pages */
+#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+
+/*
+ * The layout of the I2C EEPROM, used for bootstrap setup and for board-
+ * specific values, like ethaddr... that can be restored via the sw-reset
+ * button
+ */
+#define FACTORY_RESET_I2C_EEPROM 0x50
+#define FACTORY_RESET_ENV_OFFS 0x80
+#define FACTORY_RESET_ENV_SIZE 0x80
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFF000000
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR 0xF8000000
+#define CFG_OCM_DATA_SIZE 0x1000
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of OCM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+/* reserve some memory for POST and BOOT limit info */
+#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16)
+
+/* extra data in OCM */
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
+#define CFG_POST_MAGIC (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 8)
+#define CFG_POST_VAL (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 12)
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash 16M) initialization */
+#define CFG_EBC_PB0AP 0x05815600
+#define CFG_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0] - External Bus Controller BLAST output
+ * GPIO0[1-9] - Instruction trace outputs
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CFG_GPIO0_OSRH 0x15555550 /* Chip selects */
+#define CFG_GPIO0_OSRL 0x00000110 /* UART_DTR-pin 27 alt out */
+#define CFG_GPIO0_ISR1H 0x10000041 /* Pin 2, 12 is input */
+#define CFG_GPIO0_ISR1L 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
+#define CFG_GPIO0_TSRH 0x00000000
+#define CFG_GPIO0_TSRL 0x00000000
+#define CFG_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
+#define CFG_GPIO0_ODR 0x00000000
+
+#define CFG_GPIO_SW_RESET 1
+#define CFG_GPIO_ZEUS_PE 12
+#define CFG_GPIO_LED_RED 22
+#define CFG_GPIO_LED_GREEN 23
+
+/* Time in milli-seconds */
+#define CFG_TIME_POST 5000
+#define CFG_TIME_FACTORY_RESET 10000
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/* ENVIRONMENT VARS */
+
+#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo"
+#define CONFIG_IPADDR 192.168.1.10
+#define CONFIG_SERVERIP 192.168.1.100
+#define CONFIG_GATEWAYIP 192.168.1.100
+#define CONFIG_ETHADDR 50:00:00:00:06:00
+#define CONFIG_ETH1ADDR 50:00:00:00:06:01
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "logversion=2\0" \
+ "hostname=zeus\0" \
+ "netdev=eth0\0" \
+ "ethact=ppc_4xx_eth0\0" \
+ "netmask=255.255.255.0\0" \
+ "ramdisk_size=50000\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw" \
+ " nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw" \
+ " ramdisk=${ramdisk_size}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0," \
+ "${baudrate}\0" \
+ "net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \
+ "run nfsargs addip addtty;bootm\0" \
+ "net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \
+ "tftp ${ramdisk_mem_addr} ${file_fs};" \
+ "run ramargs addip addtty;" \
+ "bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \
+ "rootpath=/target_fs/zeus\0" \
+ "kernel_fl_addr=ff000000\0" \
+ "kernel_mem_addr=200000\0" \
+ "ramdisk_fl_addr=ff300000\0" \
+ "ramdisk_mem_addr=4000000\0" \
+ "uboot_fl_addr=fffc0000\0" \
+ "uboot_mem_addr=100000\0" \
+ "file_uboot=/zeus/u-boot.bin\0" \
+ "tftp_uboot=tftp 100000 ${file_uboot}\0" \
+ "update_uboot=protect off fffc0000 ffffffff;" \
+ "era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \
+ "protect on fffc0000 ffffffff\0" \
+ "upd_uboot=run tftp_uboot;run update_uboot\0" \
+ "file_kernel=/zeus/uImage_ba\0" \
+ "tftp_kernel=tftp 100000 ${file_kernel}\0" \
+ "update_kernel=protect off ff000000 ff17ffff;" \
+ "era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \
+ "upd_kernel=run tftp_kernel;run update_kernel\0" \
+ "file_fs=/zeus/rootfs_ba.img\0" \
+ "tftp_fs=tftp 100000 ${file_fs}\0" \
+ "update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
+ "cp.b 100000 ff300000 580000\0" \
+ "upd_fs=run tftp_fs;run update_fs\0" \
+ "bootcmd=chkreset;run ramargs addip addtty addmisc;" \
+ "bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \
+ ""
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h
index 1e8ed7a..517ecb1 100644
--- a/include/configs/zylonite.h
+++ b/include/configs/zylonite.h
@@ -76,19 +76,32 @@
#define CONFIG_BAUDRATE 115200
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
#ifdef TURN_ON_ETHERNET
-# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
+ #define CONFIG_CMD_PING
#else
-# define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
- | CFG_CMD_ENV \
- | CFG_CMD_NAND) \
- & ~(CFG_CMD_NET \
- | CFG_CMD_FLASH \
- | CFG_CMD_IMLS))
+ #define CONFIG_CMD_ENV
+ #define CONFIG_CMD_NAND
+
+ #undef CONFIG_CMD_NET
+ #undef CONFIG_CMD_FLASH
+ #undef CONFIG_CMD_IMLS
#endif
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY -1
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
@@ -100,7 +113,7 @@
#define CONFIG_CMDLINE_TAG
#define CONFIG_TIMESTAMP
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/da9030.h b/include/da9030.h
index 41108b9..3e3b202 100644
--- a/include/da9030.h
+++ b/include/da9030.h
@@ -104,3 +104,15 @@
#define SYS_CONTROL_A_HWRES_ENABLE (1<<2)
#define SYS_CONTROL_A_WDOG_ACTION (1<<3)
#define SYS_CONTROL_A_WATCHDOG (1<<7)
+
+#define MISC_CONTROLB_USB_INT_RISING (1<<2)
+#define MISC_CONTROLB_SESSION_VALID_EN (1<<3)
+
+#define USB_PUMP_USBVE (1<<0)
+#define USB_PUMP_USBVEP (1<<1)
+#define USB_PUMP_SRP_DETECT (1<<2)
+#define USB_PUMP_SESSION_VALID (1<<3)
+#define USB_PUMP_VBUS_VALID_4_0 (1<<4)
+#define USB_PUMP_VBUS_VALID_4_4 (1<<5)
+#define USB_PUMP_EN_USBVE (1<<6)
+#define USB_PUMP_EN_USBVEP (1<<7)
diff --git a/include/dataflash.h b/include/dataflash.h
index 650454e..fbd5e17 100644
--- a/include/dataflash.h
+++ b/include/dataflash.h
@@ -38,13 +38,47 @@
#include "config.h"
/*number of protected area*/
-#define NB_DATAFLASH_AREA 4
+#ifdef CONFIG_NEW_PARTITION
+# define NB_DATAFLASH_AREA 6
+#else
+# define NB_DATAFLASH_AREA 4
+#endif
+
+#ifdef CFG_NO_FLASH
+
+/*-----------------------------------------------------------------------
+ * return codes from flash_write():
+ */
+# define ERR_OK 0
+# define ERR_TIMOUT 1
+# define ERR_NOT_ERASED 2
+# define ERR_PROTECTED 4
+# define ERR_INVAL 8
+# define ERR_ALIGN 16
+# define ERR_UNKNOWN_FLASH_VENDOR 32
+# define ERR_UNKNOWN_FLASH_TYPE 64
+# define ERR_PROG_ERROR 128
+
+/*-----------------------------------------------------------------------
+ * Protection Flags for flash_protect():
+ */
+# define FLAG_PROTECT_SET 0x01
+# define FLAG_PROTECT_CLEAR 0x02
+# define FLAG_PROTECT_INVALID 0x03
+
+/*-----------------------------------------------------------------------
+ * Set Environment according to label:
+ */
+# define FLAG_SETENV 0x80
+#endif /* CFG_NO_FLASH */
/*define the area structure*/
typedef struct {
unsigned long start;
unsigned long end;
unsigned char protected;
+ unsigned char setenv;
+ unsigned char label[20];
} dataflash_protect_t;
typedef unsigned int AT91S_DataFlashStatus;
@@ -96,6 +130,7 @@ typedef struct _AT91S_DATAFLASH_INFO {
AT91S_DataflashDesc Desc;
AT91S_DataflashFeatures Device; /* Pointer on a dataflash features array */
unsigned long logical_address;
+ unsigned long end_address;
unsigned int id; /* device id */
} AT91S_DATAFLASH_INFO, *AT91PS_DATAFLASH_INFO;
@@ -106,6 +141,7 @@ typedef struct _AT91S_DATAFLASH_INFO {
#define AT45DB321 0x34
#define AT45DB642 0x3c
#define AT45DB128 0x10
+#define PAGES_PER_BLOCK 8
#define AT91C_DATAFLASH_TIMEOUT 10000 /* For AT91F_DataFlashWaitReady */
@@ -168,6 +204,7 @@ typedef struct _AT91S_DATAFLASH_INFO {
extern int size_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr, unsigned long size);
extern int prot_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr);
+extern int addr2ram(ulong addr);
extern int dataflash_real_protect (int flag, unsigned long start_addr, unsigned long end_addr);
extern int addr_dataflash (unsigned long addr);
extern int read_dataflash (unsigned long addr, unsigned long size, char *result);
@@ -175,4 +212,8 @@ extern int write_dataflash (unsigned long addr, unsigned long dest, unsigned lon
extern void dataflash_print_info (void);
extern void dataflash_perror (int err);
+#ifdef CONFIG_NEW_DF_PARTITION
+extern int AT91F_DataflashSetEnv (void); #endif
+#endif
+
#endif
diff --git a/include/asm-avr32/div64.h b/include/div64.h
index 2e0ba83..2e0ba83 100644
--- a/include/asm-avr32/div64.h
+++ b/include/div64.h
diff --git a/include/dm9161.h b/include/dm9161.h
index f5bfb19..d5d0e8d 100644
--- a/include/dm9161.h
+++ b/include/dm9161.h
@@ -43,9 +43,9 @@
#define DM9161_COLLISION_TEST (1 << 7)
/*--Bit definitions: DM9161_BMSR */
-#define DM9161_100BASE_T4 (1 << 15)
+#define DM9161_100BASE_TX (1 << 15)
#define DM9161_100BASE_TX_FD (1 << 14)
-#define DM9161_100BASE_T4_HD (1 << 13)
+#define DM9161_100BASE_TX_HD (1 << 13)
#define DM9161_10BASE_T_FD (1 << 12)
#define DM9161_10BASE_T_HD (1 << 11)
#define DM9161_MF_PREAMB_SUPPR (1 << 6)
diff --git a/include/dp83848.h b/include/dp83848.h
new file mode 100644
index 0000000..274bc4c
--- /dev/null
+++ b/include/dp83848.h
@@ -0,0 +1,88 @@
+/*
+ * DP83848 ethernet Physical layer
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+
+/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */
+
+#define DP83848_CTL_REG 0x0 /* Basic Mode Control Reg */
+#define DP83848_STAT_REG 0x1 /* Basic Mode Status Reg */
+#define DP83848_PHYID1_REG 0x2 /* PHY Idendifier Reg 1 */
+#define DP83848_PHYID2_REG 0x3 /* PHY Idendifier Reg 2 */
+#define DP83848_ANA_REG 0x4 /* Auto_Neg Advt Reg */
+#define DP83848_ANLPA_REG 0x5 /* Auto_neg Link Partner Ability Reg */
+#define DP83848_ANE_REG 0x6 /* Auto-neg Expansion Reg */
+#define DP83848_PHY_STAT_REG 0x10 /* PHY Status Register */
+#define DP83848_PHY_INTR_CTRL_REG 0x11 /* PHY Interrupt Control Register */
+#define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */
+
+/*--Bit definitions: DP83848_CTL_REG */
+#define DP83848_RESET (1 << 15) /* 1= S/W Reset */
+#define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */
+#define DP83848_SPEED_SELECT (1 << 13)
+#define DP83848_AUTONEG (1 << 12)
+#define DP83848_POWER_DOWN (1 << 11)
+#define DP83848_ISOLATE (1 << 10)
+#define DP83848_RESTART_AUTONEG (1 << 9)
+#define DP83848_DUPLEX_MODE (1 << 8)
+#define DP83848_COLLISION_TEST (1 << 7)
+
+/*--Bit definitions: DP83848_STAT_REG */
+#define DP83848_100BASE_T4 (1 << 15)
+#define DP83848_100BASE_TX_FD (1 << 14)
+#define DP83848_100BASE_TX_HD (1 << 13)
+#define DP83848_10BASE_T_FD (1 << 12)
+#define DP83848_10BASE_T_HD (1 << 11)
+#define DP83848_MF_PREAMB_SUPPR (1 << 6)
+#define DP83848_AUTONEG_COMP (1 << 5)
+#define DP83848_RMT_FAULT (1 << 4)
+#define DP83848_AUTONEG_ABILITY (1 << 3)
+#define DP83848_LINK_STATUS (1 << 2)
+#define DP83848_JABBER_DETECT (1 << 1)
+#define DP83848_EXTEND_CAPAB (1 << 0)
+
+/*--definitions: DP83848_PHYID1 */
+#define DP83848_PHYID1_OUI 0x2000
+#define DP83848_PHYID2_OUI 0x5c90
+
+/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */
+#define DP83848_NP (1 << 15)
+#define DP83848_ACK (1 << 14)
+#define DP83848_RF (1 << 13)
+#define DP83848_PAUSE (1 << 10)
+#define DP83848_T4 (1 << 9)
+#define DP83848_TX_FDX (1 << 8)
+#define DP83848_TX_HDX (1 << 7)
+#define DP83848_10_FDX (1 << 6)
+#define DP83848_10_HDX (1 << 5)
+#define DP83848_AN_IEEE_802_3 0x0001
+
+/*--Bit definitions: DP83848_ANER */
+#define DP83848_PDF (1 << 4)
+#define DP83848_LP_NP_ABLE (1 << 3)
+#define DP83848_NP_ABLE (1 << 2)
+#define DP83848_PAGE_RX (1 << 1)
+#define DP83848_LP_AN_ABLE (1 << 0)
+
+/*--Bit definitions: DP83848_PHY_STAT */
+#define DP83848_RX_ERR_LATCH (1 << 13)
+#define DP83848_POLARITY_STAT (1 << 12)
+#define DP83848_FALSE_CAR_SENSE (1 << 11)
+#define DP83848_SIG_DETECT (1 << 10)
+#define DP83848_DESCRAM_LOCK (1 << 9)
+#define DP83848_PAGE_RCV (1 << 8)
+#define DP83848_PHY_RMT_FAULT (1 << 6)
+#define DP83848_JABBER (1 << 5)
+#define DP83848_AUTONEG_COMPLETE (1 << 4)
+#define DP83848_LOOPBACK_STAT (1 << 3)
+#define DP83848_DUPLEX (1 << 2)
+#define DP83848_SPEED (1 << 1)
+#define DP83848_LINK (1 << 0)
diff --git a/include/dtt.h b/include/dtt.h
index 842a761..2e8c690 100644
--- a/include/dtt.h
+++ b/include/dtt.h
@@ -29,6 +29,7 @@
#if defined(CONFIG_DTT_LM75) || \
defined(CONFIG_DTT_DS1621) || \
+ defined(CONFIG_DTT_DS1775) || \
defined(CONFIG_DTT_LM81) || \
defined(CONFIG_DTT_ADM1021)
@@ -78,6 +79,13 @@ extern int dtt_get_temp(int sensor);
#define DTT_CONFIG 0xAC
#endif
+#if defined(CONFIG_DTT_DS1775)
+#define DTT_READ_TEMP 0x0
+#define DTT_CONFIG 0x1
+#define DTT_TEMP_HYST 0x2
+#define DTT_TEMP_OS 0x3
+#endif
+
#if defined(CONFIG_DTT_ADM1021)
#define DTT_READ_LOC_VALUE 0x00
#define DTT_READ_REM_VALUE 0x01
diff --git a/include/exports.h b/include/exports.h
index 8f7f617..d6512cb 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -23,10 +23,15 @@ void do_reset (void);
unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base);
char *getenv (char *name);
void setenv (char *varname, char *varvalue);
-#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+long simple_strtol(const char *cp,char **endp,unsigned int base);
+int strcmp(const char * cs,const char * ct);
+#ifdef CONFIG_HAS_UID
+void forceenv (char *varname, char *varvalue);
+#endif
+#if defined(CONFIG_CMD_I2C)
int i2c_write (uchar, uint, int , uchar* , int);
int i2c_read (uchar, uint, int , uchar* , int);
-#endif /* CFG_CMD_I2C */
+#endif
void app_startup(char **);
@@ -40,7 +45,7 @@ enum {
XF_MAX
};
-#define XF_VERSION 3
+#define XF_VERSION 4
#if defined(CONFIG_I386)
extern gd_t *global_data;
diff --git a/include/fdt_support.h b/include/fdt_support.h
index a276834..60fa423 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -38,5 +38,11 @@ int fdt_env(void *fdt);
int fdt_bd_t(void *fdt);
#endif
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_board_setup(void *blob, bd_t *bd);
+void ft_cpu_setup(void *blob, bd_t *bd);
+void ft_pci_setup(void *blob, bd_t *bd);
+#endif
+
#endif /* ifdef CONFIG_OF_LIBFDT */
#endif /* ifndef __FDT_SUPPORT_H */
diff --git a/include/flash.h b/include/flash.h
index 43b9c6b..b0bf733 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -119,6 +119,11 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
*/
#define FLAG_PROTECT_SET 0x01
#define FLAG_PROTECT_CLEAR 0x02
+#define FLAG_PROTECT_INVALID 0x03
+/*-----------------------------------------------------------------------
+ * Set Environment according to label:
+ */
+#define FLAG_SETENV 0x80
/*-----------------------------------------------------------------------
* Device IDs
diff --git a/include/ide.h b/include/ide.h
index 6976a6c..222f4f8 100644
--- a/include/ide.h
+++ b/include/ide.h
@@ -26,6 +26,8 @@
#define IDE_BUS(dev) (dev >> 1)
+#define ATA_CURR_BASE(dev) (CFG_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])
+
#ifdef CONFIG_IDE_LED
/*
diff --git a/include/image.h b/include/image.h
index 2f575fd..432fa22 100644
--- a/include/image.h
+++ b/include/image.h
@@ -77,6 +77,7 @@
#define IH_CPU_NIOS2 15 /* Nios-II */
#define IH_CPU_BLACKFIN 16 /* Blackfin */
#define IH_CPU_AVR32 17 /* AVR32 */
+#define IH_CPU_ST200 18 /* STMicroelectronics ST200 */
/*
* Image Types
diff --git a/include/lcd.h b/include/lcd.h
index b688583..8a4273c 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -173,10 +173,10 @@ void lcd_printf (const char *fmt, ...);
/************************************************************************/
/* ** BITMAP DISPLAY SUPPORT */
/************************************************************************/
-#if (CONFIG_COMMANDS & CFG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN)
+#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN)
# include <bmp_layout.h>
# include <asm/byteorder.h>
-#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) || CONFIG_SPLASH_SCREEN */
+#endif
/*
* Information about displays we are using. This is for configuring
diff --git a/include/led.h b/include/led.h
new file mode 100644
index 0000000..57c2b4a
--- /dev/null
+++ b/include/led.h
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2006
+ * Atmel Nordic AB <www.atmel.com>
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __LED_H
+#define __LED_H
+
+#ifndef __ASSEMBLY__
+extern void LED_init (void);
+extern void red_LED_on(void);
+extern void red_LED_off(void);
+extern void green_LED_on(void);
+extern void green_LED_off(void);
+extern void yellow_LED_on(void);
+extern void yellow_LED_off(void);
+#else
+ .extern LED_init
+ .extern red_LED_on
+ .extern red_LED_off
+ .extern yellow_LED_on
+ .extern yellow_LED_off
+ .extern green_LED_on
+ .extern green_LED_off
+#endif
+#endif
diff --git a/include/libfdt.h b/include/libfdt.h
index f8bac73..38c65a9 100644
--- a/include/libfdt.h
+++ b/include/libfdt.h
@@ -77,7 +77,13 @@ int fdt_subnode_offset_namelen(const void *fdt, int parentoffset,
const char *name, int namelen);
int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name);
-int fdt_path_offset(const void *fdt, const char *path);
+int fdt_find_node_by_path(const void *fdt, const char *path);
+int fdt_find_node_by_type(const void *fdt, int nodeoffset, const char *type);
+
+int fdt_node_is_compatible(const void *fdt, int nodeoffset,
+ const char *compat);
+int fdt_find_compatible_node(const void *fdt, int nodeoffset,
+ const char *type, const char *compat);
struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset,
const char *name, int *lenp);
@@ -134,6 +140,8 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name,
})
#define fdt_setprop_string(fdt, nodeoffset, name, str) \
fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
+int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
+ const void *val, int len, int create);
int fdt_delprop(void *fdt, int nodeoffset, const char *name);
int fdt_add_subnode_namelen(void *fdt, int parentoffset,
const char *name, int namelen);
diff --git a/include/libfdt_env.h b/include/libfdt_env.h
index e746314..78f7258 100644
--- a/include/libfdt_env.h
+++ b/include/libfdt_env.h
@@ -26,7 +26,7 @@
#include <asm/byteorder.h>
#include <linux/string.h>
-struct fdt_header *fdt; /* Pointer to the working fdt */
+extern struct fdt_header *fdt; /* Pointer to the working fdt */
#define fdt32_to_cpu(x) __be32_to_cpu(x)
#define cpu_to_fdt32(x) __cpu_to_be32(x)
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 4b48564..49ff80f 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -348,6 +348,7 @@ struct nand_chip {
#define NAND_MFR_NATIONAL 0x8f
#define NAND_MFR_RENESAS 0x07
#define NAND_MFR_STMICRO 0x20
+#define NAND_MFR_MICRON 0x2c
/**
* struct nand_flash_dev - NAND Flash Device ID Structure
diff --git a/include/linux/stat.h b/include/linux/stat.h
index 43fd53f..37f2924 100644
--- a/include/linux/stat.h
+++ b/include/linux/stat.h
@@ -67,7 +67,8 @@ struct stat {
#endif /* __PPC__ */
-#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__)
+#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__) ||\
+ defined (__microblaze__)
struct stat {
unsigned short st_dev;
diff --git a/include/logbuff.h b/include/logbuff.h
index 3acfc18..d415729 100644
--- a/include/logbuff.h
+++ b/include/logbuff.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2002
+ * (C) Copyright 2002-2007
* Detlev Zundel, dzu@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -25,6 +25,7 @@
#ifdef CONFIG_LOGBUFFER
+#define LOGBUFF_MAGIC 0xc0de4ced /* Forced by code, eh! */
#define LOGBUFF_LEN (16384) /* Must be 16k right now */
#define LOGBUFF_MASK (LOGBUFF_LEN-1)
#define LOGBUFF_OVERHEAD (4096) /* Logbuffer overhead for extra info */
@@ -32,6 +33,29 @@
#define LOGBUFF_INITIALIZED (1<<31)
+/* The mapping used here has to be the same as in setup_ext_logbuff ()
+ in linux/kernel/printk */
+
+typedef struct {
+ union {
+ struct {
+ unsigned long tag;
+ unsigned long start;
+ unsigned long con;
+ unsigned long end;
+ unsigned long chars;
+ } v2;
+ struct {
+ unsigned long dummy;
+ unsigned long tag;
+ unsigned long start;
+ unsigned long size;
+ unsigned long chars;
+ } v1;
+ };
+ unsigned char buf[0];
+} logbuff_t;
+
int drv_logbuff_init (void);
void logbuff_init_ptrs (void);
void logbuff_log(char *msg);
diff --git a/include/mk48t59.h b/include/mk48t59.h
index 03c992e..a4459c0 100644
--- a/include/mk48t59.h
+++ b/include/mk48t59.h
@@ -26,7 +26,7 @@
*/
-#if defined(CONFIG_RTC_MK48T59) && (CONFIG_COMMANDS & CFG_CMD_DATE)
+#if defined(CONFIG_RTC_MK48T59) && defined(CONFIG_CMD_DATE)
#define RTC_PORT_ADDR0 CFG_ISA_IO + 0x70
#define RTC_PORT_ADDR1 RTC_PORT_ADDR0 + 0x1
diff --git a/include/mpc512x.h b/include/mpc512x.h
new file mode 100644
index 0000000..a100b22
--- /dev/null
+++ b/include/mpc512x.h
@@ -0,0 +1,398 @@
+/*
+ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
+ * (C) Copyright 2007 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * Derived from the MPC83xx header.
+ */
+
+#ifndef __MPC512X_H__
+#define __MPC512X_H__
+
+#include <config.h>
+#if defined(CONFIG_E300)
+#include <asm/e300.h>
+#endif
+
+/* System reset offset (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET 0x0100
+#define _START_OFFSET EXC_OFF_SYS_RESET
+
+
+/* IMMRBAR - Internal Memory Register Base Address
+ */
+#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */
+#define IMMRBAR 0x0000 /* Register offset to immr */
+#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */
+#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
+
+/* LAWBAR - Local Access Window Base Address Register
+ */
+#define LPBAW 0x0020 /* Register offset to immr */
+#define LPCS0AW 0x0024
+#define LPCS1AW 0x0028
+#define LPCS2AW 0x002C
+#define LPCS3AW 0x0030
+#define LPCS4AW 0x0034
+#define LPCS5AW 0x0038
+#define LPCS6AW 0x003C
+#define LPCA7AW 0x0040
+#define SRAMBAR 0x00C4
+
+#define LPC_OFFSET 0x10000
+
+#define CS0_CONFIG 0x00000
+#define CS1_CONFIG 0x00004
+#define CS2_CONFIG 0x00008
+#define CS3_CONFIG 0x0000C
+#define CS4_CONFIG 0x00010
+#define CS5_CONFIG 0x00014
+#define CS6_CONFIG 0x00018
+#define CS7_CONFIG 0x0001C
+
+#define CS_CTRL 0x00020
+#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */
+#define CS_CTRL_IE 0x08000000 /* CS Interrupt Enable bit */
+
+/* SPRIDR - System Part and Revision ID Register
+ */
+#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */
+#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */
+
+#define SPR_5121E 0x80180000
+
+/* SPCR - System Priority Configuration Register
+ */
+#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */
+#define SPCR_PCIHPE_SHIFT (31-3)
+#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */
+#define SPCR_PCIPR_SHIFT (31-7)
+#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */
+#define SPCR_TBEN_SHIFT (31-9)
+#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */
+#define SPCR_COREPR_SHIFT (31-11)
+
+/* SWCRR - System Watchdog Control Register
+ */
+#define SWCRR 0x0904 /* Register offset to immr */
+#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */
+#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */
+#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */
+#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */
+#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
+
+/* SWCNR - System Watchdog Counter Register
+ */
+#define SWCNR 0x0908 /* Register offset to immr */
+#define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */
+#define SWCNR_RES ~(SWCNR_SWCN)
+
+/* SWSRR - System Watchdog Service Register
+ */
+#define SWSRR 0x090E /* Register offset to immr */
+
+/* ACR - Arbiter Configuration Register
+ */
+#define ACR_COREDIS 0x10000000 /* Core disable */
+#define ACR_COREDIS_SHIFT (31-7)
+#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */
+#define ACR_PIPE_DEP_SHIFT (31-15)
+#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */
+#define ACR_PCI_RPTCNT_SHIFT (31-19)
+#define ACR_RPTCNT 0x00000700 /* Repeat count */
+#define ACR_RPTCNT_SHIFT (31-23)
+#define ACR_APARK 0x00000030 /* Address parking */
+#define ACR_APARK_SHIFT (31-27)
+#define ACR_PARKM 0x0000000F /* Parking master */
+#define ACR_PARKM_SHIFT (31-31)
+
+/* ATR - Arbiter Timers Register
+ */
+#define ATR_DTO 0x00FF0000 /* Data time out */
+#define ATR_ATO 0x000000FF /* Address time out */
+
+/* AER - Arbiter Event Register
+ */
+#define AER_ETEA 0x00000020 /* Transfer error */
+#define AER_RES 0x00000010 /* Reserved transfer type */
+#define AER_ECW 0x00000008 /* External control word transfer type */
+#define AER_AO 0x00000004 /* Address Only transfer type */
+#define AER_DTO 0x00000002 /* Data time out */
+#define AER_ATO 0x00000001 /* Address time out */
+
+/* AEATR - Arbiter Event Address Register
+ */
+#define AEATR_EVENT 0x07000000 /* Event type */
+#define AEATR_MSTR_ID 0x001F0000 /* Master Id */
+#define AEATR_TBST 0x00000800 /* Transfer burst */
+#define AEATR_TSIZE 0x00000700 /* Transfer Size */
+#define AEATR_TTYPE 0x0000001F /* Transfer Type */
+
+/* RSR - Reset Status Register
+ */
+#define RSR_SWSR 0x00002000 /* software soft reset */
+#define RSR_SWSR_SHIFT 13
+#define RSR_SWHR 0x00001000 /* software hard reset */
+#define RSR_SWHR_SHIFT 12
+#define RSR_JHRS 0x00000200 /* jtag hreset */
+#define RSR_JHRS_SHIFT 9
+#define RSR_JSRS 0x00000100 /* jtag sreset status */
+#define RSR_JSRS_SHIFT 8
+#define RSR_CSHR 0x00000010 /* checkstop reset status */
+#define RSR_CSHR_SHIFT 4
+#define RSR_SWRS 0x00000008 /* software watchdog reset status */
+#define RSR_SWRS_SHIFT 3
+#define RSR_BMRS 0x00000004 /* bus monitop reset status */
+#define RSR_BMRS_SHIFT 2
+#define RSR_SRS 0x00000002 /* soft reset status */
+#define RSR_SRS_SHIFT 1
+#define RSR_HRS 0x00000001 /* hard reset status */
+#define RSR_HRS_SHIFT 0
+#define RSR_RES ~(RSR_SWSR | RSR_SWHR |\
+ RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
+ RSR_BMRS | RSR_SRS | RSR_HRS)
+/* RMR - Reset Mode Register
+ */
+#define RMR_CSRE 0x00000001 /* checkstop reset enable */
+#define RMR_CSRE_SHIFT 0
+#define RMR_RES ~(RMR_CSRE)
+
+/* RCR - Reset Control Register
+ */
+#define RCR_SWHR 0x00000002 /* software hard reset */
+#define RCR_SWSR 0x00000001 /* software soft reset */
+#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
+
+/* RCER - Reset Control Enable Register
+ */
+#define RCER_CRE 0x00000001 /* software hard reset */
+#define RCER_RES ~(RCER_CRE)
+
+/* SPMR - System PLL Mode Register
+ */
+#define SPMR_SPMF 0x0F000000
+#define SPMR_SPMF_SHIFT 24
+#define SPMR_CPMF 0x000F0000
+#define SPMR_CPMF_SHIFT 16
+
+/* SCFR1 System Clock Frequency Register 1
+ */
+#define SCFR1_IPS_DIV 0x2
+#define SCFR1_IPS_DIV_MASK 0x03800000
+#define SCFR1_IPS_DIV_SHIFT 23
+
+/* SCFR2 System Clock Frequency Register 2
+ */
+#define SCFR2_SYS_DIV 0xFC000000
+#define SCFR2_SYS_DIV_SHIFT 26
+
+/* SCCR - System Clock Control Registers
+ */
+
+/* System Clock Control Register 1 commands */
+#define CLOCK_SCCR1_CFG_EN 0x80000000
+#define CLOCK_SCCR1_LPC_EN 0x40000000
+#define CLOCK_SCCR1_NFC_EN 0x20000000
+#define CLOCK_SCCR1_PATA_EN 0x10000000
+#define CLOCK_SCCR1_PSC_EN(cn) (0x08000000 >> (cn))
+#define CLOCK_SCCR1_PSCFIFO_EN 0x00008000
+#define CLOCK_SCCR1_SATA_EN 0x00004000
+#define CLOCK_SCCR1_FEC_EN 0x00002000
+#define CLOCK_SCCR1_TPR_EN 0x00001000
+#define CLOCK_SCCR1_PCI_EN 0x00000800
+#define CLOCK_SCCR1_DDR_EN 0x00000400
+
+/* System Clock Control Register 2 commands */
+#define CLOCK_SCCR2_DIU_EN 0x80000000
+#define CLOCK_SCCR2_AXE_EN 0x40000000
+#define CLOCK_SCCR2_MEM_EN 0x20000000
+#define CLOCK_SCCR2_USB2_EN 0x10000000
+#define CLOCK_SCCR2_USB1_EN 0x08000000
+#define CLOCK_SCCR2_I2C_EN 0x04000000
+#define CLOCK_SCCR2_BDLC_EN 0x02000000
+#define CLOCK_SCCR2_SDHC_EN 0x01000000
+#define CLOCK_SCCR2_SPDIF_EN 0x00800000
+#define CLOCK_SCCR2_MBX_BUS_EN 0x00400000
+#define CLOCK_SCCR2_MBX_EN 0x00200000
+#define CLOCK_SCCR2_MBX_3D_EN 0x00100000
+#define CLOCK_SCCR2_IIM_EN 0x00080000
+
+/* PSC FIFO Command values */
+#define PSC_FIFO_RESET_SLICE 0x80
+#define PSC_FIFO_ENABLE_SLICE 0x01
+
+/* PSC FIFO Controller Command values */
+#define FIFOC_ENABLE_CLOCK_GATE 0x01
+#define FIFOC_DISABLE_CLOCK_GATE 0x00
+
+/* PSC FIFO status */
+#define PSC_FIFO_EMPTY 0x01
+
+/* PSC Command values */
+#define PSC_RX_ENABLE 0x01
+#define PSC_RX_DISABLE 0x02
+#define PSC_TX_ENABLE 0x04
+#define PSC_TX_DISABLE 0x08
+#define PSC_SEL_MODE_REG_1 0x10
+#define PSC_RST_RX 0x20
+#define PSC_RST_TX 0x30
+#define PSC_RST_ERR_STAT 0x40
+#define PSC_RST_BRK_CHG_INT 0x50
+#define PSC_START_BRK 0x60
+#define PSC_STOP_BRK 0x70
+
+/* PSC status register bits */
+#define PSC_SR_CDE 0x0080
+#define PSC_SR_TXEMP 0x0800
+#define PSC_SR_OE 0x1000
+#define PSC_SR_PE 0x2000
+#define PSC_SR_FE 0x4000
+#define PSC_SR_RB 0x8000
+
+/* PSC mode fields */
+#define PSC_MODE_5_BITS 0x00
+#define PSC_MODE_6_BITS 0x01
+#define PSC_MODE_7_BITS 0x02
+#define PSC_MODE_8_BITS 0x03
+#define PSC_MODE_PAREVEN 0x00
+#define PSC_MODE_PARODD 0x04
+#define PSC_MODE_PARFORCE 0x08
+#define PSC_MODE_PARNONE 0x10
+#define PSC_MODE_ENTIMEOUT 0x20
+#define PSC_MODE_RXRTS 0x80
+#define PSC_MODE_1_STOPBIT 0x07
+
+/*
+ * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs
+ *
+ * NOTE: individual PSC units are free to use whatever area (and size) of the
+ * FIFOC internal memory, so make sure memory areas for FIFO slices used by
+ * different PSCs do not overlap!
+ *
+ * Overall size of FIFOC memory is not documented in the MPC5121e RM, but
+ * tests indicate that it is 1024 words total.
+ */
+#define FIFOC_PSC0_TX_SIZE 0x0 /* number of 4-byte words for FIFO slice */
+#define FIFOC_PSC0_TX_ADDR 0x0
+#define FIFOC_PSC0_RX_SIZE 0x0
+#define FIFOC_PSC0_RX_ADDR 0x0
+
+#define FIFOC_PSC1_TX_SIZE 0x0
+#define FIFOC_PSC1_TX_ADDR 0x0
+#define FIFOC_PSC1_RX_SIZE 0x0
+#define FIFOC_PSC1_RX_ADDR 0x0
+
+#define FIFOC_PSC2_TX_SIZE 0x0
+#define FIFOC_PSC2_TX_ADDR 0x0
+#define FIFOC_PSC2_RX_SIZE 0x0
+#define FIFOC_PSC2_RX_ADDR 0x0
+
+#define FIFOC_PSC3_TX_SIZE 0x04
+#define FIFOC_PSC3_TX_ADDR 0x0
+#define FIFOC_PSC3_RX_SIZE 0x04
+#define FIFOC_PSC3_RX_ADDR 0x10
+
+#define FIFOC_PSC4_TX_SIZE 0x0
+#define FIFOC_PSC4_TX_ADDR 0x0
+#define FIFOC_PSC4_RX_SIZE 0x0
+#define FIFOC_PSC4_RX_ADDR 0x0
+
+#define FIFOC_PSC5_TX_SIZE 0x0
+#define FIFOC_PSC5_TX_ADDR 0x0
+#define FIFOC_PSC5_RX_SIZE 0x0
+#define FIFOC_PSC5_RX_ADDR 0x0
+
+#define FIFOC_PSC6_TX_SIZE 0x0
+#define FIFOC_PSC6_TX_ADDR 0x0
+#define FIFOC_PSC6_RX_SIZE 0x0
+#define FIFOC_PSC6_RX_ADDR 0x0
+
+#define FIFOC_PSC7_TX_SIZE 0x0
+#define FIFOC_PSC7_TX_ADDR 0x0
+#define FIFOC_PSC7_RX_SIZE 0x0
+#define FIFOC_PSC7_RX_ADDR 0x0
+
+#define FIFOC_PSC8_TX_SIZE 0x0
+#define FIFOC_PSC8_TX_ADDR 0x0
+#define FIFOC_PSC8_RX_SIZE 0x0
+#define FIFOC_PSC8_RX_ADDR 0x0
+
+#define FIFOC_PSC9_TX_SIZE 0x0
+#define FIFOC_PSC9_TX_ADDR 0x0
+#define FIFOC_PSC9_RX_SIZE 0x0
+#define FIFOC_PSC9_RX_ADDR 0x0
+
+#define FIFOC_PSC10_TX_SIZE 0x0
+#define FIFOC_PSC10_TX_ADDR 0x0
+#define FIFOC_PSC10_RX_SIZE 0x0
+#define FIFOC_PSC10_RX_ADDR 0x0
+
+#define FIFOC_PSC11_TX_SIZE 0x0
+#define FIFOC_PSC11_TX_ADDR 0x0
+#define FIFOC_PSC11_RX_SIZE 0x0
+#define FIFOC_PSC11_RX_ADDR 0x0
+
+/* IO Control Register
+ */
+
+/* Indexes in regs array */
+#define MEM_IDX 0x00
+#define SPDIF_TXCLOCK_IDX 0x73
+#define SPDIF_TX_IDX 0x74
+#define SPDIF_RX_IDX 0x75
+#define PSC0_0_IDX 0x83
+#define PSC0_1_IDX 0x84
+#define PSC0_2_IDX 0x85
+#define PSC0_3_IDX 0x86
+#define PSC0_4_IDX 0x87
+#define PSC1_0_IDX 0x88
+#define PSC1_1_IDX 0x89
+#define PSC1_2_IDX 0x8a
+#define PSC1_3_IDX 0x8b
+#define PSC1_4_IDX 0x8c
+#define PSC2_0_IDX 0x8d
+#define PSC2_1_IDX 0x8e
+#define PSC2_2_IDX 0x8f
+#define PSC2_3_IDX 0x90
+#define PSC2_4_IDX 0x91
+
+#define IOCTRL_FUNCMUX_SHIFT 7
+#define IOCTRL_FUNCMUX_FEC 1
+#define IOCTRL_MUX_FEC (IOCTRL_FUNCMUX_FEC << IOCTRL_FUNCMUX_SHIFT)
+
+/* Set for DDR */
+#define IOCTRL_MUX_DDR 0x00000036
+
+ /* Register Offset Base */
+#define MPC512X_FEC (CFG_IMMR + 0x02800)
+
+/* Number of I2C buses */
+#define I2C_BUS_CNT 3
+
+/* I2Cn control register bits */
+#define I2C_EN 0x80
+#define I2C_IEN 0x40
+#define I2C_STA 0x20
+#define I2C_TX 0x10
+#define I2C_TXAK 0x08
+#define I2C_RSTA 0x04
+#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
+
+/* I2Cn status register bits */
+#define I2C_CF 0x80
+#define I2C_AAS 0x40
+#define I2C_BB 0x20
+#define I2C_AL 0x10
+#define I2C_SRW 0x04
+#define I2C_IF 0x02
+#define I2C_RXAK 0x01
+
+#endif /* __MPC512X_H__ */
diff --git a/include/mpc5xx.h b/include/mpc5xx.h
index 7508f6d..414651f 100644
--- a/include/mpc5xx.h
+++ b/include/mpc5xx.h
@@ -36,6 +36,7 @@
* Exception offsets (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
+#define _START_OFFSET EXC_OFF_SYS_RESET
/*-----------------------------------------------------------------------
* ISB bit in IMMR to set internal memory map
@@ -75,10 +76,10 @@
#define SIUMCR_DBPC01 0x00080000 /* - " - */
#define SIUMCR_DBPC10 0x00100000 /* - " - */
#define SIUMCR_DBPC11 0x00180000 /* - " - */
-#define SIUMCR_GPC00 0x00000000 /* General Pins Config */
-#define SIUMCR_GPC01 0x00020000 /* General Pins Config */
-#define SIUMCR_GPC10 0x00040000 /* General Pins Config */
-#define SIUMCR_GPC11 0x00060000 /* General Pins Config */
+#define SIUMCR_GPC00 0x00000000 /* General Pins Config */
+#define SIUMCR_GPC01 0x00020000 /* General Pins Config */
+#define SIUMCR_GPC10 0x00040000 /* General Pins Config */
+#define SIUMCR_GPC11 0x00060000 /* General Pins Config */
#define SIUMCR_DLK 0x00010000 /* Debug Register Lock */
#define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */
#define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */
@@ -89,7 +90,7 @@
#define SIUMCR_MLRC01 0x00000400 /* - " - */
#define SIUMCR_MLRC10 0x00000800 /* - " - */
#define SIUMCR_MLRC11 0x00000c00 /* - " - */
-#define SIUMCR_MTSC 0x00000100 /* Memory transfer */
+#define SIUMCR_MTSC 0x00000100 /* Memory transfer */
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control Register
@@ -122,13 +123,13 @@
* SCCR - System Clock and reset Control Register
*/
#define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */
-#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */
+#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */
#define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */
#define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */
#define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */
#define SCCR_EBDF11 0x00060000 /* reserved */
#define SCCR_TBS 0x02000000 /* Time Base Source */
-#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
+#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
#define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */
#define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */
#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */
@@ -137,11 +138,11 @@
/*-----------------------------------------------------------------------
* MC - Memory Controller
*/
-#define BR_V 0x00000001 /* Bank valid */
-#define BR_BI 0x00000002 /* Burst inhibit */
-#define BR_PS_8 0x00000400 /* 8 bit port size */
-#define BR_PS_16 0x00000800 /* 16 bit port size */
-#define BR_PS_32 0x00000000 /* 32 bit port size */
+#define BR_V 0x00000001 /* Bank valid */
+#define BR_BI 0x00000002 /* Burst inhibit */
+#define BR_PS_8 0x00000400 /* 8 bit port size */
+#define BR_PS_16 0x00000800 /* 16 bit port size */
+#define BR_PS_32 0x00000000 /* 32 bit port size */
#define BR_LBDIR 0x00000008 /* Late burst data in progess */
#define BR_SETA 0x00000004 /* External Data Acknowledge */
#define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */
@@ -158,8 +159,8 @@
/*-----------------------------------------------------------------------
* UMCR - UIMB Module Configuration Register
*/
-#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */
-#define UMCR_HSPEED 0x10000000 /* Half speed */
+#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */
+#define UMCR_HSPEED 0x10000000 /* Half speed */
/*-----------------------------------------------------------------------
* ICTRL - I-Bus Support Control Register
@@ -173,16 +174,16 @@
* SCI - Serial communication interface
*/
-#define SCI_TDRE 0x0100 /* Transmit data register empty */
-#define SCI_TE 0x0008 /* Transmitter enabled */
+#define SCI_TDRE 0x0100 /* Transmit data register empty */
+#define SCI_TE 0x0008 /* Transmitter enabled */
#define SCI_RE 0x0004 /* Receiver enabled */
-#define SCI_RDRF 0x0040 /* Receive data register full */
-#define SCI_PE 0x0400 /* Parity enable */
-#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */
-#define SCI_SCXDR_MK 0x00ff /* Data register mask */
+#define SCI_RDRF 0x0040 /* Receive data register full */
+#define SCI_PE 0x0400 /* Parity enable */
+#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */
+#define SCI_SCXDR_MK 0x00ff /* Data register mask */
#define SCI_M_11 0x0200 /* Frame size is 11 bit */
#define SCI_M_10 0x0000 /* Frame size is 10 bit */
-#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */
+#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */
#define SCI_PORT_2 ((int)2)
#endif /* __MPC5XX_H__ */
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
index 089aa13..a4581a3 100644
--- a/include/mpc5xxx.h
+++ b/include/mpc5xxx.h
@@ -39,6 +39,7 @@
/* Exception offsets (PowerPC standard) */
#define EXC_OFF_SYS_RESET 0x0100
+#define _START_OFFSET EXC_OFF_SYS_RESET
/* useful macros for manipulating CSx_START/STOP */
#if defined(CONFIG_MGT5100)
diff --git a/include/mpc8220.h b/include/mpc8220.h
index ff7acc6..d3b1457 100644
--- a/include/mpc8220.h
+++ b/include/mpc8220.h
@@ -35,6 +35,7 @@
/* Exception offsets (PowerPC standard) */
#define EXC_OFF_SYS_RESET 0x0100
+#define _START_OFFSET EXC_OFF_SYS_RESET
/* Internal memory map */
/* MPC8220 Internal Register MMAP */
diff --git a/include/mpc824x.h b/include/mpc824x.h
index 30fc795..30f01d5 100644
--- a/include/mpc824x.h
+++ b/include/mpc824x.h
@@ -88,7 +88,7 @@
#define PREP_PCI_MEMORY_BUS 0x80000000
#define PREP_PCI_MEMORY_SIZE 0x80000000
#define MPC107_PCI_CMD 0x80000004 /* MPC107 PCI cmd reg */
-#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */
+#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */
#define PROC_INT1_ADR 0x800000a8 /* MPC107 Processor i/f cfg1 */
#define PROC_INT2_ADR 0x800000ac /* MPC107 Processor i/f cfg2 */
#define MEM_CONT1_ADR 0x800000f0 /* MPC107 Memory control config. 1 */
@@ -98,8 +98,8 @@
#define MEM_ERREN1_ADR 0x800000c0 /* MPC107 Memory error enable 1 */
#define MEM_START1_ADR 0x80000080 /* MPC107 Memory starting addr */
#define MEM_START2_ADR 0x80000084 /* MPC107 Memory starting addr-lo */
-#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/
-#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/
+#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/
+#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/
#define MEM_END1_ADR 0x80000090 /* MPC107 Memory ending address */
#define MEM_END2_ADR 0x80000094 /* MPC107 Memory ending addr-lo */
#define XMEM_END1_ADR 0x80000098 /* MPC107 Extended mem. end addrs-hi */
@@ -142,6 +142,8 @@
#define EXC_OFF_JMDDI 0x1600 /* Java Mode denorm detect Interr -- WTF??*/
#define EXC_OFF_RMTE 0x2000 /* Run Mode or Trace Exception */
+#define _START_OFFSET EXC_OFF_SYS_RESET
+
#define MAP_A_CONFIG_ADDR_HIGH 0x8000 /* Upper half of CONFIG_ADDR for Map A */
#define MAP_A_CONFIG_ADDR_LOW 0x0CF8 /* Lower half of CONFIG_ADDR for Map A */
#define MAP_A_CONFIG_DATA_HIGH 0x8000 /* Upper half of CONFIG_DAT for Map A */
diff --git a/include/mpc8260.h b/include/mpc8260.h
index d9dd92d..0525294 100644
--- a/include/mpc8260.h
+++ b/include/mpc8260.h
@@ -53,7 +53,7 @@
* Exception offsets (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
-
+#define _START_OFFSET EXC_OFF_SYS_RESET
/*-----------------------------------------------------------------------
* BCR - Bus Configuration Register 4-25
@@ -664,7 +664,7 @@
#define PSDMR_CL_3 0x00000003 /* CAS Latency = 3 */
/*-----------------------------------------------------------------------
- * LSDMR - Local Bus SDRAM Mode Register 10-24
+ * LSDMR - Local Bus SDRAM Mode Register 10-24
*/
/*
@@ -707,23 +707,23 @@
/*-----------------------------------------------------------------------
* TMR1-TMR4 - Timer Mode Registers 17-6
*/
-#define TMRx_PS_MSK 0xff00 /* Prescaler Value */
+#define TMRx_PS_MSK 0xff00 /* Prescaler Value */
#define TMRx_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt*/
-#define TMRx_OM 0x0020 /* Output Mode */
+#define TMRx_OM 0x0020 /* Output Mode */
#define TMRx_ORI 0x0010 /* Output Reference Interrupt Enable*/
-#define TMRx_FRR 0x0008 /* Free Run/Restart */
+#define TMRx_FRR 0x0008 /* Free Run/Restart */
#define TMRx_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */
-#define TMRx_GE 0x0001 /* Gate Enable */
+#define TMRx_GE 0x0001 /* Gate Enable */
#define TMRx_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event*/
#define TMRx_CE_RISING 0x0040 /* Capture on Rising TINx edge only */
#define TMRx_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */
-#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */
+#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */
-#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
+#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
#define TMRx_ICLK_IN_GEN 0x0002 /* Internal General system clock*/
#define TMRx_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16*/
-#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */
+#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */
/*-----------------------------------------------------------------------
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index c2a4ff5..4d32c6a 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -25,6 +25,7 @@
/* System reset offset (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100
+#define _START_OFFSET EXC_OFF_SYS_RESET
/* IMMRBAR - Internal Memory Register Base Address
*/
@@ -85,6 +86,8 @@
#define SPR_8360_REV12 0x80490012
#define SPR_8360E_REV20 0x80480020
#define SPR_8360_REV20 0x80490020
+#define SPR_8360E_REV21 0x80480021
+#define SPR_8360_REV21 0x80490021
#define SPR_8323E_REV10 0x80620010
#define SPR_8323_REV10 0x80630010
@@ -95,6 +98,11 @@
#define SPR_8321E_REV11 0x80660011
#define SPR_8321_REV11 0x80670011
+#define SPR_8311_REV10 0x80B30010
+#define SPR_8311E_REV10 0x80B20010
+#define SPR_8313_REV10 0x80B10010
+#define SPR_8313E_REV10 0x80B00010
+
/* SPCR - System Priority Configuration Register
*/
#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */
@@ -121,6 +129,15 @@
#define SPCR_TSEC2BDP_SHIFT (31-29)
#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */
#define SPCR_TSEC2EP_SHIFT (31-31)
+
+#elif defined(CONFIG_MPC831X)
+/* SPCR bits - MPC831x specific */
+#define SPCR_TSECDP 0x00003000 /* TSEC data priority */
+#define SPCR_TSECDP_SHIFT (31-19)
+#define SPCR_TSECEP 0x00000C00 /* TSEC emergency priority */
+#define SPCR_TSECEP_SHIFT (31-21)
+#define SPCR_TSECBDP 0x00000300 /* TSEC buffer descriptor priority */
+#define SPCR_TSECBDP_SHIFT (31-23)
#endif
/* SICRL/H - System I/O Configuration Register Low/High
@@ -195,6 +212,36 @@
#define SICRL_PCI_MSRC 0x10000000
#define SICRL_URT_CTPR 0x06000000
#define SICRL_IRQ_CTPR 0x00C00000
+
+#elif defined(CONFIG_MPC831X)
+/* SICRL bits - MPC831x specific */
+#define SICRL_LBC 0x30000000
+#define SICRL_UART 0x0C000000
+#define SICRL_SPI_A 0x03000000
+#define SICRL_SPI_B 0x00C00000
+#define SICRL_SPI_C 0x00300000
+#define SICRL_SPI_D 0x000C0000
+#define SICRL_USBDR 0x00000C00
+#define SICRL_ETSEC1_A 0x0000000C
+#define SICRL_ETSEC2_A 0x00000003
+
+/* SICRH bits - MPC831x specific */
+#define SICRH_INTR_A 0x02000000
+#define SICRH_INTR_B 0x00C00000
+#define SICRH_IIC 0x00300000
+#define SICRH_ETSEC2_B 0x000C0000
+#define SICRH_ETSEC2_C 0x00030000
+#define SICRH_ETSEC2_D 0x0000C000
+#define SICRH_ETSEC2_E 0x00003000
+#define SICRH_ETSEC2_F 0x00000C00
+#define SICRH_ETSEC2_G 0x00000300
+#define SICRH_ETSEC1_B 0x00000080
+#define SICRH_ETSEC1_C 0x00000060
+#define SICRH_GTX1_DLY 0x00000008
+#define SICRH_GTX2_DLY 0x00000004
+#define SICRH_TSOBI1 0x00000002
+#define SICRH_TSOBI2 0x00000001
+
#endif
/* SWCRR - System Watchdog Control Register
@@ -393,6 +440,28 @@
#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
+#if defined(CONFIG_MPC831X)
+#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
+#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
+#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
+#define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000
+
+#define HRCWH_RL_EXT_LEGACY 0x00000000
+#define HRCWH_RL_EXT_NAND 0x00040000
+
+#define HRCWH_TSEC1M_IN_MII 0x00000000
+#define HRCWH_TSEC1M_IN_RMII 0x00002000
+#define HRCWH_TSEC1M_IN_RGMII 0x00006000
+#define HRCWH_TSEC1M_IN_RTBI 0x0000A000
+#define HRCWH_TSEC1M_IN_SGMII 0x0000C000
+
+#define HRCWH_TSEC2M_IN_MII 0x00000000
+#define HRCWH_TSEC2M_IN_RMII 0x00000400
+#define HRCWH_TSEC2M_IN_RGMII 0x00000C00
+#define HRCWH_TSEC2M_IN_RTBI 0x00001400
+#define HRCWH_TSEC2M_IN_SGMII 0x00001800
+#endif
+
#if defined(CONFIG_MPC834X)
#define HRCWH_TSEC1M_IN_RGMII 0x00000000
#define HRCWH_TSEC1M_IN_RTBI 0x00004000
@@ -523,6 +592,20 @@
#define SCCR_TSEC2CM_1 0x10000000
#define SCCR_TSEC2CM_2 0x20000000
#define SCCR_TSEC2CM_3 0x30000000
+
+#elif defined(CONFIG_MPC831X)
+/* TSEC1 bits are for TSEC2 as well */
+#define SCCR_TSEC1CM 0xc0000000
+#define SCCR_TSEC1CM_SHIFT 30
+#define SCCR_TSEC1CM_1 0x40000000
+#define SCCR_TSEC1CM_2 0x80000000
+#define SCCR_TSEC1CM_3 0xC0000000
+
+#define SCCR_TSEC1ON 0x20000000
+#define SCCR_TSEC1ON_SHIFT 29
+#define SCCR_TSEC2ON 0x10000000
+#define SCCR_TSEC2ON_SHIFT 28
+
#endif
#define SCCR_USBMPHCM 0x00c00000
@@ -556,6 +639,25 @@
#define CSCONFIG_COL_BIT_10 0x00000002
#define CSCONFIG_COL_BIT_11 0x00000003
+/* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
+ */
+#define TIMING_CFG0_RWT 0xC0000000
+#define TIMING_CFG0_RWT_SHIFT 30
+#define TIMING_CFG0_WRT 0x30000000
+#define TIMING_CFG0_WRT_SHIFT 28
+#define TIMING_CFG0_RRT 0x0C000000
+#define TIMING_CFG0_RRT_SHIFT 26
+#define TIMING_CFG0_WWT 0x03000000
+#define TIMING_CFG0_WWT_SHIFT 24
+#define TIMING_CFG0_ACT_PD_EXIT 0x00700000
+#define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20
+#define TIMING_CFG0_PRE_PD_EXIT 0x00070000
+#define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16
+#define TIMING_CFG0_ODT_PD_EXIT 0x00000F00
+#define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8
+#define TIMING_CFG0_MRS_CYC 0x00000F00
+#define TIMING_CFG0_MRS_CYC_SHIFT 0
+
/* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
*/
#define TIMING_CFG1_PRETOACT 0x70000000
@@ -586,20 +688,33 @@
#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */
+#define TIMING_CFG2_ADD_LAT 0x70000000
+#define TIMING_CFG2_ADD_LAT_SHIFT 28
+#define TIMING_CFG2_WR_LAT_DELAY 0x00380000
+#define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19
+#define TIMING_CFG2_RD_TO_PRE 0x0000E000
+#define TIMING_CFG2_RD_TO_PRE_SHIFT 13
+#define TIMING_CFG2_CKE_PLS 0x000001C0
+#define TIMING_CFG2_CKE_PLS_SHIFT 6
+#define TIMING_CFG2_FOUR_ACT 0x0000003F
+#define TIMING_CFG2_FOUR_ACT_SHIFT 0
+
/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
*/
#define SDRAM_CFG_MEM_EN 0x80000000
#define SDRAM_CFG_SREN 0x40000000
#define SDRAM_CFG_ECC_EN 0x20000000
#define SDRAM_CFG_RD_EN 0x10000000
-#define SDRAM_CFG_SDRAM_TYPE 0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
#define SDRAM_CFG_32_BE 0x00080000
#define SDRAM_CFG_8_BE 0x00040000
#define SDRAM_CFG_NCAP 0x00020000
#define SDRAM_CFG_2T_EN 0x00008000
-#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
+#define SDRAM_CFG_BI 0x00000001
/* DDR_SDRAM_MODE - DDR SDRAM Mode Register
*/
@@ -732,11 +847,15 @@
#define BR_PS_32 0x00001800 /* Port Size 32 bit */
#define BR_DECC 0x00000600
#define BR_DECC_SHIFT 9
+#define BR_DECC_OFF 0x00000000
+#define BR_DECC_CHK 0x00000200
+#define BR_DECC_CHK_GEN 0x00000400
#define BR_WP 0x00000100
#define BR_WP_SHIFT 8
#define BR_MSEL 0x000000E0
#define BR_MSEL_SHIFT 5
#define BR_MS_GPCM 0x00000000 /* GPCM */
+#define BR_MS_FCM 0x00000020 /* FCM */
#define BR_MS_SDRAM 0x00000060 /* SDRAM */
#define BR_MS_UPMA 0x00000080 /* UPMA */
#define BR_MS_UPMB 0x000000A0 /* UPMB */
@@ -803,6 +922,34 @@
#define OR_GPCM_EAD 0x00000001
#define OR_GPCM_EAD_SHIFT 0
+#define OR_FCM_AM 0xFFFF8000
+#define OR_FCM_AM_SHIFT 15
+#define OR_FCM_BCTLD 0x00001000
+#define OR_FCM_BCTLD_SHIFT 12
+#define OR_FCM_PGS 0x00000400
+#define OR_FCM_PGS_SHIFT 10
+#define OR_FCM_CSCT 0x00000200
+#define OR_FCM_CSCT_SHIFT 9
+#define OR_FCM_CST 0x00000100
+#define OR_FCM_CST_SHIFT 8
+#define OR_FCM_CHT 0x00000080
+#define OR_FCM_CHT_SHIFT 7
+#define OR_FCM_SCY 0x00000070
+#define OR_FCM_SCY_SHIFT 4
+#define OR_FCM_SCY_1 0x00000010
+#define OR_FCM_SCY_2 0x00000020
+#define OR_FCM_SCY_3 0x00000030
+#define OR_FCM_SCY_4 0x00000040
+#define OR_FCM_SCY_5 0x00000050
+#define OR_FCM_SCY_6 0x00000060
+#define OR_FCM_SCY_7 0x00000070
+#define OR_FCM_RST 0x00000008
+#define OR_FCM_RST_SHIFT 3
+#define OR_FCM_TRLX 0x00000004
+#define OR_FCM_TRLX_SHIFT 2
+#define OR_FCM_EHTR 0x00000002
+#define OR_FCM_EHTR_SHIFT 1
+
#define OR_UPM_AM 0xFFFF8000
#define OR_UPM_AM_SHIFT 15
#define OR_UPM_XAM 0x00006000
@@ -1019,4 +1166,118 @@
#define PIWAR_IWS_1G 0x0000001D
#define PIWAR_IWS_2G 0x0000001E
+/* PMCCR1 - PCI Configuration Register 1
+ */
+#define PMCCR1_POWER_OFF 0x00000020
+
+/* FMR - Flash Mode Register
+ */
+#define FMR_CWTO 0x0000F000
+#define FMR_CWTO_SHIFT 12
+#define FMR_BOOT 0x00000800
+#define FMR_ECCM 0x00000100
+#define FMR_AL 0x00000030
+#define FMR_AL_SHIFT 4
+#define FMR_OP 0x00000003
+#define FMR_OP_SHIFT 0
+
+/* FIR - Flash Instruction Register
+ */
+#define FIR_OP0 0xF0000000
+#define FIR_OP0_SHIFT 28
+#define FIR_OP1 0x0F000000
+#define FIR_OP1_SHIFT 24
+#define FIR_OP2 0x00F00000
+#define FIR_OP2_SHIFT 20
+#define FIR_OP3 0x000F0000
+#define FIR_OP3_SHIFT 16
+#define FIR_OP4 0x0000F000
+#define FIR_OP4_SHIFT 12
+#define FIR_OP5 0x00000F00
+#define FIR_OP5_SHIFT 8
+#define FIR_OP6 0x000000F0
+#define FIR_OP6_SHIFT 4
+#define FIR_OP7 0x0000000F
+#define FIR_OP7_SHIFT 0
+#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
+#define FIR_OP_CA 0x1 /* Issue current column address */
+#define FIR_OP_PA 0x2 /* Issue current block+page address */
+#define FIR_OP_UA 0x3 /* Issue user defined address */
+#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
+#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
+#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
+#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
+#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
+#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
+#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
+#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
+#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
+#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
+#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
+#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */
+
+/* FCR - Flash Command Register
+ */
+#define FCR_CMD0 0xFF000000
+#define FCR_CMD0_SHIFT 24
+#define FCR_CMD1 0x00FF0000
+#define FCR_CMD1_SHIFT 16
+#define FCR_CMD2 0x0000FF00
+#define FCR_CMD2_SHIFT 8
+#define FCR_CMD3 0x000000FF
+#define FCR_CMD3_SHIFT 0
+
+/* FBAR - Flash Block Address Register
+ */
+#define FBAR_BLK 0x00FFFFFF
+
+/* FPAR - Flash Page Address Register
+ */
+#define FPAR_SP_PI 0x00007C00
+#define FPAR_SP_PI_SHIFT 10
+#define FPAR_SP_MS 0x00000200
+#define FPAR_SP_CI 0x000001FF
+#define FPAR_SP_CI_SHIFT 0
+#define FPAR_LP_PI 0x0003F000
+#define FPAR_LP_PI_SHIFT 12
+#define FPAR_LP_MS 0x00000800
+#define FPAR_LP_CI 0x000007FF
+#define FPAR_LP_CI_SHIFT 0
+
+/* LTESR - Transfer Error Status Register
+ */
+#define LTESR_BM 0x80000000
+#define LTESR_FCT 0x40000000
+#define LTESR_PAR 0x20000000
+#define LTESR_WP 0x04000000
+#define LTESR_ATMW 0x00800000
+#define LTESR_ATMR 0x00400000
+#define LTESR_CS 0x00080000
+#define LTESR_CC 0x00000001
+
+/* DDR Control Driver Register
+ */
+#define DDRCDR_EN 0x40000000
+#define DDRCDR_PZ 0x3C000000
+#define DDRCDR_PZ_MAXZ 0x00000000
+#define DDRCDR_PZ_HIZ 0x20000000
+#define DDRCDR_PZ_NOMZ 0x30000000
+#define DDRCDR_PZ_LOZ 0x38000000
+#define DDRCDR_PZ_MINZ 0x3C000000
+#define DDRCDR_NZ 0x3C000000
+#define DDRCDR_NZ_MAXZ 0x00000000
+#define DDRCDR_NZ_HIZ 0x02000000
+#define DDRCDR_NZ_NOMZ 0x03000000
+#define DDRCDR_NZ_LOZ 0x03800000
+#define DDRCDR_NZ_MINZ 0x03C00000
+#define DDRCDR_ODT 0x00080000
+#define DDRCDR_DDR_CFG 0x00040000
+#define DDRCDR_M_ODR 0x00000002
+#define DDRCDR_Q_DRN 0x00000001
+
+#ifndef __ASSEMBLY__
+struct pci_region;
+void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot);
+#endif
+
#endif /* __MPC83XX_H__ */
diff --git a/include/mpc85xx.h b/include/mpc85xx.h
index a4d99b2..321b24f 100644
--- a/include/mpc85xx.h
+++ b/include/mpc85xx.h
@@ -1,13 +1,14 @@
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
* Copyright(c) 2003 Motorola Inc.
- * Xianghua Xiao (x.xiao@motorola.com)
*/
#ifndef __MPC85xx_H__
#define __MPC85xx_H__
-#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
+/* define for common ppc_asm.tmpl */
+#define EXC_OFF_SYS_RESET 0x100 /* System reset */
+#define _START_OFFSET 0
#if defined(CONFIG_E500)
#include <e500.h>
diff --git a/include/mpc86xx.h b/include/mpc86xx.h
index 673bfed..9fd349a 100644
--- a/include/mpc86xx.h
+++ b/include/mpc86xx.h
@@ -8,7 +8,7 @@
#define __MPC86xx_H__
#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */
-
+#define _START_OFFSET EXC_OFF_SYS_RESET
/*
* platform register addresses
diff --git a/include/mpc8xx.h b/include/mpc8xx.h
index 2911758..bef748f 100644
--- a/include/mpc8xx.h
+++ b/include/mpc8xx.h
@@ -35,7 +35,7 @@
* Exception offsets (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
-
+#define _START_OFFSET EXC_OFF_SYS_RESET
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control Register 11-9
@@ -208,12 +208,12 @@
#define SCCR_DFBRG10 0x00001000 /* BRGCLK division by 16 */
#define SCCR_DFBRG11 0x00001800 /* BRGCLK division by 64 */
#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */
-#define SCCR_DFNL001 0x00000100 /* Division by 4 */
-#define SCCR_DFNL010 0x00000200 /* Division by 8 */
-#define SCCR_DFNL011 0x00000300 /* Division by 16 */
-#define SCCR_DFNL100 0x00000400 /* Division by 32 */
-#define SCCR_DFNL101 0x00000500 /* Division by 64 */
-#define SCCR_DFNL110 0x00000600 /* Division by 128 */
+#define SCCR_DFNL001 0x00000100 /* Division by 4 */
+#define SCCR_DFNL010 0x00000200 /* Division by 8 */
+#define SCCR_DFNL011 0x00000300 /* Division by 16 */
+#define SCCR_DFNL100 0x00000400 /* Division by 32 */
+#define SCCR_DFNL101 0x00000500 /* Division by 64 */
+#define SCCR_DFNL110 0x00000600 /* Division by 128 */
#define SCCR_DFNL111 0x00000700 /* Division by 256 (maximum) */
#define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */
#define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */
diff --git a/include/nand.h b/include/nand.h
index 23493f7..3c0752e 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -32,6 +32,7 @@ typedef struct mtd_info nand_info_t;
extern int nand_curr_device;
extern nand_info_t nand_info[];
+extern void nand_init(void);
static inline int nand_read(nand_info_t *info, ulong ofs, ulong *len, u_char *buf)
{
diff --git a/include/net.h b/include/net.h
index 461e038..603452a 100644
--- a/include/net.h
+++ b/include/net.h
@@ -99,10 +99,12 @@ struct eth_device {
int state;
int (*init) (struct eth_device*, bd_t*);
- int (*send) (struct eth_device*, volatile void* pachet, int length);
+ int (*send) (struct eth_device*, volatile void* packet, int length);
int (*recv) (struct eth_device*);
void (*halt) (struct eth_device*);
-
+#ifdef CONFIG_MCAST_TFTP
+ int (*mcast) (struct eth_device*, u32 ip, u8 set);
+#endif
struct eth_device *next;
void *priv;
};
@@ -124,6 +126,11 @@ extern int eth_rx(void); /* Check for received packets */
extern void eth_halt(void); /* stop SCC */
extern char *eth_get_name(void); /* get name of current device */
+#ifdef CONFIG_MCAST_TFTP
+int eth_mcast_join( IPaddr_t mcast_addr, u8 join);
+u32 ether_crc (size_t len, unsigned char const *p);
+#endif
+
/**********************************************************************/
/*
@@ -296,7 +303,7 @@ typedef struct icmphdr {
extern IPaddr_t NetOurGatewayIP; /* Our gateway IP addresse */
extern IPaddr_t NetOurSubnetMask; /* Our subnet mask (0 = unknown)*/
extern IPaddr_t NetOurDNSIP; /* Our Domain Name Server (0 = unknown)*/
-#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2)
+#if defined(CONFIG_BOOTP_DNS2)
extern IPaddr_t NetOurDNS2IP; /* Our 2nd Domain Name Server (0 = unknown)*/
#endif
extern char NetOurNISDomain[32]; /* Our NIS domain */
@@ -341,17 +348,17 @@ typedef enum { BOOTP, RARP, ARP, TFTP, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP
/* from net/net.c */
extern char BootFile[128]; /* Boot File name */
-#if (CONFIG_COMMANDS & CFG_CMD_PING)
+#if defined(CONFIG_CMD_PING)
extern IPaddr_t NetPingIP; /* the ip address to ping */
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_CDP)
+#if defined(CONFIG_CMD_CDP)
/* when CDP completes these hold the return values */
extern ushort CDPNativeVLAN;
extern ushort CDPApplianceVLAN;
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_SNTP)
+#if defined(CONFIG_CMD_SNTP)
extern IPaddr_t NetNtpServerIP; /* the ip address to NTP */
extern int NetTimeOffset; /* offset time from UTC */
#endif
@@ -435,6 +442,29 @@ static inline void NetCopyLong(ulong *to, ulong *from)
memcpy((void*)to, (void*)from, sizeof(ulong));
}
+/**
+ * is_zero_ether_addr - Determine if give Ethernet address is all zeros.
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is all zeroes.
+ */
+static inline int is_zero_ether_addr(const u8 *addr)
+{
+ return !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]);
+}
+
+/**
+ * is_multicast_ether_addr - Determine if the Ethernet address is a multicast.
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is a multicast address.
+ * By definition the broadcast address is also a multicast address.
+ */
+static inline int is_multicast_ether_addr(const u8 *addr)
+{
+ return (0x01 & addr[0]);
+}
+
/* Convert an IP address to a string */
extern void ip_to_string (IPaddr_t x, char *s);
diff --git a/include/pci.h b/include/pci.h
index 7c9a0e3..8e5dacc 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -302,6 +302,12 @@
#define PCI_MAX_PCI_DEVICES 32
#define PCI_MAX_PCI_FUNCTIONS 8
+#define PCI_DCR 0x54 /* PCIe Device Control Register */
+#define PCI_DSR 0x56 /* PCIe Device Status Register */
+#define PCI_LSR 0x5e /* PCIe Link Status Register */
+#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
+#define PCI_LTSSM_L0 0x16 /* L0 state */
+
/* Include the ID list */
#include <pci_ids.h>
diff --git a/include/pcmcia.h b/include/pcmcia.h
index 8f564da..7305805 100644
--- a/include/pcmcia.h
+++ b/include/pcmcia.h
@@ -31,8 +31,8 @@
* Allow configuration to select PCMCIA slot,
* or try to generate a useful default
*/
-#if ( CONFIG_COMMANDS & CFG_CMD_PCMCIA) || \
- ((CONFIG_COMMANDS & CFG_CMD_IDE) && \
+#if defined(CONFIG_CMD_PCMCIA) || \
+ (defined(CONFIG_CMD_IDE) && \
(defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) )
#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
@@ -306,14 +306,14 @@ typedef struct {
#define CISTPL_IDE_HAS_INDEX 0x20
#define CISTPL_IDE_IOIS16 0x40
-#endif /* CFG_CMD_PCMCIA || CFG_CMD_IDE && (CONFIG_IDE_8xx_PCCARD || CONFIG_IDE_8xx_DIRECT) */
+#endif
#ifdef CONFIG_8xx
extern u_int *pcmcia_pgcrx[];
#define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot])
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) \
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) \
|| defined(CONFIG_PXA_PCMCIA)
extern int check_ide_device(int slot);
#endif
diff --git a/include/post.h b/include/post.h
index cdefbdd..c8062bb 100644
--- a/include/post.h
+++ b/include/post.h
@@ -91,6 +91,8 @@ extern int post_hotkeys_pressed(void);
#define CFG_POST_SYSMON 0x00000800
#define CFG_POST_DSP 0x00001000
#define CFG_POST_CODEC 0x00002000
+#define CFG_POST_FPU 0x00004000
+#define CFG_POST_ECC 0x00008000
#endif /* CONFIG_POST */
diff --git a/include/ppc405.h b/include/ppc405.h
index a2503a9..0c7bf3e 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -27,6 +27,15 @@
/*--------------------------------------------------------------------- */
#define srr2 0x3de /* save/restore register 2 */
#define srr3 0x3df /* save/restore register 3 */
+
+ /*
+ * 405 does not really have CSRR0/1 but SRR2/3 are used during critical
+ * exception for the exact same purposes - let's alias them and have a
+ * common handling in crit_return() and CRIT_EXCEPTION
+ */
+ #define csrr0 srr2
+ #define csrr1 srr3
+
#define dbsr 0x3f0 /* debug status register */
#define dbcr0 0x3f2 /* debug control register 0 */
#define dbcr1 0x3bd /* debug control register 1 */
@@ -134,12 +143,12 @@
#define UIC_USBH1 0x00040000 /* USB Host 1 */
#define UIC_USBH2 0x00020000 /* USB Host 2 */
#define UIC_USBDEV 0x00010000 /* USB Device */
-#define UIC_ENET 0x00008000 /* Ethernet interrupt status */
-#define UIC_ENET1 0x00008000 /* dummy define */
+#define UIC_ENET 0x00008000 /* Ethernet interrupt status */
+#define UIC_ENET1 0x00008000 /* dummy define */
#define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */
#define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */
-#define UIC_MAL_SERR 0x00002000 /* MAL SERR */
+#define UIC_MAL_SERR 0x00002000 /* MAL SERR */
#define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */
#define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */
@@ -532,6 +541,18 @@
#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_3)
+#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_1)
+#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
/*
* PLL Voltage Controlled Oscillator (VCO) definitions
@@ -547,8 +568,8 @@
#define sdrcfga (SDR_DCR_BASE+0x0) /* ADDR */
#define sdrcfgd (SDR_DCR_BASE+0x1) /* Data */
-#define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data)
-#define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd)
+#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0)
+#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0)
#define sdrnand0 0x4000
#define sdrultra0 0x4040
@@ -556,6 +577,11 @@
#define sdricintstat 0x4510
#define SDR_NAND0_NDEN 0x80000000
+#define SDR_NAND0_NDBTEN 0x40000000
+#define SDR_NAND0_NDBADR_MASK 0x30000000
+#define SDR_NAND0_NDBPG_MASK 0x0f000000
+#define SDR_NAND0_NDAREN 0x00800000
+#define SDR_NAND0_NDRBEN 0x00400000
#define SDR_ULTRA0_NDGPIOBP 0x80000000
#define SDR_ULTRA0_CSN_MASK 0x78000000
@@ -563,6 +589,9 @@
#define SDR_ULTRA0_CSNSEL1 0x20000000
#define SDR_ULTRA0_CSNSEL2 0x10000000
#define SDR_ULTRA0_CSNSEL3 0x08000000
+#define SDR_ULTRA0_EBCRDYEN 0x04000000
+#define SDR_ULTRA0_SPISSINEN 0x02000000
+#define SDR_ULTRA0_NFSRSTEN 0x01000000
#define SDR_ULTRA1_LEDNENABLE 0x40000000
@@ -593,13 +622,15 @@
/*
* Macro for accessing the indirect CPR register
*/
-#define mtcpr(reg, data) mtdcr(cprcfga,reg);mtdcr(cprcfgd,data)
-#define mfcpr(reg, data) mtdcr(cprcfga,reg);data = mfdcr(cprcfgd)
+#define mtcpr(reg, data) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,data); } while (0)
+#define mfcpr(reg, data) do { mtdcr(cprcfga,reg);data = mfdcr(cprcfgd); } while (0)
#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
+#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
+
#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
@@ -869,7 +900,7 @@
#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
#define reset (CNTRL_DCR_BASE+0x3) /* reset register */
-#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
+#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
#define ecr (0xaa) /* edge conditioner register (405gpr) */
@@ -1102,13 +1133,13 @@
| UART Register Offsets
'----------------------------------------------------------------------------*/
#define DATA_REG 0x00
-#define DL_LSB 0x00
-#define DL_MSB 0x01
+#define DL_LSB 0x00
+#define DL_MSB 0x01
#define INT_ENABLE 0x01
#define FIFO_CONTROL 0x02
#define LINE_CONTROL 0x03
#define MODEM_CONTROL 0x04
-#define LINE_STATUS 0x05
+#define LINE_STATUS 0x05
#define MODEM_STATUS 0x06
#define SCRATCH 0x07
@@ -1209,6 +1240,8 @@
#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
+#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0)
+#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0)
#ifndef __ASSEMBLY__
diff --git a/include/ppc440.h b/include/ppc440.h
index bc1d7aa..38809f3 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -82,10 +82,7 @@
#define ivor13 0x19d /* interrupt vector offset register 13 */
#define ivor14 0x19e /* interrupt vector offset register 14 */
#define ivor15 0x19f /* interrupt vector offset register 15 */
-#if defined(CONFIG_440GX) || \
- defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440)
#define mcsrr0 0x23a /* machine check save/restore register 0 */
#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
#define mcsr 0x23c /* machine check status register */
@@ -115,7 +112,7 @@
#define icdbtrh 0x39f /* instruction cache debug tag register high */
#define mmucr 0x3b2 /* mmu control register */
#define ccr0 0x3b3 /* core configuration register 0 */
-#define ccr1 0x378 /* core configuration for 440x5 only */
+#define ccr1 0x378 /* core configuration for 440x5 only */
#define icdbdr 0x3d3 /* instruction cache debug data register */
#define dbdr 0x3f3 /* debug data register */
@@ -139,7 +136,7 @@
#define clk_opbd 0x00c0
#define clk_perd 0x00e0
#define clk_mald 0x0100
-#define clk_spcid 0x0120
+#define clk_spcid 0x0120
#define clk_icfg 0x0140
/* 440gx sdr register definations */
@@ -285,6 +282,30 @@
#define sdr_sdstp3 0x4003
#endif /* CONFIG_440GX */
+/*----------------------------------------------------------------------------+
+| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
++----------------------------------------------------------------------------*/
+#define CCR0_PRE 0x40000000
+#define CCR0_CRPE 0x08000000
+#define CCR0_DSTG 0x00200000
+#define CCR0_DAPUIB 0x00100000
+#define CCR0_DTB 0x00008000
+#define CCR0_GICBT 0x00004000
+#define CCR0_GDCBT 0x00002000
+#define CCR0_FLSTA 0x00000100
+#define CCR0_ICSLC_MASK 0x0000000C
+#define CCR0_ICSLT_MASK 0x00000003
+#define CCR1_TCS_MASK 0x00000080
+#define CCR1_TCS_INTCLK 0x00000000
+#define CCR1_TCS_EXTCLK 0x00000080
+#define MMUCR_SWOA 0x01000000
+#define MMUCR_U1TE 0x00400000
+#define MMUCR_U2SWOAE 0x00200000
+#define MMUCR_DULXE 0x00800000
+#define MMUCR_IULXE 0x00400000
+#define MMUCR_STS 0x00100000
+#define MMUCR_STID_MASK 0x000000FF
+
#ifdef CONFIG_440SPE
#undef sdr_sdstp2
#define sdr_sdstp2 0x0022
@@ -310,30 +331,6 @@
#define sdr_sdstp6 0x4005
#define sdr_sdstp7 0x4007
-/*----------------------------------------------------------------------------+
-| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
-+----------------------------------------------------------------------------*/
-#define CCR0_PRE 0x40000000
-#define CCR0_CRPE 0x08000000
-#define CCR0_DSTG 0x00200000
-#define CCR0_DAPUIB 0x00100000
-#define CCR0_DTB 0x00008000
-#define CCR0_GICBT 0x00004000
-#define CCR0_GDCBT 0x00002000
-#define CCR0_FLSTA 0x00000100
-#define CCR0_ICSLC_MASK 0x0000000C
-#define CCR0_ICSLT_MASK 0x00000003
-#define CCR1_TCS_MASK 0x00000080
-#define CCR1_TCS_INTCLK 0x00000000
-#define CCR1_TCS_EXTCLK 0x00000080
-#define MMUCR_SEOA 0x01000000
-#define MMUCR_U1TE 0x00400000
-#define MMUCR_U2SWOAE 0x00200000
-#define MMUCR_DULXE 0x00800000
-#define MMUCR_IULXE 0x00400000
-#define MMUCR_STS 0x00100000
-#define MMUCR_STID_MASK 0x000000FF
-
#define SDR0_CFGADDR 0x00E
#define SDR0_CFGDATA 0x00F
@@ -687,8 +684,8 @@
#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
-#define SDRAM_CODT_IO_HIZ 0x00000000
-#define SDRAM_CODT_IO_NMODE 0x00000001
+#define SDRAM_CODT_IO_HIZ 0x00000000
+#define SDRAM_CODT_IO_NMODE 0x00000001
/*-----------------------------------------------------------------------------+
| SDRAM Mode Register
@@ -956,7 +953,8 @@
#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* Pin Function Control Register 1 */
#define SDR0_PFC1 0x4101
#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
@@ -1025,7 +1023,7 @@
#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define SDR_USB2D0CR 0x0320
+#define SDR0_USB2D0CR 0x0320
#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */
#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */
#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
@@ -1103,6 +1101,8 @@
#define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */
#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */
+#define SDR0_PFC4 0x4104
+
/* USB2PHY0 Control Register */
#define SDR0_USB2PHY0CR 0x4103
#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */
@@ -1421,13 +1421,10 @@
#define uicvr uic0vr
#define uicvcr uic0vcr
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX)
/*----------------------------------------------------------------------------+
| Clock / Power-on-reset DCR's.
+----------------------------------------------------------------------------*/
-#define CPR0_CFGADDR 0x00C
-#define CPR0_CFGDATA 0x00D
-
#define CPR0_CLKUPD 0x20
#define CPR0_CLKUPD_BSY_MASK 0x80000000
#define CPR0_CLKUPD_BSY_COMPLETED 0x00000000
@@ -1493,9 +1490,11 @@
#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
#define CPR0_PERD 0xE0
+#if !defined(CONFIG_440EPX)
#define CPR0_PERD_PERDV0_MASK 0x03000000
#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+#endif
#define CPR0_MALD 0x100
#define CPR0_MALD_MALDV0_MASK 0x03000000
@@ -3314,6 +3313,23 @@
#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0)
#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0)
+/*
+ * All 44x except 440GP have CPR registers (indirect DCR)
+ */
+#if !defined(CONFIG_440GP)
+#define CPR0_CFGADDR 0x00C
+#define CPR0_CFGDATA 0x00D
+
+#define mtcpr(reg, data) do { \
+ mtdcr(CPR0_CFGADDR, reg); \
+ mtdcr(CPR0_CFGDATA, data); \
+ } while (0)
+
+#define mfcpr(reg, data) do { \
+ mtdcr(CPR0_CFGADDR, reg); \
+ data = mfdcr(CPR0_CFGDATA); \
+ } while (0)
+#endif
#ifndef __ASSEMBLY__
@@ -3338,6 +3354,19 @@ typedef struct {
unsigned long pciClkSync; /* PCI clock is synchronous */
} PPC440_SYS_INFO;
+static inline u32 get_mcsr(void)
+{
+ u32 val;
+
+ asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
+ return val;
+}
+
+static inline void set_mcsr(u32 val)
+{
+ asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
+}
+
#endif /* _ASMLANGUAGE */
#define RESET_VECTOR 0xfffffffc
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index 67759c7..ca241d2 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -22,6 +22,8 @@
#ifndef __PPC4XX_H__
#define __PPC4XX_H__
+#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
+#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
#if defined(CONFIG_440)
#include <ppc440.h>
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index 3e47e82..0019d46 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -113,11 +113,11 @@
#if defined(CONFIG_5xx)
/* Some special purpose registers */
-#define DER 149 /* Debug Enable Register */
-#define COUNTA 150 /* Breakpoint Counter */
-#define COUNTB 151 /* Breakpoint Counter */
-#define LCTRL1 156 /* Load/Store Support */
-#define LCTRL2 157 /* Load/Store Support */
+#define DER 149 /* Debug Enable Register */
+#define COUNTA 150 /* Breakpoint Counter */
+#define COUNTB 151 /* Breakpoint Counter */
+#define LCTRL1 156 /* Load/Store Support */
+#define LCTRL2 157 /* Load/Store Support */
#define ICTRL 158 /* I-Bus Support Control Register */
#define EID 81
#endif /* CONFIG_5xx */
@@ -217,7 +217,7 @@
* We assume sprg3 has the physical address of the current
* task's thread_struct.
*/
-#define EXCEPTION_PROLOG \
+#define EXCEPTION_PROLOG(reg1, reg2) \
mtspr SPRG0,r20; \
mtspr SPRG1,r21; \
mfcr r20; \
@@ -235,8 +235,10 @@
stw r22,_CTR(r21); \
mfspr r20,XER; \
stw r20,_XER(r21); \
- mfspr r22,SRR0; \
- mfspr r23,SRR1; \
+ mfspr r20, DAR_DEAR; \
+ stw r20,_DAR(r21); \
+ mfspr r22,reg1; \
+ mfspr r23,reg2; \
stw r0,GPR0(r21); \
stw r1,GPR1(r21); \
stw r2,GPR2(r21); \
@@ -249,41 +251,6 @@
*/
/*
- * Critical exception entry code. This is just like the other exception
- * code except that it uses SRR2 and SRR3 instead of SRR0 and SRR1.
- */
-#define CRITICAL_EXCEPTION_PROLOG \
- mtspr SPRG0,r20; \
- mtspr SPRG1,r21; \
- mfcr r20; \
- subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\
- stw r20,_CCR(r21); /* save registers */ \
- stw r22,GPR22(r21); \
- stw r23,GPR23(r21); \
- mfspr r20,SPRG0; \
- stw r20,GPR20(r21); \
- mfspr r22,SPRG1; \
- stw r22,GPR21(r21); \
- mflr r20; \
- stw r20,_LINK(r21); \
- mfctr r22; \
- stw r22,_CTR(r21); \
- mfspr r20,XER; \
- stw r20,_XER(r21); \
- mfspr r22,990; /* SRR2 */ \
- mfspr r23,991; /* SRR3 */ \
- stw r0,GPR0(r21); \
- stw r1,GPR1(r21); \
- stw r2,GPR2(r21); \
- stw r1,0(r21); \
- mr r1,r21; /* set new kernel sp */ \
- SAVE_4GPRS(3, r21);
-/*
- * Note: code which follows this uses cr0.eq (set if from kernel),
- * r21, r22 (SRR2), and r23 (SRR3).
- */
-
-/*
* Exception vectors.
*
* The data words for `hdlr' and `int_return' are initialized with
@@ -293,30 +260,43 @@
#define STD_EXCEPTION(n, label, hdlr) \
. = n; \
label: \
- EXCEPTION_PROLOG; \
+ EXCEPTION_PROLOG(SRR0, SRR1); \
lwz r3,GOT(transfer_to_handler); \
mtlr r3; \
addi r3,r1,STACK_FRAME_OVERHEAD; \
li r20,MSR_KERNEL; \
rlwimi r20,r23,0,25,25; \
- blrl ; \
+ blrl; \
.L_ ## label : \
- .long hdlr - _start + EXC_OFF_SYS_RESET; \
- .long int_return - _start + EXC_OFF_SYS_RESET
-
-
-#define CRIT_EXCEPTION(n, label, hdlr) \
- . = n; \
-label: \
- CRITICAL_EXCEPTION_PROLOG; \
- lwz r3,GOT(transfer_to_handler); \
- mtlr r3; \
- addi r3,r1,STACK_FRAME_OVERHEAD; \
- li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
- rlwimi r20,r23,0,25,25; \
- blrl ; \
-.L_ ## label : \
- .long hdlr - _start + EXC_OFF_SYS_RESET; \
- .long crit_return - _start + EXC_OFF_SYS_RESET
+ .long hdlr - _start + _START_OFFSET; \
+ .long int_return - _start + _START_OFFSET
+
+#define CRIT_EXCEPTION(n, label, hdlr) \
+ . = n; \
+label: \
+ EXCEPTION_PROLOG(CSRR0, CSRR1); \
+ lwz r3,GOT(transfer_to_handler); \
+ mtlr r3; \
+ addi r3,r1,STACK_FRAME_OVERHEAD; \
+ li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
+ rlwimi r20,r23,0,25,25; \
+ blrl; \
+.L_ ## label : \
+ .long hdlr - _start + _START_OFFSET; \
+ .long crit_return - _start + _START_OFFSET
+
+#define MCK_EXCEPTION(n, label, hdlr) \
+ . = n; \
+label: \
+ EXCEPTION_PROLOG(MCSRR0, MCSRR1); \
+ lwz r3,GOT(transfer_to_handler); \
+ mtlr r3; \
+ addi r3,r1,STACK_FRAME_OVERHEAD; \
+ li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
+ rlwimi r20,r23,0,25,25; \
+ blrl; \
+.L_ ## label : \
+ .long hdlr - _start + _START_OFFSET; \
+ .long mck_return - _start + _START_OFFSET
#endif /* __PPC_ASM_TMPL__ */
diff --git a/include/radeon.h b/include/radeon.h
new file mode 100644
index 0000000..3d11b05
--- /dev/null
+++ b/include/radeon.h
@@ -0,0 +1,1984 @@
+#ifndef _RADEON_H
+#define _RADEON_H
+
+
+#define RADEON_REGSIZE 0x4000
+
+
+#define MM_INDEX 0x0000
+#define MM_DATA 0x0004
+#define BUS_CNTL 0x0030
+#define HI_STAT 0x004C
+#define BUS_CNTL1 0x0034
+#define I2C_CNTL_1 0x0094
+#define CONFIG_CNTL 0x00E0
+#define CONFIG_MEMSIZE 0x00F8
+#define CONFIG_APER_0_BASE 0x0100
+#define CONFIG_APER_1_BASE 0x0104
+#define CONFIG_APER_SIZE 0x0108
+#define CONFIG_REG_1_BASE 0x010C
+#define CONFIG_REG_APER_SIZE 0x0110
+#define PAD_AGPINPUT_DELAY 0x0164
+#define PAD_CTLR_STRENGTH 0x0168
+#define PAD_CTLR_UPDATE 0x016C
+#define PAD_CTLR_MISC 0x0aa0
+#define AGP_CNTL 0x0174
+#define BM_STATUS 0x0160
+#define CAP0_TRIG_CNTL 0x0950
+#define CAP1_TRIG_CNTL 0x09c0
+#define VIPH_CONTROL 0x0C40
+#define VENDOR_ID 0x0F00
+#define DEVICE_ID 0x0F02
+#define COMMAND 0x0F04
+#define STATUS 0x0F06
+#define REVISION_ID 0x0F08
+#define REGPROG_INF 0x0F09
+#define SUB_CLASS 0x0F0A
+#define BASE_CODE 0x0F0B
+#define CACHE_LINE 0x0F0C
+#define LATENCY 0x0F0D
+#define HEADER 0x0F0E
+#define BIST 0x0F0F
+#define REG_MEM_BASE 0x0F10
+#define REG_IO_BASE 0x0F14
+#define REG_REG_BASE 0x0F18
+#define ADAPTER_ID 0x0F2C
+#define BIOS_ROM 0x0F30
+#define CAPABILITIES_PTR 0x0F34
+#define INTERRUPT_LINE 0x0F3C
+#define INTERRUPT_PIN 0x0F3D
+#define MIN_GRANT 0x0F3E
+#define MAX_LATENCY 0x0F3F
+#define ADAPTER_ID_W 0x0F4C
+#define PMI_CAP_ID 0x0F50
+#define PMI_NXT_CAP_PTR 0x0F51
+#define PMI_PMC_REG 0x0F52
+#define PM_STATUS 0x0F54
+#define PMI_DATA 0x0F57
+#define AGP_CAP_ID 0x0F58
+#define AGP_STATUS 0x0F5C
+#define AGP_COMMAND 0x0F60
+#define AIC_CTRL 0x01D0
+#define AIC_STAT 0x01D4
+#define AIC_PT_BASE 0x01D8
+#define AIC_LO_ADDR 0x01DC
+#define AIC_HI_ADDR 0x01E0
+#define AIC_TLB_ADDR 0x01E4
+#define AIC_TLB_DATA 0x01E8
+#define DAC_CNTL 0x0058
+#define DAC_CNTL2 0x007c
+#define CRTC_GEN_CNTL 0x0050
+#define MEM_CNTL 0x0140
+#define MC_CNTL 0x0140
+#define EXT_MEM_CNTL 0x0144
+#define MC_TIMING_CNTL 0x0144
+#define MC_AGP_LOCATION 0x014C
+#define MEM_IO_CNTL_A0 0x0178
+#define MEM_REFRESH_CNTL 0x0178
+#define MEM_INIT_LATENCY_TIMER 0x0154
+#define MC_INIT_GFX_LAT_TIMER 0x0154
+#define MEM_SDRAM_MODE_REG 0x0158
+#define AGP_BASE 0x0170
+#define MEM_IO_CNTL_A1 0x017C
+#define MC_READ_CNTL_AB 0x017C
+#define MEM_IO_CNTL_B0 0x0180
+#define MC_INIT_MISC_LAT_TIMER 0x0180
+#define MEM_IO_CNTL_B1 0x0184
+#define MC_IOPAD_CNTL 0x0184
+#define MC_DEBUG 0x0188
+#define MC_STATUS 0x0150
+#define MEM_IO_OE_CNTL 0x018C
+#define MC_CHIP_IO_OE_CNTL_AB 0x018C
+#define MC_FB_LOCATION 0x0148
+/* #define MC_FB_LOCATION 0x0188 */
+#define HOST_PATH_CNTL 0x0130
+#define MEM_VGA_WP_SEL 0x0038
+#define MEM_VGA_RP_SEL 0x003C
+#define HDP_DEBUG 0x0138
+#define SW_SEMAPHORE 0x013C
+#define CRTC2_GEN_CNTL 0x03f8
+#define CRTC2_DISPLAY_BASE_ADDR 0x033c
+#define SURFACE_CNTL 0x0B00
+#define SURFACE0_LOWER_BOUND 0x0B04
+#define SURFACE1_LOWER_BOUND 0x0B14
+#define SURFACE2_LOWER_BOUND 0x0B24
+#define SURFACE3_LOWER_BOUND 0x0B34
+#define SURFACE4_LOWER_BOUND 0x0B44
+#define SURFACE5_LOWER_BOUND 0x0B54
+#define SURFACE6_LOWER_BOUND 0x0B64
+#define SURFACE7_LOWER_BOUND 0x0B74
+#define SURFACE0_UPPER_BOUND 0x0B08
+#define SURFACE1_UPPER_BOUND 0x0B18
+#define SURFACE2_UPPER_BOUND 0x0B28
+#define SURFACE3_UPPER_BOUND 0x0B38
+#define SURFACE4_UPPER_BOUND 0x0B48
+#define SURFACE5_UPPER_BOUND 0x0B58
+#define SURFACE6_UPPER_BOUND 0x0B68
+#define SURFACE7_UPPER_BOUND 0x0B78
+#define SURFACE0_INFO 0x0B0C
+#define SURFACE1_INFO 0x0B1C
+#define SURFACE2_INFO 0x0B2C
+#define SURFACE3_INFO 0x0B3C
+#define SURFACE4_INFO 0x0B4C
+#define SURFACE5_INFO 0x0B5C
+#define SURFACE6_INFO 0x0B6C
+#define SURFACE7_INFO 0x0B7C
+#define SURFACE_ACCESS_FLAGS 0x0BF8
+#define SURFACE_ACCESS_CLR 0x0BFC
+#define GEN_INT_CNTL 0x0040
+#define GEN_INT_STATUS 0x0044
+#define CRTC_EXT_CNTL 0x0054
+#define RB3D_CNTL 0x1C3C
+#define WAIT_UNTIL 0x1720
+#define ISYNC_CNTL 0x1724
+#define RBBM_GUICNTL 0x172C
+#define RBBM_STATUS 0x0E40
+#define RBBM_STATUS_alt_1 0x1740
+#define RBBM_CNTL 0x00EC
+#define RBBM_CNTL_alt_1 0x0E44
+#define RBBM_SOFT_RESET 0x00F0
+#define RBBM_SOFT_RESET_alt_1 0x0E48
+#define NQWAIT_UNTIL 0x0E50
+#define RBBM_DEBUG 0x0E6C
+#define RBBM_CMDFIFO_ADDR 0x0E70
+#define RBBM_CMDFIFO_DATAL 0x0E74
+#define RBBM_CMDFIFO_DATAH 0x0E78
+#define RBBM_CMDFIFO_STAT 0x0E7C
+#define CRTC_STATUS 0x005C
+#define GPIO_VGA_DDC 0x0060
+#define GPIO_DVI_DDC 0x0064
+#define GPIO_MONID 0x0068
+#define GPIO_CRT2_DDC 0x006c
+#define PALETTE_INDEX 0x00B0
+#define PALETTE_DATA 0x00B4
+#define PALETTE_30_DATA 0x00B8
+#define CRTC_H_TOTAL_DISP 0x0200
+#define CRTC_H_SYNC_STRT_WID 0x0204
+#define CRTC_V_TOTAL_DISP 0x0208
+#define CRTC_V_SYNC_STRT_WID 0x020C
+#define CRTC_VLINE_CRNT_VLINE 0x0210
+#define CRTC_CRNT_FRAME 0x0214
+#define CRTC_GUI_TRIG_VLINE 0x0218
+#define CRTC_DEBUG 0x021C
+#define CRTC_OFFSET_RIGHT 0x0220
+#define CRTC_OFFSET 0x0224
+#define CRTC_OFFSET_CNTL 0x0228
+#define CRTC_PITCH 0x022C
+#define OVR_CLR 0x0230
+#define OVR_WID_LEFT_RIGHT 0x0234
+#define OVR_WID_TOP_BOTTOM 0x0238
+#define DISPLAY_BASE_ADDR 0x023C
+#define SNAPSHOT_VH_COUNTS 0x0240
+#define SNAPSHOT_F_COUNT 0x0244
+#define N_VIF_COUNT 0x0248
+#define SNAPSHOT_VIF_COUNT 0x024C
+#define FP_CRTC_H_TOTAL_DISP 0x0250
+#define FP_CRTC_V_TOTAL_DISP 0x0254
+#define CRT_CRTC_H_SYNC_STRT_WID 0x0258
+#define CRT_CRTC_V_SYNC_STRT_WID 0x025C
+#define CUR_OFFSET 0x0260
+#define CUR_HORZ_VERT_POSN 0x0264
+#define CUR_HORZ_VERT_OFF 0x0268
+#define CUR_CLR0 0x026C
+#define CUR_CLR1 0x0270
+#define FP_HORZ_VERT_ACTIVE 0x0278
+#define CRTC_MORE_CNTL 0x027C
+#define CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
+#define CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
+#define DAC_EXT_CNTL 0x0280
+#define FP_GEN_CNTL 0x0284
+#define FP_HORZ_STRETCH 0x028C
+#define FP_VERT_STRETCH 0x0290
+#define FP_H_SYNC_STRT_WID 0x02C4
+#define FP_V_SYNC_STRT_WID 0x02C8
+#define AUX_WINDOW_HORZ_CNTL 0x02D8
+#define AUX_WINDOW_VERT_CNTL 0x02DC
+/* #define DDA_CONFIG 0x02e0 */
+/* #define DDA_ON_OFF 0x02e4 */
+#define DVI_I2C_CNTL_1 0x02e4
+#define GRPH_BUFFER_CNTL 0x02F0
+#define GRPH2_BUFFER_CNTL 0x03F0
+#define VGA_BUFFER_CNTL 0x02F4
+#define OV0_Y_X_START 0x0400
+#define OV0_Y_X_END 0x0404
+#define OV0_PIPELINE_CNTL 0x0408
+#define OV0_REG_LOAD_CNTL 0x0410
+#define OV0_SCALE_CNTL 0x0420
+#define OV0_V_INC 0x0424
+#define OV0_P1_V_ACCUM_INIT 0x0428
+#define OV0_P23_V_ACCUM_INIT 0x042C
+#define OV0_P1_BLANK_LINES_AT_TOP 0x0430
+#define OV0_P23_BLANK_LINES_AT_TOP 0x0434
+#define OV0_BASE_ADDR 0x043C
+#define OV0_VID_BUF0_BASE_ADRS 0x0440
+#define OV0_VID_BUF1_BASE_ADRS 0x0444
+#define OV0_VID_BUF2_BASE_ADRS 0x0448
+#define OV0_VID_BUF3_BASE_ADRS 0x044C
+#define OV0_VID_BUF4_BASE_ADRS 0x0450
+#define OV0_VID_BUF5_BASE_ADRS 0x0454
+#define OV0_VID_BUF_PITCH0_VALUE 0x0460
+#define OV0_VID_BUF_PITCH1_VALUE 0x0464
+#define OV0_AUTO_FLIP_CNTRL 0x0470
+#define OV0_DEINTERLACE_PATTERN 0x0474
+#define OV0_SUBMIT_HISTORY 0x0478
+#define OV0_H_INC 0x0480
+#define OV0_STEP_BY 0x0484
+#define OV0_P1_H_ACCUM_INIT 0x0488
+#define OV0_P23_H_ACCUM_INIT 0x048C
+#define OV0_P1_X_START_END 0x0494
+#define OV0_P2_X_START_END 0x0498
+#define OV0_P3_X_START_END 0x049C
+#define OV0_FILTER_CNTL 0x04A0
+#define OV0_FOUR_TAP_COEF_0 0x04B0
+#define OV0_FOUR_TAP_COEF_1 0x04B4
+#define OV0_FOUR_TAP_COEF_2 0x04B8
+#define OV0_FOUR_TAP_COEF_3 0x04BC
+#define OV0_FOUR_TAP_COEF_4 0x04C0
+#define OV0_FLAG_CNTRL 0x04DC
+#define OV0_SLICE_CNTL 0x04E0
+#define OV0_VID_KEY_CLR_LOW 0x04E4
+#define OV0_VID_KEY_CLR_HIGH 0x04E8
+#define OV0_GRPH_KEY_CLR_LOW 0x04EC
+#define OV0_GRPH_KEY_CLR_HIGH 0x04F0
+#define OV0_KEY_CNTL 0x04F4
+#define OV0_TEST 0x04F8
+#define SUBPIC_CNTL 0x0540
+#define SUBPIC_DEFCOLCON 0x0544
+#define SUBPIC_Y_X_START 0x054C
+#define SUBPIC_Y_X_END 0x0550
+#define SUBPIC_V_INC 0x0554
+#define SUBPIC_H_INC 0x0558
+#define SUBPIC_BUF0_OFFSET 0x055C
+#define SUBPIC_BUF1_OFFSET 0x0560
+#define SUBPIC_LC0_OFFSET 0x0564
+#define SUBPIC_LC1_OFFSET 0x0568
+#define SUBPIC_PITCH 0x056C
+#define SUBPIC_BTN_HLI_COLCON 0x0570
+#define SUBPIC_BTN_HLI_Y_X_START 0x0574
+#define SUBPIC_BTN_HLI_Y_X_END 0x0578
+#define SUBPIC_PALETTE_INDEX 0x057C
+#define SUBPIC_PALETTE_DATA 0x0580
+#define SUBPIC_H_ACCUM_INIT 0x0584
+#define SUBPIC_V_ACCUM_INIT 0x0588
+#define DISP_MISC_CNTL 0x0D00
+#define DAC_MACRO_CNTL 0x0D04
+#define DISP_PWR_MAN 0x0D08
+#define DISP_TEST_DEBUG_CNTL 0x0D10
+#define DISP_HW_DEBUG 0x0D14
+#define DAC_CRC_SIG1 0x0D18
+#define DAC_CRC_SIG2 0x0D1C
+#define OV0_LIN_TRANS_A 0x0D20
+#define OV0_LIN_TRANS_B 0x0D24
+#define OV0_LIN_TRANS_C 0x0D28
+#define OV0_LIN_TRANS_D 0x0D2C
+#define OV0_LIN_TRANS_E 0x0D30
+#define OV0_LIN_TRANS_F 0x0D34
+#define OV0_GAMMA_0_F 0x0D40
+#define OV0_GAMMA_10_1F 0x0D44
+#define OV0_GAMMA_20_3F 0x0D48
+#define OV0_GAMMA_40_7F 0x0D4C
+#define OV0_GAMMA_380_3BF 0x0D50
+#define OV0_GAMMA_3C0_3FF 0x0D54
+#define DISP_MERGE_CNTL 0x0D60
+#define DISP_OUTPUT_CNTL 0x0D64
+#define DISP_LIN_TRANS_GRPH_A 0x0D80
+#define DISP_LIN_TRANS_GRPH_B 0x0D84
+#define DISP_LIN_TRANS_GRPH_C 0x0D88
+#define DISP_LIN_TRANS_GRPH_D 0x0D8C
+#define DISP_LIN_TRANS_GRPH_E 0x0D90
+#define DISP_LIN_TRANS_GRPH_F 0x0D94
+#define DISP_LIN_TRANS_VID_A 0x0D98
+#define DISP_LIN_TRANS_VID_B 0x0D9C
+#define DISP_LIN_TRANS_VID_C 0x0DA0
+#define DISP_LIN_TRANS_VID_D 0x0DA4
+#define DISP_LIN_TRANS_VID_E 0x0DA8
+#define DISP_LIN_TRANS_VID_F 0x0DAC
+#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0
+#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4
+#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8
+#define RMX_HORZ_PHASE 0x0DBC
+#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0
+#define DAC_BROAD_PULSE 0x0DC4
+#define DAC_SKEW_CLKS 0x0DC8
+#define DAC_INCR 0x0DCC
+#define DAC_NEG_SYNC_LEVEL 0x0DD0
+#define DAC_POS_SYNC_LEVEL 0x0DD4
+#define DAC_BLANK_LEVEL 0x0DD8
+#define CLOCK_CNTL_INDEX 0x0008
+#define CLOCK_CNTL_DATA 0x000C
+#define CP_RB_CNTL 0x0704
+#define CP_RB_BASE 0x0700
+#define CP_RB_RPTR_ADDR 0x070C
+#define CP_RB_RPTR 0x0710
+#define CP_RB_WPTR 0x0714
+#define CP_RB_WPTR_DELAY 0x0718
+#define CP_IB_BASE 0x0738
+#define CP_IB_BUFSZ 0x073C
+#define SCRATCH_REG0 0x15E0
+#define GUI_SCRATCH_REG0 0x15E0
+#define SCRATCH_REG1 0x15E4
+#define GUI_SCRATCH_REG1 0x15E4
+#define SCRATCH_REG2 0x15E8
+#define GUI_SCRATCH_REG2 0x15E8
+#define SCRATCH_REG3 0x15EC
+#define GUI_SCRATCH_REG3 0x15EC
+#define SCRATCH_REG4 0x15F0
+#define GUI_SCRATCH_REG4 0x15F0
+#define SCRATCH_REG5 0x15F4
+#define GUI_SCRATCH_REG5 0x15F4
+#define SCRATCH_UMSK 0x0770
+#define SCRATCH_ADDR 0x0774
+#define DP_BRUSH_FRGD_CLR 0x147C
+#define DP_BRUSH_BKGD_CLR 0x1478
+#define DST_LINE_START 0x1600
+#define DST_LINE_END 0x1604
+#define SRC_OFFSET 0x15AC
+#define SRC_PITCH 0x15B0
+#define SRC_TILE 0x1704
+#define SRC_PITCH_OFFSET 0x1428
+#define SRC_X 0x1414
+#define SRC_Y 0x1418
+#define SRC_X_Y 0x1590
+#define SRC_Y_X 0x1434
+#define DST_Y_X 0x1438
+#define DST_WIDTH_HEIGHT 0x1598
+#define DST_HEIGHT_WIDTH 0x143c
+#define DST_OFFSET 0x1404
+#define SRC_CLUT_ADDRESS 0x1780
+#define SRC_CLUT_DATA 0x1784
+#define SRC_CLUT_DATA_RD 0x1788
+#define HOST_DATA0 0x17C0
+#define HOST_DATA1 0x17C4
+#define HOST_DATA2 0x17C8
+#define HOST_DATA3 0x17CC
+#define HOST_DATA4 0x17D0
+#define HOST_DATA5 0x17D4
+#define HOST_DATA6 0x17D8
+#define HOST_DATA7 0x17DC
+#define HOST_DATA_LAST 0x17E0
+#define DP_SRC_ENDIAN 0x15D4
+#define DP_SRC_FRGD_CLR 0x15D8
+#define DP_SRC_BKGD_CLR 0x15DC
+#define SC_LEFT 0x1640
+#define SC_RIGHT 0x1644
+#define SC_TOP 0x1648
+#define SC_BOTTOM 0x164C
+#define SRC_SC_RIGHT 0x1654
+#define SRC_SC_BOTTOM 0x165C
+#define DP_CNTL 0x16C0
+#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0
+#define DP_DATATYPE 0x16C4
+#define DP_MIX 0x16C8
+#define DP_WRITE_MSK 0x16CC
+#define DP_XOP 0x17F8
+#define CLR_CMP_CLR_SRC 0x15C4
+#define CLR_CMP_CLR_DST 0x15C8
+#define CLR_CMP_CNTL 0x15C0
+#define CLR_CMP_MSK 0x15CC
+#define DSTCACHE_MODE 0x1710
+#define DSTCACHE_CTLSTAT 0x1714
+#define DEFAULT_PITCH_OFFSET 0x16E0
+#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8
+#define DEFAULT_SC_TOP_LEFT 0x16EC
+#define SRC_PITCH_OFFSET 0x1428
+#define DST_PITCH_OFFSET 0x142C
+#define DP_GUI_MASTER_CNTL 0x146C
+#define SC_TOP_LEFT 0x16EC
+#define SC_BOTTOM_RIGHT 0x16F0
+#define SRC_SC_BOTTOM_RIGHT 0x16F4
+#define RB2D_DSTCACHE_MODE 0x3428
+#define RB2D_DSTCACHE_CTLSTAT 0x342C
+#define LVDS_GEN_CNTL 0x02d0
+#define LVDS_PLL_CNTL 0x02d4
+#define FP2_GEN_CNTL 0x0288
+#define TMDS_CNTL 0x0294
+#define TMDS_CRC 0x02a0
+#define TMDS_TRANSMITTER_CNTL 0x02a4
+#define MPP_TB_CONFIG 0x01c0
+#define PAMAC0_DLY_CNTL 0x0a94
+#define PAMAC1_DLY_CNTL 0x0a98
+#define PAMAC2_DLY_CNTL 0x0a9c
+#define FW_CNTL 0x0118
+#define FCP_CNTL 0x0910
+#define VGA_DDA_ON_OFF 0x02ec
+#define TV_MASTER_CNTL 0x0800
+
+/* #define BASE_CODE 0x0f0b */
+#define BIOS_0_SCRATCH 0x0010
+#define BIOS_1_SCRATCH 0x0014
+#define BIOS_2_SCRATCH 0x0018
+#define BIOS_3_SCRATCH 0x001c
+#define BIOS_4_SCRATCH 0x0020
+#define BIOS_5_SCRATCH 0x0024
+#define BIOS_6_SCRATCH 0x0028
+#define BIOS_7_SCRATCH 0x002c
+
+#define HDP_SOFT_RESET (1 << 26)
+
+#define TV_DAC_CNTL 0x088c
+#define GPIOPAD_MASK 0x0198
+#define GPIOPAD_A 0x019c
+#define GPIOPAD_EN 0x01a0
+#define GPIOPAD_Y 0x01a4
+#define ZV_LCDPAD_MASK 0x01a8
+#define ZV_LCDPAD_A 0x01ac
+#define ZV_LCDPAD_EN 0x01b0
+#define ZV_LCDPAD_Y 0x01b4
+
+/* PLL Registers */
+#define CLK_PIN_CNTL 0x0001
+#define PPLL_CNTL 0x0002
+#define PPLL_REF_DIV 0x0003
+#define PPLL_DIV_0 0x0004
+#define PPLL_DIV_1 0x0005
+#define PPLL_DIV_2 0x0006
+#define PPLL_DIV_3 0x0007
+#define VCLK_ECP_CNTL 0x0008
+#define HTOTAL_CNTL 0x0009
+#define M_SPLL_REF_FB_DIV 0x000a
+#define AGP_PLL_CNTL 0x000b
+#define SPLL_CNTL 0x000c
+#define SCLK_CNTL 0x000d
+#define MPLL_CNTL 0x000e
+#define MDLL_CKO 0x000f
+#define MDLL_RDCKA 0x0010
+#define MCLK_CNTL 0x0012
+#define AGP_PLL_CNTL 0x000b
+#define PLL_TEST_CNTL 0x0013
+#define CLK_PWRMGT_CNTL 0x0014
+#define PLL_PWRMGT_CNTL 0x0015
+#define MCLK_MISC 0x001f
+#define P2PLL_CNTL 0x002a
+#define P2PLL_REF_DIV 0x002b
+#define PIXCLKS_CNTL 0x002d
+#define SCLK_MORE_CNTL 0x0035
+
+/* MCLK_CNTL bit constants */
+#define FORCEON_MCLKA (1 << 16)
+#define FORCEON_MCLKB (1 << 17)
+#define FORCEON_YCLKA (1 << 18)
+#define FORCEON_YCLKB (1 << 19)
+#define FORCEON_MC (1 << 20)
+#define FORCEON_AIC (1 << 21)
+
+/* SCLK_CNTL bit constants */
+#define DYN_STOP_LAT_MASK 0x00007ff8
+#define CP_MAX_DYN_STOP_LAT 0x0008
+#define SCLK_FORCEON_MASK 0xffff8000
+
+/* SCLK_MORE_CNTL bit constants */
+#define SCLK_MORE_FORCEON 0x0700
+
+/* BUS_CNTL bit constants */
+#define BUS_DBL_RESYNC 0x00000001
+#define BUS_MSTR_RESET 0x00000002
+#define BUS_FLUSH_BUF 0x00000004
+#define BUS_STOP_REQ_DIS 0x00000008
+#define BUS_ROTATION_DIS 0x00000010
+#define BUS_MASTER_DIS 0x00000040
+#define BUS_ROM_WRT_EN 0x00000080
+#define BUS_DIS_ROM 0x00001000
+#define BUS_PCI_READ_RETRY_EN 0x00002000
+#define BUS_AGP_AD_STEPPING_EN 0x00004000
+#define BUS_PCI_WRT_RETRY_EN 0x00008000
+#define BUS_MSTR_RD_MULT 0x00100000
+#define BUS_MSTR_RD_LINE 0x00200000
+#define BUS_SUSPEND 0x00400000
+#define LAT_16X 0x00800000
+#define BUS_RD_DISCARD_EN 0x01000000
+#define BUS_RD_ABORT_EN 0x02000000
+#define BUS_MSTR_WS 0x04000000
+#define BUS_PARKING_DIS 0x08000000
+#define BUS_MSTR_DISCONNECT_EN 0x10000000
+#define BUS_WRT_BURST 0x20000000
+#define BUS_READ_BURST 0x40000000
+#define BUS_RDY_READ_DLY 0x80000000
+
+/* PIXCLKS_CNTL */
+#define PIX2CLK_SRC_SEL_MASK 0x03
+#define PIX2CLK_SRC_SEL_CPUCLK 0x00
+#define PIX2CLK_SRC_SEL_PSCANCLK 0x01
+#define PIX2CLK_SRC_SEL_BYTECLK 0x02
+#define PIX2CLK_SRC_SEL_P2PLLCLK 0x03
+#define PIX2CLK_ALWAYS_ONb (1<<6)
+#define PIX2CLK_DAC_ALWAYS_ONb (1<<7)
+#define PIXCLK_TV_SRC_SEL (1 << 8)
+#define PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
+#define PIXCLK_TMDS_ALWAYS_ONb (1 << 15)
+
+
+/* CLOCK_CNTL_INDEX bit constants */
+#define PLL_WR_EN 0x00000080
+
+/* CONFIG_CNTL bit constants */
+#define CFG_VGA_RAM_EN 0x00000100
+#define CFG_ATI_REV_ID_MASK (0xf << 16)
+#define CFG_ATI_REV_A11 (0 << 16)
+#define CFG_ATI_REV_A12 (1 << 16)
+#define CFG_ATI_REV_A13 (2 << 16)
+
+/* CRTC_EXT_CNTL bit constants */
+#define VGA_ATI_LINEAR 0x00000008
+#define VGA_128KAP_PAGING 0x00000010
+#define XCRT_CNT_EN (1 << 6)
+#define CRTC_HSYNC_DIS (1 << 8)
+#define CRTC_VSYNC_DIS (1 << 9)
+#define CRTC_DISPLAY_DIS (1 << 10)
+#define CRTC_CRT_ON (1 << 15)
+
+
+/* DSTCACHE_CTLSTAT bit constants */
+#define RB2D_DC_FLUSH (3 << 0)
+#define RB2D_DC_FLUSH_ALL 0xf
+#define RB2D_DC_BUSY (1 << 31)
+
+
+/* CRTC_GEN_CNTL bit constants */
+#define CRTC_DBL_SCAN_EN 0x00000001
+#define CRTC_CUR_EN 0x00010000
+#define CRTC_INTERLACE_EN (1 << 1)
+#define CRTC_BYPASS_LUT_EN (1 << 14)
+#define CRTC_EXT_DISP_EN (1 << 24)
+#define CRTC_EN (1 << 25)
+#define CRTC_DISP_REQ_EN_B (1 << 26)
+
+/* CRTC_STATUS bit constants */
+#define CRTC_VBLANK 0x00000001
+
+/* CRTC2_GEN_CNTL bit constants */
+#define CRT2_ON (1 << 7)
+#define CRTC2_DISPLAY_DIS (1 << 23)
+#define CRTC2_EN (1 << 25)
+#define CRTC2_DISP_REQ_EN_B (1 << 26)
+
+/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
+#define CUR_LOCK 0x80000000
+
+/* GPIO bit constants */
+#define GPIO_A_0 (1 << 0)
+#define GPIO_A_1 (1 << 1)
+#define GPIO_Y_0 (1 << 8)
+#define GPIO_Y_1 (1 << 9)
+#define GPIO_EN_0 (1 << 16)
+#define GPIO_EN_1 (1 << 17)
+#define GPIO_MASK_0 (1 << 24)
+#define GPIO_MASK_1 (1 << 25)
+#define VGA_DDC_DATA_OUTPUT GPIO_A_0
+#define VGA_DDC_CLK_OUTPUT GPIO_A_1
+#define VGA_DDC_DATA_INPUT GPIO_Y_0
+#define VGA_DDC_CLK_INPUT GPIO_Y_1
+#define VGA_DDC_DATA_OUT_EN GPIO_EN_0
+#define VGA_DDC_CLK_OUT_EN GPIO_EN_1
+
+
+/* FP bit constants */
+#define FP_CRTC_H_TOTAL_MASK 000003ff
+#define FP_CRTC_H_DISP_MASK 0x01ff0000
+#define FP_CRTC_V_TOTAL_MASK 0x00000fff
+#define FP_CRTC_V_DISP_MASK 0x0fff0000
+#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
+#define FP_H_SYNC_WID_MASK 0x003f0000
+#define FP_V_SYNC_STRT_MASK 0x00000fff
+#define FP_V_SYNC_WID_MASK 0x001f0000
+#define FP_CRTC_H_TOTAL_SHIFT 0x00000000
+#define FP_CRTC_H_DISP_SHIFT 0x00000010
+#define FP_CRTC_V_TOTAL_SHIFT 0x00000000
+#define FP_CRTC_V_DISP_SHIFT 0x00000010
+#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
+#define FP_H_SYNC_WID_SHIFT 0x00000010
+#define FP_V_SYNC_STRT_SHIFT 0x00000000
+#define FP_V_SYNC_WID_SHIFT 0x00000010
+
+/* FP_GEN_CNTL bit constants */
+#define FP_FPON (1 << 0)
+#define FP_TMDS_EN (1 << 2)
+#define FP_PANEL_FORMAT (1 << 3)
+#define FP_EN_TMDS (1 << 7)
+#define FP_DETECT_SENSE (1 << 8)
+#define R200_FP_SOURCE_SEL_MASK (3 << 10)
+#define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)
+#define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)
+#define R200_FP_SOURCE_SEL_RMX (2 << 10)
+#define R200_FP_SOURCE_SEL_TRANS (3 << 10)
+#define FP_SEL_CRTC1 (0 << 13)
+#define FP_SEL_CRTC2 (1 << 13)
+#define FP_USE_VGA_HSYNC (1 << 14)
+#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
+#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
+#define FP_CRTC_DONT_SHADOW_HEND (1 << 17)
+#define FP_CRTC_USE_SHADOW_VEND (1 << 18)
+#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
+#define FP_DFP_SYNC_SEL (1 << 21)
+#define FP_CRTC_LOCK_8DOT (1 << 22)
+#define FP_CRT_SYNC_SEL (1 << 23)
+#define FP_USE_SHADOW_EN (1 << 24)
+#define FP_CRT_SYNC_ALT (1 << 26)
+
+/* FP2_GEN_CNTL bit constants */
+#define FP2_BLANK_EN (1 << 1)
+#define FP2_ON (1 << 2)
+#define FP2_PANEL_FORMAT (1 << 3)
+#define FP2_SOURCE_SEL_MASK (3 << 10)
+#define FP2_SOURCE_SEL_CRTC2 (1 << 10)
+#define FP2_SRC_SEL_MASK (3 << 13)
+#define FP2_SRC_SEL_CRTC2 (1 << 13)
+#define FP2_FP_POL (1 << 16)
+#define FP2_LP_POL (1 << 17)
+#define FP2_SCK_POL (1 << 18)
+#define FP2_LCD_CNTL_MASK (7 << 19)
+#define FP2_PAD_FLOP_EN (1 << 22)
+#define FP2_CRC_EN (1 << 23)
+#define FP2_CRC_READ_EN (1 << 24)
+#define FP2_DV0_EN (1 << 25)
+#define FP2_DV0_RATE_SEL_SDR (1 << 26)
+
+
+/* LVDS_GEN_CNTL bit constants */
+#define LVDS_ON (1 << 0)
+#define LVDS_DISPLAY_DIS (1 << 1)
+#define LVDS_PANEL_TYPE (1 << 2)
+#define LVDS_PANEL_FORMAT (1 << 3)
+#define LVDS_EN (1 << 7)
+#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00
+#define LVDS_BL_MOD_LEVEL_SHIFT 8
+#define LVDS_BL_MOD_EN (1 << 16)
+#define LVDS_DIGON (1 << 18)
+#define LVDS_BLON (1 << 19)
+#define LVDS_SEL_CRTC2 (1 << 23)
+#define LVDS_STATE_MASK \
+ (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON)
+
+/* LVDS_PLL_CNTL bit constatns */
+#define HSYNC_DELAY_SHIFT 0x1c
+#define HSYNC_DELAY_MASK (0xf << 0x1c)
+
+/* TMDS_TRANSMITTER_CNTL bit constants */
+#define TMDS_PLL_EN (1 << 0)
+#define TMDS_PLLRST (1 << 1)
+#define TMDS_RAN_PAT_RST (1 << 7)
+#define TMDS_ICHCSEL (1 << 28)
+
+/* FP_HORZ_STRETCH bit constants */
+#define HORZ_STRETCH_RATIO_MASK 0xffff
+#define HORZ_STRETCH_RATIO_MAX 4096
+#define HORZ_PANEL_SIZE (0x1ff << 16)
+#define HORZ_PANEL_SHIFT 16
+#define HORZ_STRETCH_PIXREP (0 << 25)
+#define HORZ_STRETCH_BLEND (1 << 26)
+#define HORZ_STRETCH_ENABLE (1 << 25)
+#define HORZ_AUTO_RATIO (1 << 27)
+#define HORZ_FP_LOOP_STRETCH (0x7 << 28)
+#define HORZ_AUTO_RATIO_INC (1 << 31)
+
+
+/* FP_VERT_STRETCH bit constants */
+#define VERT_STRETCH_RATIO_MASK 0xfff
+#define VERT_STRETCH_RATIO_MAX 4096
+#define VERT_PANEL_SIZE (0xfff << 12)
+#define VERT_PANEL_SHIFT 12
+#define VERT_STRETCH_LINREP (0 << 26)
+#define VERT_STRETCH_BLEND (1 << 26)
+#define VERT_STRETCH_ENABLE (1 << 25)
+#define VERT_AUTO_RATIO_EN (1 << 27)
+#define VERT_FP_LOOP_STRETCH (0x7 << 28)
+#define VERT_STRETCH_RESERVED 0xf1000000
+
+/* DAC_CNTL bit constants */
+#define DAC_8BIT_EN 0x00000100
+#define DAC_4BPP_PIX_ORDER 0x00000200
+#define DAC_CRC_EN 0x00080000
+#define DAC_MASK_ALL (0xff << 24)
+#define DAC_PDWN (1 << 15)
+#define DAC_EXPAND_MODE (1 << 14)
+#define DAC_VGA_ADR_EN (1 << 13)
+#define DAC_RANGE_CNTL (3 << 0)
+#define DAC_RANGE_CNTL_MASK 0x03
+#define DAC_BLANKING (1 << 2)
+#define DAC_CMP_EN (1 << 3)
+#define DAC_CMP_OUTPUT (1 << 7)
+
+/* DAC_CNTL2 bit constants */
+#define DAC2_EXPAND_MODE (1 << 14)
+#define DAC2_CMP_EN (1 << 7)
+#define DAC2_PALETTE_ACCESS_CNTL (1 << 5)
+
+/* DAC_EXT_CNTL bit constants */
+#define DAC_FORCE_BLANK_OFF_EN (1 << 4)
+#define DAC_FORCE_DATA_EN (1 << 5)
+#define DAC_FORCE_DATA_SEL_MASK (3 << 6)
+#define DAC_FORCE_DATA_MASK 0x0003ff00
+#define DAC_FORCE_DATA_SHIFT 8
+
+/* GEN_RESET_CNTL bit constants */
+#define SOFT_RESET_GUI 0x00000001
+#define SOFT_RESET_VCLK 0x00000100
+#define SOFT_RESET_PCLK 0x00000200
+#define SOFT_RESET_ECP 0x00000400
+#define SOFT_RESET_DISPENG_XCLK 0x00000800
+
+/* MEM_CNTL bit constants */
+#define MEM_CTLR_STATUS_IDLE 0x00000000
+#define MEM_CTLR_STATUS_BUSY 0x00100000
+#define MEM_SEQNCR_STATUS_IDLE 0x00000000
+#define MEM_SEQNCR_STATUS_BUSY 0x00200000
+#define MEM_ARBITER_STATUS_IDLE 0x00000000
+#define MEM_ARBITER_STATUS_BUSY 0x00400000
+#define MEM_REQ_UNLOCK 0x00000000
+#define MEM_REQ_LOCK 0x00800000
+#define MEM_NUM_CHANNELS_MASK 0x00000001
+#define MEM_USE_B_CH_ONLY 0x00000002
+#define RV100_MEM_HALF_MODE 0x00000008
+#define R300_MEM_NUM_CHANNELS_MASK 0x00000003
+#define R300_MEM_USE_CD_CH_ONLY 0x00000004
+
+
+/* RBBM_SOFT_RESET bit constants */
+#define SOFT_RESET_CP (1 << 0)
+#define SOFT_RESET_HI (1 << 1)
+#define SOFT_RESET_SE (1 << 2)
+#define SOFT_RESET_RE (1 << 3)
+#define SOFT_RESET_PP (1 << 4)
+#define SOFT_RESET_E2 (1 << 5)
+#define SOFT_RESET_RB (1 << 6)
+#define SOFT_RESET_HDP (1 << 7)
+
+/* SURFACE_CNTL bit consants */
+#define SURF_TRANSLATION_DIS (1 << 8)
+#define NONSURF_AP0_SWP_16BPP (1 << 20)
+#define NONSURF_AP0_SWP_32BPP (1 << 21)
+#define NONSURF_AP1_SWP_16BPP (1 << 22)
+#define NONSURF_AP1_SWP_32BPP (1 << 23)
+
+/* DEFAULT_SC_BOTTOM_RIGHT bit constants */
+#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
+#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
+
+/* MM_INDEX bit constants */
+#define MM_APER 0x80000000
+
+/* CLR_CMP_CNTL bit constants */
+#define COMPARE_SRC_FALSE 0x00000000
+#define COMPARE_SRC_TRUE 0x00000001
+#define COMPARE_SRC_NOT_EQUAL 0x00000004
+#define COMPARE_SRC_EQUAL 0x00000005
+#define COMPARE_SRC_EQUAL_FLIP 0x00000007
+#define COMPARE_DST_FALSE 0x00000000
+#define COMPARE_DST_TRUE 0x00000100
+#define COMPARE_DST_NOT_EQUAL 0x00000400
+#define COMPARE_DST_EQUAL 0x00000500
+#define COMPARE_DESTINATION 0x00000000
+#define COMPARE_SOURCE 0x01000000
+#define COMPARE_SRC_AND_DST 0x02000000
+
+
+/* DP_CNTL bit constants */
+#define DST_X_RIGHT_TO_LEFT 0x00000000
+#define DST_X_LEFT_TO_RIGHT 0x00000001
+#define DST_Y_BOTTOM_TO_TOP 0x00000000
+#define DST_Y_TOP_TO_BOTTOM 0x00000002
+#define DST_X_MAJOR 0x00000000
+#define DST_Y_MAJOR 0x00000004
+#define DST_X_TILE 0x00000008
+#define DST_Y_TILE 0x00000010
+#define DST_LAST_PEL 0x00000020
+#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000
+#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040
+#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000
+#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080
+#define DST_BRES_SIGN 0x00000100
+#define DST_HOST_BIG_ENDIAN_EN 0x00000200
+#define DST_POLYLINE_NONLAST 0x00008000
+#define DST_RASTER_STALL 0x00010000
+#define DST_POLY_EDGE 0x00040000
+
+
+/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */
+#define DST_X_MAJOR_S 0x00000000
+#define DST_Y_MAJOR_S 0x00000001
+#define DST_Y_BOTTOM_TO_TOP_S 0x00000000
+#define DST_Y_TOP_TO_BOTTOM_S 0x00008000
+#define DST_X_RIGHT_TO_LEFT_S 0x00000000
+#define DST_X_LEFT_TO_RIGHT_S 0x80000000
+
+
+/* DP_DATATYPE bit constants */
+#define DST_8BPP 0x00000002
+#define DST_15BPP 0x00000003
+#define DST_16BPP 0x00000004
+#define DST_24BPP 0x00000005
+#define DST_32BPP 0x00000006
+#define DST_8BPP_RGB332 0x00000007
+#define DST_8BPP_Y8 0x00000008
+#define DST_8BPP_RGB8 0x00000009
+#define DST_16BPP_VYUY422 0x0000000b
+#define DST_16BPP_YVYU422 0x0000000c
+#define DST_32BPP_AYUV444 0x0000000e
+#define DST_16BPP_ARGB4444 0x0000000f
+#define BRUSH_SOLIDCOLOR 0x00000d00
+#define SRC_MONO 0x00000000
+#define SRC_MONO_LBKGD 0x00010000
+#define SRC_DSTCOLOR 0x00030000
+#define BYTE_ORDER_MSB_TO_LSB 0x00000000
+#define BYTE_ORDER_LSB_TO_MSB 0x40000000
+#define DP_CONVERSION_TEMP 0x80000000
+#define HOST_BIG_ENDIAN_EN (1 << 29)
+
+
+/* DP_GUI_MASTER_CNTL bit constants */
+#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000
+#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001
+#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000
+#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002
+#define GMC_SRC_CLIP_DEFAULT 0x00000000
+#define GMC_SRC_CLIP_LEAVE 0x00000004
+#define GMC_DST_CLIP_DEFAULT 0x00000000
+#define GMC_DST_CLIP_LEAVE 0x00000008
+#define GMC_BRUSH_8x8MONO 0x00000000
+#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010
+#define GMC_BRUSH_8x1MONO 0x00000020
+#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030
+#define GMC_BRUSH_1x8MONO 0x00000040
+#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050
+#define GMC_BRUSH_32x1MONO 0x00000060
+#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070
+#define GMC_BRUSH_32x32MONO 0x00000080
+#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090
+#define GMC_BRUSH_8x8COLOR 0x000000a0
+#define GMC_BRUSH_8x1COLOR 0x000000b0
+#define GMC_BRUSH_1x8COLOR 0x000000c0
+#define GMC_BRUSH_SOLID_COLOR 0x000000d0
+#define GMC_DST_8BPP 0x00000200
+#define GMC_DST_15BPP 0x00000300
+#define GMC_DST_16BPP 0x00000400
+#define GMC_DST_24BPP 0x00000500
+#define GMC_DST_32BPP 0x00000600
+#define GMC_DST_8BPP_RGB332 0x00000700
+#define GMC_DST_8BPP_Y8 0x00000800
+#define GMC_DST_8BPP_RGB8 0x00000900
+#define GMC_DST_16BPP_VYUY422 0x00000b00
+#define GMC_DST_16BPP_YVYU422 0x00000c00
+#define GMC_DST_32BPP_AYUV444 0x00000e00
+#define GMC_DST_16BPP_ARGB4444 0x00000f00
+#define GMC_SRC_MONO 0x00000000
+#define GMC_SRC_MONO_LBKGD 0x00001000
+#define GMC_SRC_DSTCOLOR 0x00003000
+#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
+#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000
+#define GMC_DP_CONVERSION_TEMP_9300 0x00008000
+#define GMC_DP_CONVERSION_TEMP_6500 0x00000000
+#define GMC_DP_SRC_RECT 0x02000000
+#define GMC_DP_SRC_HOST 0x03000000
+#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000
+#define GMC_3D_FCN_EN_CLR 0x00000000
+#define GMC_3D_FCN_EN_SET 0x08000000
+#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000
+#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
+#define GMC_AUX_CLIP_LEAVE 0x00000000
+#define GMC_AUX_CLIP_CLEAR 0x20000000
+#define GMC_WRITE_MASK_LEAVE 0x00000000
+#define GMC_WRITE_MASK_SET 0x40000000
+#define GMC_CLR_CMP_CNTL_DIS (1 << 28)
+#define GMC_SRC_DATATYPE_COLOR (3 << 12)
+#define ROP3_S 0x00cc0000
+#define ROP3_SRCCOPY 0x00cc0000
+#define ROP3_P 0x00f00000
+#define ROP3_PATCOPY 0x00f00000
+#define DP_SRC_SOURCE_MASK (7 << 24)
+#define GMC_BRUSH_NONE (15 << 4)
+#define DP_SRC_SOURCE_MEMORY (2 << 24)
+#define GMC_BRUSH_SOLIDCOLOR 0x000000d0
+
+/* DP_MIX bit constants */
+#define DP_SRC_RECT 0x00000200
+#define DP_SRC_HOST 0x00000300
+#define DP_SRC_HOST_BYTEALIGN 0x00000400
+
+/* MPLL_CNTL bit constants */
+#define MPLL_RESET 0x00000001
+
+/* MDLL_CKO bit constants */
+#define MCKOA_SLEEP 0x00000001
+#define MCKOA_RESET 0x00000002
+#define MCKOA_REF_SKEW_MASK 0x00000700
+#define MCKOA_FB_SKEW_MASK 0x00007000
+
+/* MDLL_RDCKA bit constants */
+#define MRDCKA0_SLEEP 0x00000001
+#define MRDCKA0_RESET 0x00000002
+#define MRDCKA1_SLEEP 0x00010000
+#define MRDCKA1_RESET 0x00020000
+
+/* VCLK_ECP_CNTL constants */
+#define VCLK_SRC_SEL_MASK 0x03
+#define VCLK_SRC_SEL_CPUCLK 0x00
+#define VCLK_SRC_SEL_PSCANCLK 0x01
+#define VCLK_SRC_SEL_BYTECLK 0x02
+#define VCLK_SRC_SEL_PPLLCLK 0x03
+#define PIXCLK_ALWAYS_ONb 0x00000040
+#define PIXCLK_DAC_ALWAYS_ONb 0x00000080
+
+/* BUS_CNTL1 constants */
+#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000
+#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26
+#define BUS_CNTL1_AGPCLK_VALID 0x80000000
+
+/* PLL_PWRMGT_CNTL constants */
+#define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002
+#define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004
+#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008
+#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010
+#define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000
+#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000
+#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000
+
+/* TV_DAC_CNTL constants */
+#define TV_DAC_CNTL_BGSLEEP 0x00000040
+#define TV_DAC_CNTL_DETECT 0x00000010
+#define TV_DAC_CNTL_BGADJ_MASK 0x000f0000
+#define TV_DAC_CNTL_DACADJ_MASK 0x00f00000
+#define TV_DAC_CNTL_BGADJ__SHIFT 16
+#define TV_DAC_CNTL_DACADJ__SHIFT 20
+#define TV_DAC_CNTL_RDACPD 0x01000000
+#define TV_DAC_CNTL_GDACPD 0x02000000
+#define TV_DAC_CNTL_BDACPD 0x04000000
+
+/* DISP_MISC_CNTL constants */
+#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0)
+#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1)
+#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2)
+#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4)
+#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5)
+#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6)
+#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12)
+#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15)
+#define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16)
+#define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17)
+#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18)
+#define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19)
+
+/* DISP_PWR_MAN constants */
+#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0)
+#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4)
+#define DISP_PWR_MAN_DISP_D3_RST (1 << 16)
+#define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17)
+#define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18)
+#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19)
+#define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20)
+#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21)
+#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22)
+#define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23)
+#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24)
+#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25)
+#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26)
+
+/* masks */
+
+#define CONFIG_MEMSIZE_MASK 0x1f000000
+#define MEM_CFG_TYPE 0x40000000
+#define DST_OFFSET_MASK 0x003fffff
+#define DST_PITCH_MASK 0x3fc00000
+#define DEFAULT_TILE_MASK 0xc0000000
+#define PPLL_DIV_SEL_MASK 0x00000300
+#define PPLL_RESET 0x00000001
+#define PPLL_SLEEP 0x00000002
+#define PPLL_ATOMIC_UPDATE_EN 0x00010000
+#define PPLL_REF_DIV_MASK 0x000003ff
+#define PPLL_FB3_DIV_MASK 0x000007ff
+#define PPLL_POST3_DIV_MASK 0x00070000
+#define PPLL_ATOMIC_UPDATE_R 0x00008000
+#define PPLL_ATOMIC_UPDATE_W 0x00008000
+#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000
+#define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)
+#define R300_PPLL_REF_DIV_ACC_SHIFT 18
+
+#define GUI_ACTIVE 0x80000000
+
+
+#define MC_IND_INDEX 0x01F8
+#define MC_IND_DATA 0x01FC
+
+/* PAD_CTLR_STRENGTH */
+#define PAD_MANUAL_OVERRIDE 0x80000000
+
+/* pllCLK_PIN_CNTL */
+#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L
+#define CLK_PIN_CNTL__OSC_EN 0x00000001L
+#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L
+#define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L
+#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L
+#define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L
+#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L
+#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L
+#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L
+#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L
+#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L
+#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L
+#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L
+#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L
+#define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L
+#define CLK_PIN_CNTL__CG_SPARE 0x00004000L
+#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L
+#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L
+#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L
+#define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L
+#define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L
+#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L
+#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L
+#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L
+
+/* pllCLK_PWRMGT_CNTL */
+#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000
+#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001
+#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002
+#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003
+#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004
+#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005
+#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006
+#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007
+#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008
+#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009
+#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a
+#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c
+#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d
+#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f
+#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010
+#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011
+#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012
+#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013
+#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014
+#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015
+#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018
+#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e
+#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f
+
+/* pllP2PLL_CNTL */
+#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L
+#define P2PLL_CNTL__P2PLL_RESET 0x00000001L
+#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L
+#define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L
+#define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L
+#define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L
+#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L
+#define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L
+#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L
+#define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L
+#define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L
+#define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L
+#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L
+#define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L
+#define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L
+#define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L
+#define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L
+#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L
+#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L
+#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L
+#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L
+#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L
+#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L
+
+/* pllPIXCLKS_CNTL */
+#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000
+#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004
+#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005
+#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006
+#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007
+#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008
+#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b
+#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c
+#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d
+#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e
+#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f
+
+
+/* pllPIXCLKS_CNTL */
+#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L
+#define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L
+#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L
+#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L
+#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L
+#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L
+#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L
+#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L
+#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L
+#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L
+#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L
+#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)
+#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10)
+#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)
+#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)
+#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)
+#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18)
+#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)
+#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
+
+
+/* pllP2PLL_DIV_0 */
+#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL
+#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L
+#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L
+#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L
+#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L
+#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L
+
+/* pllSCLK_CNTL */
+#define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L
+#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L
+#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L
+#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L
+#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L
+#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L
+#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L
+#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L
+#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L
+#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L
+#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L
+#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L
+#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L
+#define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8
+#define SCLK_CNTL__FORCE_DISP2 0x00008000L
+#define SCLK_CNTL__FORCE_CP 0x00010000L
+#define SCLK_CNTL__FORCE_HDP 0x00020000L
+#define SCLK_CNTL__FORCE_DISP1 0x00040000L
+#define SCLK_CNTL__FORCE_TOP 0x00080000L
+#define SCLK_CNTL__FORCE_E2 0x00100000L
+#define SCLK_CNTL__FORCE_SE 0x00200000L
+#define SCLK_CNTL__FORCE_IDCT 0x00400000L
+#define SCLK_CNTL__FORCE_VIP 0x00800000L
+#define SCLK_CNTL__FORCE_RE 0x01000000L
+#define SCLK_CNTL__FORCE_PB 0x02000000L
+#define SCLK_CNTL__FORCE_TAM 0x04000000L
+#define SCLK_CNTL__FORCE_TDM 0x08000000L
+#define SCLK_CNTL__FORCE_RB 0x10000000L
+#define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L
+#define SCLK_CNTL__FORCE_SUBPIC 0x40000000L
+#define SCLK_CNTL__FORCE_OV0 0x80000000L
+#define SCLK_CNTL__R300_FORCE_VAP (1<<21)
+#define SCLK_CNTL__R300_FORCE_SR (1<<25)
+#define SCLK_CNTL__R300_FORCE_PX (1<<26)
+#define SCLK_CNTL__R300_FORCE_TX (1<<27)
+#define SCLK_CNTL__R300_FORCE_US (1<<28)
+#define SCLK_CNTL__R300_FORCE_SU (1<<30)
+#define SCLK_CNTL__FORCEON_MASK 0xffff8000L
+
+/* pllSCLK_CNTL2 */
+#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10)
+#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11)
+#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12)
+#define SCLK_CNTL2__R300_FORCE_TCL (1<<13)
+#define SCLK_CNTL2__R300_FORCE_CBA (1<<14)
+#define SCLK_CNTL2__R300_FORCE_GA (1<<15)
+
+/* SCLK_MORE_CNTL */
+#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L
+#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L
+#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L
+#define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L
+#define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L
+#define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L
+#define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L
+#define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L
+#define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L
+#define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L
+#define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L
+#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L
+#define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L
+#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L
+#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L
+#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L
+#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L
+#define SCLK_MORE_CNTL__FORCEON 0x00000700L
+
+/* MCLK_CNTL */
+#define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L
+#define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L
+#define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L
+#define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L
+#define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L
+#define MCLK_CNTL__FORCE_MCLKA 0x00010000L
+#define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L
+#define MCLK_CNTL__FORCE_MCLKB 0x00020000L
+#define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L
+#define MCLK_CNTL__FORCE_YCLKA 0x00040000L
+#define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L
+#define MCLK_CNTL__FORCE_YCLKB 0x00080000L
+#define MCLK_CNTL__FORCE_MC_MASK 0x00100000L
+#define MCLK_CNTL__FORCE_MC 0x00100000L
+#define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L
+#define MCLK_CNTL__FORCE_AIC 0x00200000L
+#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L
+#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L
+#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L
+#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L
+#define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21)
+#define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21)
+
+/* MCLK_MISC */
+#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L
+#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L
+#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L
+#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L
+#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L
+#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L
+#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L
+#define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L
+#define MCLK_MISC__DLL_READY_LAT 0x00000100L
+#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L
+#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L
+#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L
+#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L
+#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L
+#define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L
+#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L
+#define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L
+#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L
+#define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L
+#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L
+#define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L
+#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L
+#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L
+#define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L
+#define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L
+#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L
+#define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L
+#define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L
+
+/* VCLK_ECP_CNTL */
+#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L
+#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L
+#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L
+#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L
+#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L
+#define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L
+#define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L
+#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L
+#define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)
+
+/* PLL_PWRMGT_CNTL */
+#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L
+#define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L
+#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L
+#define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L
+#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L
+#define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L
+#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L
+#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L
+#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L
+#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L
+#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L
+#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L
+#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L
+#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L
+#define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L
+#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L
+#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L
+#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L
+#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L
+#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L
+#define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L
+#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L
+#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L
+#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L
+#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L
+#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L
+#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L
+#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L
+#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L
+#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L
+#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L
+#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L
+
+/* CLK_PWRMGT_CNTL */
+#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L
+#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L
+#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L
+#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L
+#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L
+#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L
+#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L
+#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L
+#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L
+#define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L
+#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L
+#define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L
+#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L
+#define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L
+#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L
+#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L
+#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L
+#define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L
+#define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L
+#define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L
+#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L
+#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L
+#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L
+#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L
+#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L
+#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L
+#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L
+#define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L
+#define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L
+#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L
+#define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L
+#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L
+#define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L
+#define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L
+#define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L
+#define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L
+#define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L
+#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L
+#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L
+#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L
+#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L
+#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L
+#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L
+
+/* BUS_CNTL1 */
+#define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L
+#define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L
+#define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L
+#define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L
+#define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L
+#define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L
+#define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L
+#define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L
+#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L
+#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L
+#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L
+#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L
+#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L
+#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L
+#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L
+#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L
+#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L
+#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L
+#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L
+#define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L
+#define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L
+#define BUS_CNTL1__AGPCLK_VALID 0x80000000L
+
+/* BUS_CNTL1 */
+#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000
+#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001
+#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002
+#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003
+#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005
+#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008
+#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009
+#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a
+#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b
+#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a
+#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c
+#define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f
+
+/* CRTC_OFFSET_CNTL */
+#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL
+#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L
+#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L
+#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L
+#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L
+#define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L
+#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L
+#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L
+#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L
+#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L
+
+/* CRTC_GEN_CNTL */
+#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L
+#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L
+#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L
+#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L
+#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L
+#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L
+#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L
+#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L
+#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L
+#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L
+#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L
+#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L
+#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L
+#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L
+#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L
+#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L
+#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L
+#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L
+#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L
+
+/* CRTC2_GEN_CNTL */
+#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L
+#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L
+#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L
+#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L
+#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L
+#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L
+#define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L
+#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L
+#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L
+#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L
+#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L
+#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L
+#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L
+#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L
+#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L
+#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L
+#define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L
+#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L
+#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L
+#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L
+#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L
+#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L
+
+/* AGP_CNTL */
+#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL
+#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L
+#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L
+#define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L
+#define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L
+#define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L
+#define AGP_CNTL__EN_2X_STBB 0x00000400L
+#define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L
+#define AGP_CNTL__FORCE_FULL_SBA 0x00000800L
+#define AGP_CNTL__SBA_DIS_MASK 0x00001000L
+#define AGP_CNTL__SBA_DIS 0x00001000L
+#define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L
+#define AGP_CNTL__AGP_REV_ID 0x00002000L
+#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L
+#define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L
+#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L
+#define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L
+#define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L
+#define AGP_CNTL__FORCE_INT_VREF 0x00010000L
+#define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L
+#define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L
+#define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L
+#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L
+#define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L
+#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L
+#define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L
+#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L
+#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L
+#define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L
+#define AGP_CNTL__EN_RBFCALM 0x00800000L
+#define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L
+#define AGP_CNTL__FORCE_EXT_VREF 0x01000000L
+#define AGP_CNTL__DIS_RBF_MASK 0x02000000L
+#define AGP_CNTL__DIS_RBF 0x02000000L
+#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L
+#define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L
+#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L
+#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L
+
+/* AGP_CNTL */
+#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000
+#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008
+#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009
+#define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a
+#define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b
+#define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c
+#define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d
+#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e
+#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f
+#define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010
+#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011
+#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013
+#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014
+#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015
+#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016
+#define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017
+#define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018
+#define AGP_CNTL__DIS_RBF__SHIFT 0x00000019
+#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a
+#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b
+#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e
+
+/* DISP_MISC_CNTL */
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L
+#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L
+#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L
+#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L
+#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L
+#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L
+#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L
+#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L
+#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L
+#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L
+#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L
+#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L
+#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L
+#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L
+#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L
+
+/* DISP_PWR_MAN */
+#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L
+#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L
+#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L
+#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L
+#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L
+#define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L
+#define DISP_PWR_MAN__DISP_D3_RST 0x00010000L
+#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L
+#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L
+#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L
+#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L
+#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L
+#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L
+#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L
+#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L
+#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L
+#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L
+#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L
+#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L
+#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L
+#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L
+#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L
+#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L
+#define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L
+#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L
+#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L
+#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L
+
+/* MC_IND_INDEX */
+#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL
+#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L
+#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L
+
+/* MC_IND_DATA */
+#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL
+
+/* MC_CHP_IO_CNTL_A1 */
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a
+#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c
+#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e
+#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c
+#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e
+#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f
+
+/* MC_CHP_IO_CNTL_B1 */
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a
+#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c
+#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e
+#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c
+#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e
+#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f
+
+/* MC_CHP_IO_CNTL_A1 */
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L
+#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L
+#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L
+#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L
+
+/* MC_CHP_IO_CNTL_B1 */
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L
+#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L
+#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L
+#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L
+
+/* MEM_SDRAM_MODE_REG */
+#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL
+#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L
+#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L
+#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L
+#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L
+#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L
+#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L
+#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L
+#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L
+#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L
+#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L
+#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L
+#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L
+#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L
+#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L
+
+/* MEM_SDRAM_MODE_REG */
+#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000
+#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010
+#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014
+#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017
+#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b
+#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c
+#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d
+#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e
+#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f
+
+/* MEM_REFRESH_CNTL */
+#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL
+#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L
+#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L
+#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L
+#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L
+#define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L
+#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L
+#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L
+#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L
+#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L
+#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L
+#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L
+
+/* MC_STATUS */
+#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L
+#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L
+#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L
+#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L
+#define MC_STATUS__MC_IDLE_MASK 0x00000004L
+#define MC_STATUS__MC_IDLE 0x00000004L
+#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L
+#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L
+#define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L
+#define MC_STATUS__TEST_OUT_R_BACK 0x00000800L
+#define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L
+#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L
+#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L
+#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L
+#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L
+#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L
+
+/* MDLL_CKO */
+#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L
+#define MDLL_CKO__MCKOA_SLEEP 0x00000001L
+#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L
+#define MDLL_CKO__MCKOA_RESET 0x00000002L
+#define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL
+#define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L
+#define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L
+#define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L
+#define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L
+#define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L
+#define MDLL_CKO__MCKOA_BP_SEL 0x00008000L
+#define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L
+#define MDLL_CKO__MCKOB_SLEEP 0x00010000L
+#define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L
+#define MDLL_CKO__MCKOB_RESET 0x00020000L
+#define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L
+#define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L
+#define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L
+#define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L
+#define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L
+#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L
+#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L
+
+/* MDLL_RDCKA */
+#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L
+#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L
+#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L
+#define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L
+#define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL
+#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L
+#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L
+#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L
+#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L
+#define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L
+#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L
+#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L
+#define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L
+#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L
+#define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L
+#define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L
+#define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L
+#define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L
+#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L
+#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L
+#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L
+#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L
+#define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L
+#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L
+#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L
+#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L
+
+/* MDLL_RDCKB */
+#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L
+#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L
+#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L
+#define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L
+#define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL
+#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L
+#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L
+#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L
+#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L
+#define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L
+#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L
+#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L
+#define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L
+#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L
+#define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L
+#define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L
+#define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L
+#define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L
+#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L
+#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L
+#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L
+#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L
+#define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L
+#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L
+#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L
+#define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L
+
+#define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L
+#define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L
+#define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L
+#define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L
+#define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L
+#define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L
+#define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L
+#define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L
+
+#define pllCLK_PIN_CNTL 0x0001
+#define pllPPLL_CNTL 0x0002
+#define pllPPLL_REF_DIV 0x0003
+#define pllPPLL_DIV_0 0x0004
+#define pllPPLL_DIV_1 0x0005
+#define pllPPLL_DIV_2 0x0006
+#define pllPPLL_DIV_3 0x0007
+#define pllVCLK_ECP_CNTL 0x0008
+#define pllHTOTAL_CNTL 0x0009
+#define pllM_SPLL_REF_FB_DIV 0x000A
+#define pllAGP_PLL_CNTL 0x000B
+#define pllSPLL_CNTL 0x000C
+#define pllSCLK_CNTL 0x000D
+#define pllMPLL_CNTL 0x000E
+#define pllMDLL_CKO 0x000F
+#define pllMDLL_RDCKA 0x0010
+#define pllMDLL_RDCKB 0x0011
+#define pllMCLK_CNTL 0x0012
+#define pllPLL_TEST_CNTL 0x0013
+#define pllCLK_PWRMGT_CNTL 0x0014
+#define pllPLL_PWRMGT_CNTL 0x0015
+#define pllCG_TEST_MACRO_RW_WRITE 0x0016
+#define pllCG_TEST_MACRO_RW_READ 0x0017
+#define pllCG_TEST_MACRO_RW_DATA 0x0018
+#define pllCG_TEST_MACRO_RW_CNTL 0x0019
+#define pllDISP_TEST_MACRO_RW_WRITE 0x001A
+#define pllDISP_TEST_MACRO_RW_READ 0x001B
+#define pllDISP_TEST_MACRO_RW_DATA 0x001C
+#define pllDISP_TEST_MACRO_RW_CNTL 0x001D
+#define pllSCLK_CNTL2 0x001E
+#define pllMCLK_MISC 0x001F
+#define pllTV_PLL_FINE_CNTL 0x0020
+#define pllTV_PLL_CNTL 0x0021
+#define pllTV_PLL_CNTL1 0x0022
+#define pllTV_DTO_INCREMENTS 0x0023
+#define pllSPLL_AUX_CNTL 0x0024
+#define pllMPLL_AUX_CNTL 0x0025
+#define pllP2PLL_CNTL 0x002A
+#define pllP2PLL_REF_DIV 0x002B
+#define pllP2PLL_DIV_0 0x002C
+#define pllPIXCLKS_CNTL 0x002D
+#define pllHTOTAL2_CNTL 0x002E
+#define pllSSPLL_CNTL 0x0030
+#define pllSSPLL_REF_DIV 0x0031
+#define pllSSPLL_DIV_0 0x0032
+#define pllSS_INT_CNTL 0x0033
+#define pllSS_TST_CNTL 0x0034
+#define pllSCLK_MORE_CNTL 0x0035
+
+#define ixMC_PERF_CNTL 0x0000
+#define ixMC_PERF_SEL 0x0001
+#define ixMC_PERF_REGION_0 0x0002
+#define ixMC_PERF_REGION_1 0x0003
+#define ixMC_PERF_COUNT_0 0x0004
+#define ixMC_PERF_COUNT_1 0x0005
+#define ixMC_PERF_COUNT_2 0x0006
+#define ixMC_PERF_COUNT_3 0x0007
+#define ixMC_PERF_COUNT_MEMCH_A 0x0008
+#define ixMC_PERF_COUNT_MEMCH_B 0x0009
+#define ixMC_IMP_CNTL 0x000A
+#define ixMC_CHP_IO_CNTL_A0 0x000B
+#define ixMC_CHP_IO_CNTL_A1 0x000C
+#define ixMC_CHP_IO_CNTL_B0 0x000D
+#define ixMC_CHP_IO_CNTL_B1 0x000E
+#define ixMC_IMP_CNTL_0 0x000F
+#define ixTC_MISMATCH_1 0x0010
+#define ixTC_MISMATCH_2 0x0011
+#define ixMC_BIST_CTRL 0x0012
+#define ixREG_COLLAR_WRITE 0x0013
+#define ixREG_COLLAR_READ 0x0014
+#define ixR300_MC_IMP_CNTL 0x0018
+#define ixR300_MC_CHP_IO_CNTL_A0 0x0019
+#define ixR300_MC_CHP_IO_CNTL_A1 0x001a
+#define ixR300_MC_CHP_IO_CNTL_B0 0x001b
+#define ixR300_MC_CHP_IO_CNTL_B1 0x001c
+#define ixR300_MC_CHP_IO_CNTL_C0 0x001d
+#define ixR300_MC_CHP_IO_CNTL_C1 0x001e
+#define ixR300_MC_CHP_IO_CNTL_D0 0x001f
+#define ixR300_MC_CHP_IO_CNTL_D1 0x0020
+#define ixR300_MC_IMP_CNTL_0 0x0021
+#define ixR300_MC_ELPIDA_CNTL 0x0022
+#define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023
+#define ixR300_MC_READ_CNTL_CD 0x0024
+#define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025
+#define ixR300_MC_DEBUG_CNTL 0x0026
+#define ixR300_MC_BIST_CNTL_0 0x0028
+#define ixR300_MC_BIST_CNTL_1 0x0029
+#define ixR300_MC_BIST_CNTL_2 0x002a
+#define ixR300_MC_BIST_CNTL_3 0x002b
+#define ixR300_MC_BIST_CNTL_4 0x002c
+#define ixR300_MC_BIST_CNTL_5 0x002d
+#define ixR300_MC_IMP_STATUS 0x002e
+#define ixR300_MC_DLL_CNTL 0x002f
+#define NB_TOM 0x15C
+
+#endif /* _RADEON_H */
diff --git a/include/s3c2410.h b/include/s3c2410.h
index 86495f6..87135b4 100644
--- a/include/s3c2410.h
+++ b/include/s3c2410.h
@@ -69,75 +69,75 @@ typedef enum {
#include <s3c24x0.h>
-static inline S3C24X0_MEMCTL * const S3C24X0_GetBase_MEMCTL(void)
+static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void)
{
return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
}
-static inline S3C24X0_USB_HOST * const S3C24X0_GetBase_USB_HOST(void)
+static inline S3C24X0_USB_HOST * S3C24X0_GetBase_USB_HOST(void)
{
return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
}
-static inline S3C24X0_INTERRUPT * const S3C24X0_GetBase_INTERRUPT(void)
+static inline S3C24X0_INTERRUPT * S3C24X0_GetBase_INTERRUPT(void)
{
return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
}
-static inline S3C24X0_DMAS * const S3C24X0_GetBase_DMAS(void)
+static inline S3C24X0_DMAS * S3C24X0_GetBase_DMAS(void)
{
return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
}
-static inline S3C24X0_CLOCK_POWER * const S3C24X0_GetBase_CLOCK_POWER(void)
+static inline S3C24X0_CLOCK_POWER * S3C24X0_GetBase_CLOCK_POWER(void)
{
return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
}
-static inline S3C24X0_LCD * const S3C24X0_GetBase_LCD(void)
+static inline S3C24X0_LCD * S3C24X0_GetBase_LCD(void)
{
return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
}
-static inline S3C2410_NAND * const S3C2410_GetBase_NAND(void)
+static inline S3C2410_NAND * S3C2410_GetBase_NAND(void)
{
return (S3C2410_NAND * const)S3C2410_NAND_BASE;
}
-static inline S3C24X0_UART * const S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
+static inline S3C24X0_UART * S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
{
return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
}
-static inline S3C24X0_TIMERS * const S3C24X0_GetBase_TIMERS(void)
+static inline S3C24X0_TIMERS * S3C24X0_GetBase_TIMERS(void)
{
return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
}
-static inline S3C24X0_USB_DEVICE * const S3C24X0_GetBase_USB_DEVICE(void)
+static inline S3C24X0_USB_DEVICE * S3C24X0_GetBase_USB_DEVICE(void)
{
return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
}
-static inline S3C24X0_WATCHDOG * const S3C24X0_GetBase_WATCHDOG(void)
+static inline S3C24X0_WATCHDOG * S3C24X0_GetBase_WATCHDOG(void)
{
return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
}
-static inline S3C24X0_I2C * const S3C24X0_GetBase_I2C(void)
+static inline S3C24X0_I2C * S3C24X0_GetBase_I2C(void)
{
return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
}
-static inline S3C24X0_I2S * const S3C24X0_GetBase_I2S(void)
+static inline S3C24X0_I2S * S3C24X0_GetBase_I2S(void)
{
return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
}
-static inline S3C24X0_GPIO * const S3C24X0_GetBase_GPIO(void)
+static inline S3C24X0_GPIO * S3C24X0_GetBase_GPIO(void)
{
return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
}
-static inline S3C24X0_RTC * const S3C24X0_GetBase_RTC(void)
+static inline S3C24X0_RTC * S3C24X0_GetBase_RTC(void)
{
return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
}
-static inline S3C2410_ADC * const S3C2410_GetBase_ADC(void)
+static inline S3C2410_ADC * S3C2410_GetBase_ADC(void)
{
return (S3C2410_ADC * const)S3C2410_ADC_BASE;
}
-static inline S3C24X0_SPI * const S3C24X0_GetBase_SPI(void)
+static inline S3C24X0_SPI * S3C24X0_GetBase_SPI(void)
{
return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
}
-static inline S3C2410_SDI * const S3C2410_GetBase_SDI(void)
+static inline S3C2410_SDI * S3C2410_GetBase_SDI(void)
{
return (S3C2410_SDI * const)S3C2410_SDI_BASE;
}
diff --git a/include/sata.h b/include/sata.h
new file mode 100644
index 0000000..165b471
--- /dev/null
+++ b/include/sata.h
@@ -0,0 +1,108 @@
+
+#if (DEBUG_SATA)
+#define PRINTF(fmt,args...) printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+struct sata_ioports {
+ unsigned long cmd_addr;
+ unsigned long data_addr;
+ unsigned long error_addr;
+ unsigned long feature_addr;
+ unsigned long nsect_addr;
+ unsigned long lbal_addr;
+ unsigned long lbam_addr;
+ unsigned long lbah_addr;
+ unsigned long device_addr;
+ unsigned long status_addr;
+ unsigned long command_addr;
+ unsigned long altstatus_addr;
+ unsigned long ctl_addr;
+ unsigned long bmdma_addr;
+ unsigned long scr_addr;
+};
+
+struct sata_port {
+ unsigned char port_no; /* primary=0, secondary=1 */
+ struct sata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */
+ unsigned char ctl_reg;
+ unsigned char last_ctl;
+ unsigned char port_state; /* 1-port is available and */
+ /* 0-port is not available */
+ unsigned char dev_mask;
+};
+
+/***********SATA LIBRARY SPECIFIC DEFINITIONS AND DECLARATIONS**************/
+#ifdef SATA_DECL /*SATA library specific declarations */
+#define ata_id_has_lba48(id) ((id)[83] & (1 << 10))
+#define ata_id_has_lba(id) ((id)[49] & (1 << 9))
+#define ata_id_has_dma(id) ((id)[49] & (1 << 8))
+#define ata_id_u32(id,n) \
+ (((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)]))
+#define ata_id_u64(id,n) \
+ (((u64) (id)[(n) + 3] << 48) | \
+ ((u64) (id)[(n) + 2] << 32) | \
+ ((u64) (id)[(n) + 1] << 16) | \
+ ((u64) (id)[(n) + 0]) )
+#endif
+
+#ifdef SATA_DECL /*SATA library specific declarations */
+static inline void
+ata_dump_id (u16 * id)
+{
+ PRINTF ("49==0x%04x "
+ "53==0x%04x "
+ "63==0x%04x "
+ "64==0x%04x "
+ "75==0x%04x \n", id[49], id[53], id[63], id[64], id[75]);
+ PRINTF ("80==0x%04x "
+ "81==0x%04x "
+ "82==0x%04x "
+ "83==0x%04x "
+ "84==0x%04x \n", id[80], id[81], id[82], id[83], id[84]);
+ PRINTF ("88==0x%04x " "93==0x%04x\n", id[88], id[93]);
+}
+#endif
+
+#ifdef SATA_DECL /*SATA library specific declarations */
+int sata_bus_softreset (int num);
+void sata_identify (int num, int dev);
+void sata_port (struct sata_ioports *ioport);
+void set_Feature_cmd (int num, int dev);
+int sata_devchk (struct sata_ioports *ioaddr, int dev);
+void dev_select (struct sata_ioports *ioaddr, int dev);
+u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max);
+u8 sata_chk_status (struct sata_ioports *ioaddr);
+ulong sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buffer);
+ulong sata_write (int device,ulong blknr, lbaint_t blkcnt, void * buffer);
+void msleep (int count);
+#else
+extern int sata_bus_softreset (int num);
+extern void sata_identify (int num, int dev);
+extern void sata_port (struct sata_ioports *ioport);
+extern void set_Feature_cmd (int num, int dev);
+extern ulong sata_read (int device, ulong blknr,
+ lbaint_t blkcnt, void * buffer);
+extern ulong sata_write (int device, ulong blknr,
+ lbaint_t blkcnt, void * buffer);
+extern void msleep (int count);
+#endif
+
+/************DRIVER SPECIFIC DEFINITIONS AND DECLARATIONS**************/
+
+#ifdef DRV_DECL /*Driver specific declaration */
+int init_sata (void);
+#else
+extern int init_sata (void);
+#endif
+
+#ifdef DRV_DECL /*Defines Driver Specific variables */
+struct sata_port port[CFG_SATA_MAXBUS];
+block_dev_desc_t sata_dev_desc[CFG_SATA_MAXDEVICES];
+int curr_dev = -1;
+#else
+extern struct sata_port port[CFG_SATA_MAXBUS];
+extern block_dev_desc_t sata_dev_desc[CFG_SATA_MAXDEVICES];
+extern int curr_dev;
+#endif
diff --git a/include/serial.h b/include/serial.h
index f7412fd..30bfde3 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -36,6 +36,10 @@ extern struct serial_device eserial4_device;
#endif
+extern struct serial_device serial_ffuart_device;
+extern struct serial_device serial_btuart_device;
+extern struct serial_device serial_stuart_device;
+
extern void serial_initialize(void);
extern void serial_devices_init(void);
extern int serial_assign(char * name);
diff --git a/include/sha1.h b/include/sha1.h
new file mode 100644
index 0000000..15ea13c
--- /dev/null
+++ b/include/sha1.h
@@ -0,0 +1,115 @@
+/**
+ * \file sha1.h
+ * based from http://xyssl.org/code/source/sha1/
+ * FIPS-180-1 compliant SHA-1 implementation
+ *
+ * Copyright (C) 2003-2006 Christophe Devine
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License, version 2.1 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+/*
+ * The SHA-1 standard was published by NIST in 1993.
+ *
+ * http://www.itl.nist.gov/fipspubs/fip180-1.htm
+ */
+#ifndef _SHA1_H
+#define _SHA1_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SHA1_SUM_POS -0x20
+#define SHA1_SUM_LEN 20
+
+/**
+ * \brief SHA-1 context structure
+ */
+typedef struct
+{
+ unsigned long total[2]; /*!< number of bytes processed */
+ unsigned long state[5]; /*!< intermediate digest state */
+ unsigned char buffer[64]; /*!< data block being processed */
+}
+sha1_context;
+
+/**
+ * \brief SHA-1 context setup
+ *
+ * \param ctx SHA-1 context to be initialized
+ */
+void sha1_starts( sha1_context *ctx );
+
+/**
+ * \brief SHA-1 process buffer
+ *
+ * \param ctx SHA-1 context
+ * \param input buffer holding the data
+ * \param ilen length of the input data
+ */
+void sha1_update( sha1_context *ctx, unsigned char *input, int ilen );
+
+/**
+ * \brief SHA-1 final digest
+ *
+ * \param ctx SHA-1 context
+ * \param output SHA-1 checksum result
+ */
+void sha1_finish( sha1_context *ctx, unsigned char output[20] );
+
+/**
+ * \brief Output = SHA-1( input buffer )
+ *
+ * \param input buffer holding the data
+ * \param ilen length of the input data
+ * \param output SHA-1 checksum result
+ */
+void sha1_csum( unsigned char *input, int ilen,
+ unsigned char output[20] );
+
+/**
+ * \brief Output = SHA-1( file contents )
+ *
+ * \param path input file name
+ * \param output SHA-1 checksum result
+ * \return 0 if successful, or 1 if fopen failed
+ */
+int sha1_file( char *path, unsigned char output[20] );
+
+/**
+ * \brief Output = HMAC-SHA-1( input buffer, hmac key )
+ *
+ * \param key HMAC secret key
+ * \param keylen length of the HMAC key
+ * \param input buffer holding the data
+ * \param ilen length of the input data
+ * \param output HMAC-SHA-1 result
+ */
+void sha1_hmac( unsigned char *key, int keylen,
+ unsigned char *input, int ilen,
+ unsigned char output[20] );
+
+/**
+ * \brief Checkup routine
+ *
+ * \return 0 if successful, or 1 if the test failed
+ */
+int sha1_self_test( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* sha1.h */
diff --git a/include/spartan3.h b/include/spartan3.h
index b14db03..65a3f5a 100644
--- a/include/spartan3.h
+++ b/include/spartan3.h
@@ -73,6 +73,13 @@ typedef struct {
#define XILINX_XC3S4000_SIZE 11316864/8
#define XILINX_XC3S5000_SIZE 13271936/8
+/* Spartan-3E (v3.4) */
+#define XILINX_XC3S100E_SIZE 581344/8
+#define XILINX_XC3S250E_SIZE 1353728/8
+#define XILINX_XC3S500E_SIZE 2270208/8
+#define XILINX_XC3S1200E_SIZE 3841184/8
+#define XILINX_XC3S1600E_SIZE 5969696/8
+
/* Descriptor Macros
*********************************************************************/
/* Spartan-II devices */
@@ -100,4 +107,21 @@ typedef struct {
#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S5000E_SIZE, fn_table, cookie }
+
+/* Spartan-3E devices */
+#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie }
+
#endif /* _SPARTAN3_H_ */
diff --git a/include/status_led.h b/include/status_led.h
index db4c60f..a646814 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -355,6 +355,25 @@ void status_led_set (int led, int state);
# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+#elif defined(CONFIG_MOTIONPRO)
+
+#define STATUS_LED_BIT ((vu_long *) MPC5XXX_GPT6_ENABLE)
+#define STATUS_LED_PERIOD (CFG_HZ / 10)
+#define STATUS_LED_STATE STATUS_LED_BLINKING
+
+#define STATUS_LED_BIT1 ((vu_long *) MPC5XXX_GPT7_ENABLE)
+#define STATUS_LED_PERIOD1 (CFG_HZ / 10)
+#define STATUS_LED_STATE1 STATUS_LED_OFF
+
+#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+
+#elif defined(CONFIG_BOARD_SPECIFIC_LED)
+/* led_id_t is unsigned long mask */
+typedef unsigned long led_id_t;
+
+extern void __led_toggle (led_id_t mask);
+extern void __led_init (led_id_t mask, int state);
+extern void __led_set (led_id_t mask, int state);
#else
# error Status LED configuration missing
#endif
diff --git a/include/usb.h b/include/usb.h
index bf71554..4e1539f 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -169,7 +169,10 @@ struct usb_device {
* this is how the lowlevel part communicate with the outer world
*/
-#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined (CONFIG_USB_SL811HS)
+#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \
+ defined(CONFIG_USB_OHCI_NEW) || defined (CONFIG_USB_SL811HS) || \
+ defined(CONFIG_USB_ISP116X_HCD)
+
int usb_lowlevel_init(void);
int usb_lowlevel_stop(void);
int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len);
@@ -177,6 +180,7 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
int transfer_len,struct devrequest *setup);
int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
int transfer_len, int interval);
+void usb_event_poll(void);
/* Defines */
#define USB_UHCI_VEND_ID 0x8086
@@ -230,16 +234,12 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate);
/* big endian -> little endian conversion */
/* some CPUs are already little endian e.g. the ARM920T */
-#ifdef LITTLEENDIAN
-#define swap_16(x) ((unsigned short)(x))
-#define swap_32(x) ((unsigned long)(x))
-#else
-#define swap_16(x) \
+#define __swap_16(x) \
({ unsigned short x_ = (unsigned short)x; \
(unsigned short)( \
((x_ & 0x00FFU) << 8) | ((x_ & 0xFF00U) >> 8) ); \
})
-#define swap_32(x) \
+#define __swap_32(x) \
({ unsigned long x_ = (unsigned long)x; \
(unsigned long)( \
((x_ & 0x000000FFUL) << 24) | \
@@ -247,6 +247,13 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate);
((x_ & 0x00FF0000UL) >> 8) | \
((x_ & 0xFF000000UL) >> 24) ); \
})
+
+#ifdef LITTLEENDIAN
+# define swap_16(x) (x)
+# define swap_32(x) (x)
+#else
+# define swap_16(x) __swap_16(x)
+# define swap_32(x) __swap_32(x)
#endif /* LITTLEENDIAN */
/*
diff --git a/include/usb_cdc_acm.h b/include/usb_cdc_acm.h
new file mode 100644
index 0000000..87bf50c
--- /dev/null
+++ b/include/usb_cdc_acm.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2006
+ * Bryan O'Donoghue, deckard@codehermit.ie, CodeHermit
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+/* ACM Control Requests */
+#define ACM_SEND_ENCAPSULATED_COMMAND 0x00
+#define ACM_GET_ENCAPSULATED_RESPONSE 0x01
+#define ACM_SET_COMM_FEATURE 0x02
+#define ACM_GET_COMM_FEATRUE 0x03
+#define ACM_CLEAR_COMM_FEATURE 0x04
+#define ACM_SET_LINE_ENCODING 0x20
+#define ACM_GET_LINE_ENCODING 0x21
+#define ACM_SET_CONTROL_LINE_STATE 0x22
+#define ACM_SEND_BREAK 0x23
+
+/* ACM Notification Codes */
+#define ACM_NETWORK_CONNECTION 0x00
+#define ACM_RESPONSE_AVAILABLE 0x01
+#define ACM_SERIAL_STATE 0x20
+
+/* Format of response expected by a ACM_GET_LINE_ENCODING request */
+struct rs232_emu{
+ unsigned long dter;
+ unsigned char stop_bits;
+ unsigned char parity;
+ unsigned char data_bits;
+}__attribute__((packed));
diff --git a/include/usbdcore.h b/include/usbdcore.h
index 6e92df1..cb2be72 100644
--- a/include/usbdcore.h
+++ b/include/usbdcore.h
@@ -576,6 +576,9 @@ struct usb_device_instance {
void (*event) (struct usb_device_instance *device, usb_device_event_t event, int data);
+ /* Do cdc device specific control requests */
+ int (*cdc_recv_setup)(struct usb_device_request *request, struct urb *urb);
+
/* bus interface */
struct usb_bus_instance *bus; /* which bus interface driver */
diff --git a/include/usbdcore_mpc8xx.h b/include/usbdcore_mpc8xx.h
new file mode 100644
index 0000000..9df62f4
--- /dev/null
+++ b/include/usbdcore_mpc8xx.h
@@ -0,0 +1,210 @@
+/*
+ * Copyright (C) 2006 Bryan O'Donoghue, CodeHermit
+ * bodonoghue@codehermit.ie
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the
+ * Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ */
+
+#include <commproc.h>
+
+/* Mode Register */
+#define USMOD_EN 0x01
+#define USMOD_HOST 0x02
+#define USMOD_TEST 0x04
+#define USMOD_SFTE 0x08
+#define USMOD_RESUME 0x40
+#define USMOD_LSS 0x80
+
+/* Endpoint Registers */
+#define USEP_RHS_NORM 0x00
+#define USEP_RHS_IGNORE 0x01
+#define USEP_RHS_NAK 0x02
+#define USEP_RHS_STALL 0x03
+
+#define USEP_THS_NORM 0x00
+#define USEP_THS_IGNORE 0x04
+#define USEP_THS_NAK 0x08
+#define USEP_THS_STALL 0x0C
+
+#define USEP_RTE 0x10
+#define USEP_MF 0x20
+
+#define USEP_TM_CONTROL 0x00
+#define USEP_TM_INT 0x100
+#define USEP_TM_BULK 0x200
+#define USEP_TM_ISO 0x300
+
+/* Command Register */
+#define USCOM_EP0 0x00
+#define USCOM_EP1 0x01
+#define USCOM_EP2 0x02
+#define USCOM_EP3 0x03
+
+#define USCOM_FLUSH 0x40
+#define USCOM_STR 0x80
+
+/* Event Register */
+#define USB_E_RXB 0x0001
+#define USB_E_TXB 0x0002
+#define USB_E_BSY 0x0004
+#define USB_E_SOF 0x0008
+#define USB_E_TXE1 0x0010
+#define USB_E_TXE2 0x0020
+#define USB_E_TXE3 0x0040
+#define USB_E_TXE4 0x0080
+#define USB_TX_ERRMASK (USB_E_TXE1|USB_E_TXE2|USB_E_TXE3|USB_E_TXE4)
+#define USB_E_IDLE 0x0100
+#define USB_E_RESET 0x0200
+
+/* Mask Register */
+#define USBS_IDLE 0x01
+
+/* RX Buffer Descriptor */
+#define RX_BD_OV 0x02
+#define RX_BD_CR 0x04
+#define RX_BD_AB 0x08
+#define RX_BD_NO 0x10
+#define RX_BD_PID_DATA0 0x00
+#define RX_BD_PID_DATA1 0x40
+#define RX_BD_PID_SETUP 0x80
+#define RX_BD_F 0x400
+#define RX_BD_L 0x800
+#define RX_BD_I 0x1000
+#define RX_BD_W 0x2000
+#define RX_BD_E 0x8000
+
+/* Useful masks */
+#define RX_BD_PID_BITMASK (RX_BD_PID_DATA1 | RX_BD_PID_SETUP)
+#define STALL_BITMASK (USEP_THS_STALL | USEP_RHS_STALL)
+#define NAK_BITMASK (USEP_THS_NAK | USEP_RHS_NAK)
+#define CBD_TX_BITMASK (TX_BD_R | TX_BD_L | TX_BD_TC | TX_BD_I | TX_BD_CNF)
+
+/* TX Buffer Descriptor */
+#define TX_BD_UN 0x02
+#define TX_BD_TO 0x04
+#define TX_BD_NO_PID 0x00
+#define TX_BD_PID_DATA0 0x80
+#define TX_BD_PID_DATA1 0xC0
+#define TX_BD_CNF 0x200
+#define TX_BD_TC 0x400
+#define TX_BD_L 0x800
+#define TX_BD_I 0x1000
+#define TX_BD_W 0x2000
+#define TX_BD_R 0x8000
+
+/* Implementation specific defines */
+
+#define EP_MIN_PACKET_SIZE 0x08
+#define MAX_ENDPOINTS 0x04
+#define FIFO_SIZE 0x10
+#define EP_MAX_PKT FIFO_SIZE
+#define TX_RING_SIZE 0x04
+#define RX_RING_SIZE 0x06
+#define USB_MAX_PKT 0x40
+#define TOGGLE_TX_PID(x) x= ((~x)&0x40)|0x80
+#define TOGGLE_RX_PID(x) x^= 0x40
+#define EP_ATTACHED 0x01 /* Endpoint has a urb attached or not */
+#define EP_SEND_ZLP 0x02 /* Send ZLP y/n ? */
+
+#define PROFF_USB 0x00000000
+#define CPM_USB_BASE 0x00000A00
+
+/* UDC device defines */
+#define EP0_MAX_PACKET_SIZE EP_MAX_PKT
+#define UDC_OUT_ENDPOINT 0x02
+#define UDC_OUT_PACKET_SIZE EP_MIN_PACKET_SIZE
+#define UDC_IN_ENDPOINT 0x03
+#define UDC_IN_PACKET_SIZE EP_MIN_PACKET_SIZE
+#define UDC_INT_ENDPOINT 0x01
+#define UDC_INT_PACKET_SIZE UDC_IN_PACKET_SIZE
+#define UDC_BULK_PACKET_SIZE EP_MIN_PACKET_SIZE
+
+struct mpc8xx_ep {
+ struct urb * urb;
+ unsigned char pid;
+ unsigned char sc;
+ volatile cbd_t * prx;
+};
+
+typedef struct mpc8xx_usb{
+ char usmod; /* Mode Register */
+ char usaddr; /* Slave Address Register */
+ char uscom; /* Command Register */
+ char res1; /* Reserved */
+ ushort usep[4];
+ ulong res2; /* Reserved */
+ ushort usber; /* Event Register */
+ ushort res3; /* Reserved */
+ ushort usbmr; /* Mask Register */
+ char res4; /* Reserved */
+ char usbs; /* Status Register */
+ char res5[8]; /* Reserved */
+}usb_t;
+
+typedef struct mpc8xx_parameter_ram{
+ ushort ep0ptr; /* Endpoint Pointer Register 0 */
+ ushort ep1ptr; /* Endpoint Pointer Register 1 */
+ ushort ep2ptr; /* Endpoint Pointer Register 2 */
+ ushort ep3ptr; /* Endpoint Pointer Register 3 */
+ uint rstate; /* Receive state */
+ uint rptr; /* Receive internal data pointer */
+ ushort frame_n; /* Frame number */
+ ushort rbcnt; /* Receive byte count */
+ uint rtemp; /* Receive temp cp use only */
+ uint rxusb; /* Rx Data Temp */
+ ushort rxuptr; /* Rx microcode return address temp */
+}usb_pram_t;
+
+typedef struct endpoint_parameter_block_pointer{
+ ushort rbase; /* RxBD base address */
+ ushort tbase; /* TxBD base address */
+ char rfcr; /* Rx Function code */
+ char tfcr; /* Tx Function code */
+ ushort mrblr; /* Maximum Receive Buffer Length */
+ ushort rbptr; /* RxBD pointer Next Buffer Descriptor */
+ ushort tbptr; /* TxBD pointer Next Buffer Descriptor */
+ ulong tstate; /* Transmit internal state */
+ ulong tptr; /* Transmit internal data pointer */
+ ushort tcrc; /* Transmit temp CRC */
+ ushort tbcnt; /* Transmit internal bye count */
+ ulong ttemp; /* Tx temp */
+ ushort txuptr; /* Tx microcode return address */
+ ushort res1; /* Reserved */
+}usb_epb_t;
+
+typedef enum mpc8xx_udc_state{
+ STATE_NOT_READY,
+ STATE_ERROR,
+ STATE_READY,
+}mpc8xx_udc_state_t;
+
+/* Declarations */
+int udc_init(void);
+void udc_irq(void);
+int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
+void udc_setup_ep(struct usb_device_instance *device, unsigned int ep,
+ struct usb_endpoint_instance *endpoint);
+void udc_connect(void);
+void udc_disconnect(void);
+void udc_enable(struct usb_device_instance *device);
+void udc_disable(void);
+void udc_startup_events(struct usb_device_instance *device);
+
+/* Flow control */
+void udc_set_nak(int epid);
+void udc_unset_nak (int epid);
diff --git a/include/usbdcore_omap1510.h b/include/usbdcore_omap1510.h
index 6ea3331..526fcd9 100644
--- a/include/usbdcore_omap1510.h
+++ b/include/usbdcore_omap1510.h
@@ -161,10 +161,20 @@
#define UDC_VBUS_CTRL (1 << 19)
#define UDC_VBUS_MODE (1 << 18)
-
-void omap1510_udc_irq(void);
-void omap1510_udc_noniso_irq(void);
-
+/* OMAP Endpoint parameters */
+#define EP0_MAX_PACKET_SIZE 64
+#define UDC_OUT_ENDPOINT 2
+#define UDC_OUT_PACKET_SIZE 64
+#define UDC_IN_ENDPOINT 1
+#define UDC_IN_PACKET_SIZE 64
+#define UDC_INT_ENDPOINT 5
+#define UDC_INT_PKTSIZE 16
+#define UDC_BULK_PKTSIZE 16
+
+void udc_irq (void);
+/* Flow control */
+void udc_set_nak(int epid);
+void udc_unset_nak (int epid);
/* Higher level functions for abstracting away from specific device */
void udc_endpoint_write(struct usb_endpoint_instance *endpoint);
diff --git a/include/usbdescriptors.h b/include/usbdescriptors.h
index 2d9f739..a752097 100644
--- a/include/usbdescriptors.h
+++ b/include/usbdescriptors.h
@@ -92,33 +92,42 @@
#define COMMUNICATIONS_DEVICE_CLASS 0x02
/* c.f. CDC 4.2 Table 15 */
-#define COMMUNICATIONS_INTERFACE_CLASS 0x02
+#define COMMUNICATIONS_INTERFACE_CLASS_CONTROL 0x02
+#define COMMUNICATIONS_INTERFACE_CLASS_DATA 0x0A
+#define COMMUNICATIONS_INTERFACE_CLASS_VENDOR 0x0FF
/* c.f. CDC 4.3 Table 16 */
-#define COMMUNICATIONS_NO_SUBCLASS 0x00
+#define COMMUNICATIONS_NO_SUBCLASS 0x00
#define COMMUNICATIONS_DLCM_SUBCLASS 0x01
-#define COMMUNICATIONS_ACM_SUBCLASS 0x02
-#define COMMUNICATIONS_TCM_SUBCLASS 0x03
+#define COMMUNICATIONS_ACM_SUBCLASS 0x02
+#define COMMUNICATIONS_TCM_SUBCLASS 0x03
#define COMMUNICATIONS_MCCM_SUBCLASS 0x04
-#define COMMUNICATIONS_CCM_SUBCLASS 0x05
+#define COMMUNICATIONS_CCM_SUBCLASS 0x05
#define COMMUNICATIONS_ENCM_SUBCLASS 0x06
#define COMMUNICATIONS_ANCM_SUBCLASS 0x07
/* c.f. WMCD 5.1 */
#define COMMUNICATIONS_WHCM_SUBCLASS 0x08
-#define COMMUNICATIONS_DMM_SUBCLASS 0x09
+#define COMMUNICATIONS_DMM_SUBCLASS 0x09
#define COMMUNICATIONS_MDLM_SUBCLASS 0x0a
#define COMMUNICATIONS_OBEX_SUBCLASS 0x0b
-/* c.f. CDC 4.6 Table 18 */
+/* c.f. CDC 4.4 Table 17 */
+#define COMMUNICATIONS_NO_PROTOCOL 0x00
+#define COMMUNICATIONS_V25TER_PROTOCOL 0x01 /*Common AT Hayes compatible*/
+
+/* c.f. CDC 4.5 Table 18 */
#define DATA_INTERFACE_CLASS 0x0a
+/* c.f. CDC 4.6 No Table */
+#define DATA_INTERFACE_SUBCLASS_NONE 0x00 /* No subclass pertinent */
+
/* c.f. CDC 4.7 Table 19 */
-#define COMMUNICATIONS_NO_PROTOCOL 0x00
+#define DATA_INTERFACE_PROTOCOL_NONE 0x00 /* No class protcol required */
/* c.f. CDC 5.2.3 Table 24 */
-#define CS_INTERFACE 0x24
+#define CS_INTERFACE 0x24
#define CS_ENDPOINT 0x25
/*
@@ -128,7 +137,7 @@
* c.f. WMCD 5.3 Table 5.3
*/
-#define USB_ST_HEADER 0x00
+#define USB_ST_HEADER 0x00
#define USB_ST_CMF 0x01
#define USB_ST_ACMF 0x02
#define USB_ST_DLMF 0x03
@@ -137,18 +146,18 @@
#define USB_ST_UF 0x06
#define USB_ST_CSF 0x07
#define USB_ST_TOMF 0x08
-#define USB_ST_USBTF 0x09
+#define USB_ST_USBTF 0x09
#define USB_ST_NCT 0x0a
#define USB_ST_PUF 0x0b
#define USB_ST_EUF 0x0c
#define USB_ST_MCMF 0x0d
#define USB_ST_CCMF 0x0e
#define USB_ST_ENF 0x0f
-#define USB_ST_ATMNF 0x10
+#define USB_ST_ATMNF 0x10
#define USB_ST_WHCM 0x11
#define USB_ST_MDLM 0x12
-#define USB_ST_MDLMD 0x13
+#define USB_ST_MDLMD 0x13
#define USB_ST_DMM 0x14
#define USB_ST_OBEX 0x15
#define USB_ST_CS 0x16
@@ -312,7 +321,8 @@ struct usb_class_union_function_descriptor {
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x06 */
u8 bMasterInterface;
- u8 bSlaveInterface0[0];
+ /* u8 bSlaveInterface0[0]; */
+ u8 bSlaveInterface0;
} __attribute__ ((packed));
struct usb_class_country_selection_descriptor {