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authorPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>2016-06-03 18:41:34 +0530
committerYork Sun <york.sun@nxp.com>2016-06-03 14:12:51 -0700
commit9d044fcb8c4558d7ec28089375d2de565bfd2619 (patch)
treee68e120c5097856a2e1aa7033c7c569eabf9c785 /include
parent16dacb26a5e5ec58e00ec9d1a83d0ccceb8b0de5 (diff)
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armv8: ls1012a: Add support of ls1012aqds board
QorIQ LS1012A Development System (LS1012AQDS) is a high-performance development platform, with a complete debugging environment. The LS1012AQDS board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/ls1012a_common.h145
-rw-r--r--include/configs/ls1012aqds.h191
2 files changed, 336 insertions, 0 deletions
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
new file mode 100644
index 0000000..ccd94ec
--- /dev/null
+++ b/include/configs/ls1012a_common.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1012A_COMMON_H
+#define __LS1012A_COMMON_H
+
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_FSL_LSCH2
+#define CONFIG_LS1012A
+#define CONFIG_GICV2
+
+#define CONFIG_SYS_HAS_SERDES
+
+#include <asm/arch/config.h>
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#define CONFIG_SYS_TEXT_BASE 0x40100000
+
+#define CONFIG_SYS_FSL_CLK
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 125000000
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F 1
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 /* 25MHz */
+
+/* CSU */
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+
+/*SPI device */
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 1000000
+#define CONFIG_ENV_SPI_MODE 0x03
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_FSL_SPI_INTERFACE
+#define CONFIG_SF_DATAFLASH
+
+#define CONFIG_FSL_QSPI
+#define QSPI0_AMBA_BASE 0x40000000
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_BAR
+
+#define FSL_QSPI_FLASH_SIZE (1 << 24)
+#define FSL_QSPI_FLASH_NUM 2
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE 0x40000 /* 256KB */
+#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */
+#define CONFIG_ENV_SECT_SIZE 0x40000
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* Command line configuration */
+#define CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE 128
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "initrd_high=0xffffffff\0" \
+ "verify=no\0" \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "loadaddr=0x80100000\0" \
+ "kernel_addr=0x100000\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0xa00000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "console=ttyAMA0,38400n8\0"
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
+ "earlycon=uart8250,mmio,0x21c0500"
+#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
+ "$kernel_start $kernel_size && "\
+ "bootm $kernel_load"
+#define CONFIG_BOOTDELAY 10
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS 64 /* max command args */
+
+#define CONFIG_PANIC_HANG
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1012A_COMMON_H */
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
new file mode 100644
index 0000000..2d84095
--- /dev/null
+++ b/include/configs/ls1012aqds.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1012AQDS_H__
+#define __LS1012AQDS_H__
+
+#include "ls1012a_common.h"
+
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define QIXIS_LBMAP_BRDCFG_REG 0x04
+#define QIXIS_LBMAP_SWITCH 6
+#define QIXIS_LBMAP_MASK 0xf7
+#define QIXIS_LBMAP_SHIFT 0
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x08
+#define QIXIS_RST_CTL_RESET 0x41
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#endif
+
+/*
+ * I2C bus multiplexer
+ */
+#define I2C_MUX_PCA_ADDR_PRI 0x77
+#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR 0x18
+#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_CH7301 0xC
+#define I2C_MUX_CH5 0xD
+#define I2C_MUX_CH7 0xF
+
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+
+/*
+* RTC configuration
+*/
+#define RTC
+#define CONFIG_RTC_PCF8563 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
+#define CONFIG_CMD_DATE
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
+/* DSPI */
+#define CONFIG_FSL_DSPI1
+#define CONFIG_DEFAULT_SPI_BUS 1
+
+#define CONFIG_CMD_SPI
+#define MMAP_DSPI DSPI1_BASE_ADDR
+
+#define CONFIG_SYS_DSPI_CTAR0 1
+
+#define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
+ DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_SST /* cs1 */
+
+#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+ DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
+ DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
+
+#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
+ DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_EON /* cs3 */
+
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_BUS 1
+#define CONFIG_SF_DEFAULT_CS 0
+
+/*
+* USB
+*/
+/* EHCI Support - disbaled by default */
+/*#define CONFIG_HAS_FSL_DR_USB*/
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+/*XHCI Support - enabled by default*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE
+#endif
+
+/* MMC */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controller 1 */
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+#define CONFIG_MISC_INIT_R
+
+#endif /* __LS1012AQDS_H__ */