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authorWolfgang Denk <wd@denx.de>2010-05-21 22:22:23 +0200
committerWolfgang Denk <wd@denx.de>2010-05-21 22:22:23 +0200
commit8a452c2c17bc284e3f91b8ed4aec9d2b9b342df7 (patch)
tree95d411f913fa4634df6ba86ce7af4bbbe98a92c0 /include
parent445093d175b06226549680b6894923bb0f5e50fa (diff)
parent03af5abd85637d27e96fb999ce6e3992293570b0 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-imx
Diffstat (limited to 'include')
-rw-r--r--include/configs/imx31_litekit.h19
-rw-r--r--include/configs/mx31ads.h8
-rw-r--r--include/configs/mx31pdk.h9
-rw-r--r--include/configs/mx51evk.h15
-rw-r--r--include/configs/qong.h16
-rw-r--r--include/fsl_pmic.h128
-rw-r--r--include/mc13892.h160
7 files changed, 344 insertions, 11 deletions
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 6131008..4904856 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -68,10 +68,13 @@
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC
+#define CONFIG_FSL_PMIC_BUS 1
+#define CONFIG_FSL_PMIC_CS 0
+#define CONFIG_FSL_PMIC_CLK 1000000
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+
#define CONFIG_RTC_MC13783 1
-/* MC13783 connected to CSPI2 and SS0 */
-#define CONFIG_MC13783_SPI_BUS 1
-#define CONFIG_MC13783_SPI_CS 0
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
@@ -89,6 +92,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_SPI
#define CONFIG_CMD_DATE
+#define CONFIG_CMD_NAND
#define CONFIG_BOOTDELAY 3
@@ -174,4 +178,13 @@
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV "nor0"
+/*
+ * NAND flash
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
+#define CONFIG_MXC_NAND_HWECC
+
#endif /* __CONFIG_H */
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index ec1c905..dedecd7 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -65,10 +65,12 @@
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC
+#define CONFIG_FSL_PMIC_BUS 1
+#define CONFIG_FSL_PMIC_CS 0
+#define CONFIG_FSL_PMIC_CLK 1000000
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1
-/* MC13783 connected to CSPI2 and SS0 */
-#define CONFIG_MC13783_SPI_BUS 1
-#define CONFIG_MC13783_SPI_CS 0
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index bee2f45..0414cc3 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -69,12 +69,13 @@
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC
+#define CONFIG_FSL_PMIC_BUS 1
+#define CONFIG_FSL_PMIC_CS 2
+#define CONFIG_FSL_PMIC_CLK 1000000
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1
-/* MC13783 connected to CSPI2 and SS2 */
-#define CONFIG_MC13783_SPI_BUS 1
-#define CONFIG_MC13783_SPI_CS 2
-
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 3626df7..86a4731 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -54,6 +54,8 @@
/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE 128
+#define BOARD_LATE_INIT
+
/*
* Hardware drivers
*/
@@ -61,6 +63,19 @@
#define CONFIG_SYS_MX51_UART1
/*
+ * SPI Configs
+ * */
+#define CONFIG_CMD_SPI
+
+#define CONFIG_MXC_SPI
+
+#define CONFIG_FSL_PMIC
+#define CONFIG_FSL_PMIC_BUS 0
+#define CONFIG_FSL_PMIC_CS 0
+#define CONFIG_FSL_PMIC_CLK 2500000
+#define CONFIG_FSL_PMIC_MODE (SPI_CPOL | SPI_CS_HIGH)
+
+/*
* MMC Configs
* */
#define CONFIG_FSL_ESDHC
diff --git a/include/configs/qong.h b/include/configs/qong.h
index 1d63b33..100fa3f 100644
--- a/include/configs/qong.h
+++ b/include/configs/qong.h
@@ -54,6 +54,17 @@
#define CONFIG_MX31_GPIO
+#define CONFIG_MXC_SPI
+#define CONFIG_DEFAULT_SPI_BUS 1
+#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_RTC_MC13783
+
+#define CONFIG_FSL_PMIC
+#define CONFIG_FSL_PMIC_BUS 1
+#define CONFIG_FSL_PMIC_CS 0
+#define CONFIG_FSL_PMIC_CLK 100000
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+
/* FPGA */
#define CONFIG_QONG_FPGA 1
#define CONFIG_FPGA_BASE (CS1_BASE)
@@ -73,7 +84,7 @@
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
-#define CONFIG_DISPLAY_VBEST_VGG322403
+#define CONFIG_DISPLAY_COM57H5M10XRC
/*
* Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
@@ -98,6 +109,9 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_DATE
+#define BOARD_LATE_INIT
/*
* You can compile in a MAC address and your custom net settings by using
diff --git a/include/fsl_pmic.h b/include/fsl_pmic.h
new file mode 100644
index 0000000..e3abde6
--- /dev/null
+++ b/include/fsl_pmic.h
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FSL_PMIC_H__
+#define __FSL_PMIC_H__
+
+/*
+ * The registers of different PMIC has the same meaning
+ * but the bit positions of the fields can differ or
+ * some fields has a meaning only on some devices.
+ * You have to check with the internal SPI bitmap
+ * (see Freescale Documentation) to set the registers
+ * for the device you are using
+ */
+enum {
+ REG_INT_STATUS0 = 0,
+ REG_INT_MASK0,
+ REG_INT_SENSE0,
+ REG_INT_STATUS1,
+ REG_INT_MASK1,
+ REG_INT_SENSE1,
+ REG_PU_MODE_S,
+ REG_IDENTIFICATION,
+ REG_UNUSED0,
+ REG_ACC0,
+ REG_ACC1, /*10 */
+ REG_UNUSED1,
+ REG_UNUSED2,
+ REG_POWER_CTL0,
+ REG_POWER_CTL1,
+ REG_POWER_CTL2,
+ REG_REGEN_ASSIGN,
+ REG_UNUSED3,
+ REG_MEM_A,
+ REG_MEM_B,
+ REG_RTC_TIME, /*20 */
+ REG_RTC_ALARM,
+ REG_RTC_DAY,
+ REG_RTC_DAY_ALARM,
+ REG_SW_0,
+ REG_SW_1,
+ REG_SW_2,
+ REG_SW_3,
+ REG_SW_4,
+ REG_SW_5,
+ REG_SETTING_0, /*30 */
+ REG_SETTING_1,
+ REG_MODE_0,
+ REG_MODE_1,
+ REG_POWER_MISC,
+ REG_UNUSED4,
+ REG_UNUSED5,
+ REG_UNUSED6,
+ REG_UNUSED7,
+ REG_UNUSED8,
+ REG_UNUSED9, /*40 */
+ REG_UNUSED10,
+ REG_UNUSED11,
+ REG_ADC0,
+ REG_ADC1,
+ REG_ADC2,
+ REG_ADC3,
+ REG_ADC4,
+ REG_CHARGE,
+ REG_USB0,
+ REG_USB1, /*50 */
+ REG_LED_CTL0,
+ REG_LED_CTL1,
+ REG_LED_CTL2,
+ REG_LED_CTL3,
+ REG_UNUSED12,
+ REG_UNUSED13,
+ REG_TRIM0,
+ REG_TRIM1,
+ REG_TEST0,
+ REG_TEST1, /*60 */
+ REG_TEST2,
+ REG_TEST3,
+ REG_TEST4,
+};
+
+/* REG_POWER_MISC */
+#define GPO1EN (1 << 6)
+#define GPO1STBY (1 << 7)
+#define GPO2EN (1 << 8)
+#define GPO2STBY (1 << 9)
+#define GPO3EN (1 << 10)
+#define GPO3STBY (1 << 11)
+#define GPO4EN (1 << 12)
+#define GPO4STBY (1 << 13)
+#define PWGT1SPIEN (1 << 15)
+#define PWGT2SPIEN (1 << 16)
+#define PWUP (1 << 21)
+
+/* Power Control 0 */
+#define COINCHEN (1 << 23)
+#define BATTDETEN (1 << 19)
+
+/* Interrupt status 1 */
+#define RTCRSTI (1 << 7)
+
+void pmic_show_pmic_info(void);
+void pmic_reg_write(u32 reg, u32 value);
+u32 pmic_reg_read(u32 reg);
+
+#endif
diff --git a/include/mc13892.h b/include/mc13892.h
new file mode 100644
index 0000000..b291757
--- /dev/null
+++ b/include/mc13892.h
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __MC13892_H__
+#define __MC13892_H__
+
+/* REG_CHARGE */
+
+#define VCHRG0 0
+#define VCHRG1 (1 << 1)
+#define VCHRG2 (1 << 2)
+#define ICHRG0 (1 << 3)
+#define ICHRG1 (1 << 4)
+#define ICHRG2 (1 << 5)
+#define ICHRG3 (1 << 6)
+#define ICHRGTR0 (1 << 7)
+#define ICHRGTR1 (1 << 8)
+#define ICHRGTR2 (1 << 9)
+#define FETOVRD (1 << 10)
+#define FETCTRL (1 << 11)
+#define RVRSMODE (1 << 13)
+#define OVCTRL0 (1 << 15)
+#define OVCTRL1 (1 << 16)
+#define UCHEN (1 << 17)
+#define CHRGLEDEN (1 << 18)
+#define CHRGRAWPDEN (1 << 19)
+#define CHGRESTART (1 << 20)
+#define CHGAUTOB (1 << 21)
+#define CYCLB (1 << 22)
+#define CHGAUTOVIB (1 << 23)
+
+/* REG_SETTING_0/1 */
+#define VO_1_20V 0
+#define VO_1_30V 1
+#define VO_1_50V 2
+#define VO_1_80V 3
+#define VO_1_10V 4
+#define VO_2_00V 5
+#define VO_2_77V 6
+#define VO_2_40V 7
+
+#define VIOL 2
+#define VDIG 4
+#define VGEN 6
+
+/* SWxMode for Normal/Standby Mode */
+#define SWMODE_OFF_OFF 0
+#define SWMODE_PWM_OFF 1
+#define SWMODE_PWMPS_OFF 2
+#define SWMODE_PFM_OFF 3
+#define SWMODE_AUTO_OFF 4
+#define SWMODE_PWM_PWM 5
+#define SWMODE_PWM_AUTO 6
+#define SWMODE_AUTO_AUTO 8
+#define SWMODE_PWM_PWMPS 9
+#define SWMODE_PWMS_PWMPS 10
+#define SWMODE_PWMS_AUTO 11
+#define SWMODE_AUTO_PFM 12
+#define SWMODE_PWM_PFM 13
+#define SWMODE_PWMS_PFM 14
+#define SWMODE_PFM_PFM 15
+#define SWMODE_MASK 0x0F
+
+#define SWMODE1_SHIFT 0
+#define SWMODE2_SHIFT 10
+#define SWMODE3_SHIFT 0
+#define SWMODE4_SHIFT 8
+
+/* Fields in REG_SETTING_1 */
+#define VVIDEO_2_7 (0 << 2)
+#define VVIDEO_2_775 (1 << 2)
+#define VVIDEO_2_5 (2 << 2)
+#define VVIDEO_2_6 (3 << 2)
+#define VVIDEO_MASK (3 << 2)
+#define VAUDIO_2_3 (0 << 4)
+#define VAUDIO_2_5 (1 << 4)
+#define VAUDIO_2_775 (2 << 4)
+#define VAUDIO_3_0 (3 << 4)
+#define VAUDIO_MASK (3 << 4)
+#define VSD_1_8 (0 << 6)
+#define VSD_2_0 (1 << 6)
+#define VSD_2_6 (2 << 6)
+#define VSD_2_7 (3 << 6)
+#define VSD_2_8 (4 << 6)
+#define VSD_2_9 (5 << 6)
+#define VSD_3_0 (6 << 6)
+#define VSD_3_15 (7 << 6)
+#define VSD_MASK (7 << 6)
+#define VGEN1_1_2 0
+#define VGEN1_1_5 1
+#define VGEN1_2_775 2
+#define VGEN1_3_15 3
+#define VGEN1_MASK 3
+#define VGEN2_1_2 (0 << 6)
+#define VGEN2_1_5 (1 << 6)
+#define VGEN2_1_6 (2 << 6)
+#define VGEN2_1_8 (3 << 6)
+#define VGEN2_2_7 (4 << 6)
+#define VGEN2_2_8 (5 << 6)
+#define VGEN2_3_0 (6 << 6)
+#define VGEN2_3_15 (7 << 6)
+#define VGEN2_MASK (7 << 6)
+
+/* Fields in REG_SETTING_1 */
+#define VGEN3_1_8 (0 << 14)
+#define VGEN3_2_9 (1 << 14)
+#define VGEN3_MASK (1 << 14)
+#define VDIG_1_05 (0 << 4)
+#define VDIG_1_25 (1 << 4)
+#define VDIG_1_65 (2 << 4)
+#define VDIG_1_8 (3 << 4)
+#define VDIG_MASK (3 << 4)
+#define VCAM_2_5 (0 << 16)
+#define VCAM_2_6 (1 << 16)
+#define VCAM_2_75 (2 << 16)
+#define VCAM_3_0 (3 << 16)
+#define VCAM_MASK (3 << 16)
+
+/* Reg Mode 1 */
+#define VGEN3EN (1 << 0)
+#define VGEN3STBY (1 << 1)
+#define VGEN3MODE (1 << 2)
+#define VGEN3CONFIG (1 << 3)
+#define VCAMEN (1 << 6)
+#define VCAMSTBY (1 << 7)
+#define VCAMMODE (1 << 8)
+#define VCAMCONFIG (1 << 9)
+#define VVIDEOEN (1 << 12)
+#define VIDEOSTBY (1 << 13)
+#define VVIDEOMODE (1 << 14)
+#define VAUDIOEN (1 << 15)
+#define VAUDIOSTBY (1 << 16)
+#define VSDEN (1 << 18)
+#define VSDSTBY (1 << 19)
+#define VSDMODE (1 << 20)
+
+#endif