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authorFabio Estevam <fabio.estevam@freescale.com>2012-10-15 05:37:16 +0000
committerStefano Babic <sbabic@denx.de>2012-10-17 18:09:34 +0200
commit782b02884126cc258056e8bf581a410a934f7372 (patch)
treef3abf9cfdf7cd45427aa60d4d71b79cc2c1d3995 /include
parent758c3449451f20402af72fa0754a1ce32ba9af48 (diff)
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mx5: lowlevel_init.S: Fix PLL settings for mx53
Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz. Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz instead. Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI at 1080p because the IPU clock cannot reach the requested frequency. Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its maximum frequency. Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little bit to allow easier comparison with the original clock setup from FSL U-boot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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