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authorYork Sun <yorksun@freescale.com>2014-02-10 13:59:44 -0800
committerTom Rini <trini@ti.com>2014-02-21 11:06:13 -0500
commit6b1e1254f326940e5b65c7029f71b964bdf28fd4 (patch)
treea8e596b2d01fe4a952e253b9b42972b040a4a165 /include
parent6b9e309a8a7f0f33252288f0ed8794a83a488301 (diff)
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driver/ddr: Add 256 byte interleaving support
Freescale LayerScape SoCs support controller interleaving on 256 byte size. This interleaving is mandoratory. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/fsl_ddr_sdram.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index 16cccc7..2a36431 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -76,6 +76,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#define FSL_DDR_PAGE_INTERLEAVING 0x1
#define FSL_DDR_BANK_INTERLEAVING 0x2
#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
+#define FSL_DDR_256B_INTERLEAVING 0x8
#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA
#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC
#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD