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authorMarkus Klotzbücher <Markus Klotzbümk@pollux.(none)>2006-02-28 18:05:25 +0100
committerMarkus Klotzbücher <mk@pollux.(none)>2006-02-28 18:05:25 +0100
commit6949328d7df7a98b88a8edc0f7238687a3083a22 (patch)
treea6909a0121f01c6f76df82a257682b29a750516f /include
parent0377dca227cc883bbaacbe1c442cef5bd6b0e121 (diff)
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First steps implementing NAND support. Not working, fails to read ID.
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h79
-rw-r--r--include/configs/delta.h70
2 files changed, 105 insertions, 44 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 44532c9..05ed969 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1003,12 +1003,51 @@ typedef void (*ExcpHndlr) (void) ;
#define GSDR(x) __REG2(0x40E00400, ((x) & 0x60) >> 3)
#define GCDR(x) __REG2(0x40300420, ((x) & 0x60) >> 3)
-/* Multi-funktion Pin Registers, uncomplete, only GPIO relevant pins for now */
+/* Multi-funktion Pin Registers, uncomplete, only:
+ * - GPIO
+ * - Data Flash DF_* pins defined.
+ */
#define GPIO0 __REG(0x40e10124)
#define GPIO1 __REG(0x40e10128)
#define GPIO2 __REG(0x40e1012c)
#define GPIO3 __REG(0x40e10130)
#define GPIO4 __REG(0x40e10134)
+#define nXCVREN __REG(0x40e10138)
+
+#define DF_CLE_NOE __REG(0x40e10204)
+#define DF_ALE_WE1 __REG(0x40e10208)
+
+#define DF_SCLK_E __REG(0x40e10210)
+#define nBE0 __REG(0x40e10214)
+#define nBE1 __REG(0x40e10218)
+#define DF_ALE_WE2 __REG(0x40e1021c)
+#define DF_INT_RnB __REG(0x40e10220)
+#define DF_nCS0 __REG(0x40e10224)
+#define DF_nCS1 __REG(0x40e10228)
+#define DF_nWE __REG(0x40e1022c)
+#define DF_nRE __REG(0x40e10230)
+#define nLUA __REG(0x40e10234)
+#define nLLA __REG(0x40e10238)
+#define DF_ADDR0 __REG(0x40e1023c)
+#define DF_ADDR1 __REG(0x40e10240)
+#define DF_ADDR2 __REG(0x40e10244)
+#define DF_ADDR3 __REG(0x40e10248)
+#define DF_IO0 __REG(0x40e1024c)
+#define DF_IO8 __REG(0x40e10250)
+#define DF_IO1 __REG(0x40e10254)
+#define DF_IO9 __REG(0x40e10258)
+#define DF_IO2 __REG(0x40e1025c)
+#define DF_IO10 __REG(0x40e10260)
+#define DF_IO3 __REG(0x40e10264)
+#define DF_IO11 __REG(0x40e10268)
+#define DF_IO4 __REG(0x40e1026c)
+#define DF_IO12 __REG(0x40e10270)
+#define DF_IO5 __REG(0x40e10274)
+#define DF_IO13 __REG(0x40e10278)
+#define DF_IO6 __REG(0x40e1027c)
+#define DF_IO14 __REG(0x40e10280)
+#define DF_IO7 __REG(0x40e10284)
+#define DF_IO15 __REG(0x40e10288)
#define GPIO5 __REG(0x40e1028c)
#define GPIO6 __REG(0x40e10290)
@@ -2022,19 +2061,19 @@ typedef void (*ExcpHndlr) (void) ;
/* Data Flash Controller Registers */
-#define NDCR __REG_2(0x43100000) /* Data Flash Control register */
-#define NDTR0CS0 __REG_2(0x43100004) /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
-#define NDTR0CS1 __REG_2(0x43100008) /* Data Controller Timing Parameter 0 Register for ND_nCS1 */
-#define NDTR1CS0 __REG_2(0x4310000C) /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
-#define NDTR1CS1 __REG_2(0x43100010) /* Data Controller Timing Parameter 1 Register for ND_nCS1 */
-#define NDSR __REG_2(0x43100014) /* Data Controller Status Register */
-#define NDPCR __REG_2(0x43100018) /* Data Controller Page Count Register */
-#define NDBDR0 __REG_2(0x4310001C) /* Data Controller Bad Block Register 0 */
-#define NDBDR1 __REG_2(0x43100020) /* Data Controller Bad Block Register 1 */
-#define NDDB __REG_2(0x43100040) /* Data Controller Data Buffer */
-#define NDCB0 __REG_2(0x43100048) /* Data Controller Command Buffer0 */
-#define NDCB1 __REG_2(0x4310004C) /* Data Controller Command Buffer1 */
-#define NDCB2 __REG_2(0x43100050) /* Data Controller Command Buffer2 */
+#define NDCR __REG(0x43100000) /* Data Flash Control register */
+#define NDTR0CS0 __REG(0x43100004) /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
+/* #define NDTR0CS1 __REG(0x43100008) /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */
+#define NDTR1CS0 __REG(0x4310000C) /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
+/* #define NDTR1CS1 __REG(0x43100010) /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */
+#define NDSR __REG(0x43100014) /* Data Controller Status Register */
+#define NDPCR __REG(0x43100018) /* Data Controller Page Count Register */
+#define NDBDR0 __REG(0x4310001C) /* Data Controller Bad Block Register 0 */
+#define NDBDR1 __REG(0x43100020) /* Data Controller Bad Block Register 1 */
+#define NDDB __REG(0x43100040) /* Data Controller Data Buffer */
+#define NDCB0 __REG(0x43100048) /* Data Controller Command Buffer0 */
+#define NDCB1 __REG(0x4310004C) /* Data Controller Command Buffer1 */
+#define NDCB2 __REG(0x43100050) /* Data Controller Command Buffer2 */
#define NDCR_SPARE_EN (0x1<<31)
#define NDCR_ECC_EN (0x1<<30)
@@ -2052,6 +2091,18 @@ typedef void (*ExcpHndlr) (void) ;
#define NDCR_RA_START (0x1<<15)
#define NDCR_PG_PER_BLK (0x1<<14)
#define NDCR_ND_ARB_EN (0x1<<12)
+#define NDCE_RDYM (0x1<<11)
+#define NDCE_CS0_PAGEDM (0x1<<10)
+#define NDCE_CS1_PAGEDM (0x1<<9)
+#define NDCE_CS0_CMDDM (0x1<<8)
+#define NDCE_CS1_CMDDM (0x1<<7)
+#define NDCE_CS0_BBDM (0x1<<6)
+#define NDCE_CS1_BBDM (0x1<<5)
+#define NDCE_DBERRM (0x1<<4)
+#define NDCE_SBERRM (0x1<<3)
+#define NDCE_WRDREQM (0x1<<2)
+#define NDCE_RDDREQM (0x1<<1)
+#define NDCE_WRCMDREQM (0x1)
#define NDSR_RDY (0x1<<11)
#define NDSR_CS0_PAGED (0x1<<10)
diff --git a/include/configs/delta.h b/include/configs/delta.h
index 5b42069..9bc2954 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -73,7 +73,9 @@
#ifdef TURN_ON_ETHERNET
# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
#else
-# define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET)
+# define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_NAND) \
+ & ~(CFG_CMD_NET | CFG_CMD_FLASH | \
+ CFG_CMD_ENV | CFG_CMD_IMLS))
#endif
@@ -152,20 +154,41 @@
#define PHYS_SDRAM_4 0xa3000000 /* SDRAM Bank #4 */
#define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
-#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
-#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
-#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
-
#define CFG_DRAM_BASE 0xa0000000 /* at CS0 */
#define CFG_DRAM_SIZE 0x04000000 /* 64 MB Ram */
#define CFG_SKIP_DRAM_SCRUB 1
-#define CFG_FLASH_BASE PHYS_FLASH_1
-
-#define FPGA_REGS_BASE_PHYSICAL 0x08000000
+/*
+ * NAND Flash
+ */
+/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
+#define CONFIG_NEW_NAND_CODE
+#define CFG_NAND0_BASE 0x10000000
+#undef CFG_NAND1_BASE
+
+#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define SECTORSIZE 512
+/* #define NAND_NO_RB */
+#define NAND_DELAY_US 25 /* mk@tbd: could be 0, I guess */
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NO_FLASH 1
+#ifndef CGF_NO_FLASH
+/* these are required by the environment code */
+#define PHYS_FLASH_1 CFG_NAND0_BASE /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE 0x04000000 /* 64 MB */
+#define PHYS_FLASH_BANK_SIZE 0x04000000 /* 64 MB Banks */
+#define PHYS_FLASH_SECT_SIZE (SECTORSIZE*1024) /* KB sectors (x2) */
+#endif
/*
* GPIO settings
@@ -215,6 +238,7 @@
/*
* FLASH and environment organization
*/
+#ifndef CFG_NO_FLASH
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
@@ -222,30 +246,16 @@
#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
+
/* NOTE: many default partitioning schemes assume the kernel starts at the
* second sector, not an environment. You have been warned!
*/
#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE
+#endif /* #ifndef CFG_NO_FLASH */
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
-#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
-#define CFG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16)
-
-
-/*
- * FPGA Offsets
- */
-#define WHOAMI_OFFSET 0x00
-#define HEXLED_OFFSET 0x10
-#define BLANKLED_OFFSET 0x40
-#define DISCRETELED_OFFSET 0x40
-#define CNFG_SWITCHES_OFFSET 0x50
-#define USER_SWITCHES_OFFSET 0x60
-#define MISC_WR_OFFSET 0x80
-#define MISC_RD_OFFSET 0x90
-#define INT_MASK_OFFSET 0xC0
-#define INT_CLEAR_OFFSET 0xD0
-#define GP_OFFSET 0x100
+#define CFG_ENV_IS_NOWHERE
+/* #define CFG_ENV_IS_IN_NAND 1 */
+#define CFG_ENV_OFFSET 0x40000
+#define CFG_ENV_SIZE 0x4000
#endif /* __CONFIG_H */