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authorMarkus Klotzbuecher <mk@denx.de>2007-04-23 13:17:22 +0200
committerMarkus Klotzbuecher <mk@pollux.denx.de>2007-04-23 13:17:22 +0200
commit61ea75aa07838435ec570ac85a2e3fc038844596 (patch)
tree20135a513c4c9d0bddb2a8ceaf009a8ed5e8bbdf /include
parente2fb36a57f364016b973b1db255531e07cfefd52 (diff)
parent14da5f7675bbb427c469e3f45006e027b6e21db9 (diff)
downloadu-boot-imx-61ea75aa07838435ec570ac85a2e3fc038844596.zip
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Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'include')
-rw-r--r--include/74xx_7xx.h2
-rw-r--r--include/asm-avr32/arch-at32ap7000/clk.h70
-rw-r--r--include/asm-avr32/arch-at32ap7000/gpio.h212
-rw-r--r--include/asm-avr32/arch-at32ap7000/hmatrix2.h8
-rw-r--r--include/asm-avr32/arch-at32ap7000/memory-map.h81
-rw-r--r--include/asm-avr32/arch-at32ap7000/mmc.h96
-rw-r--r--include/asm-avr32/arch-at32ap7000/platform.h146
-rw-r--r--include/asm-avr32/global_data.h4
-rw-r--r--include/asm-avr32/initcalls.h2
-rw-r--r--include/asm-blackfin/arch-bf533/bf533_serial.h6
-rw-r--r--include/asm-blackfin/arch-bf533/bf5xx_rtc.h6
-rw-r--r--include/asm-blackfin/arch-bf533/cplbtab.h482
-rw-r--r--include/asm-blackfin/arch-bf533/irq.h6
-rw-r--r--include/asm-blackfin/arch-bf537/bf537_serial.h6
-rw-r--r--include/asm-blackfin/arch-bf537/bf5xx_rtc.h6
-rw-r--r--include/asm-blackfin/arch-bf537/cplbtab.h408
-rw-r--r--include/asm-blackfin/arch-bf537/irq.h6
-rw-r--r--include/asm-blackfin/arch-bf561/bf561_serial.h6
-rw-r--r--include/asm-blackfin/arch-common/bf53x_rtc.h6
-rw-r--r--include/asm-blackfin/bitops.h6
-rw-r--r--include/asm-blackfin/blackfin.h6
-rw-r--r--include/asm-blackfin/blackfin_defs.h6
-rw-r--r--include/asm-blackfin/byteorder.h6
-rw-r--r--include/asm-blackfin/cplb.h10
-rw-r--r--include/asm-blackfin/current.h6
-rw-r--r--include/asm-blackfin/delay.h6
-rw-r--r--include/asm-blackfin/entry.h7
-rw-r--r--include/asm-blackfin/errno.h6
-rw-r--r--include/asm-blackfin/global_data.h6
-rw-r--r--include/asm-blackfin/hw_irq.h6
-rw-r--r--include/asm-blackfin/io-kernel.h6
-rw-r--r--include/asm-blackfin/io.h7
-rw-r--r--include/asm-blackfin/irq.h6
-rw-r--r--include/asm-blackfin/linkage.h6
-rw-r--r--include/asm-blackfin/machdep.h6
-rw-r--r--include/asm-blackfin/mem_init.h6
-rw-r--r--include/asm-blackfin/page.h123
-rw-r--r--include/asm-blackfin/page_offset.h6
-rw-r--r--include/asm-blackfin/posix_types.h6
-rw-r--r--include/asm-blackfin/processor.h6
-rw-r--r--include/asm-blackfin/ptrace.h6
-rw-r--r--include/asm-blackfin/segment.h6
-rw-r--r--include/asm-blackfin/setup.h6
-rw-r--r--include/asm-blackfin/shared_resources.h6
-rw-r--r--include/asm-blackfin/string.h7
-rw-r--r--include/asm-blackfin/system.h6
-rw-r--r--include/asm-blackfin/traps.h6
-rw-r--r--include/asm-blackfin/types.h6
-rw-r--r--include/asm-blackfin/u-boot.h8
-rw-r--r--include/asm-blackfin/uaccess.h6
-rw-r--r--include/asm-blackfin/virtconvert.h7
-rw-r--r--include/asm-microblaze/microblaze_intc.h (renamed from include/asm-microblaze/suzaku.h)25
-rw-r--r--include/asm-microblaze/microblaze_timer.h41
-rw-r--r--include/asm-ppc/global_data.h3
-rw-r--r--include/asm-ppc/gpio.h56
-rw-r--r--include/configs/IceCube.h2
-rw-r--r--include/configs/MPC8360EMDS.h6
-rw-r--r--include/configs/NC650.h12
-rw-r--r--include/configs/acadia.h300
-rw-r--r--include/configs/atstk1002.h69
-rw-r--r--include/configs/katmai.h2
-rw-r--r--include/configs/ml401.h230
-rw-r--r--include/configs/mpc7448hpc2.h411
-rw-r--r--include/configs/sc3.h10
-rw-r--r--include/configs/sequoia.h16
-rw-r--r--include/configs/suzaku.h7
-rw-r--r--include/configs/xupv2p.h174
-rw-r--r--include/configs/yosemite.h1
-rw-r--r--include/configs/yucca.h2
-rw-r--r--include/fdt.h79
-rw-r--r--include/fdt_support.h (renamed from include/asm-microblaze/platform.h)25
-rw-r--r--include/libfdt.h146
-rw-r--r--include/libfdt_env.h36
-rw-r--r--include/linux/mii.h158
-rw-r--r--include/linux/stat.h91
-rw-r--r--include/ppc405.h2
-rw-r--r--include/ppc440.h25
-rw-r--r--include/serial.h2
-rw-r--r--include/tsi108.h221
79 files changed, 2425 insertions, 1605 deletions
diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h
index 33e396a..ba73bae 100644
--- a/include/74xx_7xx.h
+++ b/include/74xx_7xx.h
@@ -111,7 +111,7 @@ typedef enum __cpu_t {
CPU_750CX, CPU_750FX, CPU_750GX,
CPU_7400,
CPU_7410,
- CPU_7448,
+ CPU_7447A, CPU_7448,
CPU_7450, CPU_7455, CPU_7457,
CPU_UNKNOWN} cpu_t;
diff --git a/include/asm-avr32/arch-at32ap7000/clk.h b/include/asm-avr32/arch-at32ap7000/clk.h
new file mode 100644
index 0000000..7e20d97
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap7000/clk.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_ARCH_CLK_H__
+#define __ASM_AVR32_ARCH_CLK_H__
+
+#ifdef CONFIG_PLL
+#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
+#else
+#define MAIN_CLK_RATE (CFG_OSC0_HZ)
+#endif
+
+static inline unsigned long get_cpu_clk_rate(void)
+{
+ return MAIN_CLK_RATE >> CFG_CLKDIV_CPU;
+}
+static inline unsigned long get_hsb_clk_rate(void)
+{
+ return MAIN_CLK_RATE >> CFG_CLKDIV_HSB;
+}
+static inline unsigned long get_pba_clk_rate(void)
+{
+ return MAIN_CLK_RATE >> CFG_CLKDIV_PBA;
+}
+static inline unsigned long get_pbb_clk_rate(void)
+{
+ return MAIN_CLK_RATE >> CFG_CLKDIV_PBB;
+}
+
+/* Accessors for specific devices. More will be added as needed. */
+static inline unsigned long get_sdram_clk_rate(void)
+{
+ return get_hsb_clk_rate();
+}
+static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
+{
+ return get_pba_clk_rate();
+}
+static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
+{
+ return get_pbb_clk_rate();
+}
+static inline unsigned long get_macb_hclk_rate(unsigned int dev_id)
+{
+ return get_hsb_clk_rate();
+}
+static inline unsigned long get_mci_clk_rate(void)
+{
+ return get_pbb_clk_rate();
+}
+
+#endif /* __ASM_AVR32_ARCH_CLK_H__ */
diff --git a/include/asm-avr32/arch-at32ap7000/gpio.h b/include/asm-avr32/arch-at32ap7000/gpio.h
new file mode 100644
index 0000000..e4812d4
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap7000/gpio.h
@@ -0,0 +1,212 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_ARCH_GPIO_H__
+#define __ASM_AVR32_ARCH_GPIO_H__
+
+#include <asm/arch/memory-map.h>
+
+#define NR_GPIO_CONTROLLERS 5
+
+/*
+ * Pin numbers identifying specific GPIO pins on the chip.
+ */
+#define GPIO_PIOA_BASE (0)
+#define GPIO_PIN_PA0 (GPIO_PIOA_BASE + 0)
+#define GPIO_PIN_PA1 (GPIO_PIOA_BASE + 1)
+#define GPIO_PIN_PA2 (GPIO_PIOA_BASE + 2)
+#define GPIO_PIN_PA3 (GPIO_PIOA_BASE + 3)
+#define GPIO_PIN_PA4 (GPIO_PIOA_BASE + 4)
+#define GPIO_PIN_PA5 (GPIO_PIOA_BASE + 5)
+#define GPIO_PIN_PA6 (GPIO_PIOA_BASE + 6)
+#define GPIO_PIN_PA7 (GPIO_PIOA_BASE + 7)
+#define GPIO_PIN_PA8 (GPIO_PIOA_BASE + 8)
+#define GPIO_PIN_PA9 (GPIO_PIOA_BASE + 9)
+#define GPIO_PIN_PA10 (GPIO_PIOA_BASE + 10)
+#define GPIO_PIN_PA11 (GPIO_PIOA_BASE + 11)
+#define GPIO_PIN_PA12 (GPIO_PIOA_BASE + 12)
+#define GPIO_PIN_PA13 (GPIO_PIOA_BASE + 13)
+#define GPIO_PIN_PA14 (GPIO_PIOA_BASE + 14)
+#define GPIO_PIN_PA15 (GPIO_PIOA_BASE + 15)
+#define GPIO_PIN_PA16 (GPIO_PIOA_BASE + 16)
+#define GPIO_PIN_PA17 (GPIO_PIOA_BASE + 17)
+#define GPIO_PIN_PA18 (GPIO_PIOA_BASE + 18)
+#define GPIO_PIN_PA19 (GPIO_PIOA_BASE + 19)
+#define GPIO_PIN_PA20 (GPIO_PIOA_BASE + 20)
+#define GPIO_PIN_PA21 (GPIO_PIOA_BASE + 21)
+#define GPIO_PIN_PA22 (GPIO_PIOA_BASE + 22)
+#define GPIO_PIN_PA23 (GPIO_PIOA_BASE + 23)
+#define GPIO_PIN_PA24 (GPIO_PIOA_BASE + 24)
+#define GPIO_PIN_PA25 (GPIO_PIOA_BASE + 25)
+#define GPIO_PIN_PA26 (GPIO_PIOA_BASE + 26)
+#define GPIO_PIN_PA27 (GPIO_PIOA_BASE + 27)
+#define GPIO_PIN_PA28 (GPIO_PIOA_BASE + 28)
+#define GPIO_PIN_PA29 (GPIO_PIOA_BASE + 29)
+#define GPIO_PIN_PA30 (GPIO_PIOA_BASE + 30)
+#define GPIO_PIN_PA31 (GPIO_PIOA_BASE + 31)
+
+#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
+#define GPIO_PIN_PB0 (GPIO_PIOB_BASE + 0)
+#define GPIO_PIN_PB1 (GPIO_PIOB_BASE + 1)
+#define GPIO_PIN_PB2 (GPIO_PIOB_BASE + 2)
+#define GPIO_PIN_PB3 (GPIO_PIOB_BASE + 3)
+#define GPIO_PIN_PB4 (GPIO_PIOB_BASE + 4)
+#define GPIO_PIN_PB5 (GPIO_PIOB_BASE + 5)
+#define GPIO_PIN_PB6 (GPIO_PIOB_BASE + 6)
+#define GPIO_PIN_PB7 (GPIO_PIOB_BASE + 7)
+#define GPIO_PIN_PB8 (GPIO_PIOB_BASE + 8)
+#define GPIO_PIN_PB9 (GPIO_PIOB_BASE + 9)
+#define GPIO_PIN_PB10 (GPIO_PIOB_BASE + 10)
+#define GPIO_PIN_PB11 (GPIO_PIOB_BASE + 11)
+#define GPIO_PIN_PB12 (GPIO_PIOB_BASE + 12)
+#define GPIO_PIN_PB13 (GPIO_PIOB_BASE + 13)
+#define GPIO_PIN_PB14 (GPIO_PIOB_BASE + 14)
+#define GPIO_PIN_PB15 (GPIO_PIOB_BASE + 15)
+#define GPIO_PIN_PB16 (GPIO_PIOB_BASE + 16)
+#define GPIO_PIN_PB17 (GPIO_PIOB_BASE + 17)
+#define GPIO_PIN_PB18 (GPIO_PIOB_BASE + 18)
+#define GPIO_PIN_PB19 (GPIO_PIOB_BASE + 19)
+#define GPIO_PIN_PB20 (GPIO_PIOB_BASE + 20)
+#define GPIO_PIN_PB21 (GPIO_PIOB_BASE + 21)
+#define GPIO_PIN_PB22 (GPIO_PIOB_BASE + 22)
+#define GPIO_PIN_PB23 (GPIO_PIOB_BASE + 23)
+#define GPIO_PIN_PB24 (GPIO_PIOB_BASE + 24)
+#define GPIO_PIN_PB25 (GPIO_PIOB_BASE + 25)
+#define GPIO_PIN_PB26 (GPIO_PIOB_BASE + 26)
+#define GPIO_PIN_PB27 (GPIO_PIOB_BASE + 27)
+#define GPIO_PIN_PB28 (GPIO_PIOB_BASE + 28)
+#define GPIO_PIN_PB29 (GPIO_PIOB_BASE + 29)
+#define GPIO_PIN_PB30 (GPIO_PIOB_BASE + 30)
+
+#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
+#define GPIO_PIN_PC0 (GPIO_PIOC_BASE + 0)
+#define GPIO_PIN_PC1 (GPIO_PIOC_BASE + 1)
+#define GPIO_PIN_PC2 (GPIO_PIOC_BASE + 2)
+#define GPIO_PIN_PC3 (GPIO_PIOC_BASE + 3)
+#define GPIO_PIN_PC4 (GPIO_PIOC_BASE + 4)
+#define GPIO_PIN_PC5 (GPIO_PIOC_BASE + 5)
+#define GPIO_PIN_PC6 (GPIO_PIOC_BASE + 6)
+#define GPIO_PIN_PC7 (GPIO_PIOC_BASE + 7)
+#define GPIO_PIN_PC8 (GPIO_PIOC_BASE + 8)
+#define GPIO_PIN_PC9 (GPIO_PIOC_BASE + 9)
+#define GPIO_PIN_PC10 (GPIO_PIOC_BASE + 10)
+#define GPIO_PIN_PC11 (GPIO_PIOC_BASE + 11)
+#define GPIO_PIN_PC12 (GPIO_PIOC_BASE + 12)
+#define GPIO_PIN_PC13 (GPIO_PIOC_BASE + 13)
+#define GPIO_PIN_PC14 (GPIO_PIOC_BASE + 14)
+#define GPIO_PIN_PC15 (GPIO_PIOC_BASE + 15)
+#define GPIO_PIN_PC16 (GPIO_PIOC_BASE + 16)
+#define GPIO_PIN_PC17 (GPIO_PIOC_BASE + 17)
+#define GPIO_PIN_PC18 (GPIO_PIOC_BASE + 18)
+#define GPIO_PIN_PC19 (GPIO_PIOC_BASE + 19)
+#define GPIO_PIN_PC20 (GPIO_PIOC_BASE + 20)
+#define GPIO_PIN_PC21 (GPIO_PIOC_BASE + 21)
+#define GPIO_PIN_PC22 (GPIO_PIOC_BASE + 22)
+#define GPIO_PIN_PC23 (GPIO_PIOC_BASE + 23)
+#define GPIO_PIN_PC24 (GPIO_PIOC_BASE + 24)
+#define GPIO_PIN_PC25 (GPIO_PIOC_BASE + 25)
+#define GPIO_PIN_PC26 (GPIO_PIOC_BASE + 26)
+#define GPIO_PIN_PC27 (GPIO_PIOC_BASE + 27)
+#define GPIO_PIN_PC28 (GPIO_PIOC_BASE + 28)
+#define GPIO_PIN_PC29 (GPIO_PIOC_BASE + 29)
+#define GPIO_PIN_PC30 (GPIO_PIOC_BASE + 30)
+#define GPIO_PIN_PC31 (GPIO_PIOC_BASE + 31)
+
+#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
+#define GPIO_PIN_PD0 (GPIO_PIOD_BASE + 0)
+#define GPIO_PIN_PD1 (GPIO_PIOD_BASE + 1)
+#define GPIO_PIN_PD2 (GPIO_PIOD_BASE + 2)
+#define GPIO_PIN_PD3 (GPIO_PIOD_BASE + 3)
+#define GPIO_PIN_PD4 (GPIO_PIOD_BASE + 4)
+#define GPIO_PIN_PD5 (GPIO_PIOD_BASE + 5)
+#define GPIO_PIN_PD6 (GPIO_PIOD_BASE + 6)
+#define GPIO_PIN_PD7 (GPIO_PIOD_BASE + 7)
+#define GPIO_PIN_PD8 (GPIO_PIOD_BASE + 8)
+#define GPIO_PIN_PD9 (GPIO_PIOD_BASE + 9)
+#define GPIO_PIN_PD10 (GPIO_PIOD_BASE + 10)
+#define GPIO_PIN_PD11 (GPIO_PIOD_BASE + 11)
+#define GPIO_PIN_PD12 (GPIO_PIOD_BASE + 12)
+#define GPIO_PIN_PD13 (GPIO_PIOD_BASE + 13)
+#define GPIO_PIN_PD14 (GPIO_PIOD_BASE + 14)
+#define GPIO_PIN_PD15 (GPIO_PIOD_BASE + 15)
+#define GPIO_PIN_PD16 (GPIO_PIOD_BASE + 16)
+#define GPIO_PIN_PD17 (GPIO_PIOD_BASE + 17)
+
+#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
+#define GPIO_PIN_PE0 (GPIO_PIOE_BASE + 0)
+#define GPIO_PIN_PE1 (GPIO_PIOE_BASE + 1)
+#define GPIO_PIN_PE2 (GPIO_PIOE_BASE + 2)
+#define GPIO_PIN_PE3 (GPIO_PIOE_BASE + 3)
+#define GPIO_PIN_PE4 (GPIO_PIOE_BASE + 4)
+#define GPIO_PIN_PE5 (GPIO_PIOE_BASE + 5)
+#define GPIO_PIN_PE6 (GPIO_PIOE_BASE + 6)
+#define GPIO_PIN_PE7 (GPIO_PIOE_BASE + 7)
+#define GPIO_PIN_PE8 (GPIO_PIOE_BASE + 8)
+#define GPIO_PIN_PE9 (GPIO_PIOE_BASE + 9)
+#define GPIO_PIN_PE10 (GPIO_PIOE_BASE + 10)
+#define GPIO_PIN_PE11 (GPIO_PIOE_BASE + 11)
+#define GPIO_PIN_PE12 (GPIO_PIOE_BASE + 12)
+#define GPIO_PIN_PE13 (GPIO_PIOE_BASE + 13)
+#define GPIO_PIN_PE14 (GPIO_PIOE_BASE + 14)
+#define GPIO_PIN_PE15 (GPIO_PIOE_BASE + 15)
+#define GPIO_PIN_PE16 (GPIO_PIOE_BASE + 16)
+#define GPIO_PIN_PE17 (GPIO_PIOE_BASE + 17)
+#define GPIO_PIN_PE18 (GPIO_PIOE_BASE + 18)
+#define GPIO_PIN_PE19 (GPIO_PIOE_BASE + 19)
+#define GPIO_PIN_PE20 (GPIO_PIOE_BASE + 20)
+#define GPIO_PIN_PE21 (GPIO_PIOE_BASE + 21)
+#define GPIO_PIN_PE22 (GPIO_PIOE_BASE + 22)
+#define GPIO_PIN_PE23 (GPIO_PIOE_BASE + 23)
+#define GPIO_PIN_PE24 (GPIO_PIOE_BASE + 24)
+#define GPIO_PIN_PE25 (GPIO_PIOE_BASE + 25)
+#define GPIO_PIN_PE26 (GPIO_PIOE_BASE + 26)
+
+static inline void *gpio_pin_to_addr(unsigned int pin)
+{
+ switch (pin >> 5) {
+ case 0:
+ return (void *)PIOA_BASE;
+ case 1:
+ return (void *)PIOB_BASE;
+ case 2:
+ return (void *)PIOC_BASE;
+ case 3:
+ return (void *)PIOD_BASE;
+ case 4:
+ return (void *)PIOE_BASE;
+ default:
+ return NULL;
+ }
+}
+
+void gpio_select_periph_A(unsigned int pin, int use_pullup);
+void gpio_select_periph_B(unsigned int pin, int use_pullup);
+
+void gpio_enable_ebi(void);
+void gpio_enable_usart0(void);
+void gpio_enable_usart1(void);
+void gpio_enable_usart2(void);
+void gpio_enable_usart3(void);
+void gpio_enable_macb0(void);
+void gpio_enable_macb1(void);
+void gpio_enable_mmci(void);
+
+#endif /* __ASM_AVR32_ARCH_GPIO_H__ */
diff --git a/include/asm-avr32/arch-at32ap7000/hmatrix2.h b/include/asm-avr32/arch-at32ap7000/hmatrix2.h
index e6df4b7..b0e787a 100644
--- a/include/asm-avr32/arch-at32ap7000/hmatrix2.h
+++ b/include/asm-avr32/arch-at32ap7000/hmatrix2.h
@@ -224,9 +224,9 @@
| HMATRIX2_BF(name,value))
/* Register access macros */
-#define hmatrix2_readl(port,reg) \
- readl((port)->regs + HMATRIX2_##reg)
-#define hmatrix2_writel(port,reg,value) \
- writel((value), (port)->regs + HMATRIX2_##reg)
+#define hmatrix2_readl(reg) \
+ readl((void *)HMATRIX_BASE + HMATRIX2_##reg)
+#define hmatrix2_writel(reg,value) \
+ writel((value), (void *)HMATRIX_BASE + HMATRIX2_##reg)
#endif /* __ASM_AVR32_HMATRIX2_H__ */
diff --git a/include/asm-avr32/arch-at32ap7000/memory-map.h b/include/asm-avr32/arch-at32ap7000/memory-map.h
index 8ffe851..5513e88 100644
--- a/include/asm-avr32/arch-at32ap7000/memory-map.h
+++ b/include/asm-avr32/arch-at32ap7000/memory-map.h
@@ -19,43 +19,48 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#ifndef __ASM_AVR32_PART_MEMORY_MAP_H__
-#define __ASM_AVR32_PART_MEMORY_MAP_H__
+#ifndef __AT32AP7000_MEMORY_MAP_H__
+#define __AT32AP7000_MEMORY_MAP_H__
-#define AUDIOC_BASE 0xFFF02800
-#define DAC_BASE 0xFFF02000
-#define DMAC_BASE 0xFF200000
-#define ECC_BASE 0xFFF03C00
-#define HISI_BASE 0xFFF02C00
-#define HMATRIX_BASE 0xFFF00800
-#define HSDRAMC_BASE 0xFFF03800
-#define HSMC_BASE 0xFFF03400
-#define LCDC_BASE 0xFF000000
-#define MACB0_BASE 0xFFF01800
-#define MACB1_BASE 0xFFF01C00
-#define MMCI_BASE 0xFFF02400
-#define PIOA_BASE 0xFFE02800
-#define PIOB_BASE 0xFFE02C00
-#define PIOC_BASE 0xFFE03000
-#define PIOD_BASE 0xFFE03400
-#define PIOE_BASE 0xFFE03800
-#define PSIF_BASE 0xFFE03C00
-#define PWM_BASE 0xFFF01400
-#define SM_BASE 0xFFF00000
-#define INTC_BASE 0XFFF00400
-#define SPI0_BASE 0xFFE00000
-#define SPI1_BASE 0xFFE00400
-#define SSC0_BASE 0xFFE01C00
-#define SSC1_BASE 0xFFE02000
-#define SSC2_BASE 0xFFE02400
-#define TIMER0_BASE 0xFFF00C00
-#define TIMER1_BASE 0xFFF01000
-#define TWI_BASE 0xFFE00800
-#define USART0_BASE 0xFFE00C00
-#define USART1_BASE 0xFFE01000
-#define USART2_BASE 0xFFE01400
-#define USART3_BASE 0xFFE01800
-#define USB_FIFO 0xFF300000
-#define USB_BASE 0xFFF03000
+/* Devices on the High Speed Bus (HSB) */
+#define LCDC_BASE 0xFF000000
+#define DMAC_BASE 0xFF200000
+#define USB_FIFO 0xFF300000
-#endif /* __ASM_AVR32_PART_MEMORY_MAP_H__ */
+/* Devices on Peripheral Bus A (PBA) */
+#define SPI0_BASE 0xFFE00000
+#define SPI1_BASE 0xFFE00400
+#define TWI_BASE 0xFFE00800
+#define USART0_BASE 0xFFE00C00
+#define USART1_BASE 0xFFE01000
+#define USART2_BASE 0xFFE01400
+#define USART3_BASE 0xFFE01800
+#define SSC0_BASE 0xFFE01C00
+#define SSC1_BASE 0xFFE02000
+#define SSC2_BASE 0xFFE02400
+#define PIOA_BASE 0xFFE02800
+#define PIOB_BASE 0xFFE02C00
+#define PIOC_BASE 0xFFE03000
+#define PIOD_BASE 0xFFE03400
+#define PIOE_BASE 0xFFE03800
+#define PSIF_BASE 0xFFE03C00
+
+/* Devices on Peripheral Bus B (PBB) */
+#define SM_BASE 0xFFF00000
+#define INTC_BASE 0xFFF00400
+#define HMATRIX_BASE 0xFFF00800
+#define TIMER0_BASE 0xFFF00C00
+#define TIMER1_BASE 0xFFF01000
+#define PWM_BASE 0xFFF01400
+#define MACB0_BASE 0xFFF01800
+#define MACB1_BASE 0xFFF01C00
+#define DAC_BASE 0xFFF02000
+#define MMCI_BASE 0xFFF02400
+#define AUDIOC_BASE 0xFFF02800
+#define HISI_BASE 0xFFF02C00
+#define USB_BASE 0xFFF03000
+#define HSMC_BASE 0xFFF03400
+#define HSDRAMC_BASE 0xFFF03800
+#define ECC_BASE 0xFFF03C00
+
+#endif /* __AT32AP7000_MEMORY_MAP_H__ */
diff --git a/include/asm-avr32/arch-at32ap7000/mmc.h b/include/asm-avr32/arch-at32ap7000/mmc.h
new file mode 100644
index 0000000..fcfbbb3
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap7000/mmc.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_MMC_H
+#define __ASM_AVR32_MMC_H
+
+struct mmc_cid {
+ unsigned long psn;
+ unsigned short oid;
+ unsigned char mid;
+ unsigned char prv;
+ unsigned char mdt;
+ char pnm[7];
+};
+
+struct mmc_csd
+{
+ u8 csd_structure:2,
+ spec_vers:4,
+ rsvd1:2;
+ u8 taac;
+ u8 nsac;
+ u8 tran_speed;
+ u16 ccc:12,
+ read_bl_len:4;
+ u64 read_bl_partial:1,
+ write_blk_misalign:1,
+ read_blk_misalign:1,
+ dsr_imp:1,
+ rsvd2:2,
+ c_size:12,
+ vdd_r_curr_min:3,
+ vdd_r_curr_max:3,
+ vdd_w_curr_min:3,
+ vdd_w_curr_max:3,
+ c_size_mult:3,
+ sector_size:5,
+ erase_grp_size:5,
+ wp_grp_size:5,
+ wp_grp_enable:1,
+ default_ecc:2,
+ r2w_factor:3,
+ write_bl_len:4,
+ write_bl_partial:1,
+ rsvd3:5;
+ u8 file_format_grp:1,
+ copy:1,
+ perm_write_protect:1,
+ tmp_write_protect:1,
+ file_format:2,
+ ecc:2;
+ u8 crc:7;
+ u8 one:1;
+};
+
+/* MMC Command numbers */
+#define MMC_CMD_GO_IDLE_STATE 0
+#define MMC_CMD_SEND_OP_COND 1
+#define MMC_CMD_ALL_SEND_CID 2
+#define MMC_CMD_SET_RELATIVE_ADDR 3
+#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3
+#define MMC_CMD_SET_DSR 4
+#define MMC_CMD_SELECT_CARD 7
+#define MMC_CMD_SEND_CSD 9
+#define MMC_CMD_SEND_CID 10
+#define MMC_CMD_SEND_STATUS 13
+#define MMC_CMD_SET_BLOCKLEN 16
+#define MMC_CMD_READ_SINGLE_BLOCK 17
+#define MMC_CMD_READ_MULTIPLE_BLOCK 18
+#define MMC_CMD_WRITE_BLOCK 24
+#define MMC_CMD_APP_CMD 55
+
+#define MMC_ACMD_SD_SEND_OP_COND 41
+
+#define R1_ILLEGAL_COMMAND (1 << 22)
+#define R1_APP_CMD (1 << 5)
+
+#endif /* __ASM_AVR32_MMC_H */
diff --git a/include/asm-avr32/arch-at32ap7000/platform.h b/include/asm-avr32/arch-at32ap7000/platform.h
deleted file mode 100644
index 7590501..0000000
--- a/include/asm-avr32/arch-at32ap7000/platform.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * Copyright (C) 2005-2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _ASM_AVR32_ARCH_PM_H
-#define _ASM_AVR32_ARCH_PM_H
-
-#include <config.h>
-
-enum clock_domain_id {
- CLOCK_CPU,
- CLOCK_HSB,
- CLOCK_PBA,
- CLOCK_PBB,
- NR_CLOCK_DOMAINS,
-};
-
-enum resource_type {
- RESOURCE_GPIO,
- RESOURCE_CLOCK,
-};
-
-enum gpio_func {
- GPIO_FUNC_GPIO,
- GPIO_FUNC_A,
- GPIO_FUNC_B,
-};
-
-enum device_id {
- DEVICE_HEBI,
- DEVICE_PBA_BRIDGE,
- DEVICE_PBB_BRIDGE,
- DEVICE_HRAMC,
- /* GPIO controllers must be kept together */
- DEVICE_PIOA,
- DEVICE_PIOB,
- DEVICE_PIOC,
- DEVICE_PIOD,
- DEVICE_PIOE,
- DEVICE_SM,
- DEVICE_INTC,
- DEVICE_HMATRIX,
-#if defined(CFG_HPDC)
- DEVICE_HPDC,
-#endif
-#if defined(CFG_MACB0)
- DEVICE_MACB0,
-#endif
-#if defined(CFG_MACB1)
- DEVICE_MACB1,
-#endif
-#if defined(CFG_LCDC)
- DEVICE_LCDC,
-#endif
-#if defined(CFG_USART0)
- DEVICE_USART0,
-#endif
-#if defined(CFG_USART1)
- DEVICE_USART1,
-#endif
-#if defined(CFG_USART2)
- DEVICE_USART2,
-#endif
-#if defined(CFG_USART3)
- DEVICE_USART3,
-#endif
-#if defined(CFG_MMCI)
- DEVICE_MMCI,
-#endif
-#if defined(CFG_DMAC)
- DEVICE_DMAC,
-#endif
- NR_DEVICES,
- NO_DEVICE = -1,
-};
-
-struct resource {
- enum resource_type type;
- union {
- struct {
- unsigned long base;
- } iomem;
- struct {
- unsigned char nr_pins;
- enum device_id gpio_dev;
- enum gpio_func func;
- unsigned short start;
- } gpio;
- struct {
- enum clock_domain_id id;
- unsigned char index;
- } clock;
- } u;
-};
-
-struct device {
- void *regs;
- unsigned int nr_resources;
- const struct resource *resource;
-};
-
-struct clock_domain {
- unsigned short reg;
- enum clock_domain_id id;
- enum device_id bridge;
-};
-
-extern const struct device chip_device[NR_DEVICES];
-extern const struct clock_domain chip_clock[NR_CLOCK_DOMAINS];
-
-/**
- * Set up PIO, clock management and I/O memory for a device.
- */
-const struct device *get_device(enum device_id devid);
-void put_device(const struct device *dev);
-
-int gpio_set_func(enum device_id gpio_devid, unsigned int start,
- unsigned int nr_pins, enum gpio_func func);
-void gpio_free(enum device_id gpio_devid, unsigned int start,
- unsigned int nr_pins);
-
-void pm_init(void);
-int pm_enable_clock(enum clock_domain_id id, unsigned int index);
-void pm_disable_clock(enum clock_domain_id id, unsigned int index);
-unsigned long pm_get_clock_freq(enum clock_domain_id domain);
-
-void cpu_enable_sdram(void);
-
-#endif /* _ASM_AVR32_ARCH_PM_H */
diff --git a/include/asm-avr32/global_data.h b/include/asm-avr32/global_data.h
index 01d836c..681c514 100644
--- a/include/asm-avr32/global_data.h
+++ b/include/asm-avr32/global_data.h
@@ -35,10 +35,8 @@
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- const struct device *console_uart;
- const struct device *sm;
unsigned long baudrate;
- unsigned long sdram_size;
+ unsigned long stack_end; /* highest stack address */
unsigned long have_console; /* serial_init() was called */
unsigned long reloc_off; /* Relocation Offset */
unsigned long env_addr; /* Address of env struct */
diff --git a/include/asm-avr32/initcalls.h b/include/asm-avr32/initcalls.h
index 7ba25cd..583e5dc 100644
--- a/include/asm-avr32/initcalls.h
+++ b/include/asm-avr32/initcalls.h
@@ -26,8 +26,6 @@
extern int cpu_init(void);
extern int timer_init(void);
-extern void board_init_memories(void);
-extern void board_init_pio(void);
extern void board_init_info(void);
#endif /* __ASM_AVR32_INITCALLS_H__ */
diff --git a/include/asm-blackfin/arch-bf533/bf533_serial.h b/include/asm-blackfin/arch-bf533/bf533_serial.h
index ce58863..65749ee 100644
--- a/include/asm-blackfin/arch-bf533/bf533_serial.h
+++ b/include/asm-blackfin/arch-bf533/bf533_serial.h
@@ -1,7 +1,7 @@
/*
* U-boot bf533_serial.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BF533_SERIAL_H_
diff --git a/include/asm-blackfin/arch-bf533/bf5xx_rtc.h b/include/asm-blackfin/arch-bf533/bf5xx_rtc.h
index bc09922..f4440a8 100644
--- a/include/asm-blackfin/arch-bf533/bf5xx_rtc.h
+++ b/include/asm-blackfin/arch-bf533/bf5xx_rtc.h
@@ -1,7 +1,7 @@
/*
* U-boot - bf533_rtc.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BF533_RTC_H_
diff --git a/include/asm-blackfin/arch-bf533/cplbtab.h b/include/asm-blackfin/arch-bf533/cplbtab.h
deleted file mode 100644
index 89f0325..0000000
--- a/include/asm-blackfin/arch-bf533/cplbtab.h
+++ /dev/null
@@ -1,482 +0,0 @@
-/*This file is subject to the terms and conditions of the GNU General Public
- * License.
- *
- * Blackfin BF533/2.6 support : LG Soft India
- * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
- * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
- * shouldn't be victimized. cplbmgr.S search logic is corrected
- * to findout the appropriate victim.
- * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
- * : LG Soft India
- */
-#include <config.h>
-
-#ifndef __ARCH_BFINNOMMU_CPLBTAB_H
-#define __ARCH_BFINNOMMU_CPLBTAB_H
-
-/*************************************************************************
- * ICPLB TABLE
- *************************************************************************/
-
-.data
-/* This table is configurable */
- .align 4;
-
-/* Data Attibutes*/
-
-#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
-#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
-
-/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
-
-#define ANOMALY_05000158 0x200
-#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
-#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
-#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
-#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
-#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
-#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
-
-#else /*Write Through */
-#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
-#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
-#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
-#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
-#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
-#endif
-
-.align 4;
-.global _ipdt_table _ipdt_table:.byte4 0x00000000;
-.byte4(SDRAM_IKERNEL); /*SDRAM_Page0 */
-.byte4 0x00400000;
-.byte4(SDRAM_IKERNEL); /*SDRAM_Page1 */
-.byte4 0x00800000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page2 */
-.byte4 0x00C00000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page3 */
-.byte4 0x01000000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page4 */
-.byte4 0x01400000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page5 */
-.byte4 0x01800000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page6 */
-.byte4 0x01C00000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page7 */
-#ifndef CONFIG_EZKIT /*STAMP Memory regions */
-.byte4 0x02000000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page8 */
-.byte4 0x02400000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page9 */
-.byte4 0x02800000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page10 */
-.byte4 0x02C00000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page11 */
-.byte4 0x03000000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page12 */
-.byte4 0x03400000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page13 */
-.byte4 0x03800000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page14 */
-.byte4 0x03C00000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page15 */
-#endif
-.byte4 0x20000000;
-.byte4(SDRAM_EBIU); /* Async Memory Bank 2 (Secnd) */
-
-#ifdef CONFIG_STAMP
-.byte4 0x04000000;
-.byte4(SDRAM_IGENERIC);
-.byte4 0x04400000;
-.byte4(SDRAM_IGENERIC);
-.byte4 0x04800000;
-.byte4(SDRAM_IGENERIC);
-.byte4 0x04C00000;
-.byte4(SDRAM_IGENERIC);
-.byte4 0x05000000;
-.byte4(SDRAM_IGENERIC);
-.byte4 0x05400000;
-.byte4(SDRAM_IGENERIC);
-.byte4 0x05800000;
-.byte4(SDRAM_IGENERIC);
-.byte4 0x05C00000;
-.byte4(SDRAM_IGENERIC);
-.byte4 0x06000000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page25 */
-.byte4 0x06400000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page26 */
-.byte4 0x06800000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page27 */
-.byte4 0x06C00000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page28 */
-.byte4 0x07000000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page29 */
-.byte4 0x07400000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page30 */
-.byte4 0x07800000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page31 */
-.byte4 0x07C00000;
-.byte4(SDRAM_IKERNEL); /*SDRAM_Page32 */
-#endif
-.byte4 0xffffffff; /* end of section - termination */
-
-/**********************************************************************
- * PAGE DESCRIPTOR TABLE
- *
- **********************************************************************/
-
-/* Till here we are discussing about the static memory management model.
- * However, the operating envoronments commonly define more CPLB
- * descriptors to cover the entire addressable memory than will fit into
- * the available on-chip 16 CPLB MMRs. When this happens, the below table
- * will be used which will hold all the potentially required CPLB descriptors
- *
- * This is how Page descriptor Table is implemented in uClinux/Blackfin.
- */
-.global _dpdt_table _dpdt_table:.byte4 0x00000000;
-.byte4(SDRAM_DKERNEL); /*SDRAM_Page0 */
-.byte4 0x00400000;
-.byte4(SDRAM_DKERNEL); /*SDRAM_Page1 */
-.byte4 0x00800000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page2 */
-.byte4 0x00C00000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page3 */
-.byte4 0x01000000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page4 */
-.byte4 0x01400000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page5 */
-.byte4 0x01800000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page6 */
-.byte4 0x01C00000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page7 */
-
-#ifndef CONFIG_EZKIT
-.byte4 0x02000000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page8 */
-.byte4 0x02400000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page9 */
-.byte4 0x02800000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page10 */
-.byte4 0x02C00000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page11 */
-.byte4 0x03000000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page12 */
-.byte4 0x03400000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page13 */
-.byte4 0x03800000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page14 */
-.byte4 0x03C00000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page15 */
-#endif
-
-#ifdef CONFIG_STAMP
-.byte4 0x04000000;
-.byte4(SDRAM_DGENERIC);
-.byte4 0x04400000;
-.byte4(SDRAM_DGENERIC);
-.byte4 0x04800000;
-.byte4(SDRAM_DGENERIC);
-.byte4 0x04C00000;
-.byte4(SDRAM_DGENERIC);
-.byte4 0x05000000;
-.byte4(SDRAM_DGENERIC);
-.byte4 0x05400000;
-.byte4(SDRAM_DGENERIC);
-.byte4 0x05800000;
-.byte4(SDRAM_DGENERIC);
-.byte4 0x05C00000;
-.byte4(SDRAM_DGENERIC);
-.byte4 0x06000000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page25 */
-.byte4 0x06400000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page26 */
-.byte4 0x06800000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page27 */
-.byte4 0x06C00000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page28 */
-.byte4 0x07000000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page29 */
-.byte4 0x07400000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page30 */
-.byte4 0x07800000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page31 */
-.byte4 0x07C00000;
-.byte4(SDRAM_DKERNEL); /*SDRAM_Page32 */
-#endif
-
-.byte4 0x20000000;
-.byte4(SDRAM_EBIU); /* Async Memory Bank 0 (Prim A) */
-
-#if (BFIN_CPU == ADSP_BF533)
-.byte4 0xFF800000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF801000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF802000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF803000;
-.byte4(L1_DMEMORY);
-#endif
-.byte4 0xFF804000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF805000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF806000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF807000;
-.byte4(L1_DMEMORY);
-#if (BFIN_CPU == ADSP_BF533)
-.byte4 0xFF900000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF901000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF902000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF903000;
-.byte4(L1_DMEMORY);
-#endif
-#if ((BFIN_CPU == ADSP_BF532) || (BFIN_CPU == ADSP_BF533))
-.byte4 0xFF904000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF905000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF906000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF907000;
-.byte4(L1_DMEMORY);
-#endif
-.byte4 0xFFB00000;
-.byte4(L1_DMEMORY);
-
-.byte4 0xffffffff; /*end of section - termination */
-
-#ifdef CONFIG_CPLB_INFO
-.global _ipdt_swapcount_table; /* swapin count first, then swapout count */
-_ipdt_swapcount_table:
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 10 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 20 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 30 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 40 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 50 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 60 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 70 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 80 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 90 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 100 */
-
-.global _dpdt_swapcount_table; /* swapin count first, then swapout count */
-_dpdt_swapcount_table:
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 10 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 20 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 30 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 40 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 50 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 60 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 70 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 80 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 80 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 100 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 110 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 120 */
-#endif
-
-#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/
diff --git a/include/asm-blackfin/arch-bf533/irq.h b/include/asm-blackfin/arch-bf533/irq.h
index 9c5230d..3235745 100644
--- a/include/asm-blackfin/arch-bf533/irq.h
+++ b/include/asm-blackfin/arch-bf533/irq.h
@@ -1,7 +1,7 @@
/*
* U-boot bf533_irq.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* This file is based on
* linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
@@ -33,8 +33,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BF533_IRQ_H_
diff --git a/include/asm-blackfin/arch-bf537/bf537_serial.h b/include/asm-blackfin/arch-bf537/bf537_serial.h
index 1610411..64088f2 100644
--- a/include/asm-blackfin/arch-bf537/bf537_serial.h
+++ b/include/asm-blackfin/arch-bf537/bf537_serial.h
@@ -1,7 +1,7 @@
/*
* U-boot bf537_serial.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BF537_SERIAL_H_
diff --git a/include/asm-blackfin/arch-bf537/bf5xx_rtc.h b/include/asm-blackfin/arch-bf537/bf5xx_rtc.h
index 0043e42..db5cc6f 100644
--- a/include/asm-blackfin/arch-bf537/bf5xx_rtc.h
+++ b/include/asm-blackfin/arch-bf537/bf5xx_rtc.h
@@ -1,7 +1,7 @@
/*
* U-boot - bf537_rtc.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BF537_RTC_H_
diff --git a/include/asm-blackfin/arch-bf537/cplbtab.h b/include/asm-blackfin/arch-bf537/cplbtab.h
deleted file mode 100644
index c5151bb..0000000
--- a/include/asm-blackfin/arch-bf537/cplbtab.h
+++ /dev/null
@@ -1,408 +0,0 @@
-/*This file is subject to the terms and conditions of the GNU General Public
- * License.
- *
- * Blackfin BF533/2.6 support : LG Soft India
- * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
- * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
- * shouldn't be victimized. cplbmgr.S search logic is corrected
- * to findout the appropriate victim.
- * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
- * : LG Soft India
- */
-#include <config.h>
-
-#ifndef __ARCH_BFINNOMMU_CPLBTAB_H
-#define __ARCH_BFINNOMMU_CPLBTAB_H
-
-/*
- * ICPLB TABLE
- */
-
-.data
-/* This table is configurable */
- .align 4;
-
-/* Data Attibutes*/
-
-#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
-#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
-
-/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
-
-#define ANOMALY_05000158 0x200
-#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
-#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
-#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
-#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
-#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
-#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
-
-#else /*Write Through */
-#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
-#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
-#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
-#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
-#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
-#endif
-
-.align 4;
-.global _ipdt_table _ipdt_table:.byte4 0x00000000;
-.byte4(SDRAM_IKERNEL); /*SDRAM_Page0 */
-.byte4 0x00400000;
-.byte4(SDRAM_IKERNEL); /*SDRAM_Page1 */
-.byte4 0x00800000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page2 */
-.byte4 0x00C00000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page3 */
-.byte4 0x01000000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page4 */
-.byte4 0x01400000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page5 */
-.byte4 0x01800000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page6 */
-.byte4 0x01C00000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page7 */
-.byte4 0x02000000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page8 */
-.byte4 0x02400000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page9 */
-.byte4 0x02800000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page10 */
-.byte4 0x02C00000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page11 */
-.byte4 0x03000000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page12 */
-.byte4 0x03400000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page13 */
-.byte4 0x03800000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page14 */
-.byte4 0x03C00000;
-.byte4(SDRAM_IGENERIC); /*SDRAM_Page15 */
-.byte4 0x20000000;
-.byte4(SDRAM_EBIU); /* Async Memory Bank 2 (Secnd) */
-
-.byte4 0xffffffff; /* end of section - termination */
-
-/*
- * PAGE DESCRIPTOR TABLE
- *
- */
-
-/*
- * Till here we are discussing about the static memory management model.
- * However, the operating envoronments commonly define more CPLB
- * descriptors to cover the entire addressable memory than will fit into
- * the available on-chip 16 CPLB MMRs. When this happens, the below table
- * will be used which will hold all the potentially required CPLB descriptors
- *
- * This is how Page descriptor Table is implemented in uClinux/Blackfin.
- */
-.global _dpdt_table _dpdt_table:.byte4 0x00000000;
-.byte4(SDRAM_DKERNEL); /*SDRAM_Page0 */
-.byte4 0x00400000;
-.byte4(SDRAM_DKERNEL); /*SDRAM_Page1 */
-.byte4 0x00800000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page2 */
-.byte4 0x00C00000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page3 */
-.byte4 0x01000000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page4 */
-.byte4 0x01400000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page5 */
-.byte4 0x01800000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page6 */
-.byte4 0x01C00000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page7 */
-.byte4 0x02000000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page8 */
-.byte4 0x02400000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page9 */
-.byte4 0x02800000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page10 */
-.byte4 0x02C00000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page11 */
-.byte4 0x03000000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page12 */
-.byte4 0x03400000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page13 */
-.byte4 0x03800000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page14 */
-.byte4 0x03C00000;
-.byte4(SDRAM_DGENERIC); /*SDRAM_Page15 */
-.byte4 0x20000000;
-.byte4(SDRAM_EBIU); /* Async Memory Bank 0 (Prim A) */
-
-#if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537))
-.byte4 0xFF800000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF801000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF802000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF803000;
-.byte4(L1_DMEMORY);
-#endif
-.byte4 0xFF804000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF805000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF806000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF807000;
-.byte4(L1_DMEMORY);
-#if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537))
-.byte4 0xFF900000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF901000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF902000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF903000;
-.byte4(L1_DMEMORY);
-#endif
-.byte4 0xFF904000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF905000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF906000;
-.byte4(L1_DMEMORY);
-.byte4 0xFF907000;
-.byte4(L1_DMEMORY);
-
-.byte4 0xFFB00000;
-.byte4(L1_DMEMORY);
-
-.byte4 0xffffffff; /*end of section - termination */
-
-#ifdef CONFIG_CPLB_INFO
-.global _ipdt_swapcount_table; /* swapin count first, then swapout count */
-_ipdt_swapcount_table:
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 10 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 20 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 30 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 40 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 50 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 60 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 70 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 80 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 90 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 100 */
-
-.global _dpdt_swapcount_table; /* swapin count first, then swapout count */
-_dpdt_swapcount_table:
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 10 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 20 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 30 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 40 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 50 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 60 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 70 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 80 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 80 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 100 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 110 */
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000;
-.byte4 0x00000000; /* 120 */
-
-#endif
-
-#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/
diff --git a/include/asm-blackfin/arch-bf537/irq.h b/include/asm-blackfin/arch-bf537/irq.h
index 4cb4c15..527d8a2 100644
--- a/include/asm-blackfin/arch-bf537/irq.h
+++ b/include/asm-blackfin/arch-bf537/irq.h
@@ -1,7 +1,7 @@
/*
* U-boot bf537_irq.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* This file is based on
* linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
@@ -33,8 +33,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BF537_IRQ_H_
diff --git a/include/asm-blackfin/arch-bf561/bf561_serial.h b/include/asm-blackfin/arch-bf561/bf561_serial.h
index 0810228..eb01ca2 100644
--- a/include/asm-blackfin/arch-bf561/bf561_serial.h
+++ b/include/asm-blackfin/arch-bf561/bf561_serial.h
@@ -1,7 +1,7 @@
/*
* U-boot bf561_serial.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BF561_SERIAL_H_
diff --git a/include/asm-blackfin/arch-common/bf53x_rtc.h b/include/asm-blackfin/arch-common/bf53x_rtc.h
index bc09922..f4440a8 100644
--- a/include/asm-blackfin/arch-common/bf53x_rtc.h
+++ b/include/asm-blackfin/arch-common/bf53x_rtc.h
@@ -1,7 +1,7 @@
/*
* U-boot - bf533_rtc.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BF533_RTC_H_
diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h
index 7766c4a..438e50b 100644
--- a/include/asm-blackfin/bitops.h
+++ b/include/asm-blackfin/bitops.h
@@ -1,7 +1,7 @@
/*
* U-boot - bitops.h Routines for bit operations
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BLACKFIN_BITOPS_H
diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h
index 0ec9207..bf502a4 100644
--- a/include/asm-blackfin/blackfin.h
+++ b/include/asm-blackfin/blackfin.h
@@ -1,7 +1,7 @@
/*
* U-boot - blackfin.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BLACKFIN_H_
diff --git a/include/asm-blackfin/blackfin_defs.h b/include/asm-blackfin/blackfin_defs.h
index 2190215..451d29c 100644
--- a/include/asm-blackfin/blackfin_defs.h
+++ b/include/asm-blackfin/blackfin_defs.h
@@ -1,7 +1,7 @@
/*
* U-boot - blackfin_defs.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef __BLACKFIN_DEFS_H__
diff --git a/include/asm-blackfin/byteorder.h b/include/asm-blackfin/byteorder.h
index 3b4df4e..a1a52a5 100644
--- a/include/asm-blackfin/byteorder.h
+++ b/include/asm-blackfin/byteorder.h
@@ -1,7 +1,7 @@
/*
* U-boot - byteorder.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BLACKFIN_BYTEORDER_H
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
index dd695e1..9d8d9ec 100644
--- a/include/asm-blackfin/cplb.h
+++ b/include/asm-blackfin/cplb.h
@@ -50,7 +50,7 @@
#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
@@ -61,20 +61,20 @@
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
-#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
#else /*Write Through */
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
-#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
#endif
#if defined(CONFIG_BF561)
-#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM +L1 + ASYNC_Memory */
+#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 4) /* SDRAM +L1 + ASYNC_Memory */
#else
-#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 3) /* SDRAM + L1 + ASYNC_Memory */
+#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM + L1 + ASYNC_Memory */
#endif
#endif /* _CPLB_H */
diff --git a/include/asm-blackfin/current.h b/include/asm-blackfin/current.h
index 108c279..ed2b851 100644
--- a/include/asm-blackfin/current.h
+++ b/include/asm-blackfin/current.h
@@ -1,7 +1,7 @@
/*
* U-boot - current.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BLACKFIN_CURRENT_H
diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h
index 0c01e9f..ea0b366 100644
--- a/include/asm-blackfin/delay.h
+++ b/include/asm-blackfin/delay.h
@@ -1,7 +1,7 @@
/*
* U-boot - delay.h Routines for introducing delays
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BLACKFIN_DELAY_H
diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h
index b64d406..eb84f11 100644
--- a/include/asm-blackfin/entry.h
+++ b/include/asm-blackfin/entry.h
@@ -1,7 +1,7 @@
/*
* U-boot - entry.h Routines for context saving and restoring
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef __BLACKFIN_ENTRY_H
@@ -27,7 +27,6 @@
#include <linux/config.h>
#include <asm/setup.h>
-#include <asm/page.h>
/*
* Stack layout in 'ret_from_exception':
diff --git a/include/asm-blackfin/errno.h b/include/asm-blackfin/errno.h
index 713bba0..0d2c618 100644
--- a/include/asm-blackfin/errno.h
+++ b/include/asm-blackfin/errno.h
@@ -1,7 +1,7 @@
/*
* U-boot - errno.h Error number defines
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BLACKFIN_ERRNO_H
diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h
index 1c73853..9024d0a 100644
--- a/include/asm-blackfin/global_data.h
+++ b/include/asm-blackfin/global_data.h
@@ -1,7 +1,7 @@
/*
* U-boot - global_data.h Declarations for global data of u-boot
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef __ASM_GBL_DATA_H
diff --git a/include/asm-blackfin/hw_irq.h b/include/asm-blackfin/hw_irq.h
index baa3e0c..9b36055 100644
--- a/include/asm-blackfin/hw_irq.h
+++ b/include/asm-blackfin/hw_irq.h
@@ -1,7 +1,7 @@
/*
* U-boot - hw_irq.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* This file is based on
* linux/arch/$(ARCH)/platform/$(PLATFORM)/hw_irq.h
@@ -24,8 +24,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#include <linux/config.h>
diff --git a/include/asm-blackfin/io-kernel.h b/include/asm-blackfin/io-kernel.h
index 3c087c3..5d0ad06 100644
--- a/include/asm-blackfin/io-kernel.h
+++ b/include/asm-blackfin/io-kernel.h
@@ -1,7 +1,7 @@
/*
* U-boot - io-kernel.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BLACKFIN_IO_H
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
index 6bab6e7..332d2c6 100644
--- a/include/asm-blackfin/io.h
+++ b/include/asm-blackfin/io.h
@@ -1,7 +1,7 @@
/*
* U-boot - io.h IO routines
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BLACKFIN_IO_H
@@ -37,6 +37,7 @@ extern void cf_outb(unsigned char val, volatile unsigned char *addr);
static inline void sync(void)
{
+ __builtin_bfin_ssync();
}
/*
diff --git a/include/asm-blackfin/irq.h b/include/asm-blackfin/irq.h
index aede742..1fff316 100644
--- a/include/asm-blackfin/irq.h
+++ b/include/asm-blackfin/irq.h
@@ -1,7 +1,7 @@
/*
* U-boot - irq.h Interrupt related header file
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* This file was based on
* linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
@@ -31,8 +31,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BLACKFIN_IRQ_H_
diff --git a/include/asm-blackfin/linkage.h b/include/asm-blackfin/linkage.h
index 18f0c36..4fc1acf 100644
--- a/include/asm-blackfin/linkage.h
+++ b/include/asm-blackfin/linkage.h
@@ -1,7 +1,7 @@
/*
* U-boot - linkage.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _LINUX_LINKAGE_H
diff --git a/include/asm-blackfin/machdep.h b/include/asm-blackfin/machdep.h
index 4fea74c..8bf9473 100644
--- a/include/asm-blackfin/machdep.h
+++ b/include/asm-blackfin/machdep.h
@@ -1,7 +1,7 @@
/*
* U-boot - machdep.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BLACKFIN_MACHDEP_H
diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h
index d9d8bf9..cb448ad 100644
--- a/include/asm-blackfin/mem_init.h
+++ b/include/asm-blackfin/mem_init.h
@@ -1,7 +1,7 @@
/*
* U-boot - mem_init.h Header file for memory initialization
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#if (CONFIG_MEM_MT48LC16M16A2TG_75 || \
diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h
deleted file mode 100644
index d59828c..0000000
--- a/include/asm-blackfin/page.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * U-boot - page.h
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _BLACKFIN_PAGE_H
-#define _BLACKFIN_PAGE_H
-
-#include <linux/config.h>
-
-/* PAGE_SHIFT determines the page size */
-
-#define PAGE_SHIFT (12)
-#define PAGE_SIZE (4096)
-#define PAGE_MASK (~(PAGE_SIZE-1))
-
-#ifdef __KERNEL__
-
-#include <asm/setup.h>
-
-#if PAGE_SHIFT < 13
-#define KTHREAD_SIZE (8192)
-#else
-#define KTHREAD_SIZE PAGE_SIZE
-#endif
-
-#ifndef __ASSEMBLY__
-
-#define get_user_page(vaddr) __get_free_page(GFP_KERNEL)
-#define free_user_page(page, addr) free_page(addr)
-
-#define clear_page(page) memset((page), 0, PAGE_SIZE)
-#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE)
-
-#define clear_user_page(page, vaddr) clear_page(page)
-#define copy_user_page(to, from, vaddr) copy_page(to, from)
-
-/*
- * These are used to make use of C type-checking..
- */
-typedef struct {
- unsigned long pte;
-} pte_t;
-typedef struct {
- unsigned long pmd[16];
-} pmd_t;
-typedef struct {
- unsigned long pgd;
-} pgd_t;
-typedef struct {
- unsigned long pgprot;
-} pgprot_t;
-
-#define pte_val(x) ((x).pte)
-#define pmd_val(x) ((&x)->pmd[0])
-#define pgd_val(x) ((x).pgd)
-#define pgprot_val(x) ((x).pgprot)
-
-#define __pte(x) ((pte_t) { (x) } )
-#define __pmd(x) ((pmd_t) { (x) } )
-#define __pgd(x) ((pgd_t) { (x) } )
-#define __pgprot(x) ((pgprot_t) { (x) } )
-
-/* to align the pointer to the (next) page boundary */
-#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)
-
-/* Pure 2^n version of get_order */
-extern __inline__ int get_order(unsigned long size)
-{
- int order;
-
- size = (size - 1) >> (PAGE_SHIFT - 1);
- order = -1;
- do {
- size >>= 1;
- order++;
- } while (size);
- return order;
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#include <asm/page_offset.h>
-
-#define PAGE_OFFSET (PAGE_OFFSET_RAW)
-
-#ifndef __ASSEMBLY__
-
-#define __pa(vaddr) virt_to_phys((void *)vaddr)
-#define __va(paddr) phys_to_virt((unsigned long)paddr)
-
-#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)
-#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
-#define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
-
-#define PAGE_BUG(page) do { \
- BUG(); \
-} while (0)
-
-#endif
-
-#endif
-
-#endif
diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h
index 262473f..cfd8f1f 100644
--- a/include/asm-blackfin/page_offset.h
+++ b/include/asm-blackfin/page_offset.h
@@ -1,7 +1,7 @@
/*
* U-boot - page_offset.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
/*
diff --git a/include/asm-blackfin/posix_types.h b/include/asm-blackfin/posix_types.h
index f1f2b5f..27889e8 100644
--- a/include/asm-blackfin/posix_types.h
+++ b/include/asm-blackfin/posix_types.h
@@ -1,7 +1,7 @@
/*
* U-boot - posix_types.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef __ARCH_BLACKFIN_POSIX_TYPES_H
diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h
index df49bed..6cd4f56 100644
--- a/include/asm-blackfin/processor.h
+++ b/include/asm-blackfin/processor.h
@@ -1,7 +1,7 @@
/*
* U-boot - processor.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* This file is based on
* include/asm-m68k/processor.h
@@ -23,8 +23,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef __ASM_BLACKFIN_PROCESSOR_H
diff --git a/include/asm-blackfin/ptrace.h b/include/asm-blackfin/ptrace.h
index afd5777..f1b7d00 100644
--- a/include/asm-blackfin/ptrace.h
+++ b/include/asm-blackfin/ptrace.h
@@ -1,7 +1,7 @@
/*
* U-boot - ptrace.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BLACKFIN_PTRACE_H
diff --git a/include/asm-blackfin/segment.h b/include/asm-blackfin/segment.h
index 9e6d817..f309543 100644
--- a/include/asm-blackfin/segment.h
+++ b/include/asm-blackfin/segment.h
@@ -1,7 +1,7 @@
/*
* U-boot - segment.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BLACKFIN_SEGMENT_H
diff --git a/include/asm-blackfin/setup.h b/include/asm-blackfin/setup.h
index a3c1715..b6b8267 100644
--- a/include/asm-blackfin/setup.h
+++ b/include/asm-blackfin/setup.h
@@ -1,7 +1,7 @@
/*
* U-boot - setup.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* This file is based on
* asm/setup.h -- Definition of the Linux/Blackfin setup information
@@ -22,8 +22,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BLACKFIN_SETUP_H
diff --git a/include/asm-blackfin/shared_resources.h b/include/asm-blackfin/shared_resources.h
index fbef186..d280ffe 100644
--- a/include/asm-blackfin/shared_resources.h
+++ b/include/asm-blackfin/shared_resources.h
@@ -1,7 +1,7 @@
/*
* U-boot - setup.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _SHARED_RESOURCES_H_
diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h
index aac6bc9..dd50207 100644
--- a/include/asm-blackfin/string.h
+++ b/include/asm-blackfin/string.h
@@ -1,7 +1,7 @@
/*
* U-boot - string.h String functions
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
/* Changed by Lineo Inc. May 2001 */
@@ -30,7 +30,6 @@
#ifdef __KERNEL__ /* only set these up for kernel code */
#include <asm/setup.h>
-#include <asm/page.h>
#include <config.h>
#include <asm/blackfin.h>
diff --git a/include/asm-blackfin/system.h b/include/asm-blackfin/system.h
index 0e53adf..eda887f 100644
--- a/include/asm-blackfin/system.h
+++ b/include/asm-blackfin/system.h
@@ -1,7 +1,7 @@
/*
* U-boot - system.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BLACKFIN_SYSTEM_H
diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h
index 29e6eba..b90ceda 100644
--- a/include/asm-blackfin/traps.h
+++ b/include/asm-blackfin/traps.h
@@ -1,7 +1,7 @@
/*
* U-boot - traps.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* This file is based on
* linux/include/asm/traps.h
@@ -23,8 +23,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
/*
diff --git a/include/asm-blackfin/types.h b/include/asm-blackfin/types.h
index 942ed27..665a419 100644
--- a/include/asm-blackfin/types.h
+++ b/include/asm-blackfin/types.h
@@ -1,7 +1,7 @@
/*
* U-boot - types.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _BLACKFIN_TYPES_H
diff --git a/include/asm-blackfin/u-boot.h b/include/asm-blackfin/u-boot.h
index e1a435a..b4928da 100644
--- a/include/asm-blackfin/u-boot.h
+++ b/include/asm-blackfin/u-boot.h
@@ -1,7 +1,7 @@
/*
* U-boot - u-boot.h Structure declarations for board specific data
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -21,15 +21,15 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _U_BOOT_H_
#define _U_BOOT_H_ 1
typedef struct bd_info {
- int bi_baudrate; /* serial console baudrate */
+ int bi_baudrate; /* serial console baudrate */
unsigned long bi_ip_addr; /* IP Address */
unsigned char bi_enetaddr[6]; /* Ethernet adress */
unsigned long bi_arch_number; /* unique id for this board */
diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h
index 61e2bfe..6e913bb 100644
--- a/include/asm-blackfin/uaccess.h
+++ b/include/asm-blackfin/uaccess.h
@@ -1,7 +1,7 @@
/*
* U-boot - uaccess.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* This file is based on
* Based on: include/asm-m68knommu/uaccess.h
@@ -22,8 +22,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef __BLACKFIN_UACCESS_H
diff --git a/include/asm-blackfin/virtconvert.h b/include/asm-blackfin/virtconvert.h
index 769f5a0..9eda9f8 100644
--- a/include/asm-blackfin/virtconvert.h
+++ b/include/asm-blackfin/virtconvert.h
@@ -1,7 +1,7 @@
/*
* U-boot - virtconvert.h
*
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef __BLACKFIN_VIRT_CONVERT__
@@ -33,7 +33,6 @@
#include <linux/config.h>
#include <asm/setup.h>
-#include <asm/page.h>
#define mm_vtop(vaddr) ((unsigned long) vaddr)
#define mm_ptov(vaddr) ((unsigned long) vaddr)
diff --git a/include/asm-microblaze/suzaku.h b/include/asm-microblaze/microblaze_intc.h
index c57a144..6635aea 100644
--- a/include/asm-microblaze/suzaku.h
+++ b/include/asm-microblaze/microblaze_intc.h
@@ -1,7 +1,7 @@
/*
- * (C) Copyright 2004 Atmark Techno, Inc.
+ * (C) Copyright 2007 Michal Simek
*
- * Yasushi SHOJI <yashi@atmark-techno.com>
+ * Michal SIMEK <monstr@monstr.cz>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -13,7 +13,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -22,6 +22,19 @@
* MA 02111-1307 USA
*/
-/* System Register (GPIO) */
-#define MICROBLAZE_SYSREG_BASE_ADDR 0xFFFFA000
-#define MICROBLAZE_SYSREG_RECONFIGURE (1 << 0)
+typedef volatile struct microblaze_intc_t {
+ int isr; /* interrupt status register */
+ int ipr; /* interrupt pending register */
+ int ier; /* interrupt enable register */
+ int iar; /* interrupt acknowledge register */
+ int sie; /* set interrupt enable bits */
+ int cie; /* clear interrupt enable bits */
+ int ivr; /* interrupt vector register */
+ int mer; /* master enable register */
+} microblaze_intc_t;
+
+struct irq_action {
+ interrupt_handler_t *handler; /* pointer to interrupt rutine */
+ void *arg;
+ int count; /* number of interrupt */
+};
diff --git a/include/asm-microblaze/microblaze_timer.h b/include/asm-microblaze/microblaze_timer.h
new file mode 100644
index 0000000..844c8db
--- /dev/null
+++ b/include/asm-microblaze/microblaze_timer.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal SIMEK <monstr@monstr.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define TIMER_ENABLE_ALL 0x400 /* ENALL */
+#define TIMER_PWM 0x200 /* PWMA0 */
+#define TIMER_INTERRUPT 0x100 /* T0INT */
+#define TIMER_ENABLE 0x080 /* ENT0 */
+#define TIMER_ENABLE_INTR 0x040 /* ENIT0 */
+#define TIMER_RESET 0x020 /* LOAD0 */
+#define TIMER_RELOAD 0x010 /* ARHT0 */
+#define TIMER_EXT_CAPTURE 0x008 /* CAPT0 */
+#define TIMER_EXT_COMPARE 0x004 /* GENT0 */
+#define TIMER_DOWN_COUNT 0x002 /* UDT0 */
+#define TIMER_CAPTURE_MODE 0x001 /* MDT0 */
+
+typedef volatile struct microblaze_timer_t {
+ int control; /* control/statuc register TCSR */
+ int loadreg; /* load register TLR */
+ int counter; /* timer/counter register */
+} microblaze_timer_t;
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index c113b7e..26bc875 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -49,6 +49,9 @@ typedef struct global_data {
unsigned long scc_clk;
unsigned long brg_clk;
#endif
+#if defined(CONFIG_MPC7448HPC2)
+ unsigned long mem_clk;
+#endif
#if defined(CONFIG_MPC83XX)
/* There are other clocks in the MPC83XX */
u32 csb_clk;
diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h
new file mode 100644
index 0000000..114dc92
--- /dev/null
+++ b/include/asm-ppc/gpio.h
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* 4xx PPC's have 2 GPIO controllers */
+#if defined(CONFIG_405EZ) || \
+ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define GPIO_GROUP_MAX 2
+#else
+#define GPIO_GROUP_MAX 1
+#endif
+
+#define GPIO_MAX 32
+#define GPIO_ALT1_SEL 0x40000000
+#define GPIO_ALT2_SEL 0x80000000
+#define GPIO_ALT3_SEL 0xc0000000
+#define GPIO_IN_SEL 0x40000000
+#define GPIO_MASK 0xc0000000
+
+#define GPIO_VAL(gpio) (0x80000000 >> (gpio))
+
+#ifndef __ASSEMBLY__
+typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
+typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
+typedef enum gpio_out { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t;
+
+typedef struct {
+ unsigned long add; /* gpio core base address */
+ gpio_driver_t in_out; /* Driver Setting */
+ gpio_select_t alt_nb; /* Selected Alternate */
+} gpio_param_s;
+#endif
+
+void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
+void gpio_write_bit(int pin, int val);
+void gpio_set_chip_configuration(void);
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index c380c54..6c6480d 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -189,7 +189,7 @@
#define OF_CPU "PowerPC,5200@0"
#define OF_SOC "soc5200@f0000000"
-#define OF_TBCLK (bd->bi_busfreq / 8)
+#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
/*
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index d2af0e1..79937dc 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -342,8 +342,12 @@
#endif
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
+#undef CONFIG_OF_FLAT_TREE
#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_HAS_BD_T 1
+#define CONFIG_OF_HAS_UBOOT_ENV 1
+
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
diff --git a/include/configs/NC650.h b/include/configs/NC650.h
index 8da29c4..a12c8da 100644
--- a/include/configs/NC650.h
+++ b/include/configs/NC650.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
+ * (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de
* (C) Copyright 2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
@@ -237,18 +237,8 @@
/*
* NAND flash support
*/
-#define CFG_NAND_LEGACY
-
#define CFG_MAX_NAND_DEVICE 1
-#define NAND_ChipID_UNKNOWN 0x00
-#define SECTORSIZE 512
-#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-#define ADDR_COLUMN 1
-#define NAND_NO_RB
-
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index 9e02ca3..35b6a51 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -31,20 +31,18 @@
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
-#define CONFIG_ACADIA 1 /* Board is Acadia */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
-#undef CFG_DRAM_TEST /* Disable-takes long time */
+#define CONFIG_ACADIA 1 /* Board is Acadia */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */
#define CONFIG_NO_SERIAL_EEPROM
/*#undef CONFIG_NO_SERIAL_EEPROM*/
#ifdef CONFIG_NO_SERIAL_EEPROM
-
/*----------------------------------------------------------------------------
* PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
* assuming a 66MHz input clock to the 405EZ.
@@ -59,24 +57,125 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE 0x00000000
-#define CFG_FLASH_BASE 0xFE000000
#define CFG_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN (384 * 1024)/* Reserve 128 kB for malloc() */
+#define CFG_MALLOC_LEN (512 * 1024)/* Reserve 512 kB for malloc() */
+
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xfe000000
#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_CPLD_BASE 0x80000000
+#define CFG_NAND_ADDR 0xd0000000
#define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */
-/*
- * Define here the location of the environment variables (FLASH).
- * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
- * supported for backward compatibility.
- */
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM 1 /* OCM as init ram */
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR 0xF8000000
+#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* size for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#define CFG_BASE_BAUD 691200
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI 1
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
- #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#else
- #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
+#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
+#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
#endif
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * RAM (CRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_MBYTES_RAM 64 /* 64MB */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible) */
+#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
+#define CONFIG_DTT_AD7414 1 /* use AD7414 */
+#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
+#define CFG_DTT_MAX_TEMP 70
+#define CFG_DTT_LOW_TEMP -30
+#define CFG_DTT_HYSTERESIS 3
+
+#if 0 /* test-only... */
+/*-----------------------------------------------------------------------
+ * SPI stuff - Define to include SPI control
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SPI
+#endif
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ *----------------------------------------------------------------------*/
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0 /* PHY address */
+#define CONFIG_NET_MULTI 1
+#define CFG_RX_ETH_BUFFER 16 /* # of rx buffers & descriptors*/
+
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
@@ -122,13 +221,6 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_NET_MULTI 1
-#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
@@ -166,7 +258,6 @@
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
CFG_CMD_USB)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -174,76 +265,34 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-/*
+/*-----------------------------------------------------------------------
* Miscellaneous configurable options
- */
+ *----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
-#define CFG_BASE_BAUD 691200
-#define CONFIG_BAUDRATE 115200
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
-
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* I2C SYSMON (LM75, AD7414 is almost compatible) */
-#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
-#define CONFIG_DTT_AD7414 1 /* use AD7414 */
-#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
-#define CFG_DTT_MAX_TEMP 70
-#define CFG_DTT_LOW_TEMP -30
-#define CFG_DTT_HYSTERESIS 3
-
-#if 0 /* test-only... */
-/*-----------------------------------------------------------------------
- * SPI stuff - Define to include SPI control
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SPI
-#endif
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
@@ -251,39 +300,13 @@
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
-#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-
-#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
-#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
-#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
-
-#undef CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
-#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
-#endif
-
#ifdef TEST_ONLY_NAND
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
#define CFG_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
-#define CFG_NAND_BASE (CFG_NAND + CFG_NAND_CS)
+#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
#endif
@@ -297,50 +320,42 @@
#endif
/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR 0xF8000000
-#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
-#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */
-#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
-
-#define CFG_GBL_DATA_SIZE 128 /* size for initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
- */
-#define CFG_NAND 0xd0000000
+ *----------------------------------------------------------------------*/
#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
-/* Memory Bank 0 (Flash) initialization */
+/* Memory Bank 0 (Flash) initialization */
#define CFG_EBC_PB0AP 0x03337200
-#define CFG_EBC_PB0CR 0xfe0bc000 /* BAS=0xFE0,BS=32MB,BU=R/W,BW=32bit */
+#define CFG_EBC_PB0CR 0xfe0bc000
-/* Memory Bank 1 (CRAM) initialization */
+/* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
+/* Memory Bank 1 (CRAM) initialization */
#define CFG_EBC_PB1AP 0x030400c0
#define CFG_EBC_PB1CR 0x000bc000
-/* Memory Bank 2 (CRAM) initialization */
+/* Memory Bank 2 (CRAM) initialization */
#define CFG_EBC_PB2AP 0x030400c0
#define CFG_EBC_PB2CR 0x020bc000
/* Memory Bank 3 (NAND-FLASH) initialization */
#define CFG_EBC_PB3AP 0x018003c0
-#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000)
+#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000)
-/* Memory Bank 4 (CPLD) initialization */
+/* Memory Bank 4 (CPLD) initialization */
#define CFG_EBC_PB4AP 0x04006000
-#define CFG_EBC_PB4CR 0x80018000 /* BAS=0x000,BS=16MB,BU=R/W,BW=32bit */
+#define CFG_EBC_PB4CR (CFG_CPLD_BASE | 0x18000)
#define CFG_EBC_CFG 0xf8400000
/*-----------------------------------------------------------------------
+ * GPIO Setup
+ *----------------------------------------------------------------------*/
+#define CFG_GPIO_CRAM_CLK 8
+#define CFG_GPIO_CRAM_WAIT 9
+#define CFG_GPIO_CRAM_ADV 10
+#define CFG_GPIO_CRAM_CRE (32 + 21)
+
+/*-----------------------------------------------------------------------
* Definitions for GPIO_0 setup (PPC405EZ specific)
*
* GPIO0[0-3] - External Bus Controller CS_4 - CS_7 Outputs
@@ -389,25 +404,6 @@
#define CFG_GPIO1_TSRL 0x00000000
#define CFG_GPIO1_TCR 0xFFFF8014
-/*-----------------------------------------------------------------------
- * EPLD Regs.
- */
-#define EPLD_BASE 0x80000000
-#define EPLD_ETHRSTBOOT 0x10
-#define EPLD_CTRL 0x14
-#define EPLD_MUXOE 0x16
-
-/*
- * State definations
- */
-#define LOAK_INIT 0x494e4954 /* ASCII "INIT" */
-#define LOAK_NONE 0x4e4f4e45 /* ASCII "NONE" */
-#define LOAK_CRAM 0x4352414d /* ASCII "CRAM" */
-#define LOAK_PSRAM 0x50535241 /* ASCII "PSRA" - PSRAM */
-#define LOAK_OCM 0x4f434d20 /* ASCII "OCM " */
-#define LOAK_ZERO 0x5a45524f /* ASCII "ZERO" */
-#define LOAK_SPL 0x53504c20 /* ASCII "SPL" */
-
/*
* Internal Definitions
*
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index 458ebab..beaf385 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -62,11 +62,14 @@
*/
#define CFG_PLL0_OPT 0x04
-#define CFG_USART1 1
-
-#define CFG_CONSOLE_UART_DEV DEVICE_USART1
+#undef CONFIG_USART0
+#define CONFIG_USART1 1
+#undef CONFIG_USART2
+#undef CONFIG_USART3
/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION 1
+
#define CONFIG_CMDLINE_TAG 1
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
@@ -75,16 +78,47 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS \
- "console=ttyUS0 root=/dev/mtdblock1 fbmem=600k"
+ "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2 fbmem=600k"
+
+#define CONFIG_BOOTCOMMAND \
+ "fsload; bootm $(fileaddr)"
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_AUTOBOOT 1
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT \
+ "Press SPACE to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*
+ * These are "locally administered ethernet addresses" generated by
+ * ./tools/gen_eth_addr
+ *
+ * After booting the board for the first time, new addresses should be
+ * generated and assigned to the environment variables "ethaddr" and
+ * "eth1addr".
+ */
+#define CONFIG_ETHADDR "6a:87:71:14:cd:cb"
+#define CONFIG_ETH1ADDR "ca:f8:15:e6:3e:e6"
+#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
+#define CONFIG_NET_MULTI 1
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_SUBNETMASK \
+ | CONFIG_BOOTP_GATEWAY)
#define CONFIG_COMMANDS (CFG_CMD_BDI \
| CFG_CMD_LOADS \
| CFG_CMD_LOADB \
- /* | CFG_CMD_IMI */ \
+ | CFG_CMD_IMI \
/* | CFG_CMD_CACHE */ \
| CFG_CMD_FLASH \
| CFG_CMD_MEMORY \
- /* | CFG_CMD_NET */ \
+ | CFG_CMD_NET \
| CFG_CMD_ENV \
/* | CFG_CMD_IRQ */ \
| CFG_CMD_BOOTD \
@@ -96,7 +130,7 @@
/* | CFG_CMD_I2C */ \
| CFG_CMD_REGINFO \
/* | CFG_CMD_DATE */ \
- /* | CFG_CMD_DHCP */ \
+ | CFG_CMD_DHCP \
/* | CFG_CMD_AUTOSCRIPT */ \
/* | CFG_CMD_MII */ \
| CFG_CMD_MISC \
@@ -106,19 +140,22 @@
/* | CFG_CMD_SAVES */ \
/* | CFG_CMD_SPI */ \
/* | CFG_CMD_PING */ \
- /* | CFG_CMD_MMC */ \
- /* | CFG_CMD_FAT */ \
- /* | CFG_CMD_IMLS */ \
+ | CFG_CMD_MMC \
+ | CFG_CMD_FAT \
+ | CFG_CMD_IMLS \
/* | CFG_CMD_ITEST */ \
- /* | CFG_CMD_EXT2 */ \
+ | CFG_CMD_EXT2 \
+ | CFG_CMD_JFFS2 \
)
#include <cmd_confdefs.h>
#define CONFIG_ATMEL_USART 1
+#define CONFIG_MACB 1
#define CONFIG_PIO2 1
#define CFG_NR_PIOS 5
#define CFG_HSDRAMC 1
+#define CONFIG_MMC 1
#define CFG_DCACHE_LINESZ 32
#define CFG_ICACHE_LINESZ 32
@@ -150,16 +187,8 @@
#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
#define CFG_MALLOC_LEN (256*1024)
-#define CFG_MALLOC_END \
- ({ \
- DECLARE_GLOBAL_DATA_PTR; \
- CFG_SDRAM_BASE + gd->sdram_size; \
- })
-#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN)
-
#define CFG_DMA_ALLOC_LEN (16384)
-#define CFG_DMA_ALLOC_END (CFG_MALLOC_START)
-#define CFG_DMA_ALLOC_START (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN)
+
/* Allow 2MB for the kernel run-time image */
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000)
#define CFG_BOOTPARAMS_LEN (16 * 1024)
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index 1606d0d..7f55366 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -78,7 +78,7 @@
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
-#define CFG_ACE_BASE 0xe0000000 /* Xilinx ACE controller - Compact Flash */
+#define CFG_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in internal SRAM)
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
new file mode 100644
index 0000000..cb159e7
--- /dev/null
+++ b/include/configs/ml401.h
@@ -0,0 +1,230 @@
+/*
+ * (C) Copyright 2007 Czech Technical University.
+ *
+ * Michal SIMEK <monstr@seznam.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "../board/xilinx/ml401/xparameters.h"
+
+#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
+#define CONFIG_ML401 1 /* ML401 Board */
+
+/* uart */
+#define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR
+#define CONFIG_BAUDRATE XILINX_UART_BAUDRATE
+#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
+
+/* setting reset address */
+#define CFG_RESET_ADDRESS TEXT_BASE
+
+/* ethernet */
+#define CONFIG_EMACLITE 1
+#define XPAR_EMAC_0_DEVICE_ID XPAR_XEMAC_NUM_INSTANCES
+
+/* gpio */
+#define CFG_GPIO_0 1
+#define CFG_GPIO_0_ADDR XILINX_GPIO_BASEADDR
+
+/* interrupt controller */
+#define CFG_INTC_0 1
+#define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR
+#define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
+
+/* timer */
+#define CFG_TIMER_0 1
+#define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR
+#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
+#define FREQUENCE XILINX_CLOCK_FREQ
+#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
+
+/*
+ * memory layout - Example
+ * TEXT_BASE = 0x1200_0000;
+ * CFG_SRAM_BASE = 0x1000_0000;
+ * CFG_SRAM_SIZE = 0x0400_0000;
+ *
+ * CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
+ * CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
+ * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
+ *
+ * 0x1000_0000 CFG_SDRAM_BASE
+ * FREE
+ * 0x1200_0000 TEXT_BASE
+ * U-BOOT code
+ * 0x1202_0000
+ * FREE
+ *
+ * STACK
+ * 0x13F7_F000 CFG_MALLOC_BASE
+ * MALLOC_AREA 256kB Alloc
+ * 0x11FB_F000 CFG_MONITOR_BASE
+ * MONITOR_CODE 256kB Env
+ * 0x13FF_F000 CFG_GBL_DATA_OFFSET
+ * GLOBAL_DATA 4kB bd, gd
+ * 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
+ */
+
+/* ddr sdram - main memory */
+#define CFG_SDRAM_BASE XILINX_RAM_START
+#define CFG_SDRAM_SIZE XILINX_RAM_SIZE
+#define CFG_MEMTEST_START CFG_SDRAM_BASE
+#define CFG_MEMTEST_END (CFG_SDRAM_BASE + 0x1000)
+
+/* global pointer */
+#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
+#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */
+
+/* monitor code */
+#define SIZE 0x40000
+#define CFG_MONITOR_LEN SIZE
+#define CFG_MONITOR_BASE (CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
+#define CFG_MONITOR_END (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_MALLOC_LEN SIZE
+#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+
+/* stack */
+#define CFG_INIT_SP_OFFSET CFG_MONITOR_BASE
+
+/*#define RAMENV */
+#define FLASH
+
+#ifdef FLASH
+ #define CFG_FLASH_BASE XILINX_FLASH_START
+ #define CFG_FLASH_SIZE XILINX_FLASH_SIZE
+ #define CFG_FLASH_CFI 1
+ #define CFG_FLASH_CFI_DRIVER 1
+ #define CFG_FLASH_EMPTY_INFO 1 /* ?empty sector */
+ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+ #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+
+ #ifdef RAMENV
+ #define CFG_ENV_IS_NOWHERE 1
+ #define CFG_ENV_SIZE 0x1000
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
+
+ #else /* !RAMENV */
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_ADDR 0x40000
+ #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+ #define CFG_ENV_SIZE 0x2000
+ #endif /* !RAMBOOT */
+#else /* !FLASH */
+ /* ENV in RAM */
+ #define CFG_NO_FLASH 1
+ #define CFG_ENV_IS_NOWHERE 1
+ #define CFG_ENV_SIZE 0x1000
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
+#endif /* !FLASH */
+
+#ifdef FLASH
+ #ifdef RAMENV
+ #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
+ CFG_CMD_MEMORY |\
+ CFG_CMD_MISC |\
+ CFG_CMD_AUTOSCRIPT |\
+ CFG_CMD_IRQ |\
+ CFG_CMD_ASKENV |\
+ CFG_CMD_BDI |\
+ CFG_CMD_RUN |\
+ CFG_CMD_LOADS |\
+ CFG_CMD_LOADB |\
+ CFG_CMD_IMI |\
+ CFG_CMD_NET |\
+ CFG_CMD_CACHE |\
+ CFG_CMD_IMLS |\
+ CFG_CMD_FLASH |\
+ CFG_CMD_PING \
+ )
+ #else /* !RAMENV */
+ #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
+ CFG_CMD_MEMORY |\
+ CFG_CMD_MISC |\
+ CFG_CMD_AUTOSCRIPT |\
+ CFG_CMD_IRQ |\
+ CFG_CMD_ASKENV |\
+ CFG_CMD_BDI |\
+ CFG_CMD_RUN |\
+ CFG_CMD_LOADS |\
+ CFG_CMD_LOADB |\
+ CFG_CMD_IMI |\
+ CFG_CMD_NET |\
+ CFG_CMD_CACHE |\
+ CFG_CMD_IMLS |\
+ CFG_CMD_FLASH |\
+ CFG_CMD_PING |\
+ CFG_CMD_ENV |\
+ CFG_CMD_SAVES \
+ )
+
+ #endif
+
+#else /* !FLASH */
+ #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
+ CFG_CMD_MEMORY |\
+ CFG_CMD_MISC |\
+ CFG_CMD_AUTOSCRIPT |\
+ CFG_CMD_IRQ |\
+ CFG_CMD_ASKENV |\
+ CFG_CMD_BDI |\
+ CFG_CMD_RUN |\
+ CFG_CMD_LOADS |\
+ CFG_CMD_LOADB |\
+ CFG_CMD_IMI |\
+ CFG_CMD_NET |\
+ CFG_CMD_CACHE |\
+ CFG_CMD_PING \
+ )
+#endif /* !FLASH */
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/* Miscellaneous configurable options */
+#define CFG_PROMPT "U-Boot-mONStR> "
+#define CFG_CBSIZE 512 /* size of console buffer */
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
+#define CFG_MAXARGS 15 /* max number of command args */
+#define CFG_LONGHELP
+#define CFG_LOAD_ADDR 0x12000000 /* default load address */
+
+#define CONFIG_BOOTDELAY 30
+#define CONFIG_BOOTARGS "root=romfs"
+#define CONFIG_HOSTNAME "ml401"
+#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
+#define CONFIG_IPADDR 192.168.0.3
+#define CONFIG_SERVERIP 192.168.0.5
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
+
+/* architecture dependent code */
+#define CFG_USR_EXCEP /* user exception */
+#define CFG_HZ 1000
+
+/* system ace */
+/*#define CONFIG_SYSTEMACE
+#define DEBUG_SYSTEMACE
+#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
+#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
+#define CONFIG_DOS_PARTITION
+*/
+#endif /* __CONFIG_H */
diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h
new file mode 100644
index 0000000..243a3f6
--- /dev/null
+++ b/include/configs/mpc7448hpc2.h
@@ -0,0 +1,411 @@
+/*
+ * Copyright (c) 2005 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2006
+ * Alex Bounine , Tundra Semiconductor Corp.
+ * Roy Zang , <tie-fei.zang@freescale.com> Freescale Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board specific configuration options for Freescale
+ * MPC7448HPC2 (High-Performance Computing II) (Taiga) board
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+/* Board Configuration Definitions */
+/* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */
+
+#define CONFIG_MPC7448HPC2
+
+#define CONFIG_74xx
+#define CONFIG_750FX /* this option to enable init of extended BATs */
+#define CONFIG_ALTIVEC /* undef to disable */
+
+#define CFG_BOARD_NAME "MPC7448 HPC II"
+#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II"
+
+#define CFG_OCN_CLK 133000000 /* 133 MHz */
+#define CFG_CONFIG_BUS_CLK 133000000
+
+#define CFG_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */
+
+#undef CONFIG_ECC /* disable ECC support */
+
+/* Board-specific Initialization Functions to be called */
+#define CFG_BOARD_ASM_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
+
+/*#define CFG_HUSH_PARSER */
+#undef CFG_HUSH_PARSER
+
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,7448@0"
+#define OF_TSI "tsi108@c0000000"
+#define OF_TBCLK (bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808"
+
+/*
+ * The following defines let you select what serial you want to use
+ * for your console driver.
+ *
+ * what to do:
+ * If you have hacked a serial cable onto the second DUART channel,
+ * change the CFG_DUART port from 1 to 0 below.
+ *
+ */
+
+#define CONFIG_CONS_INDEX 1
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK CFG_OCN_CLK * 8
+
+#define CFG_NS16550_COM1 (CFG_TSI108_CSR_RST_BASE+0x7808)
+#define CFG_NS16550_COM2 (CFG_TSI108_CSR_RST_BASE+0x7C08)
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#undef CONFIG_BOOTARGS
+/* #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\"
+ * to mount root filesystem over NFS;echo" */
+
+#if (CONFIG_BOOTDELAY >= 0)
+#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\
+ setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
+ ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200"
+#endif
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+
+#define CONFIG_SERIAL "No. 1"
+
+/* Networking Configuration */
+
+#define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */
+
+#define CONFIG_TSI108_ETH
+#define CONFIG_TSI108_ETH_NUM_PORTS 2
+
+#define CONFIG_NET_MULTI
+
+#define CONFIG_BOOTFILE zImage.initrd.elf
+#define CONFIG_LOADADDR 0x400000
+
+/*-------------------------------------------------------------------------- */
+
+#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
+#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
+ CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_ASKENV \
+ | CFG_CMD_CACHE \
+ | CFG_CMD_PCI \
+ | CFG_CMD_I2C \
+ | CFG_CMD_SDRAM \
+ | CFG_CMD_EEPROM \
+ | CFG_CMD_FLASH \
+ | CFG_CMD_ENV \
+ | CFG_CMD_BSP \
+ | CFG_CMD_DHCP \
+ | CFG_CMD_PING \
+ | CFG_CMD_DATE)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*set date in u-boot*/
+#define CONFIG_RTC_M48T35A
+#define CFG_NVRAM_BASE_ADDR 0xfc000000
+#define CFG_NVRAM_SIZE 0x8000
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_VERSION_VARIABLE 1
+#define CONFIG_TSI108_I2C
+
+#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)/* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x00400000 /* default load address */
+
+#define CFG_HZ 1000 /* decr freq: 1ms ticks */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+/*
+ * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
+ * To an unused memory region. The stack will remain in cache until RAM
+ * is initialized
+ */
+#undef CFG_INIT_RAM_LOCK
+#define CFG_INIT_RAM_ADDR 0x07d00000 /* unused memory region */
+#define CFG_INIT_RAM_END 0x4000/* larger space - we have SDRAM initialized */
+
+#define CFG_GBL_DATA_SIZE 128/* size in bytes reserved for init data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+
+#define CFG_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */
+#define CFG_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */
+
+#define CFG_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */
+#define CFG_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */
+
+#define CFG_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */
+
+#define CFG_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */
+
+#define CFG_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */
+
+#define CFG_FLASH_BASE 0xff000000 /* Base Address of Flash device */
+#define CFG_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */
+
+#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */
+
+#define PCI0_IO_BASE_BOOTM 0xfd000000
+
+#define CFG_RESET_ADDRESS 0x3fffff00
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE TEXT_BASE /* u-boot code base */
+#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
+
+/* Peripheral Device section */
+
+/*
+ * Resources on the Tsi108
+ */
+
+#define CFG_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */
+#define CFG_TSI108_CSR_BASE CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */
+
+#define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */
+
+#undef DISABLE_PBM
+
+/*
+ * PCI stuff
+ *
+ */
+
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_TSI108_PCI /* include tsi108 pci support */
+
+#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
+#define PCI_HOST_FORCE 1 /* configure as pci host */
+#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
+
+#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+/* PCI MEMORY MAP section */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
+
+/* PCI Memory Space */
+#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS)
+#define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) /* 0xE0000000 */
+#define CFG_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */
+
+/* PCI I/O Space */
+#define CFG_PCI_IO_BUS 0x00000000
+#define CFG_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */
+
+#define CFG_PCI_IO_SIZE 0x01000000 /* 16MB */
+
+#define _IO_BASE 0x00000000 /* points to PCI I/O space */
+
+/* PCI Config Space mapping */
+#define CFG_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */
+#define CFG_PCI_CFG_SIZE 0x01000000 /* 16MB */
+
+#define CFG_IBAT0U 0xFE0003FF
+#define CFG_IBAT0L 0xFE000002
+
+#define CFG_IBAT1U 0x00007FFF
+#define CFG_IBAT1L 0x00000012
+
+#define CFG_IBAT2U 0x80007FFF
+#define CFG_IBAT2L 0x80000022
+
+#define CFG_IBAT3U 0x00000000
+#define CFG_IBAT3L 0x00000000
+
+#define CFG_IBAT4U 0x00000000
+#define CFG_IBAT4L 0x00000000
+
+#define CFG_IBAT5U 0x00000000
+#define CFG_IBAT5L 0x00000000
+
+#define CFG_IBAT6U 0x00000000
+#define CFG_IBAT6L 0x00000000
+
+#define CFG_IBAT7U 0x00000000
+#define CFG_IBAT7L 0x00000000
+
+#define CFG_DBAT0U 0xE0003FFF
+#define CFG_DBAT0L 0xE000002A
+
+#define CFG_DBAT1U 0x00007FFF
+#define CFG_DBAT1L 0x00000012
+
+#define CFG_DBAT2U 0x00000000
+#define CFG_DBAT2L 0x00000000
+
+#define CFG_DBAT3U 0xC0000003
+#define CFG_DBAT3L 0xC000002A
+
+#define CFG_DBAT4U 0x00000000
+#define CFG_DBAT4L 0x00000000
+
+#define CFG_DBAT5U 0x00000000
+#define CFG_DBAT5L 0x00000000
+
+#define CFG_DBAT6U 0x00000000
+#define CFG_DBAT6L 0x00000000
+
+#define CFG_DBAT7U 0x00000000
+#define CFG_DBAT7L 0x00000000
+
+/* I2C addresses for the two DIMM SPD chips */
+#define DIMM0_I2C_ADDR 0x51
+#define DIMM1_I2C_ADDR 0x52
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1/* Flash can be at one of two addresses */
+#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_WRITE_SWAPPED_DATA
+
+#define PHYS_FLASH_SIZE 0x01000000
+#define CFG_MAX_FLASH_SECT (128)
+
+#define CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_ADDR 0xFC000000
+
+#define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * L2CR setup -- make sure this is right for your board!
+ * look in include/mpc74xx.h for the defines used here
+ */
+#undef CFG_L2
+
+#define L2_INIT 0
+#define L2_ENABLE (L2_INIT | L2CR_L2E)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CFG_SERIAL_HANG_IN_EXCEPTION
+#endif /* __CONFIG_H */
diff --git a/include/configs/sc3.h b/include/configs/sc3.h
index 8298084..6b6acfa 100644
--- a/include/configs/sc3.h
+++ b/include/configs/sc3.h
@@ -133,8 +133,8 @@
#if 1 /* feel free to disable for development */
#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
-#define CONFIG_AUTOBOOT_PROMPT "\nSC3 - booting... stop with S\n"
-#define CONFIG_AUTOBOOT_DELAY_STR "S" /* 1st "password" */
+#define CONFIG_AUTOBOOT_PROMPT "\nSC3 - booting... stop with ENTER\n"
+#define CONFIG_AUTOBOOT_DELAY_STR "\n" /* 1st "password" */
#endif
/*
@@ -416,11 +416,11 @@ extern unsigned long offsetOfEnvironment;
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
-/* No command line, one static partition Partition 3 contains jffs2 rootfs */
+/* No command line, one static partition */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV "nand0"
-#define CONFIG_JFFS2_PART_SIZE 0x00400000
-#define CONFIG_JFFS2_PART_OFFSET 0x00c00000
+#define CONFIG_JFFS2_PART_SIZE 0x01000000
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
/*-----------------------------------------------------------------------
* Cache Configuration
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 29f3b40..1f19621 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -33,7 +33,6 @@
*----------------------------------------------------------------------*/
/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
#ifndef CONFIG_RAINIER
-#define CONFIG_SEQUOIA 1 /* Board is Sequoia */
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
#else
#define CONFIG_440GRX 1 /* Specific PPC440GRx */
@@ -75,9 +74,7 @@
* Initial RAM & stack pointer
*----------------------------------------------------------------------*/
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
-#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
-
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
@@ -381,9 +378,6 @@
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
-#define CFG_FLASH CFG_FLASH_BASE
-#define CFG_NAND 0xD0000000
-#define CFG_CPLD 0xC0000000
/*
* On Sequoia CS0 and CS3 are switched when configuring for NAND booting
@@ -392,25 +386,25 @@
#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CFG_EBC_PB0AP 0x03017200
-#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000)
+#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000)
/* Memory Bank 3 (NAND-FLASH) initialization */
#define CFG_EBC_PB3AP 0x018003c0
-#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000)
+#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000)
#else
#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
/* Memory Bank 3 (NOR-FLASH) initialization */
#define CFG_EBC_PB3AP 0x03017200
-#define CFG_EBC_PB3CR (CFG_FLASH | 0xda000)
+#define CFG_EBC_PB3CR (CFG_FLASH_BASE | 0xda000)
/* Memory Bank 0 (NAND-FLASH) initialization */
#define CFG_EBC_PB0AP 0x018003c0
-#define CFG_EBC_PB0CR (CFG_NAND | 0x1c000)
+#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000)
#endif
/* Memory Bank 2 (CPLD) initialization */
#define CFG_EBC_PB2AP 0x24814580
-#define CFG_EBC_PB2CR (CFG_CPLD | 0x38000)
+#define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x38000)
/*-----------------------------------------------------------------------
* NAND FLASH
diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h
index 1ee6be1..8224555 100644
--- a/include/configs/suzaku.h
+++ b/include/configs/suzaku.h
@@ -44,12 +44,17 @@
#define CFG_FLASH_SIZE 0x00400000
#define CFG_RESET_ADDRESS 0xfff00100
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CFG_MONITOR_BASE (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - (1024 * 1024))
+#define CFG_MONITOR_BASE (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - (1024 * 1024))
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
+#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - (1024 * 1024))
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 115200 }
+/* System Register (GPIO) */
+#define MICROBLAZE_SYSREG_BASE_ADDR 0xFFFFA000
+#define MICROBLAZE_SYSREG_RECONFIGURE (1 << 0)
+
#define CONFIG_COMMANDS (CONFIG__CMD_DFL)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h
new file mode 100644
index 0000000..a2f4810
--- /dev/null
+++ b/include/configs/xupv2p.h
@@ -0,0 +1,174 @@
+/*
+ * (C) Copyright 2007 Czech Technical University.
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "../board/xilinx/xupv2p/xparameters.h"
+
+#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
+#define CONFIG_XUPV2P 1
+
+/* uart */
+#define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR
+#define CONFIG_BAUDRATE XILINX_UART_BAUDRATE
+#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
+
+/* ethernet */
+#define CONFIG_EMAC 1
+#define XPAR_EMAC_0_DEVICE_ID XPAR_XEMAC_NUM_INSTANCES
+
+/*
+ * setting reset address
+ *
+ * TEXT_BASE is set to place, where the U-BOOT run in RAM, but
+ * if you want to store U-BOOT in flash, set CFG_RESET_ADDRESS
+ * to FLASH memory and after loading bitstream jump to FLASH.
+ * U-BOOT auto-relocate to TEXT_BASE. After RESET command Microblaze
+ * jump to CFG_RESET_ADDRESS where is the original U-BOOT code.
+ */
+#define CFG_RESET_ADDRESS 0x36000000
+
+/* gpio */
+#define CFG_GPIO_0 1
+#define CFG_GPIO_0_ADDR XILINX_GPIO_BASEADDR
+
+/* interrupt controller */
+#define CFG_INTC_0 1
+#define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR
+#define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
+
+/* timer */
+#define CFG_TIMER_0 1
+#define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR
+#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
+#define FREQUENCE XILINX_CLOCK_FREQ
+#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
+
+/*
+ * memory layout - Example
+ * TEXT_BASE = 0x3600_0000;
+ * CFG_SRAM_BASE = 0x3000_0000;
+ * CFG_SRAM_SIZE = 0x1000_0000;
+ *
+ * CFG_GBL_DATA_OFFSET = 0x3000_0000 + 0x1000_0000 - 0x1000 = 0x3FFF_F000
+ * CFG_MONITOR_BASE = 0x3FFF_F000 - 0x40000 = 0x3FFB_F000
+ * CFG_MALLOC_BASE = 0x3FFB_F000 - 0x40000 = 0x3FF7_F000
+ *
+ * 0x3000_0000 CFG_SDRAM_BASE
+ * FREE
+ * 0x3600_0000 TEXT_BASE
+ * U-BOOT code
+ * 0x3602_0000
+ * FREE
+ *
+ * STACK
+ * 0x3FF7_F000 CFG_MALLOC_BASE
+ * MALLOC_AREA 256kB Alloc
+ * 0x3FFB_F000 CFG_MONITOR_BASE
+ * MONITOR_CODE 256kB Env
+ * 0x3FFF_F000 CFG_GBL_DATA_OFFSET
+ * GLOBAL_DATA 4kB bd, gd
+ * 0x4000_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
+ */
+
+/* ddr sdram - main memory */
+#define CFG_SDRAM_BASE XILINX_RAM_START
+#define CFG_SDRAM_SIZE XILINX_RAM_SIZE
+#define CFG_MEMTEST_START CFG_SDRAM_BASE
+#define CFG_MEMTEST_END (CFG_SDRAM_BASE + 0x1000)
+
+/* global pointer */
+#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
+#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */
+
+/* monitor code */
+#define SIZE 0x40000
+#define CFG_MONITOR_LEN SIZE
+#define CFG_MONITOR_BASE (CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
+#define CFG_MONITOR_END (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_MALLOC_LEN SIZE
+#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+
+/* stack */
+#define CFG_INIT_SP_OFFSET CFG_MALLOC_BASE
+
+#define CFG_NO_FLASH 1
+#define CFG_ENV_IS_NOWHERE 1
+#define CFG_ENV_SIZE 0x1000
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
+#define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
+ CFG_CMD_MEMORY |\
+ CFG_CMD_IRQ |\
+ CFG_CMD_BDI |\
+ CFG_CMD_NET |\
+ CFG_CMD_IMI |\
+ CFG_CMD_ECHO |\
+ CFG_CMD_CACHE |\
+ CFG_CMD_RUN |\
+ CFG_CMD_AUTOSCRIPT |\
+ CFG_CMD_ASKENV |\
+ CFG_CMD_LOADS |\
+ CFG_CMD_LOADB |\
+ CFG_CMD_MISC |\
+ CFG_CMD_PING \
+ )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/* Miscellaneous configurable options */
+#define CFG_PROMPT "U-Boot-mONStR> "
+#define CFG_CBSIZE 512 /* size of console buffer */
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
+#define CFG_MAXARGS 15 /* max number of command args */
+#define CFG_LONGHELP
+#define CFG_LOAD_ADDR 0x12000000 /* default load address */
+
+#define CONFIG_BOOTDELAY 30
+#define CONFIG_BOOTARGS "root=romfs"
+#define CONFIG_HOSTNAME "ml401"
+#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
+#define CONFIG_IPADDR 192.168.0.3
+#define CONFIG_SERVERIP 192.168.0.5
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
+
+/* architecture dependent code */
+#define CFG_USR_EXCEP /* user exception */
+#define CFG_HZ 1000
+
+#define CONFIG_PREBOOT "echo U-BOOT by mONStR;" \
+ "base 0;" \
+ "echo"
+
+
+/* system ace */
+/*#define CONFIG_SYSTEMACE
+#define DEBUG_SYSTEMACE
+#define CFG_SYSTEMACE_BASE 0xCF000000
+#define CFG_SYSTEMACE_WIDTH 16
+#define CONFIG_DOS_PARTITION*/
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index b59f75b..0a41dff 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -32,7 +32,6 @@
*----------------------------------------------------------------------*/
/* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/
#ifndef CONFIG_YELLOWSTONE
-#define CONFIG_YOSEMITE 1 /* Board is Yosemite */
#define CONFIG_440EP 1 /* Specific PPC440EP support */
#define CONFIG_HOSTNAME yosemite
#else
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index eb4859c..7f8b022 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -120,7 +120,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/
-#undef CONFIG_DDR_ECC /* no ECC support for now */
+#define CONFIG_DDR_ECC 1 /* with ECC support */
/*-----------------------------------------------------------------------
* I2C
diff --git a/include/fdt.h b/include/fdt.h
new file mode 100644
index 0000000..3dd3aca
--- /dev/null
+++ b/include/fdt.h
@@ -0,0 +1,79 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public License
+ * as published by the Free Software Foundation; either version 2.1 of
+ * the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _FDT_H
+#define _FDT_H
+
+#ifndef __ASSEMBLY__
+
+struct fdt_header {
+ uint32_t magic; /* magic word FDT_MAGIC */
+ uint32_t totalsize; /* total size of DT block */
+ uint32_t off_dt_struct; /* offset to structure */
+ uint32_t off_dt_strings; /* offset to strings */
+ uint32_t off_mem_rsvmap; /* offset to memory reserve map */
+ uint32_t version; /* format version */
+ uint32_t last_comp_version; /* last compatible version */
+
+ /* version 2 fields below */
+ uint32_t boot_cpuid_phys; /* Which physical CPU id we're
+ booting on */
+ /* version 3 fields below */
+ uint32_t size_dt_strings; /* size of the strings block */
+
+ /* version 17 fields below */
+ uint32_t size_dt_struct; /* size of the structure block */
+};
+
+struct fdt_reserve_entry {
+ uint64_t address;
+ uint64_t size;
+};
+
+struct fdt_node_header {
+ uint32_t tag;
+ char name[0];
+};
+
+struct fdt_property {
+ uint32_t tag;
+ uint32_t len;
+ uint32_t nameoff;
+ char data[0];
+};
+
+#endif /* !__ASSEMBLY */
+
+#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */
+#define FDT_TAGSIZE sizeof(uint32_t)
+
+#define FDT_BEGIN_NODE 0x1 /* Start node: full name */
+#define FDT_END_NODE 0x2 /* End node */
+#define FDT_PROP 0x3 /* Property: name off,
+ size, content */
+#define FDT_NOP 0x4 /* nop */
+#define FDT_END 0x9
+
+#define FDT_V1_SIZE (7*sizeof(uint32_t))
+#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(uint32_t))
+#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(uint32_t))
+#define FDT_V16_SIZE FDT_V3_SIZE
+#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(uint32_t))
+
+#endif /* _FDT_H */
diff --git a/include/asm-microblaze/platform.h b/include/fdt_support.h
index 2096cce..a276834 100644
--- a/include/asm-microblaze/platform.h
+++ b/include/fdt_support.h
@@ -1,7 +1,6 @@
/*
- * (C) Copyright 2004 Atmark Techno, Inc.
- *
- * Yasushi SHOJI <yashi@atmark-techno.com>
+ * (C) Copyright 2007
+ * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -22,8 +21,22 @@
* MA 02111-1307 USA
*/
-#include <config.h>
+#ifndef __FDT_SUPPORT_H
+#define __FDT_SUPPORT_H
+
+#ifdef CONFIG_OF_LIBFDT
+
+#include <fdt.h>
+
+int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force);
-#ifdef CONFIG_SUZAKU
-#include <asm/suzaku.h>
+#ifdef CONFIG_OF_HAS_UBOOT_ENV
+int fdt_env(void *fdt);
#endif
+
+#ifdef CONFIG_OF_HAS_BD_T
+int fdt_bd_t(void *fdt);
+#endif
+
+#endif /* ifdef CONFIG_OF_LIBFDT */
+#endif /* ifndef __FDT_SUPPORT_H */
diff --git a/include/libfdt.h b/include/libfdt.h
new file mode 100644
index 0000000..f8bac73
--- /dev/null
+++ b/include/libfdt.h
@@ -0,0 +1,146 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public License
+ * as published by the Free Software Foundation; either version 2.1 of
+ * the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _LIBFDT_H
+#define _LIBFDT_H
+
+#include <fdt.h>
+#include <libfdt_env.h>
+
+#define FDT_FIRST_SUPPORTED_VERSION 0x10
+#define FDT_LAST_SUPPORTED_VERSION 0x11
+
+/* Error codes: informative error codes */
+#define FDT_ERR_NOTFOUND 1
+#define FDT_ERR_EXISTS 2
+#define FDT_ERR_NOSPACE 3
+
+/* Error codes: codes for bad parameters */
+#define FDT_ERR_BADOFFSET 4
+#define FDT_ERR_BADPATH 5
+#define FDT_ERR_BADSTATE 6
+
+/* Error codes: codes for bad device tree blobs */
+#define FDT_ERR_TRUNCATED 7
+#define FDT_ERR_BADMAGIC 8
+#define FDT_ERR_BADVERSION 9
+#define FDT_ERR_BADSTRUCTURE 10
+#define FDT_ERR_BADLAYOUT 11
+
+#define FDT_ERR_MAX 11
+
+#define fdt_get_header(fdt, field) \
+ (fdt32_to_cpu(((struct fdt_header *)(fdt))->field))
+#define fdt_magic(fdt) (fdt_get_header(fdt, magic))
+#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize))
+#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct))
+#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings))
+#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap))
+#define fdt_version(fdt) (fdt_get_header(fdt, version))
+#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version))
+#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys))
+#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings))
+#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct))
+
+#define fdt_set_header(fdt, field, val) \
+ ((struct fdt_header *)(fdt))->field = cpu_to_fdt32(val)
+
+int fdt_check_header(const void *fdt);
+
+void *fdt_offset_ptr(const void *fdt, int offset, int checklen);
+
+#define fdt_offset_ptr_typed(fdt, offset, var) \
+ ((typeof(var))(fdt_offset_ptr((fdt), (offset), sizeof(*(var)))))
+
+int fdt_move(const void *fdt, void *buf, int bufsize);
+
+/* Read-only functions */
+char *fdt_string(const void *fdt, int stroffset);
+
+int fdt_subnode_offset_namelen(const void *fdt, int parentoffset,
+ const char *name, int namelen);
+int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name);
+
+int fdt_path_offset(const void *fdt, const char *path);
+
+struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset,
+ const char *name, int *lenp);
+void *fdt_getprop(const void *fdt, int nodeoffset,
+ const char *name, int *lenp);
+
+uint32_t fdt_next_tag(const void *fdt, int offset,
+ int *nextoffset, char **namep);
+int fdt_num_reservemap(void *fdt, int *used, int *total);
+int fdt_get_reservemap(void *fdt, int n, struct fdt_reserve_entry *re);
+
+/* Write-in-place functions */
+int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,
+ const void *val, int len);
+
+#define fdt_setprop_inplace_typed(fdt, nodeoffset, name, val) \
+ ({ \
+ typeof(val) x = val; \
+ fdt_setprop_inplace(fdt, nodeoffset, name, &x, sizeof(x)); \
+ })
+
+int fdt_nop_property(void *fdt, int nodeoffset, const char *name);
+int fdt_nop_node(void *fdt, int nodeoffset);
+int fdt_insert_reservemap_entry(void *fdt, int n, uint64_t addr, uint64_t size);
+
+
+/* Sequential-write functions */
+int fdt_create(void *buf, int bufsize);
+int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size);
+int fdt_finish_reservemap(void *fdt);
+int fdt_begin_node(void *fdt, const char *name);
+int fdt_property(void *fdt, const char *name, const void *val, int len);
+#define fdt_property_typed(fdt, name, val) \
+ ({ \
+ typeof(val) x = (val); \
+ fdt_property((fdt), (name), &x, sizeof(x)); \
+ })
+#define fdt_property_string(fdt, name, str) \
+ fdt_property(fdt, name, str, strlen(str)+1)
+int fdt_end_node(void *fdt);
+int fdt_finish(void *fdt);
+int fdt_replace_reservemap_entry(void *fdt, int n, uint64_t addr, uint64_t size);
+
+/* Read-write functions */
+int fdt_open_into(void *fdt, void *buf, int bufsize);
+int fdt_pack(void *fdt);
+
+int fdt_setprop(void *fdt, int nodeoffset, const char *name,
+ const void *val, int len);
+#define fdt_setprop_typed(fdt, nodeoffset, name, val) \
+ ({ \
+ typeof(val) x = (val); \
+ fdt_setprop((fdt), (nodeoffset), (name), &x, sizeof(x)); \
+ })
+#define fdt_setprop_string(fdt, nodeoffset, name, str) \
+ fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
+int fdt_delprop(void *fdt, int nodeoffset, const char *name);
+int fdt_add_subnode_namelen(void *fdt, int parentoffset,
+ const char *name, int namelen);
+int fdt_add_subnode(void *fdt, int parentoffset, const char *name);
+int fdt_del_node(void *fdt, int nodeoffset);
+
+/* Extra functions */
+const char *fdt_strerror(int errval);
+
+#endif /* _LIBFDT_H */
diff --git a/include/libfdt_env.h b/include/libfdt_env.h
new file mode 100644
index 0000000..e746314
--- /dev/null
+++ b/include/libfdt_env.h
@@ -0,0 +1,36 @@
+/*
+ * libfdt - Flat Device Tree manipulation (build/run environment adaptation)
+ * Copyright (C) 2007 Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
+ * Original version written by David Gibson, IBM Corporation.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public License
+ * as published by the Free Software Foundation; either version 2.1 of
+ * the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _LIBFDT_ENV_H
+#define _LIBFDT_ENV_H
+
+#include <stddef.h>
+#include <linux/types.h>
+#include <asm/byteorder.h>
+#include <linux/string.h>
+
+struct fdt_header *fdt; /* Pointer to the working fdt */
+
+#define fdt32_to_cpu(x) __be32_to_cpu(x)
+#define cpu_to_fdt32(x) __cpu_to_be32(x)
+#define fdt64_to_cpu(x) __be64_to_cpu(x)
+#define cpu_to_fdt64(x) __cpu_to_be64(x)
+
+#endif /* _LIBFDT_ENV_H */
diff --git a/include/linux/mii.h b/include/linux/mii.h
new file mode 100644
index 0000000..7c63095
--- /dev/null
+++ b/include/linux/mii.h
@@ -0,0 +1,158 @@
+/*
+ * linux/mii.h: definitions for MII-compatible transceivers
+ * Originally drivers/net/sunhme.h.
+ *
+ * Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com)
+ */
+
+#ifndef __LINUX_MII_H__
+#define __LINUX_MII_H__
+
+/* Generic MII registers. */
+
+#define MII_BMCR 0x00 /* Basic mode control register */
+#define MII_BMSR 0x01 /* Basic mode status register */
+#define MII_PHYSID1 0x02 /* PHYS ID 1 */
+#define MII_PHYSID2 0x03 /* PHYS ID 2 */
+#define MII_ADVERTISE 0x04 /* Advertisement control reg */
+#define MII_LPA 0x05 /* Link partner ability reg */
+#define MII_EXPANSION 0x06 /* Expansion register */
+#define MII_DCOUNTER 0x12 /* Disconnect counter */
+#define MII_FCSCOUNTER 0x13 /* False carrier counter */
+#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
+#define MII_RERRCOUNTER 0x15 /* Receive error counter */
+#define MII_SREVISION 0x16 /* Silicon revision */
+#define MII_RESV1 0x17 /* Reserved... */
+#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
+#define MII_PHYADDR 0x19 /* PHY address */
+#define MII_RESV2 0x1a /* Reserved... */
+#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
+#define MII_NCONFIG 0x1c /* Network interface config */
+
+/* Basic mode control register. */
+#define BMCR_RESV 0x003f /* Unused... */
+#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
+#define BMCR_CTST 0x0080 /* Collision test */
+#define BMCR_FULLDPLX 0x0100 /* Full duplex */
+#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
+#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
+#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
+#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
+#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
+#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
+#define BMCR_RESET 0x8000 /* Reset the DP83840 */
+
+/* Basic mode status register. */
+#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
+#define BMSR_JCD 0x0002 /* Jabber detected */
+#define BMSR_LSTATUS 0x0004 /* Link status */
+#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
+#define BMSR_RFAULT 0x0010 /* Remote fault detected */
+#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
+#define BMSR_RESV 0x07c0 /* Unused... */
+#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
+#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
+#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
+#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
+#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
+
+/* Advertisement control register. */
+#define ADVERTISE_SLCT 0x001f /* Selector bits */
+#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
+#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
+#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
+#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
+#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
+#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
+#define ADVERTISE_RESV 0x1c00 /* Unused... */
+#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
+#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
+#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
+
+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
+ ADVERTISE_CSMA)
+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
+ ADVERTISE_100HALF | ADVERTISE_100FULL)
+
+/* Link partner ability register. */
+#define LPA_SLCT 0x001f /* Same as advertise selector */
+#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
+#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
+#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
+#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
+#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
+#define LPA_RESV 0x1c00 /* Unused... */
+#define LPA_RFAULT 0x2000 /* Link partner faulted */
+#define LPA_LPACK 0x4000 /* Link partner acked us */
+#define LPA_NPAGE 0x8000 /* Next page bit */
+
+#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
+#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+
+/* Expansion register for auto-negotiation. */
+#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
+#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
+#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
+#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
+#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
+#define EXPANSION_RESV 0xffe0 /* Unused... */
+
+/* N-way test register. */
+#define NWAYTEST_RESV1 0x00ff /* Unused... */
+#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
+#define NWAYTEST_RESV2 0xfe00 /* Unused... */
+
+
+/**
+ * mii_nway_result
+ * @negotiated: value of MII ANAR and'd with ANLPAR
+ *
+ * Given a set of MII abilities, check each bit and returns the
+ * currently supported media, in the priority order defined by
+ * IEEE 802.3u. We use LPA_xxx constants but note this is not the
+ * value of LPA solely, as described above.
+ *
+ * The one exception to IEEE 802.3u is that 100baseT4 is placed
+ * between 100T-full and 100T-half. If your phy does not support
+ * 100T4 this is fine. If your phy places 100T4 elsewhere in the
+ * priority order, you will need to roll your own function.
+ */
+static inline unsigned int mii_nway_result (unsigned int negotiated)
+{
+ unsigned int ret;
+
+ if (negotiated & LPA_100FULL)
+ ret = LPA_100FULL;
+ else if (negotiated & LPA_100BASE4)
+ ret = LPA_100BASE4;
+ else if (negotiated & LPA_100HALF)
+ ret = LPA_100HALF;
+ else if (negotiated & LPA_10FULL)
+ ret = LPA_10FULL;
+ else
+ ret = LPA_10HALF;
+
+ return ret;
+}
+
+/**
+ * mii_duplex
+ * @duplex_lock: Non-zero if duplex is locked at full
+ * @negotiated: value of MII ANAR and'd with ANLPAR
+ *
+ * A small helper function for a common case. Returns one
+ * if the media is operating or locked at full duplex, and
+ * returns zero otherwise.
+ */
+static inline unsigned int mii_duplex (unsigned int duplex_lock,
+ unsigned int negotiated)
+{
+ if (duplex_lock)
+ return 1;
+ if (mii_nway_result(negotiated) & LPA_DUPLEX)
+ return 1;
+ return 0;
+}
+
+
+#endif /* __LINUX_MII_H__ */
diff --git a/include/linux/stat.h b/include/linux/stat.h
index 4d05aa9..43fd53f 100644
--- a/include/linux/stat.h
+++ b/include/linux/stat.h
@@ -7,7 +7,7 @@
extern "C" {
#endif
-#define S_IFMT 00170000 /* type of file */
+#define S_IFMT 00170000 /* type of file */
#define S_IFSOCK 0140000 /* named socket */
#define S_IFLNK 0120000 /* symbolic link */
#define S_IFREG 0100000 /* regular */
@@ -49,20 +49,20 @@ struct stat {
ino_t st_ino; /* file id */
mode_t st_mode; /* ownership/protection */
nlink_t st_nlink; /* number of links */
- uid_t st_uid; /* user id */
- gid_t st_gid; /* group id */
+ uid_t st_uid; /* user id */
+ gid_t st_gid; /* group id */
dev_t st_rdev;
off_t st_size; /* file size in # of bytes */
- unsigned long st_blksize; /* block size */
- unsigned long st_blocks; /* file size in # of blocks */
- unsigned long st_atime; /* time file was last accessed */
- unsigned long __unused1;
- unsigned long st_mtime; /* time file was last modified */
- unsigned long __unused2;
- unsigned long st_ctime; /* time file status was last changed */
- unsigned long __unused3;
- unsigned long __unused4;
- unsigned long __unused5;
+ unsigned long st_blksize; /* block size */
+ unsigned long st_blocks; /* file size in # of blocks */
+ unsigned long st_atime; /* time file was last accessed */
+ unsigned long __unused1;
+ unsigned long st_mtime; /* time file was last modified */
+ unsigned long __unused2;
+ unsigned long st_ctime; /* time file status was last changed */
+ unsigned long __unused3;
+ unsigned long __unused4;
+ unsigned long __unused5;
};
#endif /* __PPC__ */
@@ -97,34 +97,59 @@ struct stat {
#if defined (__MIPS__)
struct stat {
- dev_t st_dev;
- long st_pad1[3];
- ino_t st_ino;
- mode_t st_mode;
- nlink_t st_nlink;
- uid_t st_uid;
- gid_t st_gid;
- dev_t st_rdev;
- long st_pad2[2];
- off_t st_size;
- long st_pad3;
+ dev_t st_dev;
+ long st_pad1[3];
+ ino_t st_ino;
+ mode_t st_mode;
+ nlink_t st_nlink;
+ uid_t st_uid;
+ gid_t st_gid;
+ dev_t st_rdev;
+ long st_pad2[2];
+ off_t st_size;
+ long st_pad3;
/*
* Actually this should be timestruc_t st_atime, st_mtime and st_ctime
* but we don't have it under Linux.
*/
- time_t st_atime;
- long reserved0;
- time_t st_mtime;
- long reserved1;
- time_t st_ctime;
- long reserved2;
- long st_blksize;
- long st_blocks;
- long st_pad4[14];
+ time_t st_atime;
+ long reserved0;
+ time_t st_mtime;
+ long reserved1;
+ time_t st_ctime;
+ long reserved2;
+ long st_blksize;
+ long st_blocks;
+ long st_pad4[14];
};
#endif /* __MIPS__ */
+#if defined(__AVR32__)
+
+struct stat {
+ unsigned long st_dev;
+ unsigned long st_ino;
+ unsigned short st_mode;
+ unsigned short st_nlink;
+ unsigned short st_uid;
+ unsigned short st_gid;
+ unsigned long st_rdev;
+ unsigned long st_size;
+ unsigned long st_blksize;
+ unsigned long st_blocks;
+ unsigned long st_atime;
+ unsigned long st_atime_nsec;
+ unsigned long st_mtime;
+ unsigned long st_mtime_nsec;
+ unsigned long st_ctime;
+ unsigned long st_ctime_nsec;
+ unsigned long __unused4;
+ unsigned long __unused5;
+};
+
+#endif /* __AVR32__ */
+
#ifdef __cplusplus
}
#endif
diff --git a/include/ppc405.h b/include/ppc405.h
index 08f10d2..a2503a9 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -570,6 +570,8 @@
#define SDR_ICTX0_STAT 0x40000000
#define SDR_ICTX1_STAT 0x20000000
+#define SDR_PINSTP 0x40
+
/******************************************************************************
* Control
******************************************************************************/
diff --git a/include/ppc440.h b/include/ppc440.h
index 9b15c2c..bc1d7aa 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -148,7 +148,7 @@
#define sdrcfgd (SDR_DCR_BASE+0x1)
#define sdr_sdstp0 0x0020 /* */
#define sdr_sdstp1 0x0021 /* */
-#define sdr_pinstp 0x0040
+#define SDR_PINSTP 0x0040
#define sdr_sdcs 0x0060
#define sdr_ecid0 0x0080
#define sdr_ecid1 0x0081
@@ -3290,29 +3290,6 @@
#define GPIO1_ISR3H (GPIO1_BASE+0x44)
#endif
-#define GPIO_GROUP_MAX 2
-#define GPIO_MAX 32
-#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
-#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
-#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
-#define GPIO_MASK 0xC0000000 /* GPIO_MASK */
-#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
- /* For the other GPIO number, you must shift */
-
-#define GPIO_VAL(gpio) (0x80000000 >> (gpio))
-
-#ifndef __ASSEMBLY__
-
-typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
-typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
-
-typedef struct { unsigned long add; /* gpio core base address */
- gpio_driver_t in_out; /* Driver Setting */
- gpio_select_t alt_nb; /* Selected Alternate */
-} gpio_param_s;
-
-#endif /* __ASSEMBLY__ */
-
/*
* Macros for accessing the indirect EBC registers
*/
diff --git a/include/serial.h b/include/serial.h
index 4880059..f7412fd 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -23,7 +23,7 @@ extern struct serial_device serial_scc_device;
extern struct serial_device * default_serial_console (void);
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
- || defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
+ || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
#if defined(CFG_NS16550_SERIAL)
diff --git a/include/tsi108.h b/include/tsi108.h
new file mode 100644
index 0000000..ba62e7a
--- /dev/null
+++ b/include/tsi108.h
@@ -0,0 +1,221 @@
+/*****************************************************************************
+ * (C) Copyright 2003; Tundra Semiconductor Corp.
+ * (C) Copyright 2006; Freescale Semiconductor Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *****************************************************************************/
+
+/*
+ * FILENAME: tsi108.h
+ *
+ * Originator: Alex Bounine
+ *
+ * DESCRIPTION:
+ * Common definitions for the Tundra Tsi108 bridge chip
+ *
+ */
+
+#ifndef _TSI108_H_
+#define _TSI108_H_
+
+#define TSI108_HLP_REG_OFFSET (0x0000)
+#define TSI108_PCI_REG_OFFSET (0x1000)
+#define TSI108_CLK_REG_OFFSET (0x2000)
+#define TSI108_PB_REG_OFFSET (0x3000)
+#define TSI108_SD_REG_OFFSET (0x4000)
+#define TSI108_MPIC_REG_OFFSET (0x7400)
+
+#define PB_ID (0x000)
+#define PB_RSR (0x004)
+#define PB_BUS_MS_SELECT (0x008)
+#define PB_ISR (0x00C)
+#define PB_ARB_CTRL (0x018)
+#define PB_PVT_CTRL2 (0x034)
+#define PB_SCR (0x400)
+#define PB_ERRCS (0x404)
+#define PB_AERR (0x408)
+#define PB_REG_BAR (0x410)
+#define PB_OCN_BAR1 (0x414)
+#define PB_OCN_BAR2 (0x418)
+#define PB_SDRAM_BAR1 (0x41C)
+#define PB_SDRAM_BAR2 (0x420)
+#define PB_MCR (0xC00)
+#define PB_MCMD (0xC04)
+
+#define HLP_B0_ADDR (0x000)
+#define HLP_B1_ADDR (0x010)
+#define HLP_B2_ADDR (0x020)
+#define HLP_B3_ADDR (0x030)
+
+#define HLP_B0_MASK (0x004)
+#define HLP_B1_MASK (0x014)
+#define HLP_B2_MASK (0x024)
+#define HLP_B3_MASK (0x034)
+
+#define HLP_B0_CTRL0 (0x008)
+#define HLP_B1_CTRL0 (0x018)
+#define HLP_B2_CTRL0 (0x028)
+#define HLP_B3_CTRL0 (0x038)
+
+#define HLP_B0_CTRL1 (0x00C)
+#define HLP_B1_CTRL1 (0x01C)
+#define HLP_B2_CTRL1 (0x02C)
+#define HLP_B3_CTRL1 (0x03C)
+
+#define PCI_CSR (0x004)
+#define PCI_P2O_BAR0 (0x010)
+#define PCI_P2O_BAR0_UPPER (0x014)
+#define PCI_P2O_BAR2 (0x018)
+#define PCI_P2O_BAR2_UPPER (0x01C)
+#define PCI_P2O_BAR3 (0x020)
+#define PCI_P2O_BAR3_UPPER (0x024)
+
+#define PCI_MISC_CSR (0x040)
+#define PCI_P2O_PAGE_SIZES (0x04C)
+
+#define PCI_PCIX_STAT (0x0F4)
+
+#define PCI_IRP_STAT (0x184)
+
+#define PCI_PFAB_BAR0 (0x204)
+#define PCI_PFAB_BAR0_UPPER (0x208)
+#define PCI_PFAB_IO (0x20C)
+#define PCI_PFAB_IO_UPPER (0x210)
+
+#define PCI_PFAB_MEM32 (0x214)
+#define PCI_PFAB_MEM32_REMAP (0x218)
+#define PCI_PFAB_MEM32_MASK (0x21C)
+
+#define CG_PLL0_CTRL0 (0x210)
+#define CG_PLL0_CTRL1 (0x214)
+#define CG_PLL1_CTRL0 (0x220)
+#define CG_PLL1_CTRL1 (0x224)
+#define CG_PWRUP_STATUS (0x234)
+
+#define MPIC_CSR(n) (0x30C + (n * 0x40))
+
+#define SD_CTRL (0x000)
+#define SD_STATUS (0x004)
+#define SD_TIMING (0x008)
+#define SD_REFRESH (0x00C)
+#define SD_INT_STATUS (0x010)
+#define SD_INT_ENABLE (0x014)
+#define SD_INT_SET (0x018)
+#define SD_D0_CTRL (0x020)
+#define SD_D1_CTRL (0x024)
+#define SD_D0_BAR (0x028)
+#define SD_D1_BAR (0x02C)
+#define SD_ECC_CTRL (0x040)
+#define SD_DLL_STATUS (0x250)
+
+#define TS_SD_CTRL_ENABLE (1 << 31)
+
+#define PB_ERRCS_ES (1 << 1)
+#define PB_ISR_PBS_RD_ERR (1 << 8)
+#define PCI_IRP_STAT_P_CSR (1 << 23)
+
+/*
+ * I2C : Register address offset definitions
+ */
+#define I2C_CNTRL1 (0x00000000)
+#define I2C_CNTRL2 (0x00000004)
+#define I2C_RD_DATA (0x00000008)
+#define I2C_TX_DATA (0x0000000c)
+
+/*
+ * I2C : Register Bit Masks and Reset Values
+ * definitions for every register
+ */
+
+/* I2C_CNTRL1 : Reset Value */
+#define I2C_CNTRL1_RESET_VALUE (0x0000000a)
+
+/* I2C_CNTRL1 : Register Bits Masks Definitions */
+#define I2C_CNTRL1_DEVCODE (0x0000000f)
+#define I2C_CNTRL1_PAGE (0x00000700)
+#define I2C_CNTRL1_BYTADDR (0x00ff0000)
+#define I2C_CNTRL1_I2CWRITE (0x01000000)
+
+/* I2C_CNTRL1 : Read/Write Bit Mask Definition */
+#define I2C_CNTRL1_RWMASK (0x01ff070f)
+
+/* I2C_CNTRL1 : Unused/Reserved bits Definition */
+#define I2C_CNTRL1_RESERVED (0xfe00f8f0)
+
+/* I2C_CNTRL2 : Reset Value */
+#define I2C_CNTRL2_RESET_VALUE (0x00000000)
+
+/* I2C_CNTRL2 : Register Bits Masks Definitions */
+#define I2C_CNTRL2_SIZE (0x00000003)
+#define I2C_CNTRL2_LANE (0x0000000c)
+#define I2C_CNTRL2_MULTIBYTE (0x00000010)
+#define I2C_CNTRL2_START (0x00000100)
+#define I2C_CNTRL2_WR_STATUS (0x00010000)
+#define I2C_CNTRL2_RD_STATUS (0x00020000)
+#define I2C_CNTRL2_I2C_TO_ERR (0x04000000)
+#define I2C_CNTRL2_I2C_CFGERR (0x08000000)
+#define I2C_CNTRL2_I2C_CMPLT (0x10000000)
+
+/* I2C_CNTRL2 : Read/Write Bit Mask Definition */
+#define I2C_CNTRL2_RWMASK (0x0000011f)
+
+/* I2C_CNTRL2 : Unused/Reserved bits Definition */
+#define I2C_CNTRL2_RESERVED (0xe3fcfee0)
+
+/* I2C_RD_DATA : Reset Value */
+#define I2C_RD_DATA_RESET_VALUE (0x00000000)
+
+/* I2C_RD_DATA : Register Bits Masks Definitions */
+#define I2C_RD_DATA_RBYTE0 (0x000000ff)
+#define I2C_RD_DATA_RBYTE1 (0x0000ff00)
+#define I2C_RD_DATA_RBYTE2 (0x00ff0000)
+#define I2C_RD_DATA_RBYTE3 (0xff000000)
+
+/* I2C_RD_DATA : Read/Write Bit Mask Definition */
+#define I2C_RD_DATA_RWMASK (0x00000000)
+
+/* I2C_RD_DATA : Unused/Reserved bits Definition */
+#define I2C_RD_DATA_RESERVED (0x00000000)
+
+/* I2C_TX_DATA : Reset Value */
+#define I2C_TX_DATA_RESET_VALUE (0x00000000)
+
+/* I2C_TX_DATA : Register Bits Masks Definitions */
+#define I2C_TX_DATA_TBYTE0 (0x000000ff)
+#define I2C_TX_DATA_TBYTE1 (0x0000ff00)
+#define I2C_TX_DATA_TBYTE2 (0x00ff0000)
+#define I2C_TX_DATA_TBYTE3 (0xff000000)
+
+/* I2C_TX_DATA : Read/Write Bit Mask Definition */
+#define I2C_TX_DATA_RWMASK (0xffffffff)
+
+/* I2C_TX_DATA : Unused/Reserved bits Definition */
+#define I2C_TX_DATA_RESERVED (0x00000000)
+
+#define TSI108_I2C_OFFSET 0x7000 /* offset for general use I2C channel */
+#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* offset for SPD I2C channel */
+
+#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */
+
+/* I2C status codes */
+
+#define TSI108_I2C_SUCCESS 0
+#define TSI108_I2C_PARAM_ERR 1
+#define TSI108_I2C_TIMEOUT_ERR 2
+#define TSI108_I2C_IF_BUSY 3
+#define TSI108_I2C_IF_ERROR 4
+
+#endif /* _TSI108_H_ */