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authorTom Rini <trini@konsulko.com>2016-06-28 15:59:05 -0400
committerTom Rini <trini@konsulko.com>2016-06-28 15:59:05 -0400
commit44faff24f58859bdc1acf28ac739020b5091678a (patch)
tree54833aa6404deed2a2f29ba387fa795cd78da118 /include
parent6f0aea39aeb093a404a7dc21a0f79fa75ca851db (diff)
parentdee01e426b39eac974364c0658fca431894987c3 (diff)
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Merge git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'include')
-rw-r--r--include/configs/ls1043aqds.h9
-rw-r--r--include/fsl_esdhc.h7
2 files changed, 10 insertions, 6 deletions
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index a19eaee..ee8cb23 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -10,11 +10,7 @@
#include "ls1043a_common.h"
#define CONFIG_DISPLAY_CPUINFO
-#ifdef CONFIG_QSPI_BOOT
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-#else
#define CONFIG_DISPLAY_BOARDINFO
-#endif
#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_TEXT_BASE 0x82000000
@@ -29,8 +25,8 @@ unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#define CONFIG_SKIP_LOWLEVEL_INIT
@@ -225,6 +221,7 @@ unsigned long get_board_ddr_clk(void);
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
#define CONFIG_SYS_NO_FLASH
#endif
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index fa760a5..c6f4666 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -35,6 +35,12 @@
#define SYSCTL_RSTC 0x02000000
#define SYSCTL_RSTD 0x04000000
+#define VENDORSPEC_CKEN 0x00004000
+#define VENDORSPEC_PEREN 0x00002000
+#define VENDORSPEC_HCKEN 0x00001000
+#define VENDORSPEC_IPGEN 0x00000800
+#define VENDORSPEC_INIT 0x20007809
+
#define IRQSTAT 0x0002e030
#define IRQSTAT_DMAE (0x10000000)
#define IRQSTAT_AC12E (0x01000000)
@@ -171,6 +177,7 @@ struct fsl_esdhc_cfg {
phys_addr_t esdhc_base;
u32 sdhc_clk;
u8 max_bus_width;
+ u8 wp_enable;
struct mmc_config cfg;
};