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authorWolfgang Denk <wd@pollux.denx.de>2007-03-08 22:42:44 +0100
committerWolfgang Denk <wd@denx.de>2007-03-08 22:42:44 +0100
commit37896293bc991bddb75ccac887b54e9a61f36320 (patch)
tree0c51c9b1254d3805323299f433e3ea7b1d0e281c /include
parent769104c9356594deb2092e204a39c05b33202d6c (diff)
parent781e026c8aa6f7e9eb5f0e72cc4d20971219b148 (diff)
downloadu-boot-imx-37896293bc991bddb75ccac887b54e9a61f36320.zip
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Merge with /home/wd/git/u-boot/custodian/u-boot-mpc83xx
Diffstat (limited to 'include')
-rw-r--r--include/asm-ppc/e300.h5
-rw-r--r--include/asm-ppc/global_data.h4
-rw-r--r--include/asm-ppc/immap_83xx.h1958
-rw-r--r--include/asm-ppc/immap_qe.h6
-rw-r--r--include/configs/MPC832XEMDS.h631
-rw-r--r--include/configs/MPC8349EMDS.h56
-rw-r--r--include/configs/MPC8349ITX.h459
-rw-r--r--include/configs/MPC8360EMDS.h43
-rw-r--r--include/configs/TQM834x.h11
-rw-r--r--include/configs/sbc8349.h734
-rw-r--r--include/mpc83xx.h1325
11 files changed, 2858 insertions, 2374 deletions
diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h
index 79dcae4..ff9512f 100644
--- a/include/asm-ppc/e300.h
+++ b/include/asm-ppc/e300.h
@@ -15,6 +15,11 @@
#define PVR_8360_REV10 (PVR_83xx | 0x0020)
#define PVR_8360_REV11 (PVR_83xx | 0x0020)
+#if defined(CONFIG_MPC832X)
+#undef PVR_83xx
+#define PVR_83xx 0x80840000
+#endif
+
/*
* Hardware Implementation-Dependent Register 0 (HID0)
*/
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 8bc61b6..c113b7e 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -52,12 +52,12 @@ typedef struct global_data {
#if defined(CONFIG_MPC83XX)
/* There are other clocks in the MPC83XX */
u32 csb_clk;
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbmph_clk;
u32 usbdr_clk;
-#endif /* CONFIG_MPC8349 */
+#endif /* CONFIG_MPC834X */
u32 core_clk;
u32 i2c1_clk;
u32 i2c2_clk;
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 43cde5e..5e088d6 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -3,20 +3,11 @@
*
* MPC83xx Internal Memory Map
*
- * History :
- * 20060601: Daveliu (daveliu@freescale.com)
- * TanyaJiang (tanya.jiang@freescale.com)
- * Unified variable names for mpc83xx
- * 2005 : Mandy Lavi (mandy.lavi@freescale.com)
- * support for mpc8360e
- * 2004 : Eran Liberty (liberty@freescale.com)
- * Initialized for mpc8349
- * based on:
- * MPC8260 Internal Memory Map
- * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
- * MPC85xx Internal Memory Map
- * Copyright(c) 2002,2003 Motorola Inc.
- * Xianghua Xiao (x.xiao@motorola.com)
+ * Contributors:
+ * Dave Liu <daveliu@freescale.com>
+ * Tanya Jiang <tanya.jiang@freescale.com>
+ * Mandy Lavi <mandy.lavi@freescale.com>
+ * Eran Liberty <liberty@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -25,7 +16,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -37,36 +28,24 @@
#ifndef __IMMAP_83xx__
#define __IMMAP_83xx__
-#include <config.h>
#include <asm/types.h>
#include <asm/fsl_i2c.h>
/*
- * Local Access Window.
+ * Local Access Window
*/
typedef struct law83xx {
u32 bar; /* LBIU local access window base address register */
-/* Identifies the 20 most-significant address bits of the base of local
- * access window n. The specified base address should be aligned to the
- * window size, as defined by LBLAWARn[SIZE].
- */
-#define LAWBAR_BAR 0xFFFFF000
-#define LAWBAR_RES ~(LAWBAR_BAR)
u32 ar; /* LBIU local access window attribute register */
} law83xx_t;
/*
- * System configuration registers.
+ * System configuration registers
*/
typedef struct sysconf83xx {
u32 immrbar; /* Internal memory map base address register */
u8 res0[0x04];
u32 altcbar; /* Alternate configuration base address register */
-/* Identifies the12 most significant address bits of an alternate base
- * address used for boot sequencer configuration accesses.
- */
-#define ALTCBAR_BASE_ADDR 0xFFF00000
-#define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */
u8 res1[0x14];
law83xx_t lblaw[4]; /* LBIU local access window */
u8 res2[0x20];
@@ -77,116 +56,14 @@ typedef struct sysconf83xx {
u32 sgprl; /* System General Purpose Register Low */
u32 sgprh; /* System General Purpose Register High */
u32 spridr; /* System Part and Revision ID Register */
-#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification. */
-#define SPRIDR_REVID 0x0000FFFF /* Revision Identification. */
u8 res5[0x04];
u32 spcr; /* System Priority Configuration Register */
-#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable. */
-#define SPCR_PCIHPE_SHIFT (31-3)
-#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority. */
-#define SPCR_PCIPR_SHIFT (31-7)
-#define SPCR_OPT 0x00800000 /* Optimize */
-#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable. */
-#define SPCR_TBEN_SHIFT (31-9)
-#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority. */
-#define SPCR_COREPR_SHIFT (31-11)
-#if defined (CONFIG_MPC8349)
-#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority. */
-#define SPCR_TSEC1DP_SHIFT (31-19)
-#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */
-#define SPCR_TSEC1BDP_SHIFT (31-21)
-#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority. */
-#define SPCR_TSEC1EP_SHIFT (31-23)
-#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority. */
-#define SPCR_TSEC2DP_SHIFT (31-27)
-#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */
-#define SPCR_TSEC2BDP_SHIFT (31-29)
-#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority. */
-#define SPCR_TSEC2EP_SHIFT (31-31)
-#define SPCR_RES ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \
- | SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \
- | SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP)
-#elif defined (CONFIG_MPC8360)
-#define SPCR_RES ~(SPCR_PCIHPE|SPCR_PCIPR|SPCR_OPT|SPCR_TBEN|SPCR_COREPR)
-#endif
- u32 sicrl; /* System General Purpose Register Low */
-#if defined (CONFIG_MPC8349)
-#define SICRL_LDP_A 0x80000000
-#define SICRL_USB1 0x40000000
-#define SICRL_USB0 0x20000000
-#define SICRL_UART 0x0C000000
-#define SICRL_GPIO1_A 0x02000000
-#define SICRL_GPIO1_B 0x01000000
-#define SICRL_GPIO1_C 0x00800000
-#define SICRL_GPIO1_D 0x00400000
-#define SICRL_GPIO1_E 0x00200000
-#define SICRL_GPIO1_F 0x00180000
-#define SICRL_GPIO1_G 0x00040000
-#define SICRL_GPIO1_H 0x00020000
-#define SICRL_GPIO1_I 0x00010000
-#define SICRL_GPIO1_J 0x00008000
-#define SICRL_GPIO1_K 0x00004000
-#define SICRL_GPIO1_L 0x00003000
-#define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \
- | SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \
- | SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \
- | SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \
- | SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L )
-#elif defined (CONFIG_MPC8360)
-#define SICRL_LDP_A 0xC0000000
-#define SICRL_LCLK_1 0x10000000
-#define SICRL_LCLK_2 0x08000000
-#define SICRL_SRCID_A 0x03000000
-#define SICRL_IRQ_CKSTP_A 0x00C00000
-#define SICRL_RES ~(SICRL_LDP_A | SICRL_LCLK_1 | SICRL_LCLK_2 | \
- SICRL_SRCID_A | SICRL_IRQ_CKSTP_A)
-#endif
- u32 sicrh; /* System General Purpose Register High */
-#define SICRH_DDR 0x80000000
-#if defined (CONFIG_MPC8349)
-#define SICRH_TSEC1_A 0x10000000
-#define SICRH_TSEC1_B 0x08000000
-#define SICRH_TSEC1_C 0x04000000
-#define SICRH_TSEC1_D 0x02000000
-#define SICRH_TSEC1_E 0x01000000
-#define SICRH_TSEC1_F 0x00800000
-#define SICRH_TSEC2_A 0x00400000
-#define SICRH_TSEC2_B 0x00200000
-#define SICRH_TSEC2_C 0x00100000
-#define SICRH_TSEC2_D 0x00080000
-#define SICRH_TSEC2_E 0x00040000
-#define SICRH_TSEC2_F 0x00020000
-#define SICRH_TSEC2_G 0x00010000
-#define SICRH_TSEC2_H 0x00008000
-#define SICRH_GPIO2_A 0x00004000
-#define SICRH_GPIO2_B 0x00002000
-#define SICRH_GPIO2_C 0x00001000
-#define SICRH_GPIO2_D 0x00000800
-#define SICRH_GPIO2_E 0x00000400
-#define SICRH_GPIO2_F 0x00000200
-#define SICRH_GPIO2_G 0x00000180
-#define SICRH_GPIO2_H 0x00000060
-#define SICRH_TSOBI1 0x00000002
-#define SICRH_TSOBI2 0x00000001
-#define SICRH_RES ~( SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \
- | SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \
- | SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \
- | SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \
- | SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \
- | SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \
- | SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \
- | SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \
- | SICRH_TSOBI2)
-#elif defined (CONFIG_MPC8360)
-#define SICRH_SECONDARY_DDR 0x40000000
-#define SICRH_SDDROE 0x02000000 /* SDDRIOE bit from reset configuration word high. */
-#define SICRH_UC1EOBI 0x00000004 /* UCC1 Ethernet Output Buffer Impedance. */
-#define SICRH_UC2E1OBI 0x00000002 /* UCC2 Ethernet pin option 1 Output Buffer Impedance. */
-#define SICRH_UC2E2OBI 0x00000001 /* UCC2 Ethernet pin option 2 Output Buffer Impedance. */
-#define SICRH_RES ~(SICRH_DDR | SICRH_SECONDARY_DDR | SICRH_SDDROE | \
- SICRH_UC2E1OBI | SICRH_UC2E2OBI | SICRH_UC2E2OBI)
-#endif
- u8 res6[0xE4];
+ u32 sicrl; /* System I/O Configuration Register Low */
+ u32 sicrh; /* System I/O Configuration Register High */
+ u8 res6[0x0C];
+ u32 ddrcdr; /* DDR Control Driver Register */
+ u32 ddrdsr; /* DDR Debug Status Register */
+ u8 res7[0xD0];
} sysconf83xx_t;
/*
@@ -196,11 +73,8 @@ typedef struct wdt83xx {
u8 res0[4];
u32 swcrr; /* System watchdog control register */
u32 swcnr; /* System watchdog count register */
-#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
-#define SWCNR_RES ~(SWCNR_SWCN)
u8 res1[2];
u16 swsrr; /* System watchdog service register */
-#define SWSRR_WS 0x0000FFFF /* Software Watchdog Service Field. */
u8 res2[0xF0];
} wdt83xx_t;
@@ -209,91 +83,46 @@ typedef struct wdt83xx {
*/
typedef struct rtclk83xx {
u32 cnr; /* control register */
-#define CNR_CLEN 0x00000080 /* Clock Enable Control Bit */
-#define CNR_CLIN 0x00000040 /* Input Clock Control Bit */
-#define CNR_AIM 0x00000002 /* Alarm Interrupt Mask Bit */
-#define CNR_SIM 0x00000001 /* Second Interrupt Mask Bit */
-#define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM)
u32 ldr; /* load register */
-#define LDR_CLDV 0xFFFFFFFF /* Contains the 32-bit value to be
- * loaded in a 32-bit RTC counter.*/
u32 psr; /* prescale register */
-#define PSR_PRSC 0xFFFFFFFF /* RTC Prescaler bits. */
- u32 ctr; /* Counter value field register */
-#define CRT_CNTV 0xFFFFFFFF /* RTC Counter value field. */
+ u32 ctr; /* counter value field register */
u32 evr; /* event register */
-#define RTEVR_SIF 0x00000001 /* Second Interrupt Flag Bit */
-#define RTEVR_AIF 0x00000002 /* Alarm Interrupt Flag Bit */
-#define RTEVR_RES ~(RTEVR_SIF | RTEVR_AIF)
-#define PTEVR_PIF 0x00000001 /* Periodic interrupt flag bit. */
-#define PTEVR_RES ~(PTEVR_PIF)
u32 alr; /* alarm register */
u8 res0[0xE8];
} rtclk83xx_t;
/*
- * Global timper module
+ * Global timer module
*/
-
typedef struct gtm83xx {
- u8 cfr1; /* Timer1/2 Configuration */
-#define CFR1_PCAS 0x80 /* Pair Cascade mode */
-#define CFR1_BCM 0x40 /* Backward compatible mode */
-#define CFR1_STP2 0x20 /* Stop timer */
-#define CFR1_RST2 0x10 /* Reset timer */
-#define CFR1_GM2 0x08 /* Gate mode for pin 2 */
-#define CFR1_GM1 0x04 /* Gate mode for pin 1 */
-#define CFR1_STP1 0x02 /* Stop timer */
-#define CFR1_RST1 0x01 /* Reset timer */
-#define CFR1_RES ~(CFR1_PCAS | CFR1_STP2 | CFR1_RST2 | CFR1_GM2 |\
- CFR1_GM1 | CFR1_STP1 | CFR1_RST1)
+ u8 cfr1; /* Timer1/2 Configuration */
u8 res0[3];
- u8 cfr2; /* Timer3/4 Configuration */
-#define CFR2_PCAS 0x80 /* Pair Cascade mode */
-#define CFR2_SCAS 0x40 /* Super Cascade mode */
-#define CFR2_STP4 0x20 /* Stop timer */
-#define CFR2_RST4 0x10 /* Reset timer */
-#define CFR2_GM4 0x08 /* Gate mode for pin 4 */
-#define CFR2_GM3 0x04 /* Gate mode for pin 3 */
-#define CFR2_STP3 0x02 /* Stop timer */
-#define CFR2_RST3 0x01 /* Reset timer */
+ u8 cfr2; /* Timer3/4 Configuration */
u8 res1[10];
- u16 mdr1; /* Timer1 Mode Register */
-#define MDR_SPS 0xff00 /* Secondary Prescaler value */
-#define MDR_CE 0x00c0 /* Capture edge and enable interrupt */
-#define MDR_OM 0x0020 /* Output mode */
-#define MDR_ORI 0x0010 /* Output reference interrupt enable */
-#define MDR_FRR 0x0008 /* Free run/restart */
-#define MDR_ICLK 0x0006 /* Input clock source for the timer */
-#define MDR_GE 0x0001 /* Gate enable */
- u16 mdr2; /* Timer2 Mode Register */
- u16 rfr1; /* Timer1 Reference Register */
- u16 rfr2; /* Timer2 Reference Register */
- u16 cpr1; /* Timer1 Capture Register */
- u16 cpr2; /* Timer2 Capture Register */
- u16 cnr1; /* Timer1 Counter Register */
- u16 cnr2; /* Timer2 Counter Register */
- u16 mdr3; /* Timer3 Mode Register */
- u16 mdr4; /* Timer4 Mode Register */
- u16 rfr3; /* Timer3 Reference Register */
- u16 rfr4; /* Timer4 Reference Register */
- u16 cpr3; /* Timer3 Capture Register */
- u16 cpr4; /* Timer4 Capture Register */
- u16 cnr3; /* Timer3 Counter Register */
- u16 cnr4; /* Timer4 Counter Register */
- u16 evr1; /* Timer1 Event Register */
- u16 evr2; /* Timer2 Event Register */
- u16 evr3; /* Timer3 Event Register */
- u16 evr4; /* Timer4 Event Register */
-#define GTEVR_REF 0x0002 /* Output reference event */
-#define GTEVR_CAP 0x0001 /* Counter Capture event */
-#define GTEVR_RES ~(EVR_CAP|EVR_REF)
- u16 psr1; /* Timer1 Prescaler Register */
- u16 psr2; /* Timer2 Prescaler Register */
- u16 psr3; /* Timer3 Prescaler Register */
- u16 psr4; /* Timer4 Prescaler Register */
-#define GTPSR_PPS 0x00FF /* Primary Prescaler Bits. */
-#define GTPSR_RES ~(GTPSR_PPS)
+ u16 mdr1; /* Timer1 Mode Register */
+ u16 mdr2; /* Timer2 Mode Register */
+ u16 rfr1; /* Timer1 Reference Register */
+ u16 rfr2; /* Timer2 Reference Register */
+ u16 cpr1; /* Timer1 Capture Register */
+ u16 cpr2; /* Timer2 Capture Register */
+ u16 cnr1; /* Timer1 Counter Register */
+ u16 cnr2; /* Timer2 Counter Register */
+ u16 mdr3; /* Timer3 Mode Register */
+ u16 mdr4; /* Timer4 Mode Register */
+ u16 rfr3; /* Timer3 Reference Register */
+ u16 rfr4; /* Timer4 Reference Register */
+ u16 cpr3; /* Timer3 Capture Register */
+ u16 cpr4; /* Timer4 Capture Register */
+ u16 cnr3; /* Timer3 Counter Register */
+ u16 cnr4; /* Timer4 Counter Register */
+ u16 evr1; /* Timer1 Event Register */
+ u16 evr2; /* Timer2 Event Register */
+ u16 evr3; /* Timer3 Event Register */
+ u16 evr4; /* Timer4 Event Register */
+ u16 psr1; /* Timer1 Prescaler Register */
+ u16 psr2; /* Timer2 Prescaler Register */
+ u16 psr3; /* Timer3 Prescaler Register */
+ u16 psr4; /* Timer4 Prescaler Register */
u8 res[0xC0];
} gtm83xx_t;
@@ -301,188 +130,31 @@ typedef struct gtm83xx {
* Integrated Programmable Interrupt Controller
*/
typedef struct ipic83xx {
- u32 sicfr; /* System Global Interrupt Configuration Register (SICFR) */
-#define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */
-#define SICFR_MPSB 0x00400000 /* Mixed interrupts Priority Scheme for group B */
-#define SICFR_MPSA 0x00200000 /* Mixed interrupts Priority Scheme for group A */
-#define SICFR_IPSD 0x00080000 /* Internal interrupts Priority Scheme for group D */
-#define SICFR_IPSA 0x00010000 /* Internal interrupts Priority Scheme for group A */
-#define SICFR_HPIT 0x00000300 /* HPI priority position IPIC output interrupt Type */
-#define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT)
- u32 sivcr; /* System Global Interrupt Vector Register (SIVCR) */
-#define SICVR_IVECX 0xfc000000 /* Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation) */
-#define SICVR_IVEC 0x0000007f /* Interrupt vector */
-#define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC)
- u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */
-#if defined (CONFIG_MPC8349)
-#define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */
-#define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */
-#define SIIH_TSEC1ER 0x20000000 /* TSEC1 Eror interrupt */
-#define SIIH_TSEC2TX 0x10000000 /* TSEC2 Tx interrupt */
-#define SIIH_TSEC2RX 0x08000000 /* TSEC2 Rx interrupt */
-#define SIIH_TSEC2ER 0x04000000 /* TSEC2 Eror interrupt */
-#define SIIH_USB2DR 0x02000000 /* USB2 DR interrupt */
-#define SIIH_USB2MPH 0x01000000 /* USB2 MPH interrupt */
-#endif
-#if defined (CONFIG_MPC8360)
-#define SIIH_H_QE_H 0x80000000 /* QE high interrupt */
-#define SIIH_H_QE_L 0x40000000 /* QE low interrupt */
-#endif
-#define SIIH_UART1 0x00000080 /* UART1 interrupt */
-#define SIIH_UART2 0x00000040 /* UART2 interrupt */
-#define SIIH_SEC 0x00000020 /* SEC interrupt */
-#define SIIH_I2C1 0x00000004 /* I2C1 interrupt */
-#define SIIH_I2C2 0x00000002 /* I2C2 interrupt */
-#if defined (CONFIG_MPC8349)
-#define SIIH_SPI 0x00000001 /* SPI interrupt */
-#define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \
- | SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \
- | SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \
- | SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \
- | SIIH_I2C2 | SIIH_SPI)
-#endif
-#if defined (CONFIG_MPC8360)
-#define SIIH_RES ~(SIIH_H_QE_H | SIIH_H_QE_L | SIIH_H_UART1 | \
- SIIH_H_UART2| SIIH_H_SEC | SIIH_H_I2C1 |SIIH_H_I2C2)
-#endif
- u32 sipnr_l; /* System Internal Interrupt Pending Register - Low (SIPNR_L) */
-#define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */
-#define SIIL_PIT 0x40000000 /* PIT interrupt */
-#define SIIL_PCI1 0x20000000 /* PCI1 interrupt */
-#if defined (CONFIG_MPC8349)
-#define SIIL_PCI2 0x10000000 /* PCI2 interrupt */
-#endif
-#define SIIL_RTCA 0x08000000 /* RTC ALARM interrupt */
-#define SIIL_MU 0x04000000 /* Message Unit interrupt */
-#define SIIL_SBA 0x02000000 /* System Bus Arbiter interrupt */
-#define SIIL_DMA 0x01000000 /* DMA interrupt */
-#define SIIL_GTM4 0x00800000 /* GTM4 interrupt */
-#define SIIL_GTM8 0x00400000 /* GTM8 interrupt */
-#if defined (CONFIG_MPC8349)
-#define SIIL_GPIO1 0x00200000 /* GPIO1 interrupt */
-#define SIIL_GPIO2 0x00100000 /* GPIO2 interrupt */
-#endif
-#if defined (CONFIG_MPC8360)
-#define SIIL_QEP 0x00200000 /* QE ports interrupt */
-#define SIIL_SDDR 0x00100000 /* SDDR interrupt */
-#endif
-#define SIIL_DDR 0x00080000 /* DDR interrupt */
-#define SIIL_LBC 0x00040000 /* LBC interrupt */
-#define SIIL_GTM2 0x00020000 /* GTM2 interrupt */
-#define SIIL_GTM6 0x00010000 /* GTM6 interrupt */
-#define SIIL_PMC 0x00008000 /* PMC interrupt */
-#define SIIL_GTM3 0x00000800 /* GTM3 interrupt */
-#define SIIL_GTM7 0x00000400 /* GTM7 interrupt */
-#define SIIL_GTM1 0x00000020 /* GTM1 interrupt */
-#define SIIL_GTM5 0x00000010 /* GTM5 interrupt */
-#define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */
-#if defined (CONFIG_MPC8349)
-#define SIIL_RES ~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \
- | SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \
- | SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \
- | SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \
- | SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \
- | SIIL_GTM5 |SIIL_DPTC )
-#endif
-#if defined (CONFIG_MPC8360)
-#define SIIL_RES ~(SIIL_RTCS |SIIL_PIT |SIIL_PCI1 |SIIL_RTCALR \
- |SIIL_MU |SIIL_SBA |SIIL_DMA |SIIL_GTM4 |SIIL_GTM8 \
- |SIIL_QEP | SIIL_SDDR| SIIL_DDR |SIIL_LBC |SIIL_GTM2 \
- |SIIL_GTM6 |SIIL_PMC |SIIL_GTM3 |SIIL_GTM7 |SIIL_GTM1 \
- |SIIL_GTM5 )
-#endif
- u32 siprr_a; /* System Internal Interrupt Group A Priority Register (PRR) */
+ u32 sicfr; /* System Global Interrupt Configuration Register */
+ u32 sivcr; /* System Global Interrupt Vector Register */
+ u32 sipnr_h; /* System Internal Interrupt Pending Register - High */
+ u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */
+ u32 siprr_a; /* System Internal Interrupt Group A Priority Register */
u8 res0[8];
- u32 siprr_d; /* System Internal Interrupt Group D Priority Register (PRR) */
- u32 simsr_h; /* System Internal Interrupt Mask Register - High (SIIH) */
- u32 simsr_l; /* System Internal Interrupt Mask Register - Low (SIIL) */
+ u32 siprr_d; /* System Internal Interrupt Group D Priority Register */
+ u32 simsr_h; /* System Internal Interrupt Mask Register - High */
+ u32 simsr_l; /* System Internal Interrupt Mask Register - Low */
u8 res1[4];
- u32 sepnr; /* System External Interrupt Pending Register (SEI) */
- u32 smprr_a; /* System Mixed Interrupt Group A Priority Register (PRR) */
- u32 smprr_b; /* System Mixed Interrupt Group B Priority Register (PRR) */
-#define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */
-#define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */
-#define PRR_2 0x03800000 /* Priority Register, Position 2 programming */
-#define PRR_3 0x00700000 /* Priority Register, Position 3 programming */
-#define PRR_4 0x0000e000 /* Priority Register, Position 4 programming */
-#define PRR_5 0x00001c00 /* Priority Register, Position 5 programming */
-#define PRR_6 0x00000380 /* Priority Register, Position 6 programming */
-#define PRR_7 0x00000070 /* Priority Register, Position 7 programming */
-#define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7)
- u32 semsr; /* System External Interrupt Mask Register (SEI) */
-#define SEI_IRQ0 0x80000000 /* IRQ0 external interrupt */
-#define SEI_IRQ1 0x40000000 /* IRQ1 external interrupt */
-#define SEI_IRQ2 0x20000000 /* IRQ2 external interrupt */
-#define SEI_IRQ3 0x10000000 /* IRQ3 external interrupt */
-#define SEI_IRQ4 0x08000000 /* IRQ4 external interrupt */
-#define SEI_IRQ5 0x04000000 /* IRQ5 external interrupt */
-#define SEI_IRQ6 0x02000000 /* IRQ6 external interrupt */
-#define SEI_IRQ7 0x01000000 /* IRQ7 external interrupt */
-#define SEI_SIRQ0 0x00008000 /* SIRQ0 external interrupt */
-#define SEI_RES ~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \
- | SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \
- | SEI_SIRQ0)
- u32 secnr; /* System External Interrupt Control Register (SECNR) */
-#define SECNR_MIXB0T 0xc0000000 /* MIXB0 priority position IPIC output interrupt type */
-#define SECNR_MIXB1T 0x30000000 /* MIXB1 priority position IPIC output interrupt type */
-#define SECNR_MIXA0T 0x00c00000 /* MIXA0 priority position IPIC output interrupt type */
-#define SECNR_SYSA1T 0x00300000 /* MIXA1 priority position IPIC output interrupt type */
-#define SECNR_EDI0 0x00008000 /* IRQ0 external interrupt edge/level detect */
-#define SECNR_EDI1 0x00004000 /* IRQ1 external interrupt edge/level detect */
-#define SECNR_EDI2 0x00002000 /* IRQ2 external interrupt edge/level detect */
-#define SECNR_EDI3 0x00001000 /* IRQ3 external interrupt edge/level detect */
-#define SECNR_EDI4 0x00000800 /* IRQ4 external interrupt edge/level detect */
-#define SECNR_EDI5 0x00000400 /* IRQ5 external interrupt edge/level detect */
-#define SECNR_EDI6 0x00000200 /* IRQ6 external interrupt edge/level detect */
-#define SECNR_EDI7 0x00000100 /* IRQ7 external interrupt edge/level detect */
-#define SECNR_RES ~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \
- | SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \
- | SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \
- | SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7)
- u32 sersr; /* System Error Status Register (SERR) */
- u32 sermr; /* System Error Mask Register (SERR) */
-#define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */
-#define SERR_WDT 0x40000000 /* WDT MCP request */
-#define SERR_SBA 0x20000000 /* SBA MCP request */
-#if defined (CONFIG_MPC8349)
-#define SERR_DDR 0x10000000 /* DDR MCP request */
-#define SERR_LBC 0x08000000 /* LBC MCP request */
-#define SERR_PCI1 0x04000000 /* PCI1 MCP request */
-#define SERR_PCI2 0x02000000 /* PCI2 MCP request */
-#endif
-#if defined (CONFIG_MPC8360)
-#define SERR_CIEE 0x10000000 /* CIEE MCP request */
-#define SERR_CMEE 0x08000000 /* CMEEMCP request */
-#define SERR_PCI 0x04000000 /* PCI MCP request */
-#endif
-#define SERR_MU 0x01000000 /* MU MCP request */
-#define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */
-#if defined (CONFIG_MPC8349)
-#define SERR_RES ~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \
- |SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \
- |SERR_RNC )
-#elif defined (CONFIG_MPC8360)
-#define SERR_RES ~( SERR_IRQ0|SERR_WDT |SERR_SBA |SERR_CIEE\
- |SERR_CMEE|SERR_PCI|SERR_MU)
-#endif
- u32 sercr; /* System Error Control Register (SERCR) */
-#define SERCR_MCPR 0x00000001 /* MCP Route */
-#define SERCR_RES ~(SERCR_MCPR)
+ u32 sepnr; /* System External Interrupt Pending Register */
+ u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */
+ u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */
+ u32 semsr; /* System External Interrupt Mask Register */
+ u32 secnr; /* System External Interrupt Control Register */
+ u32 sersr; /* System Error Status Register */
+ u32 sermr; /* System Error Mask Register */
+ u32 sercr; /* System Error Control Register */
u8 res2[4];
- u32 sifcr_h; /* System Internal Interrupt Force Register - High (SIIH) */
- u32 sifcr_l; /* System Internal Interrupt Force Register - Low (SIIL) */
- u32 sefcr; /* System External Interrupt Force Register (SEI) */
- u32 serfr; /* System Error Force Register (SERR) */
+ u32 sifcr_h; /* System Internal Interrupt Force Register - High */
+ u32 sifcr_l; /* System Internal Interrupt Force Register - Low */
+ u32 sefcr; /* System External Interrupt Force Register */
+ u32 serfr; /* System Error Force Register */
u32 scvcr; /* System Critical Interrupt Vector Register */
-#define SCVCR_CVECX 0xFC000000 /* Backward (MPC8260) compatible
- critical interrupt vector. */
-#define SCVCR_CVEC 0x0000007F /* Critical interrupt vector */
-#define SCVCR_RES ~(SCVCR_CVECX|SCVCR_CVEC)
u32 smvcr; /* System Management Interrupt Vector Register */
-#define SMVCR_CVECX 0xFC000000 /* Backward (MPC8260) compatible
- critical interrupt vector. */
-#define SMVCR_CVEC 0x0000007F /* Critical interrupt vector */
-#define SMVCR_RES ~(SMVCR_CVECX|SMVCR_CVEC)
u8 res3[0x98];
} ipic83xx_t;
@@ -491,43 +163,14 @@ typedef struct ipic83xx {
*/
typedef struct arbiter83xx {
u32 acr; /* Arbiter Configuration Register */
-#define ACR_COREDIS 0x10000000 /* Core disable. */
-#define ACR_COREDIS_SHIFT (31-7)
-#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */
-#define ACR_PIPE_DEP_SHIFT (31-15)
-#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */
-#define ACR_PCI_RPTCNT_SHIFT (31-19)
-#define ACR_RPTCNT 0x00000700 /* Repeat count. */
-#define ACR_RPTCNT_SHIFT (31-23)
-#define ACR_APARK 0x00000030 /* Address parking. */
-#define ACR_APARK_SHIFT (31-27)
-#define ACR_PARKM 0x0000000F /* Parking master. */
-#define ACR_PARKM_SHIFT (31-31)
-#define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM)
u32 atr; /* Arbiter Timers Register */
-#define ATR_DTO 0x00FF0000 /* Data time out. */
-#define ATR_ATO 0x000000FF /* Address time out. */
-#define ATR_RES ~(ATR_DTO|ATR_ATO)
u8 res[4];
- u32 aer; /* Arbiter Event Register (AE) */
- u32 aidr; /* Arbiter Interrupt Definition Register (AE) */
- u32 amr; /* Arbiter Mask Register (AE) */
+ u32 aer; /* Arbiter Event Register */
+ u32 aidr; /* Arbiter Interrupt Definition Register */
+ u32 amr; /* Arbiter Mask Register */
u32 aeatr; /* Arbiter Event Attributes Register */
-#define AEATR_EVENT 0x07000000 /* Event type. */
-#define AEATR_MSTR_ID 0x001F0000 /* Master Id. */
-#define AEATR_TBST 0x00000800 /* Transfer burst. */
-#define AEATR_TSIZE 0x00000700 /* Transfer Size. */
-#define AEATR_TTYPE 0x0000001F /* Transfer Type. */
-#define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE)
u32 aeadr; /* Arbiter Event Address Register */
- u32 aerr; /* Arbiter Event Response Register (AE) */
-#define AE_ETEA 0x00000020 /* Transfer error. */
-#define AE_RES_ 0x00000010 /* Reserved transfer type. */
-#define AE_ECW 0x00000008 /* External control word transfer type. */
-#define AE_AO 0x00000004 /* Address Only transfer type. */
-#define AE_DTO 0x00000002 /* Data time out. */
-#define AE_ATO 0x00000001 /* Address time out. */
-#define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO)
+ u32 aerr; /* Arbiter Event Response Register */
u8 res1[0xDC];
} arbiter83xx_t;
@@ -535,184 +178,24 @@ typedef struct arbiter83xx {
* Reset Module
*/
typedef struct reset83xx {
- u32 rcwl; /* RCWL Register */
-#define RCWL_LBIUCM 0x80000000 /* LBIUCM */
-#define RCWL_LBIUCM_SHIFT 31
-#define RCWL_DDRCM 0x40000000 /* DDRCM */
-#define RCWL_DDRCM_SHIFT 30
-#if defined (CONFIG_MPC8349)
-#define RCWL_SVCOD 0x30000000 /* SVCOD */
-#endif
-#define RCWL_SPMF 0x0f000000 /* SPMF */
-#define RCWL_SPMF_SHIFT 24
-#define RCWL_COREPLL 0x007F0000 /* COREPLL */
-#define RCWL_COREPLL_SHIFT 16
-#define RCWL_CEVCOD 0x000000C0 /* CEVCOD */
-#define RCWL_CEPDF 0x00000020 /* CEPDF */
-#define RCWL_CEPDF_SHIFT 5
-#define RCWL_CEPMF 0x0000001F /* CEPMF */
-#define RCWL_CEPMF_SHIFT 0
-#if defined (CONFIG_MPC8349)
-#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)
-#elif defined (CONFIG_MPC8360)
-#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SPMF|RCWL_COREPLL|RCWL_CEPDF|RCWL_CEPMF)
-#endif
- u32 rcwh; /* RCHL Register */
-#define RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#define RCWH_PCIHOST_SHIFT 31
-#if defined (CONFIG_MPC8349)
-#define RCWH_PCI64 0x40000000 /* PCI64 */
-#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB */
-#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB */
-#elif defined (CONFIG_MPC8360)
-#define RCWH_PCIARB 0x20000000 /* PCI internal arbiter mode. */
-#define RCWH_PCICKDRV 0x10000000 /* PCI clock output drive. */
-#endif
-#define RCWH_COREDIS 0x08000000 /* COREDIS */
-#define RCWH_BMS 0x04000000 /* BMS */
-#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ */
-#define RCWH_SWEN 0x00800000 /* SWEN */
-#define RCWH_ROMLOC 0x00700000 /* ROMLOC */
-#if defined (CONFIG_MPC8349)
-#define RCWH_TSEC1M 0x0000c000 /* TSEC1M */
-#define RCWH_TSEC2M 0x00003000 /* TSEC2M */
-#define RCWH_TPR 0x00000100 /* TPR */
-#elif defined (CONFIG_MPC8360)
-#define RCWH_SDDRIOE 0x00000010 /* Secondary DDR IO Enable. */
-#endif
-#define RCWH_TLE 0x00000008 /* TLE */
-#define RCWH_LALE 0x00000004 /* LALE */
-#if defined (CONFIG_MPC8349)
-#define RCWH_RES ~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \
- | RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \
- | RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \
- | RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \
- | RCWH_TLE | RCWH_LALE)
-#elif defined (CONFIG_MPC8360)
-#define RCWH_RES ~(RCWH_PCIHOST|RCWH_PCIARB|RCWH_PCICKDRV \
- |RCWH_COREDIS|RCWH_BMS|RCWH_BOOTSEQ|RCWH_SWEN \
- |RCWH_SDDRIOE |RCWH_TLE)
-#endif
+ u32 rcwl; /* Reset Configuration Word Low Register */
+ u32 rcwh; /* Reset Configuration Word High Register */
u8 res0[8];
- u32 rsr; /* Reset status Register */
-#define RSR_RSTSRC 0xE0000000 /* Reset source */
-#define RSR_RSTSRC_SHIFT 29
-#define RSR_BSF 0x00010000 /* Boot seq. fail */
-#define RSR_BSF_SHIFT 16
-#define RSR_SWSR 0x00002000 /* software soft reset */
-#define RSR_SWSR_SHIFT 13
-#define RSR_SWHR 0x00001000 /* software hard reset */
-#define RSR_SWHR_SHIFT 12
-#define RSR_JHRS 0x00000200 /* jtag hreset */
-#define RSR_JHRS_SHIFT 9
-#define RSR_JSRS 0x00000100 /* jtag sreset status */
-#define RSR_JSRS_SHIFT 8
-#define RSR_CSHR 0x00000010 /* checkstop reset status */
-#define RSR_CSHR_SHIFT 4
-#define RSR_SWRS 0x00000008 /* software watchdog reset status */
-#define RSR_SWRS_SHIFT 3
-#define RSR_BMRS 0x00000004 /* bus monitop reset status */
-#define RSR_BMRS_SHIFT 2
-#define RSR_SRS 0x00000002 /* soft reset status */
-#define RSR_SRS_SHIFT 1
-#define RSR_HRS 0x00000001 /* hard reset status */
-#define RSR_HRS_SHIFT 0
-#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS)
- u32 rmr; /* Reset mode Register */
-#define RMR_CSRE 0x00000001 /* checkstop reset enable */
-#define RMR_CSRE_SHIFT 0
-#define RMR_RES ~(RMR_CSRE)
- u32 rpr; /* Reset protection Register */
- u32 rcr; /* Reset Control Register */
-#define RCR_SWHR 0x00000002 /* software hard reset */
-#define RCR_SWSR 0x00000001 /* software soft reset */
-#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
- u32 rcer; /* Reset Control Enable Register */
-#define RCER_CRE 0x00000001 /* software hard reset */
-#define RCER_RES ~(RCER_CRE)
+ u32 rsr; /* Reset Status Register */
+ u32 rmr; /* Reset Mode Register */
+ u32 rpr; /* Reset protection Register */
+ u32 rcr; /* Reset Control Register */
+ u32 rcer; /* Reset Control Enable Register */
u8 res1[0xDC];
} reset83xx_t;
+/*
+ * Clock Module
+ */
typedef struct clk83xx {
- u32 spmr; /* system PLL mode Register */
-#define SPMR_LBIUCM 0x80000000 /* LBIUCM */
-#define SPMR_DDRCM 0x40000000 /* DDRCM */
-#if defined (CONFIG_MPC8349)
-#define SPMR_SVCOD 0x30000000 /* SVCOD */
-#endif
-#define SPMR_SPMF 0x0F000000 /* SPMF */
-#define SPMR_CKID 0x00800000 /* CKID */
-#define SPMR_CKID_SHIFT 23
-#define SPMR_COREPLL 0x007F0000 /* COREPLL */
-#define SPMR_CEVCOD 0x000000C0 /* CEVCOD */
-#define SPMR_CEPDF 0x00000020 /* CEPDF */
-#define SPMR_CEPMF 0x0000001F /* CEPMF */
-#if defined (CONFIG_MPC8349)
-#define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \
- | SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \
- | SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF)
-#elif defined (CONFIG_MPC8360)
-#define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SPMF \
- | SPMR_CKID | SPMR_COREPLL | SPMR_CEVCOD \
- | SPMR_CEPDF | SPMR_CEPMF)
-#endif
- u32 occr; /* output clock control Register */
-#define OCCR_PCICOE0 0x80000000 /* PCICOE0 */
-#define OCCR_PCICOE1 0x40000000 /* PCICOE1 */
-#define OCCR_PCICOE2 0x20000000 /* PCICOE2 */
-#if defined (CONFIG_MPC8349)
-#define OCCR_PCICOE3 0x10000000 /* PCICOE3 */
-#define OCCR_PCICOE4 0x08000000 /* PCICOE4 */
-#define OCCR_PCICOE5 0x04000000 /* PCICOE5 */
-#define OCCR_PCICOE6 0x02000000 /* PCICOE6 */
-#define OCCR_PCICOE7 0x01000000 /* PCICOE7 */
-#endif
-#define OCCR_PCICD0 0x00800000 /* PCICD0 */
-#define OCCR_PCICD1 0x00400000 /* PCICD1 */
-#define OCCR_PCICD2 0x00200000 /* PCICD2 */
-#if defined (CONFIG_MPC8349)
-#define OCCR_PCICD3 0x00100000 /* PCICD3 */
-#define OCCR_PCICD4 0x00080000 /* PCICD4 */
-#define OCCR_PCICD5 0x00040000 /* PCICD5 */
-#define OCCR_PCICD6 0x00020000 /* PCICD6 */
-#define OCCR_PCICD7 0x00010000 /* PCICD7 */
-#define OCCR_PCI1CR 0x00000002 /* PCI1CR */
-#define OCCR_PCI2CR 0x00000001 /* PCI2CR */
-#define OCCR_RES ~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \
- | OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \
- | OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \
- | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICD3 \
- | OCCR_PCICD4 | OCCR_PCICD5 | OCCR_PCICD6 \
- | OCCR_PCICD7 | OCCR_PCI1CR | OCCR_PCI2CR )
-#endif
-#if defined (CONFIG_MPC8360)
-#define OCCR_PCICR 0x00000002 /* PCI clock rate */
-#define OCCR_RES ~(OCCR_PCICOE0|OCCR_PCICOE1|OCCR_PCICOE2 \
- |OCCR_PCICD0|OCCR_PCICD1|OCCR_PCICD2|OCCR_PCICR )
-#endif
- u32 sccr; /* system clock control Register */
-#if defined (CONFIG_MPC8349)
-#define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */
-#define SCCR_TSEC1CM_SHIFT 30
-#define SCCR_TSEC2CM 0x30000000 /* TSEC2CM */
-#define SCCR_TSEC2CM_SHIFT 28
-#endif
-#define SCCR_ENCCM 0x03000000 /* ENCCM */
-#define SCCR_ENCCM_SHIFT 24
-#if defined (CONFIG_MPC8349)
-#define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM */
-#define SCCR_USBMPHCM_SHIFT 22
-#define SCCR_USBDRCM 0x00300000 /* USBDRCM */
-#define SCCR_USBDRCM_SHIFT 20
-#endif
-#define SCCR_PCICM 0x00010000 /* PCICM */
-#if defined (CONFIG_MPC8349)
-#define SCCR_RES ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \
- | SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM)
-#endif
-#if defined (CONFIG_MPC8360)
-#define SCCR_RES ~(SCCR_ENCCM | SCCR_PCICM)
-#endif
+ u32 spmr; /* system PLL mode Register */
+ u32 occr; /* output clock control Register */
+ u32 sccr; /* system clock control Register */
u8 res0[0xF4];
} clk83xx_t;
@@ -720,27 +203,14 @@ typedef struct clk83xx {
* Power Management Control Module
*/
typedef struct pmc83xx {
- u32 pmccr; /* PMC Configuration Register */
-#define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */
-#define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */
-#if defined (CONFIG_MPC8360)
-#define PMCCR_SDLPEN 0x00000004 /* Secondary DDR SDRAM Low Power Enable */
-#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN | PMCCR_SDLPEN)
-#elif defined (CONFIG_MPC8349)
-#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN)
-#endif
- u32 pmcer; /* PMC Event Register */
-#define PMCER_PMCI 0x00000001 /* PMC Interrupt */
-#define PMCER_RES ~(PMCER_PMCI)
- u32 pmcmr; /* PMC Mask Register */
-#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */
-#define PMCMR_RES ~(PMCMR_PMCIE)
+ u32 pmccr; /* PMC Configuration Register */
+ u32 pmcer; /* PMC Event Register */
+ u32 pmcmr; /* PMC Mask Register */
u8 res0[0xF4];
} pmc83xx_t;
-#if defined (CONFIG_MPC8349)
/*
- * general purpose I/O module
+ * General purpose I/O module
*/
typedef struct gpio83xx {
u32 dir; /* direction register */
@@ -751,124 +221,20 @@ typedef struct gpio83xx {
u32 icr; /* external interrupt control register */
u8 res0[0xE8];
} gpio83xx_t;
-#endif
-#if defined (CONFIG_MPC8360)
/*
* QE Ports Interrupts Registers
*/
typedef struct qepi83xx {
u8 res0[0xC];
u32 qepier; /* QE Ports Interrupt Event Register */
-#define QEPIER_PA15 0x80000000
-#define QEPIER_PA16 0x40000000
-#define QEPIER_PA29 0x20000000
-#define QEPIER_PA30 0x10000000
-#define QEPIER_PB3 0x08000000
-#define QEPIER_PB5 0x04000000
-#define QEPIER_PB12 0x02000000
-#define QEPIER_PB13 0x01000000
-#define QEPIER_PB26 0x00800000
-#define QEPIER_PB27 0x00400000
-#define QEPIER_PC27 0x00200000
-#define QEPIER_PC28 0x00100000
-#define QEPIER_PC29 0x00080000
-#define QEPIER_PD12 0x00040000
-#define QEPIER_PD13 0x00020000
-#define QEPIER_PD16 0x00010000
-#define QEPIER_PD17 0x00008000
-#define QEPIER_PD26 0x00004000
-#define QEPIER_PD27 0x00002000
-#define QEPIER_PE12 0x00001000
-#define QEPIER_PE13 0x00000800
-#define QEPIER_PE24 0x00000400
-#define QEPIER_PE25 0x00000200
-#define QEPIER_PE26 0x00000100
-#define QEPIER_PE27 0x00000080
-#define QEPIER_PE31 0x00000040
-#define QEPIER_PF20 0x00000020
-#define QEPIER_PG31 0x00000010
-#define QEPIER_RES ~(QEPIER_PA15|QEPIER_PA16|QEPIER_PA29|QEPIER_PA30|QEPIER_PB3 \
- |QEPIER_PB5|QEPIER_PB12|QEPIER_PB13|QEPIER_PB26|QEPIER_PB27 \
- |QEPIER_PC27|QEPIER_PC28|QEPIER_PC29|QEPIER_PD12|QEPIER_PD13 \
- |QEPIER_PD16|QEPIER_PD17|QEPIER_PD26|QEPIER_PD27|QEPIER_PE12 \
- |QEPIER_PE13|QEPIER_PE24|QEPIER_PE25|QEPIER_PE26|QEPIER_PE27 \
- |QEPIER_PE31|QEPIER_PF20|QEPIER_PG31)
u32 qepimr; /* QE Ports Interrupt Mask Register */
-#define QEPIMR_PA15 0x80000000
-#define QEPIMR_PA16 0x40000000
-#define QEPIMR_PA29 0x20000000
-#define QEPIMR_PA30 0x10000000
-#define QEPIMR_PB3 0x08000000
-#define QEPIMR_PB5 0x04000000
-#define QEPIMR_PB12 0x02000000
-#define QEPIMR_PB13 0x01000000
-#define QEPIMR_PB26 0x00800000
-#define QEPIMR_PB27 0x00400000
-#define QEPIMR_PC27 0x00200000
-#define QEPIMR_PC28 0x00100000
-#define QEPIMR_PC29 0x00080000
-#define QEPIMR_PD12 0x00040000
-#define QEPIMR_PD13 0x00020000
-#define QEPIMR_PD16 0x00010000
-#define QEPIMR_PD17 0x00008000
-#define QEPIMR_PD26 0x00004000
-#define QEPIMR_PD27 0x00002000
-#define QEPIMR_PE12 0x00001000
-#define QEPIMR_PE13 0x00000800
-#define QEPIMR_PE24 0x00000400
-#define QEPIMR_PE25 0x00000200
-#define QEPIMR_PE26 0x00000100
-#define QEPIMR_PE27 0x00000080
-#define QEPIMR_PE31 0x00000040
-#define QEPIMR_PF20 0x00000020
-#define QEPIMR_PG31 0x00000010
-#define QEPIMR_RES ~(QEPIMR_PA15|QEPIMR_PA16|QEPIMR_PA29|QEPIMR_PA30|QEPIMR_PB3 \
- |QEPIMR_PB5|QEPIMR_PB12|QEPIMR_PB13|QEPIMR_PB26|QEPIMR_PB27 \
- |QEPIMR_PC27|QEPIMR_PC28|QEPIMR_PC29|QEPIMR_PD12|QEPIMR_PD13 \
- |QEPIMR_PD16|QEPIMR_PD17|QEPIMR_PD26|QEPIMR_PD27|QEPIMR_PE12 \
- |QEPIMR_PE13|QEPIMR_PE24|QEPIMR_PE25|QEPIMR_PE26|QEPIMR_PE27 \
- |QEPIMR_PE31|QEPIMR_PF20|QEPIMR_PG31)
u32 qepicr; /* QE Ports Interrupt Control Register */
-#define QEPICR_PA15 0x80000000
-#define QEPICR_PA16 0x40000000
-#define QEPICR_PA29 0x20000000
-#define QEPICR_PA30 0x10000000
-#define QEPICR_PB3 0x08000000
-#define QEPICR_PB5 0x04000000
-#define QEPICR_PB12 0x02000000
-#define QEPICR_PB13 0x01000000
-#define QEPICR_PB26 0x00800000
-#define QEPICR_PB27 0x00400000
-#define QEPICR_PC27 0x00200000
-#define QEPICR_PC28 0x00100000
-#define QEPICR_PC29 0x00080000
-#define QEPICR_PD12 0x00040000
-#define QEPICR_PD13 0x00020000
-#define QEPICR_PD16 0x00010000
-#define QEPICR_PD17 0x00008000
-#define QEPICR_PD26 0x00004000
-#define QEPICR_PD27 0x00002000
-#define QEPICR_PE12 0x00001000
-#define QEPICR_PE13 0x00000800
-#define QEPICR_PE24 0x00000400
-#define QEPICR_PE25 0x00000200
-#define QEPICR_PE26 0x00000100
-#define QEPICR_PE27 0x00000080
-#define QEPICR_PE31 0x00000040
-#define QEPICR_PF20 0x00000020
-#define QEPICR_PG31 0x00000010
-#define QEPICR_RES ~(QEPICR_PA15|QEPICR_PA16|QEPICR_PA29|QEPICR_PA30|QEPICR_PB3 \
- |QEPICR_PB5|QEPICR_PB12|QEPICR_PB13|QEPICR_PB26|QEPICR_PB27 \
- |QEPICR_PC27|QEPICR_PC28|QEPICR_PC29|QEPICR_PD12|QEPICR_PD13 \
- |QEPICR_PD16|QEPICR_PD17|QEPICR_PD26|QEPICR_PD27|QEPICR_PE12 \
- |QEPICR_PE13|QEPICR_PE24|QEPICR_PE25|QEPICR_PE26|QEPICR_PE27 \
- |QEPICR_PE31|QEPICR_PF20|QEPICR_PG31)
u8 res1[0xE8];
} qepi83xx_t;
/*
- * general purpose I/O module
+ * QE Parallel I/O Ports
*/
typedef struct gpio_n {
u32 podr; /* Open Drain Register */
@@ -879,238 +245,93 @@ typedef struct gpio_n {
u32 ppar2; /* Pin Assignment Register 2 */
} gpio_n_t;
-typedef struct gpio83xx {
+typedef struct qegpio83xx {
gpio_n_t ioport[0x7];
u8 res0[0x358];
-} gpio83xx_t;
+} qepio83xx_t;
/*
* QE Secondary Bus Access Windows
*/
-
typedef struct qesba83xx {
u32 lbmcsar; /* Local bus memory controller start address */
-#define LBMCSAR_SA 0x000FFFFF /* 20 most-significant bits of the start address */
-#define LBMCSAR_RES ~(LBMCSAR_SA)
u32 sdmcsar; /* Secondary DDR memory controller start address */
-#define SDMCSAR_SA 0x000FFFFF /* 20 most-significant bits of the start address */
-#define SDMCSAR_RES ~(SDMCSAR_SA)
u8 res0[0x38];
u32 lbmcear; /* Local bus memory controller end address */
-#define LBMCEAR_EA 0x000FFFFF /* 20 most-significant bits of the end address */
-#define LBMCEAR_RES ~(LBMCEAR_EA)
u32 sdmcear; /* Secondary DDR memory controller end address */
-#define SDMCEAR_EA 0x000FFFFF /* 20 most-significant bits of the end address */
-#define SDMCEAR_RES ~(SDMCEAR_EA)
u8 res1[0x38];
- u32 lbmcar; /* Local bus memory controller attributes */
-#define LBMCAR_WEN 0x00000001 /* Forward transactions to the QE local bus */
-#define LBMCAR_RES ~(LBMCAR_WEN)
+ u32 lbmcar; /* Local bus memory controller attributes */
u32 sdmcar; /* Secondary DDR memory controller attributes */
-#define SDMCAR_WEN 0x00000001 /* Forward transactions to the second DDR bus */
-#define SDMCAR_RES ~(SDMCAR_WEN)
- u8 res2[0x778];
+ u8 res2[0x378];
} qesba83xx_t;
-#endif
/*
* DDR Memory Controller Memory Map
*/
typedef struct ddr_cs_bnds {
u32 csbnds;
-#define CSBNDS_SA 0x00FF0000
-#define CSBNDS_SA_SHIFT 8
-#define CSBNDS_EA 0x000000FF
-#define CSBNDS_EA_SHIFT 24
u8 res0[4];
} ddr_cs_bnds_t;
typedef struct ddr83xx {
- ddr_cs_bnds_t csbnds[4]; /**< Chip Select x Memory Bounds */
+ ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
u8 res0[0x60];
- u32 cs_config[4]; /**< Chip Select x Configuration */
-#define CSCONFIG_EN 0x80000000
-#define CSCONFIG_AP 0x00800000
-#define CSCONFIG_ROW_BIT 0x00000700
-#define CSCONFIG_ROW_BIT_12 0x00000000
-#define CSCONFIG_ROW_BIT_13 0x00000100
-#define CSCONFIG_ROW_BIT_14 0x00000200
-#define CSCONFIG_COL_BIT 0x00000007
-#define CSCONFIG_COL_BIT_8 0x00000000
-#define CSCONFIG_COL_BIT_9 0x00000001
-#define CSCONFIG_COL_BIT_10 0x00000002
-#define CSCONFIG_COL_BIT_11 0x00000003
- u8 res1[0x78];
- u32 timing_cfg_1; /**< SDRAM Timing Configuration 1 */
-#define TIMING_CFG1_PRETOACT 0x70000000
-#define TIMING_CFG1_PRETOACT_SHIFT 28
-#define TIMING_CFG1_ACTTOPRE 0x0F000000
-#define TIMING_CFG1_ACTTOPRE_SHIFT 24
-#define TIMING_CFG1_ACTTORW 0x00700000
-#define TIMING_CFG1_ACTTORW_SHIFT 20
-#define TIMING_CFG1_CASLAT 0x00070000
-#define TIMING_CFG1_CASLAT_SHIFT 16
-#define TIMING_CFG1_REFREC 0x0000F000
-#define TIMING_CFG1_REFREC_SHIFT 12
-#define TIMING_CFG1_WRREC 0x00000700
-#define TIMING_CFG1_WRREC_SHIFT 8
-#define TIMING_CFG1_ACTTOACT 0x00000070
-#define TIMING_CFG1_ACTTOACT_SHIFT 4
-#define TIMING_CFG1_WRTORD 0x00000007
-#define TIMING_CFG1_WRTORD_SHIFT 0
-#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
-#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
-
- u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */
-#define TIMING_CFG2_CPO 0x0F000000
-#define TIMING_CFG2_CPO_SHIFT 24
-#define TIMING_CFG2_ACSM 0x00080000
-#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
-#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
-#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */
-
- u32 sdram_cfg; /**< SDRAM Control Configuration */
-#define SDRAM_CFG_MEM_EN 0x80000000
-#define SDRAM_CFG_SREN 0x40000000
-#define SDRAM_CFG_ECC_EN 0x20000000
-#define SDRAM_CFG_RD_EN 0x10000000
-#define SDRAM_CFG_SDRAM_TYPE 0x03000000
-#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
-#define SDRAM_CFG_DYN_PWR 0x00200000
-#define SDRAM_CFG_32_BE 0x00080000
-#define SDRAM_CFG_8_BE 0x00040000
-#define SDRAM_CFG_NCAP 0x00020000
-#define SDRAM_CFG_2T_EN 0x00008000
-#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
-
+ u32 cs_config[4]; /* Chip Select x Configuration */
+ u8 res1[0x70];
+ u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
+ u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
+ u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
+ u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
+ u32 sdram_cfg; /* SDRAM Control Configuration */
+ u32 sdram_cfg2; /* SDRAM Control Configuration 2 */
+ u32 sdram_mode; /* SDRAM Mode Configuration */
+ u32 sdram_mode2; /* SDRAM Mode Configuration 2 */
+ u32 sdram_md_cntl; /* SDRAM Mode Control */
+ u32 sdram_interval; /* SDRAM Interval Configuration */
+ u32 ddr_data_init; /* SDRAM Data Initialization */
u8 res2[4];
- u32 sdram_mode; /**< SDRAM Mode Configuration */
-#define SDRAM_MODE_ESD 0xFFFF0000
-#define SDRAM_MODE_ESD_SHIFT 16
-#define SDRAM_MODE_SD 0x0000FFFF
-#define SDRAM_MODE_SD_SHIFT 0
-#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */
-#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */
-#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
-#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */
-#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */
-#define DDR_MODE_WEAK 0x0002 /* weak drivers */
-#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */
-#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */
-#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
-#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
-#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
-#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
-#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */
-#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */
-#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
-#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
-#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125 µs */
-#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */
-#define DDR_MODE_MODEREG 0x0000 /* select mode register */
-
- u8 res3[8];
- u32 sdram_interval; /**< SDRAM Interval Configuration */
-#define SDRAM_INTERVAL_REFINT 0x3FFF0000
-#define SDRAM_INTERVAL_REFINT_SHIFT 16
-#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
-#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
- u8 res9[8];
- u32 sdram_clk_cntl;
-#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
-#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000
-#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
-#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000
-#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000
-
- u8 res4[0xCCC];
- u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
- u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
- u32 ecc_err_inject; /**< Memory Data Path Error Injection Mask ECC */
-#define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */
-#define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */
-#define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */
-#define ECC_ERR_INJECT_EEIM_SHIFT 0
- u8 res5[0x14];
- u32 capture_data_hi; /**< Memory Data Path Read Capture High */
- u32 capture_data_lo; /**< Memory Data Path Read Capture Low */
- u32 capture_ecc; /**< Memory Data Path Read Capture ECC */
-#define CAPTURE_ECC_ECE (0xff000000>>24)
-#define CAPTURE_ECC_ECE_SHIFT 0
+ u32 sdram_clk_cntl; /* SDRAM Clock Control */
+ u8 res3[0x14];
+ u32 ddr_init_addr; /* DDR training initialization address */
+ u32 ddr_init_ext_addr; /* DDR training initialization extended address */
+ u8 res4[0xAA8];
+ u32 ddr_ip_rev1; /* DDR IP block revision 1 */
+ u32 ddr_ip_rev2; /* DDR IP block revision 2 */
+ u8 res5[0x200];
+ u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */
+ u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */
+ u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */
u8 res6[0x14];
- u32 err_detect; /**< Memory Error Detect */
-#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */
-#define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */
-#define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */
-#define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */
- u32 err_disable; /**< Memory Error Disable */
-#define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */
-#define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */
-#define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */
-#define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED|ECC_ERROR_DISABLE_SBED|ECC_ERROR_DISABLE_MBED)
- u32 err_int_en; /**< Memory Error Interrupt Enable */
-#define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */
-#define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */
-#define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */
-#define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE|ECC_ERR_INT_EN_SBEE|ECC_ERR_INT_EN_MSEE)
- u32 capture_attributes; /**< Memory Error Attributes Capture */
-#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */
-#define ECC_CAPT_ATTR_BNUM_SHIFT 28
-#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */
-#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0
-#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1
-#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2
-#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3
-#define ECC_CAPT_ATTR_TSIZ_SHIFT 24
-#define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */
-#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
-#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
-#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4
-#define ECC_CAPT_ATTR_TSRC_TSEC2 0x5
-#define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07)
-#define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8
-#define ECC_CAPT_ATTR_TSRC_I2C 0x9
-#define ECC_CAPT_ATTR_TSRC_JTAG 0xA
-#define ECC_CAPT_ATTR_TSRC_PCI1 0xD
-#define ECC_CAPT_ATTR_TSRC_PCI2 0xE
-#define ECC_CAPT_ATTR_TSRC_DMA 0xF
-#define ECC_CAPT_ATTR_TSRC_SHIFT 16
-#define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */
-#define ECC_CAPT_ATTR_TTYP_WRITE 0x1
-#define ECC_CAPT_ATTR_TTYP_READ 0x2
-#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3
-#define ECC_CAPT_ATTR_TTYP_SHIFT 12
-#define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */
- u32 capture_address; /**< Memory Error Address Capture */
- u32 capture_ext_address;/**< Memory Error Extended Address Capture */
- u32 err_sbe; /**< Memory Single-Bit ECC Error Management */
-#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */
-#define ECC_ERROR_MAN_SBET_SHIFT 16
-#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */
-#define ECC_ERROR_MAN_SBEC_SHIFT 0
- u8 res7[0xA4];
+ u32 capture_data_hi; /* Memory Data Path Read Capture High */
+ u32 capture_data_lo; /* Memory Data Path Read Capture Low */
+ u32 capture_ecc; /* Memory Data Path Read Capture ECC */
+ u8 res7[0x14];
+ u32 err_detect; /* Memory Error Detect */
+ u32 err_disable; /* Memory Error Disable */
+ u32 err_int_en; /* Memory Error Interrupt Enable */
+ u32 capture_attributes; /* Memory Error Attributes Capture */
+ u32 capture_address; /* Memory Error Address Capture */
+ u32 capture_ext_address;/* Memory Error Extended Address Capture */
+ u32 err_sbe; /* Memory Single-Bit ECC Error Management */
+ u8 res8[0xA4];
u32 debug_reg;
- u8 res8[0xFC];
+ u8 res9[0xFC];
} ddr83xx_t;
/*
- * I2C1 Controller
- */
-
-/*
* DUART
*/
typedef struct duart83xx {
- u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */
- u8 uier_udmb; /**< combined register for UIER and UDMB */
- u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */
- u8 ulcr; /**< line control register */
- u8 umcr; /**< MODEM control register */
- u8 ulsr; /**< line status register */
- u8 umsr; /**< MODEM status register */
- u8 uscr; /**< scratch register */
+ u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */
+ u8 uier_udmb; /* combined register for UIER and UDMB */
+ u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */
+ u8 ulcr; /* line control register */
+ u8 umcr; /* MODEM control register */
+ u8 ulsr; /* line status register */
+ u8 umsr; /* MODEM status register */
+ u8 uscr; /* scratch register */
u8 res0[8];
- u8 udsr; /**< DMA status register */
+ u8 udsr; /* DMA status register */
u8 res1[3];
u8 res2[0xEC];
} duart83xx_t;
@@ -1119,75 +340,52 @@ typedef struct duart83xx {
* Local Bus Controller Registers
*/
typedef struct lbus_bank {
- u32 br; /**< Base Register */
- u32 or; /**< Base Register */
+ u32 br; /* Base Register */
+ u32 or; /* Option Register */
} lbus_bank_t;
typedef struct lbus83xx {
lbus_bank_t bank[8];
u8 res0[0x28];
- u32 mar; /**< UPM Address Register */
+ u32 mar; /* UPM Address Register */
u8 res1[0x4];
- u32 mamr; /**< UPMA Mode Register */
- u32 mbmr; /**< UPMB Mode Register */
- u32 mcmr; /**< UPMC Mode Register */
+ u32 mamr; /* UPMA Mode Register */
+ u32 mbmr; /* UPMB Mode Register */
+ u32 mcmr; /* UPMC Mode Register */
u8 res2[0x8];
- u32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
- u32 mdr; /**< UPM Data Register */
+ u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
+ u32 mdr; /* UPM Data Register */
u8 res3[0x8];
- u32 lsdmr; /**< SDRAM Mode Register */
+ u32 lsdmr; /* SDRAM Mode Register */
u8 res4[0x8];
- u32 lurt; /**< UPM Refresh Timer */
- u32 lsrt; /**< SDRAM Refresh Timer */
+ u32 lurt; /* UPM Refresh Timer */
+ u32 lsrt; /* SDRAM Refresh Timer */
u8 res5[0x8];
- u32 ltesr; /**< Transfer Error Status Register */
- u32 ltedr; /**< Transfer Error Disable Register */
- u32 lteir; /**< Transfer Error Interrupt Register */
- u32 lteatr; /**< Transfer Error Attributes Register */
- u32 ltear; /**< Transfer Error Address Register */
+ u32 ltesr; /* Transfer Error Status Register */
+ u32 ltedr; /* Transfer Error Disable Register */
+ u32 lteir; /* Transfer Error Interrupt Register */
+ u32 lteatr; /* Transfer Error Attributes Register */
+ u32 ltear; /* Transfer Error Address Register */
u8 res6[0xC];
- u32 lbcr; /**< Configuration Register */
-#define LBCR_LDIS 0x80000000
-#define LBCR_LDIS_SHIFT 31
-#define LBCR_BCTLC 0x00C00000
-#define LBCR_BCTLC_SHIFT 22
-#define LBCR_LPBSE 0x00020000
-#define LBCR_LPBSE_SHIFT 17
-#define LBCR_EPAR 0x00010000
-#define LBCR_EPAR_SHIFT 16
-#define LBCR_BMT 0x0000FF00
-#define LBCR_BMT_SHIFT 8
- u32 lcrr; /**< Clock Ratio Register */
-#define LCRR_DBYP 0x80000000
-#define LCRR_DBYP_SHIFT 31
-#define LCRR_BUFCMDC 0x30000000
-#define LCRR_BUFCMDC_SHIFT 28
-#define LCRR_ECL 0x03000000
-#define LCRR_ECL_SHIFT 24
-#define LCRR_EADC 0x00030000
-#define LCRR_EADC_SHIFT 16
-#define LCRR_CLKDIV 0x0000000F
-#define LCRR_CLKDIV_SHIFT 0
-
+ u32 lbcr; /* Configuration Register */
+ u32 lcrr; /* Clock Ratio Register */
u8 res7[0x28];
u8 res8[0xF00];
} lbus83xx_t;
-#if defined (CONFIG_MPC8349)
/*
* Serial Peripheral Interface
*/
typedef struct spi83xx {
- u32 mode; /**< mode register */
- u32 event; /**< event register */
- u32 mask; /**< mask register */
- u32 com; /**< command register */
+ u32 mode; /* mode register */
+ u32 event; /* event register */
+ u32 mask; /* mask register */
+ u32 com; /* command register */
u8 res0[0x10];
- u32 tx; /**< transmit register */
- u32 rx; /**< receive register */
- u8 res1[0xD8];
+ u32 tx; /* transmit register */
+ u32 rx; /* receive register */
+ u8 res1[0xFD8];
} spi83xx_t;
-#endif
/*
* DMA/Messaging Unit
@@ -1197,21 +395,17 @@ typedef struct dma83xx {
u32 omisr; /* 0x30 Outbound message interrupt status register */
u32 omimr; /* 0x34 Outbound message interrupt mask register */
u32 res1[0x6]; /* 0x38-0x49 reserved */
-
u32 imr0; /* 0x50 Inbound message register 0 */
u32 imr1; /* 0x54 Inbound message register 1 */
u32 omr0; /* 0x58 Outbound message register 0 */
u32 omr1; /* 0x5C Outbound message register 1 */
-
u32 odr; /* 0x60 Outbound doorbell register */
u32 res2; /* 0x64-0x67 reserved */
u32 idr; /* 0x68 Inbound doorbell register */
u32 res3[0x5]; /* 0x6C-0x79 reserved */
-
u32 imisr; /* 0x80 Inbound message interrupt status register */
u32 imimr; /* 0x84 Inbound message interrupt mask register */
u32 res4[0x1E]; /* 0x88-0x99 reserved */
-
u32 dmamr0; /* 0x100 DMA 0 mode register */
u32 dmasr0; /* 0x104 DMA 0 status register */
u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */
@@ -1223,7 +417,6 @@ typedef struct dma83xx {
u32 dmabcr0; /* 0x120 DMA 0 byte count register */
u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */
u32 res8[0x16]; /* 0x128-0x179 reserved */
-
u32 dmamr1; /* 0x180 DMA 1 mode register */
u32 dmasr1; /* 0x184 DMA 1 status register */
u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */
@@ -1235,7 +428,6 @@ typedef struct dma83xx {
u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */
u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */
u32 res12[0x16]; /* 0x1A8-0x199 reserved */
-
u32 dmamr2; /* 0x200 DMA 2 mode register */
u32 dmasr2; /* 0x204 DMA 2 status register */
u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */
@@ -1247,7 +439,6 @@ typedef struct dma83xx {
u32 dmabcr2; /* 0x220 DMA 2 byte count register */
u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */
u32 res16[0x16]; /* 0x228-0x279 reserved */
-
u32 dmamr3; /* 0x280 DMA 3 mode register */
u32 dmasr3; /* 0x284 DMA 3 status register */
u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */
@@ -1258,39 +449,15 @@ typedef struct dma83xx {
u32 res19; /* 0x29C reserved */
u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */
u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */
-
u32 dmagsr; /* 0x2A8 DMA general status register */
u32 res20[0x15]; /* 0x2AC-0x2FF reserved */
} dma83xx_t;
-/* DMAMRn bits */
-#define DMA_CHANNEL_START (0x00000001) /* Bit - DMAMRn CS */
-#define DMA_CHANNEL_TRANSFER_MODE_DIRECT (0x00000004) /* Bit - DMAMRn CTM */
-#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN (0x00001000) /* Bit - DMAMRn SAHE */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B (0x00000000) /* 2Bit- DMAMRn SAHTS 1byte */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B (0x00004000) /* 2Bit- DMAMRn SAHTS 2bytes */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B (0x00008000) /* 2Bit- DMAMRn SAHTS 4bytes */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B (0x0000c000) /* 2Bit- DMAMRn SAHTS 8bytes */
-#define DMA_CHANNEL_SNOOP (0x00010000) /* Bit - DMAMRn DMSEN */
-
-/* DMASRn bits */
-#define DMA_CHANNEL_BUSY (0x00000004) /* Bit - DMASRn CB */
-#define DMA_CHANNEL_TRANSFER_ERROR (0x00000080) /* Bit - DMASRn TE */
-
/*
* PCI Software Configuration Registers
*/
typedef struct pciconf83xx {
u32 config_address;
-#define PCI_CONFIG_ADDRESS_EN 0x80000000
-#define PCI_CONFIG_ADDRESS_BN_SHIFT 16
-#define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000
-#define PCI_CONFIG_ADDRESS_DN_SHIFT 11
-#define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800
-#define PCI_CONFIG_ADDRESS_FN_SHIFT 8
-#define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700
-#define PCI_CONFIG_ADDRESS_RN_SHIFT 0
-#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc
u32 config_data;
u32 int_ack;
u8 res[116];
@@ -1313,34 +480,6 @@ typedef struct pci_outbound_window {
*/
typedef struct ios83xx {
pot83xx_t pot[6];
-#define POTAR_TA_MASK 0x000fffff
-#define POBAR_BA_MASK 0x000fffff
-#define POCMR_EN 0x80000000
-#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */
-#define POCMR_SE 0x20000000 /* streaming enable */
-#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */
-#define POCMR_CM_MASK 0x000fffff
-#define POCMR_CM_4G 0x00000000
-#define POCMR_CM_2G 0x00080000
-#define POCMR_CM_1G 0x000C0000
-#define POCMR_CM_512M 0x000E0000
-#define POCMR_CM_256M 0x000F0000
-#define POCMR_CM_128M 0x000F8000
-#define POCMR_CM_64M 0x000FC000
-#define POCMR_CM_32M 0x000FE000
-#define POCMR_CM_16M 0x000FF000
-#define POCMR_CM_8M 0x000FF800
-#define POCMR_CM_4M 0x000FFC00
-#define POCMR_CM_2M 0x000FFE00
-#define POCMR_CM_1M 0x000FFF00
-#define POCMR_CM_512K 0x000FFF80
-#define POCMR_CM_256K 0x000FFFC0
-#define POCMR_CM_128K 0x000FFFE0
-#define POCMR_CM_64K 0x000FFFF0
-#define POCMR_CM_32K 0x000FFFF8
-#define POCMR_CM_16K 0x000FFFFC
-#define POCMR_CM_8K 0x000FFFFE
-#define POCMR_CM_4K 0x000FFFFF
u8 res0[0x60];
u32 pmcr;
u8 res1[4];
@@ -1353,74 +492,13 @@ typedef struct ios83xx {
*/
typedef struct pcictrl83xx {
u32 esr;
-#define ESR_MERR 0x80000000
-#define ESR_APAR 0x00000400
-#define ESR_PCISERR 0x00000200
-#define ESR_MPERR 0x00000100
-#define ESR_TPERR 0x00000080
-#define ESR_NORSP 0x00000040
-#define ESR_TABT 0x00000020
u32 ecdr;
-#define ECDR_APAR 0x00000400
-#define ECDR_PCISERR 0x00000200
-#define ECDR_MPERR 0x00000100
-#define ECDR_TPERR 0x00000080
-#define ECDR_NORSP 0x00000040
-#define ECDR_TABT 0x00000020
u32 eer;
-#define EER_APAR 0x00000400
-#define EER_PCISERR 0x00000200
-#define EER_MPERR 0x00000100
-#define EER_TPERR 0x00000080
-#define EER_NORSP 0x00000040
-#define EER_TABT 0x00000020
u32 eatcr;
-#define EATCR_ERRTYPR_MASK 0x70000000
-#define EATCR_ERRTYPR_APR 0x00000000 /* address parity error */
-#define EATCR_ERRTYPR_WDPR 0x10000000 /* write data parity error */
-#define EATCR_ERRTYPR_RDPR 0x20000000 /* read data parity error */
-#define EATCR_ERRTYPR_MA 0x30000000 /* master abort */
-#define EATCR_ERRTYPR_TA 0x40000000 /* target abort */
-#define EATCR_ERRTYPR_SE 0x50000000 /* system error indication received */
-#define EATCR_ERRTYPR_PEA 0x60000000 /* parity error indication received on a read */
-#define EATCR_ERRTYPR_PEW 0x70000000 /* parity error indication received on a write */
-#define EATCR_BN_MASK 0x0f000000 /* beat number */
-#define EATCR_BN_1st 0x00000000
-#define EATCR_BN_2ed 0x01000000
-#define EATCR_BN_3rd 0x02000000
-#define EATCR_BN_4th 0x03000000
-#define EATCR_BN_5th 0x0400000
-#define EATCR_BN_6th 0x05000000
-#define EATCR_BN_7th 0x06000000
-#define EATCR_BN_8th 0x07000000
-#define EATCR_BN_9th 0x08000000
-#define EATCR_TS_MASK 0x00300000 /* transaction size */
-#define EATCR_TS_4 0x00000000
-#define EATCR_TS_1 0x00100000
-#define EATCR_TS_2 0x00200000
-#define EATCR_TS_3 0x00300000
-#define EATCR_ES_MASK 0x000f0000 /* error source */
-#define EATCR_ES_EM 0x00000000 /* external master */
-#define EATCR_ES_DMA 0x00050000
-#define EATCR_CMD_MASK 0x0000f000
-#if defined (CONFIG_MPC8349)
-#define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable */
-#endif
-#define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */
-#if defined (CONFIG_MPC8349)
-#define EATCR_HPB 0x00000004 /* high parity bit */
-#endif
-#define EATCR_PB 0x00000002 /* parity bit */
-#define EATCR_VI 0x00000001 /* error information valid */
u32 eacr;
u32 eeacr;
-#if defined (CONFIG_MPC8349)
u32 edlcr;
u32 edhcr;
-#elif defined (CONFIG_MPC8360)
- u32 edcr; /* was edlcr */
- u8 res_edcr[0x4];
-#endif
u32 gcr;
u32 ecr;
u32 gsr;
@@ -1443,41 +521,8 @@ typedef struct pcictrl83xx {
u8 res6[4];
u32 piwar0;
u8 res7[132];
-#define PITAR_TA_MASK 0x000fffff
-#define PIBAR_MASK 0xffffffff
-#define PIEBAR_EBA_MASK 0x000fffff
-#define PIWAR_EN 0x80000000
-#define PIWAR_PF 0x20000000
-#define PIWAR_RTT_MASK 0x000f0000
-#define PIWAR_RTT_NO_SNOOP 0x00040000
-#define PIWAR_RTT_SNOOP 0x00050000
-#define PIWAR_WTT_MASK 0x0000f000
-#define PIWAR_WTT_NO_SNOOP 0x00004000
-#define PIWAR_WTT_SNOOP 0x00005000
-#define PIWAR_IWS_MASK 0x0000003F
-#define PIWAR_IWS_4K 0x0000000B
-#define PIWAR_IWS_8K 0x0000000C
-#define PIWAR_IWS_16K 0x0000000D
-#define PIWAR_IWS_32K 0x0000000E
-#define PIWAR_IWS_64K 0x0000000F
-#define PIWAR_IWS_128K 0x00000010
-#define PIWAR_IWS_256K 0x00000011
-#define PIWAR_IWS_512K 0x00000012
-#define PIWAR_IWS_1M 0x00000013
-#define PIWAR_IWS_2M 0x00000014
-#define PIWAR_IWS_4M 0x00000015
-#define PIWAR_IWS_8M 0x00000016
-#define PIWAR_IWS_16M 0x00000017
-#define PIWAR_IWS_32M 0x00000018
-#define PIWAR_IWS_64M 0x00000019
-#define PIWAR_IWS_128M 0x0000001A
-#define PIWAR_IWS_256M 0x0000001B
-#define PIWAR_IWS_512M 0x0000001C
-#define PIWAR_IWS_1G 0x0000001D
-#define PIWAR_IWS_2G 0x0000001E
} pcictrl83xx_t;
-#if defined (CONFIG_MPC8349)
/*
* USB
*/
@@ -1491,7 +536,6 @@ typedef struct usb83xx {
typedef struct tsec83xx {
u8 fixme[0x1000];
} tsec83xx_t;
-#endif
/*
* Security
@@ -1500,581 +544,119 @@ typedef struct security83xx {
u8 fixme[0x10000];
} security83xx_t;
-#if defined (CONFIG_MPC8360)
-/*
- * iram
- */
-typedef struct iram83xx {
- u32 iadd; /* I-RAM address register */
- u32 idata; /* I-RAM data register */
- u8 res0[0x78];
-} iram83xx_t;
-
-/*
- * Interrupt Controller
- */
-typedef struct irq83xx {
- u32 cicr; /* QE system interrupt configuration */
- u32 civec; /* QE system interrupt vector register */
- u32 cripnr; /* QE RISC interrupt pending register */
- u32 cipnr; /* QE system interrupt pending register */
- u32 cipxcc; /* QE interrupt priority register */
- u32 cipycc; /* QE interrupt priority register */
- u32 cipwcc; /* QE interrupt priority register */
- u32 cipzcc; /* QE interrupt priority register */
- u32 cimr; /* QE system interrupt mask register */
- u32 crimr; /* QE RISC interrupt mask register */
- u32 cicnr; /* QE system interrupt control register */
- u8 res0[0x4];
- u32 ciprta; /* QE system interrupt priority register for RISC tasks A */
- u32 ciprtb; /* QE system interrupt priority register for RISC tasks B */
- u8 res1[0x4];
- u32 cricr; /* QE system RISC interrupt control */
- u8 res2[0x20];
- u32 chivec; /* QE high system interrupt vector */
- u8 res3[0x1C];
-} irq83xx_t;
-
-/*
- * Communications Processor
- */
-typedef struct cp83xx {
- u32 cecr; /* QE command register */
- u32 ceccr; /* QE controller configuration register */
- u32 cecdr; /* QE command data register */
- u8 res0[0xA];
- u16 ceter; /* QE timer event register */
- u8 res1[0x2];
- u16 cetmr; /* QE timers mask register */
- u32 cetscr; /* QE time-stamp timer control register */
- u32 cetsr1; /* QE time-stamp register 1 */
- u32 cetsr2; /* QE time-stamp register 2 */
- u8 res2[0x8];
- u32 cevter; /* QE virtual tasks event register */
- u32 cevtmr; /* QE virtual tasks mask register */
- u16 cercr; /* QE RAM control register */
- u8 res3[0x2];
- u8 res4[0x24];
- u16 ceexe1; /* QE external request 1 event register */
- u8 res5[0x2];
- u16 ceexm1; /* QE external request 1 mask register */
- u8 res6[0x2];
- u16 ceexe2; /* QE external request 2 event register */
- u8 res7[0x2];
- u16 ceexm2; /* QE external request 2 mask register */
- u8 res8[0x2];
- u16 ceexe3; /* QE external request 3 event register */
- u8 res9[0x2];
- u16 ceexm3; /* QE external request 3 mask register */
- u8 res10[0x2];
- u16 ceexe4; /* QE external request 4 event register */
- u8 res11[0x2];
- u16 ceexm4; /* QE external request 4 mask register */
- u8 res12[0x2];
- u8 res13[0x280];
-} cp83xx_t;
-
-/*
- * QE Multiplexer
- */
-
-typedef struct qmx83xx {
- u32 cmxgcr; /* CMX general clock route register */
- u32 cmxsi1cr_l; /* CMX SI1 clock route low register */
- u32 cmxsi1cr_h; /* CMX SI1 clock route high register */
- u32 cmxsi1syr; /* CMX SI1 SYNC route register */
- u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */
- u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */
- u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */
- u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */
- u32 cmxupcr; /* CMX UPC clock route register */
- u8 res0[0x1C];
-} qmx83xx_t;
-
-/*
-* QE Timers
-*/
-
-typedef struct qet83xx {
- u8 gtcfr1; /* Timer 1 and Timer 2 global configuration register */
- u8 res0[0x3];
- u8 gtcfr2; /* Timer 3 and timer 4 global configuration register */
- u8 res1[0xB];
- u16 gtmdr1; /* Timer 1 mode register */
- u16 gtmdr2; /* Timer 2 mode register */
- u16 gtrfr1; /* Timer 1 reference register */
- u16 gtrfr2; /* Timer 2 reference register */
- u16 gtcpr1; /* Timer 1 capture register */
- u16 gtcpr2; /* Timer 2 capture register */
- u16 gtcnr1; /* Timer 1 counter */
- u16 gtcnr2; /* Timer 2 counter */
- u16 gtmdr3; /* Timer 3 mode register */
- u16 gtmdr4; /* Timer 4 mode register */
- u16 gtrfr3; /* Timer 3 reference register */
- u16 gtrfr4; /* Timer 4 reference register */
- u16 gtcpr3; /* Timer 3 capture register */
- u16 gtcpr4; /* Timer 4 capture register */
- u16 gtcnr3; /* Timer 3 counter */
- u16 gtcnr4; /* Timer 4 counter */
- u16 gtevr1; /* Timer 1 event register */
- u16 gtevr2; /* Timer 2 event register */
- u16 gtevr3; /* Timer 3 event register */
- u16 gtevr4; /* Timer 4 event register */
- u16 gtps; /* Timer 1 prescale register */
- u8 res2[0x46];
-} qet83xx_t;
-
-/*
-* spi
-*/
-
-typedef struct spi83xx {
- u8 res0[0x20];
- u32 spmode; /* SPI mode register */
- u8 res1[0x2];
- u8 spie; /* SPI event register */
- u8 res2[0x1];
- u8 res3[0x2];
- u8 spim; /* SPI mask register */
- u8 res4[0x1];
- u8 res5[0x1];
- u8 spcom; /* SPI command register */
- u8 res6[0x2];
- u32 spitd; /* SPI transmit data register (cpu mode) */
- u32 spird; /* SPI receive data register (cpu mode) */
- u8 res7[0x8];
-} spi83xx_t;
-
-/*
-* mcc
-*/
-
-typedef struct mcc83xx {
- u32 mcce; /* MCC event register */
- u32 mccm; /* MCC mask register */
- u32 mccf; /* MCC configuration register */
- u32 merl; /* MCC emergency request level register */
- u8 res0[0xF0];
-} mcc83xx_t;
-
-/*
-* brg
-*/
-
-typedef struct brg83xx {
- u32 brgc1; /* BRG1 configuration register */
- u32 brgc2; /* BRG2 configuration register */
- u32 brgc3; /* BRG3 configuration register */
- u32 brgc4; /* BRG4 configuration register */
- u32 brgc5; /* BRG5 configuration register */
- u32 brgc6; /* BRG6 configuration register */
- u32 brgc7; /* BRG7 configuration register */
- u32 brgc8; /* BRG8 configuration register */
- u32 brgc9; /* BRG9 configuration register */
- u32 brgc10; /* BRG10 configuration register */
- u32 brgc11; /* BRG11 configuration register */
- u32 brgc12; /* BRG12 configuration register */
- u32 brgc13; /* BRG13 configuration register */
- u32 brgc14; /* BRG14 configuration register */
- u32 brgc15; /* BRG15 configuration register */
- u32 brgc16; /* BRG16 configuration register */
- u8 res0[0x40];
-} brg83xx_t;
-
-/*
-* USB
-*/
-
-typedef struct usb83xx {
- u8 usmod; /* USB mode register */
- u8 usadd; /* USB address register */
- u8 uscom; /* USB command register */
- u8 res0[0x1];
- u16 usep0; /* USB endpoint register 0 */
- u16 usep1; /* USB endpoint register 1 */
- u16 usep2; /* USB endpoint register 2 */
- u16 usep3; /* USB endpoint register 3 */
- u8 res1[0x4];
- u16 usber; /* USB event register */
- u8 res2[0x2];
- u16 usbmr; /* USB mask register */
- u8 res3[0x1];
- u8 usbs; /* USB status register */
- u32 ussft; /* USB start of frame timer */
- u8 res4[0x24];
-} usb83xx_t;
-
-/*
-* SI
-*/
-
-typedef struct si1_83xx {
- u16 siamr1; /* SI1 TDMA mode register */
- u16 sibmr1; /* SI1 TDMB mode register */
- u16 sicmr1; /* SI1 TDMC mode register */
- u16 sidmr1; /* SI1 TDMD mode register */
- u8 siglmr1_h; /* SI1 global mode register high */
- u8 res0[0x1];
- u8 sicmdr1_h; /* SI1 command register high */
- u8 res2[0x1];
- u8 sistr1_h; /* SI1 status register high */
- u8 res3[0x1];
- u16 sirsr1_h; /* SI1 RAM shadow address register high */
- u8 sitarc1; /* SI1 RAM counter Tx TDMA */
- u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
- u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
- u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
- u8 sirarc1; /* SI1 RAM counter Rx TDMA */
- u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
- u8 sircrc1; /* SI1 RAM counter Rx TDMC */
- u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
- u8 res4[0x8];
- u16 siemr1; /* SI1 TDME mode register 16 bits */
- u16 sifmr1; /* SI1 TDMF mode register 16 bits */
- u16 sigmr1; /* SI1 TDMG mode register 16 bits */
- u16 sihmr1; /* SI1 TDMH mode register 16 bits */
- u8 siglmg1_l; /* SI1 global mode register low 8 bits */
- u8 res5[0x1];
- u8 sicmdr1_l; /* SI1 command register low 8 bits */
- u8 res6[0x1];
- u8 sistr1_l; /* SI1 status register low 8 bits */
- u8 res7[0x1];
- u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */
- u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
- u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
- u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
- u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
- u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
- u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
- u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
- u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
- u8 res8[0x8];
- u32 siml1; /* SI1 multiframe limit register */
- u8 siedm1; /* SI1 extended diagnostic mode register */
- u8 res9[0xBB];
-} si1_83xx_t;
-
-/*
-* SI Routing Tables
-*/
-
-typedef struct sir83xx {
- u8 tx[0x400];
- u8 rx[0x400];
- u8 res0[0x800];
-} sir83xx_t;
-
-/*
-* ucc
-*/
-
-typedef struct uslow {
- u32 gumr_l; /* UCCx general mode register (low) */
- u32 gumr_h; /* UCCx general mode register (high) */
- u16 upsmr; /* UCCx protocol-specific mode register */
- u8 res0[0x2];
- u16 utodr; /* UCCx transmit on demand register */
- u16 udsr; /* UCCx data synchronization register */
- u16 ucce; /* UCCx event register */
- u8 res1[0x2];
- u16 uccm; /* UCCx mask register */
- u8 res2[0x1];
- u8 uccs; /* UCCx status register */
- u8 res3[0x1E8];
-} uslow_t;
-
-typedef struct ufast {
- u32 gumr; /* UCCx general mode register */
- u32 upsmr; /* UCCx protocol-specific mode register */
- u16 utodr; /* UCCx transmit on demand register */
- u8 res0[0x2];
- u16 udsr; /* UCCx data synchronization register */
- u8 res1[0x2];
- u32 ucce; /* UCCx event register */
- u32 uccm; /* UCCx mask register. */
- u8 uccs; /* UCCx status register */
- u8 res2[0x7];
- u32 urfb; /* UCC receive FIFO base */
- u16 urfs; /* UCC receive FIFO size */
- u8 res3[0x2];
- u16 urfet; /* UCC receive FIFO emergency threshold */
- u16 urfset; /* UCC receive FIFO special emergency threshold */
- u32 utfb; /* UCC transmit FIFO base */
- u16 utfs; /* UCC transmit FIFO size */
- u8 res4[0x2];
- u16 utfet; /* UCC transmit FIFO emergency threshold */
- u8 res5[0x2];
- u16 utftt; /* UCC transmit FIFO transmit threshold */
- u8 res6[0x2];
- u16 utpt; /* UCC transmit polling timer */
- u32 urtry; /* UCC retry counter register */
- u8 res7[0x4C];
- u8 guemr; /* UCC general extended mode register */
- u8 res8[0x3];
- u8 res9[0x6C];
- u32 maccfg1; /* Mac configuration register #1 */
- u32 maccfg2; /* Mac configuration register #2 */
- u16 ipgifg; /* Interframe gap register */
- u8 res10[0x2];
- u32 hafdup; /* Half-duplex register */
- u8 res11[0xC];
- u32 emtr; /* Ethernet MAC test register */
- u32 miimcfg; /* MII mgmt configuration register */
- u32 miimcom; /* MII mgmt command register */
- u32 miimadd; /* MII mgmt address register */
- u32 miimcon; /* MII mgmt control register */
- u32 miistat; /* MII mgmt status register */
- u32 miimnd; /* MII mgmt indication register */
- u32 ifctl; /* Interface control register */
- u32 ifstat; /* Interface status register */
- u32 macstnaddr1; /* Station address part 1 register */
- u32 macstnaddr2; /* Station address part 2 register */
- u8 res12[0x8];
- u32 uempr; /* UCC Ethernet MAC parameter register */
- u32 utbipa; /* UCC TBI address */
- u16 uescr; /* UCC Ethernet statistics control register */
- u8 res13[0x26];
- u32 tx64; /* Transmit and receive 64-byte frame counter */
- u32 tx127; /* Transmit and receive 65- to 127-byte frame counter */
- u32 tx255; /* Transmit and receive 128- to 255-byte frame counter */
- u32 rx64; /* Receive and receive 64-byte frame counter */
- u32 rx127; /* Receive and receive 65- to 127-byte frame counter */
- u32 rx255; /* Receive and receive 128- to 255-byte frame counter */
- u32 txok; /* Transmit good bytes counter */
- u32 txcf; /* Transmit control frame counter */
- u32 tmca; /* Transmit multicast control frame counter */
- u32 tbca; /* Transmit broadcast packet counter */
- u32 rxfok; /* Receive frame OK counter */
- u32 rbyt; /* Receive good and bad bytes counter */
- u32 rxbok; /* Receive bytes OK counter */
- u32 rmca; /* Receive multicast packet counter */
- u32 rbca; /* Receive broadcast packet counter */
- u32 scar; /* Statistics carry register */
- u32 scam; /* Statistics carry mask register */
- u8 res14[0x3C];
-} ufast_t;
-
-typedef struct ucc83xx {
- union {
- uslow_t slow;
- ufast_t fast;
- };
-} ucc83xx_t;
-
-/*
-* MultiPHY UTOPIA POS Controllers
-*/
-
-typedef struct upc83xx {
- u32 upgcr; /* UTOPIA/POS general configuration register */
-#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
-#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
-#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
-#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing: */
-#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
- u32 uplpa; /* UTOPIA/POS last PHY address */
- u32 uphec; /* ATM HEC register */
- u32 upuc; /* UTOPIA/POS UCC configuration */
- u32 updc1; /* UTOPIA/POS device 1 configuration */
- u32 updc2; /* UTOPIA/POS device 2 configuration */
- u32 updc3; /* UTOPIA/POS device 3 configuration */
- u32 updc4; /* UTOPIA/POS device 4 configuration */
- u32 upstpa; /* UTOPIA/POS STPA threshold */
- u8 res0[0xC];
- u32 updrs1_h; /* UTOPIA/POS device 1 rate select */
- u32 updrs1_l; /* UTOPIA/POS device 1 rate select */
- u32 updrs2_h; /* UTOPIA/POS device 2 rate select */
- u32 updrs2_l; /* UTOPIA/POS device 2 rate select */
- u32 updrs3_h; /* UTOPIA/POS device 3 rate select */
- u32 updrs3_l; /* UTOPIA/POS device 3 rate select */
- u32 updrs4_h; /* UTOPIA/POS device 4 rate select */
- u32 updrs4_l; /* UTOPIA/POS device 4 rate select */
- u32 updrp1; /* UTOPIA/POS device 1 receive priority low */
- u32 updrp2; /* UTOPIA/POS device 2 receive priority low */
- u32 updrp3; /* UTOPIA/POS device 3 receive priority low */
- u32 updrp4; /* UTOPIA/POS device 4 receive priority low */
- u32 upde1; /* UTOPIA/POS device 1 event */
- u32 upde2; /* UTOPIA/POS device 2 event */
- u32 upde3; /* UTOPIA/POS device 3 event */
- u32 upde4; /* UTOPIA/POS device 4 event */
- u16 uprp1;
- u16 uprp2;
- u16 uprp3;
- u16 uprp4;
- u8 res1[0x8];
- u16 uptirr1_0; /* Device 1 transmit internal rate 0 */
- u16 uptirr1_1; /* Device 1 transmit internal rate 1 */
- u16 uptirr1_2; /* Device 1 transmit internal rate 2 */
- u16 uptirr1_3; /* Device 1 transmit internal rate 3 */
- u16 uptirr2_0; /* Device 2 transmit internal rate 0 */
- u16 uptirr2_1; /* Device 2 transmit internal rate 1 */
- u16 uptirr2_2; /* Device 2 transmit internal rate 2 */
- u16 uptirr2_3; /* Device 2 transmit internal rate 3 */
- u16 uptirr3_0; /* Device 3 transmit internal rate 0 */
- u16 uptirr3_1; /* Device 3 transmit internal rate 1 */
- u16 uptirr3_2; /* Device 3 transmit internal rate 2 */
- u16 uptirr3_3; /* Device 3 transmit internal rate 3 */
- u16 uptirr4_0; /* Device 4 transmit internal rate 0 */
- u16 uptirr4_1; /* Device 4 transmit internal rate 1 */
- u16 uptirr4_2; /* Device 4 transmit internal rate 2 */
- u16 uptirr4_3; /* Device 4 transmit internal rate 3 */
- u32 uper1; /* Device 1 port enable register */
- u32 uper2; /* Device 2 port enable register */
- u32 uper3; /* Device 3 port enable register */
- u32 uper4; /* Device 4 port enable register */
- u8 res2[0x150];
-} upc83xx_t;
-
-/*
-* SDMA
-*/
-
-typedef struct sdma83xx {
- u32 sdsr; /* Serial DMA status register */
- u32 sdmr; /* Serial DMA mode register */
- u32 sdtr1; /* SDMA system bus threshold register */
- u32 sdtr2; /* SDMA secondary bus threshold register */
- u32 sdhy1; /* SDMA system bus hysteresis register */
- u32 sdhy2; /* SDMA secondary bus hysteresis register */
- u32 sdta1; /* SDMA system bus address register */
- u32 sdta2; /* SDMA secondary bus address register */
- u32 sdtm1; /* SDMA system bus MSNUM register */
- u32 sdtm2; /* SDMA secondary bus MSNUM register */
- u8 res0[0x10];
- u32 sdaqr; /* SDMA address bus qualify register */
- u32 sdaqmr; /* SDMA address bus qualify mask register */
- u8 res1[0x4];
- u32 sdwbcr; /* SDMA CAM entries base register */
- u8 res2[0x38];
-} sdma83xx_t;
-
-/*
-* Debug Space
-*/
-
-typedef struct dbg83xx {
- u32 bpdcr; /* Breakpoint debug command register */
- u32 bpdsr; /* Breakpoint debug status register */
- u32 bpdmr; /* Breakpoint debug mask register */
- u32 bprmrr0; /* Breakpoint request mode risc register 0 */
- u32 bprmrr1; /* Breakpoint request mode risc register 1 */
- u8 res0[0x8];
- u32 bprmtr0; /* Breakpoint request mode trb register 0 */
- u32 bprmtr1; /* Breakpoint request mode trb register 1 */
- u8 res1[0x8];
- u32 bprmir; /* Breakpoint request mode immediate register */
- u32 bprmsr; /* Breakpoint request mode serial register */
- u32 bpemr; /* Breakpoint exit mode register */
- u8 res2[0x48];
-} dbg83xx_t;
-
-/*
-* RISC Special Registers (Trap and Breakpoint)
-*/
+#if defined(CONFIG_MPC834X)
+typedef struct immap {
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ gtm83xx_t gtm[2]; /* Global Timers Module */
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ gpio83xx_t gpio[2]; /* General purpose I/O module */
+ u8 res0[0x200];
+ u8 dll_ddr[0x100];
+ u8 dll_lbc[0x100];
+ u8 res1[0xE00];
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+ fsl_i2c_t i2c[2]; /* I2C Controllers */
+ u8 res2[0x1300];
+ duart83xx_t duart[2]; /* DUART */
+ u8 res3[0x900];
+ lbus83xx_t lbus; /* Local Bus Controller Registers */
+ u8 res4[0x1000];
+ spi83xx_t spi; /* Serial Peripheral Interface */
+ dma83xx_t dma; /* DMA */
+ pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
+ ios83xx_t ios; /* Sequencer */
+ pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
+ u8 res5[0x19900];
+ usb83xx_t usb;
+ tsec83xx_t tsec[2];
+ u8 res6[0xA000];
+ security83xx_t security;
+ u8 res7[0xC0000];
+} immap_t;
-typedef struct rsp83xx {
- u8 fixme[0x100];
-} rsp83xx_t;
-#endif
+#elif defined(CONFIG_MPC8360)
+typedef struct immap {
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ u8 res0[0x200];
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ qepi83xx_t qepi; /* QE Ports Interrupts Registers */
+ u8 res1[0x300];
+ u8 dll_ddr[0x100];
+ u8 dll_lbc[0x100];
+ u8 res2[0x200];
+ qepio83xx_t qepio; /* QE Parallel I/O ports */
+ qesba83xx_t qesba; /* QE Secondary Bus Access Windows */
+ u8 res3[0x400];
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+ fsl_i2c_t i2c[2]; /* I2C Controllers */
+ u8 res4[0x1300];
+ duart83xx_t duart[2]; /* DUART */
+ u8 res5[0x900];
+ lbus83xx_t lbus; /* Local Bus Controller Registers */
+ u8 res6[0x2000];
+ dma83xx_t dma; /* DMA */
+ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
+ u8 res7[128];
+ ios83xx_t ios; /* Sequencer (IOS) */
+ pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
+ u8 res8[0x4A00];
+ ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */
+ u8 res9[0x22000];
+ security83xx_t security;
+ u8 res10[0xC0000];
+ u8 qe[0x100000]; /* QE block */
+} immap_t;
+#elif defined(CONFIG_MPC832X)
typedef struct immap {
- sysconf83xx_t sysconf; /* System configuration */
- wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
- rtclk83xx_t rtc; /* Real Time Clock Module Registers */
- rtclk83xx_t pit; /* Periodic Interval Timer */
- gtm83xx_t gtm[2]; /* Global Timers Module */
- ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
- arbiter83xx_t arbiter; /* System Arbiter Registers */
- reset83xx_t reset; /* Reset Module */
- clk83xx_t clk; /* System Clock Module */
- pmc83xx_t pmc; /* Power Management Control Module */
-#if defined (CONFIG_MPC8349)
- gpio83xx_t pgio[2]; /* general purpose I/O module */
-#elif defined (CONFIG_MPC8360)
- qepi83xx_t qepi; /* QE Ports Interrupts Registers */
-#endif
- u8 res0[0x200];
-#if defined (CONFIG_MPC8360)
- u8 DLL_LBDDR[0x100];
-#endif
- u8 DDL_DDR[0x100];
- u8 DDL_LBIU[0x100];
-#if defined (CONFIG_MPC8349)
- u8 res1[0xE00];
-#elif defined (CONFIG_MPC8360)
- u8 res1[0x200];
- gpio83xx_t gpio; /* General purpose I/O module */
- qesba83xx_t qesba; /* QE Secondary Bus Access Windows */
-#endif
- ddr83xx_t ddr; /* DDR Memory Controller Memory */
- fsl_i2c_t i2c[2]; /* I2C Controllers */
- u8 res2[0x1300];
- duart83xx_t duart[2]; /* DUART */
-#if defined (CONFIG_MPC8349)
- u8 res3[0x900];
- lbus83xx_t lbus; /* Local Bus Controller Registers */
- u8 res4[0x1000];
- spi83xx_t spi; /* Serial Peripheral Interface */
- u8 res5[0xF00];
-#elif defined (CONFIG_MPC8360)
- u8 res3[0x900];
- lbus83xx_t lbus; /* Local Bus Controller */
- u8 res4[0x2000];
-#endif
- dma83xx_t dma; /* DMA */
-#if defined (CONFIG_MPC8349)
- pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
- ios83xx_t ios; /* Sequencer */
- pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
- u8 res6[0x19900];
- usb83xx_t usb;
- tsec83xx_t tsec[2];
- u8 res7[0xA000];
- security83xx_t security;
-#elif defined (CONFIG_MPC8360)
- pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
- u8 res_5[128];
- ios83xx_t ios; /* Sequencer (IOS) */
- pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
- u8 res6[0x4A00];
- ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */
- u8 res7[0x22000];
- security83xx_t security;
- u8 res8[0xC0000];
- iram83xx_t iram; /* IRAM */
- irq83xx_t irq; /* Interrupt Controller */
- cp83xx_t cp; /* Communications Processor */
- qmx83xx_t qmx; /* QE Multiplexer */
- qet83xx_t qet; /* QE Timers */
- spi83xx_t spi[0x2]; /* spi */
- mcc83xx_t mcc; /* mcc */
- brg83xx_t brg; /* brg */
- usb83xx_t usb; /* USB */
- si1_83xx_t si1; /* SI */
- u8 res9[0x800];
- sir83xx_t sir; /* SI Routing Tables */
- ucc83xx_t ucc1; /* ucc1 */
- ucc83xx_t ucc3; /* ucc3 */
- ucc83xx_t ucc5; /* ucc5 */
- ucc83xx_t ucc7; /* ucc7 */
- u8 res10[0x600];
- upc83xx_t upc1; /* MultiPHY UTOPIA POS Controller 1 */
- ucc83xx_t ucc2; /* ucc2 */
- ucc83xx_t ucc4; /* ucc4 */
- ucc83xx_t ucc6; /* ucc6 */
- ucc83xx_t ucc8; /* ucc8 */
- u8 res11[0x600];
- upc83xx_t upc2; /* MultiPHY UTOPIA POS Controller 2 */
- sdma83xx_t sdma; /* SDMA */
- dbg83xx_t dbg; /* Debug Space */
- rsp83xx_t rsp[0x2]; /* RISC Special Registers (Trap and Breakpoint) */
- u8 res12[0x300];
- u8 res13[0x3A00];
- u8 res14[0x8000]; /* 0x108000 - 0x110000 */
- u8 res15[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */
- u8 res16[0x24000]; /* 0x11C000 - 0x140000 */
- u8 res17[0xC0000]; /* 0x140000 - 0x200000 */
-#endif
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ gtm83xx_t gtm[2]; /* Global Timers Module */
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ qepi83xx_t qepi; /* QE Ports Interrupts Registers */
+ u8 res0[0x300];
+ u8 dll_ddr[0x100];
+ u8 dll_lbc[0x100];
+ u8 res1[0x200];
+ qepio83xx_t qepio; /* QE Parallel I/O ports */
+ u8 res2[0x800];
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+ fsl_i2c_t i2c[2]; /* I2C Controllers */
+ u8 res3[0x1300];
+ duart83xx_t duart[2]; /* DUART */
+ u8 res4[0x900];
+ lbus83xx_t lbus; /* Local Bus Controller Registers */
+ u8 res5[0x2000];
+ dma83xx_t dma; /* DMA */
+ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
+ u8 res6[128];
+ ios83xx_t ios; /* Sequencer (IOS) */
+ pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
+ u8 res7[0x27A00];
+ security83xx_t security;
+ u8 res8[0xC0000];
+ u8 qe[0x100000]; /* QE block */
} immap_t;
+#endif
#endif /* __IMMAP_83xx__ */
diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h
index f385032..950b949 100644
--- a/include/asm-ppc/immap_qe.h
+++ b/include/asm-ppc/immap_qe.h
@@ -547,4 +547,10 @@ typedef struct qe_immap {
extern qe_map_t *qe_immr;
+#if defined(CONFIG_MPC8360)
+#define QE_MURAM_SIZE 0xc000UL
+#elif defined(CONFIG_MPC832X)
+#define QE_MURAM_SIZE 0x4000UL
+#endif
+
#endif /* __IMMAP_QE_H__ */
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
new file mode 100644
index 0000000..cecb225
--- /dev/null
+++ b/include/configs/MPC832XEMDS.h
@@ -0,0 +1,631 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 family */
+#define CONFIG_QE 1 /* Has QE */
+#define CONFIG_MPC83XX 1 /* MPC83xx family */
+#define CONFIG_MPC832X 1 /* MPC832x CPU specific */
+#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
+
+/*
+ * System Clock Setup
+ */
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
+#else
+#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ 66000000
+#endif
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CFG_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_2X1 |\
+ HRCWL_VCO_1X2 |\
+ HRCWL_CSB_TO_CLKIN_2X1 |\
+ HRCWL_CORE_TO_CSB_2X1 |\
+ HRCWL_CE_PLL_VCO_DIV_2 |\
+ HRCWL_CE_PLL_DIV_1X1 |\
+ HRCWL_CE_TO_PLL_1X3)
+
+#ifdef CONFIG_PCISLAVE
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_AGENT |\
+ HRCWH_PCI1_ARBITER_DISABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0XFFF00100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_BIG_ENDIAN |\
+ HRCWH_LALE_NORMAL)
+#else
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_BIG_ENDIAN |\
+ HRCWH_LALE_NORMAL)
+#endif
+
+/*
+ * System IO Config
+ */
+#define CFG_SICRL 0x00000000
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+
+/*
+ * IMMR new address
+ */
+#define CFG_IMMR 0xE0000000
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
+
+#undef CONFIG_SPD_EEPROM
+#if defined(CONFIG_SPD_EEPROM)
+/* Determine DDR configuration from I2C interface
+ */
+#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
+#else
+/* Manually set up DDR parameters
+ */
+#define CFG_DDR_SIZE 128 /* MB */
+#define CFG_DDR_CS0_CONFIG 0x80840102
+#define CFG_DDR_TIMING_0 0x00220802
+#define CFG_DDR_TIMING_1 0x3935d322
+#define CFG_DDR_TIMING_2 0x0f9048ca
+#define CFG_DDR_TIMING_3 0x00000000
+#define CFG_DDR_CLK_CNTL 0x02000000
+#define CFG_DDR_MODE 0x44400232
+#define CFG_DDR_MODE2 0x8000c000
+#define CFG_DDR_INTERVAL 0x03200064
+#define CFG_DDR_CS0_BNDS 0x00000007
+#define CFG_DDR_SDRAM_CFG 0x43080000
+#define CFG_DDR_SDRAM_CFG2 0x00401000
+#endif
+
+/*
+ * Memory test
+ */
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00000000 /* memtest region */
+#define CFG_MEMTEST_END 0x00100000
+
+/*
+ * The reserved memory
+ */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2)
+#define CFG_LBC_LBCR 0x00000000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI /* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
+#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
+
+#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
+#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
+
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
+ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+ BR_V) /* valid */
+#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
+
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+
+/*
+ * BCSR on the Local Bus
+ */
+#define CFG_BCSR 0xF8000000
+#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
+#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
+
+#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
+#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
+
+/*
+ * SDRAM on the Local Bus
+ */
+#undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */
+
+#ifdef CFG_LB_SDRAM
+#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
+#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+
+#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE
+#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
+
+/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ * port size = 32-bits = BR2[19:20] = 11
+ * no parity checking = BR2[21:22] = 00
+ * SDRAM for MSEL = BR2[24:26] = 011
+ * Valid = BR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ * 64MB mask for AM, OR2[0:7] = 1111 1100
+ * XAM, OR2[17:18] = 11
+ * 9 columns OR2[19-21] = 010
+ * 13 rows OR2[23-25] = 100
+ * EAD set for extra time OR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CFG_OR2_PRELIM 0xfc006901
+
+#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
+#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
+
+#define CFG_LBC_LSDMR_COMMON 0x0063b723
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_PCHALL)
+#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_MRW)
+#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_NORMAL)
+
+#endif
+
+/*
+ * Windows to access PIB via local bus
+ */
+#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
+#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
+
+/*
+ * CS2 on Local Bus, to PIB
+ */
+#define CFG_BR2_PRELIM 0xf8008801 /* CS2 base address at 0xf8008000 */
+#define CFG_OR2_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
+
+/*
+ * CS3 on Local Bus, to PIB
+ */
+#define CFG_BR3_PRELIM 0xf8010801 /* CS3 base address at 0xf8010000 */
+#define CFG_OR3_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,8323@0"
+#define OF_SOC "soc8323@e0000000"
+#define OF_QE "qe@e0100000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500"
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_FSL_I2C
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
+#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI_MEM_BASE 0x80000000
+#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
+#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI_MMIO_BASE 0x90000000
+#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
+#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
+#define CFG_PCI_IO_BASE 0xE0300000
+#define CFG_PCI_IO_PHYS 0xE0300000
+#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
+
+#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE
+#define CFG_PCI_SLV_MEM_BUS 0x00000000
+#define CFG_PCI_SLV_MEM_SIZE 0x80000000
+
+
+#ifdef CONFIG_PCI
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
+
+#endif /* CONFIG_PCI */
+
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME "Freescale GETH"
+
+#define CONFIG_UEC_ETH1 /* ETH3 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CFG_UEC1_UCC_NUM 2 /* UCC3 */
+#define CFG_UEC1_RX_CLK QE_CLK9
+#define CFG_UEC1_TX_CLK QE_CLK10
+#define CFG_UEC1_ETH_TYPE FAST_ETH
+#define CFG_UEC1_PHY_ADDR 3
+#define CFG_UEC1_INTERFACE_MODE ENET_100_MII
+#endif
+
+#define CONFIG_UEC_ETH2 /* ETH4 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CFG_UEC2_UCC_NUM 3 /* UCC4 */
+#define CFG_UEC2_RX_CLK QE_CLK7
+#define CFG_UEC2_TX_CLK QE_CLK8
+#define CFG_UEC2_ETH_TYPE FAST_ETH
+#define CFG_UEC2_PHY_ADDR 4
+#define CFG_UEC2_INTERFACE_MODE ENET_100_MII
+#endif
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+ #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+ #define CFG_ENV_SIZE 0x2000
+#else
+ #define CFG_NO_FLASH 1 /* Flash is not usable now */
+ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+ #define CFG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_PCI)
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_ASKENV \
+ | CFG_CMD_PCI \
+ | CFG_CMD_I2C) \
+ & \
+ ~(CFG_CMD_ENV \
+ | CFG_CMD_LOADS))
+#else
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_ASKENV \
+ | CFG_CMD_I2C) \
+ & \
+ ~(CFG_CMD_ENV \
+ | CFG_CMD_LOADS))
+#endif
+#else
+#if defined(CONFIG_PCI)
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_PCI \
+ | CFG_CMD_PING \
+ | CFG_CMD_ASKENV \
+ | CFG_CMD_I2C)
+#else
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_ASKENV \
+ | CFG_CMD_I2C )
+#endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CFG_HID0_INIT 0x000000000
+#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CFG_HID2 HID2_HBE
+
+/*
+ * Cache Config
+ */
+#define CFG_DCACHE_SIZE 16384
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
+#endif
+
+/*
+ * MMU Setup
+ */
+
+/* DDR: cache cacheable */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+
+/* IMMRBAR & PCI IO: cache-inhibit and guarded */
+#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+
+/* BCSR: cache-inhibit and guarded */
+#define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U CFG_IBAT3U
+
+#define CFG_IBAT4L (0)
+#define CFG_IBAT4U (0)
+#define CFG_DBAT4L CFG_IBAT4L
+#define CFG_DBAT4U CFG_IBAT4U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10)
+#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT5L CFG_IBAT5L
+#define CFG_DBAT5U CFG_IBAT5U
+
+#ifdef CONFIG_PCI
+/* PCI MEM space: cacheable */
+#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT7L CFG_IBAT7L
+#define CFG_DBAT7U CFG_IBAT7U
+#else
+#define CFG_IBAT6L (0)
+#define CFG_IBAT6U (0)
+#define CFG_IBAT7L (0)
+#define CFG_IBAT7U (0)
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+#define CFG_DBAT7L CFG_IBAT7L
+#define CFG_DBAT7U CFG_IBAT7U
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_UEC_ETH)
+#define CONFIG_ETHADDR 00:04:9f:ef:03:01
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=1000000\0" \
+ "ramdiskfile=ramfs.83xx\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=mpc832xemds.dtb\0" \
+ ""
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 5bed2d0..0460be9 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -60,17 +60,6 @@
#endif
#endif
-#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK))
-#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */
-#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */
-#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */
-#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */
-#define CFG_SCCR_VAL ( CFG_SCCR_INIT \
- | CFG_SCCR_TSEC1CM \
- | CFG_SCCR_TSEC2CM \
- | CFG_SCCR_ENCCM \
- | CFG_SCCR_USBCM )
-
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
#define CFG_IMMR 0xE0000000
@@ -82,7 +71,7 @@
/*
* DDR Setup
*/
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_DDR_ECC /* support DDR ECC function */
#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
@@ -101,8 +90,15 @@
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_BASE
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#undef CONFIG_DDR_2T_TIMING
+/*
+ * DDRCDR - DDR Control Driver Register
+ */
+#define CFG_DDRCDR_VALUE 0x80080001
+
#if defined(CONFIG_SPD_EEPROM)
/*
* Determine DDR configuration from I2C interface.
@@ -113,6 +109,21 @@
* Manually set up DDR parameters
*/
#define CFG_DDR_SIZE 256 /* MB */
+#if defined(CONFIG_DDR_II)
+#define CFG_DDRCDR 0x80080001
+#define CFG_DDR_CS2_BNDS 0x0000000f
+#define CFG_DDR_CS2_CONFIG 0x80330102
+#define CFG_DDR_TIMING_0 0x00220802
+#define CFG_DDR_TIMING_1 0x38357322
+#define CFG_DDR_TIMING_2 0x2f9048c8
+#define CFG_DDR_TIMING_3 0x00000000
+#define CFG_DDR_CLK_CNTL 0x02000000
+#define CFG_DDR_MODE 0x47d00432
+#define CFG_DDR_MODE2 0x8000c000
+#define CFG_DDR_INTERVAL 0x03cf0080
+#define CFG_DDR_SDRAM_CFG 0x43000000
+#define CFG_DDR_SDRAM_CFG2 0x00401000
+#else
#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
#define CFG_DDR_TIMING_1 0x36332321
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
@@ -127,6 +138,7 @@
#define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */
#endif
#endif
+#endif
/*
* SDRAM on the Local Bus
@@ -140,19 +152,20 @@
#define CFG_FLASH_CFI /* use the Common Flash Interface */
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
-#define CFG_FLASH_SIZE 8 /* flash size in MB */
+#define CFG_FLASH_SIZE 32 /* max flash size in MB */
/* #define CFG_FLASH_USE_BUFFER_WRITE */
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \
- (2 << BR_PS_SHIFT) | /* 32 bit port size */ \
+ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
BR_V) /* valid */
-
-#define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */
+#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
+ OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
+ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */
-#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
+#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
-#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
+#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
@@ -197,7 +210,11 @@
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
#define CFG_LBC_LBCR 0x00000000
-#define CFG_LB_SDRAM /* if board has SRDAM on local bus */
+/*
+ * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
+ * if board has SRDAM on local bus, you can define CFG_LB_SDRAM
+ */
+#undef CFG_LB_SDRAM
#ifdef CFG_LB_SDRAM
/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
@@ -314,6 +331,7 @@
#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index cbdbb29..37bbfb3 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -21,7 +21,7 @@
*/
/*
- MPC8349E-mITX board configuration file
+ MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
Memory map:
@@ -31,11 +31,11 @@
0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
- 0xF000_0000-0xF000_FFFF Compact Flash
+ 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
0xF001_0000-0xF001_FFFF Local bus expansion slot
- 0xF800_0000-0xF801_FFFF GBE L2 Switch VSC7385
- 0xFF00_0000-0xFF7F_FFFF Alternative bank of Flash memory (8MB)
- 0xFF80_0000-0xFFFF_FFFF Boot Flash (8 MB)
+ 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
+ 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
+ 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
I2C address list:
Align. Board
@@ -56,7 +56,9 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
+#if (TEXT_BASE == 0xFE000000)
+#define CFG_LOWBOOT
+#endif
/*
* High Level Configuration Options
@@ -64,14 +66,26 @@
#define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */
#define CONFIG_MPC8349 /* MPC8349 specific */
-#define CONFIG_PCI
+#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */
+
+
+/* On-board devices */
+#ifdef CONFIG_MPC8349ITX
#define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */
-#define CONFIG_RTC_DS1337
+#define CONFIG_VSC7385 /* The Vitesse 7385 5-port switch */
+#endif
-/* I2C */
+#define CONFIG_PCI
+#define CONFIG_RTC_DS1337
#define CONFIG_HARD_I2C
+#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
+/*
+ * Device configurations
+ */
+
+/* I2C */
#ifdef CONFIG_HARD_I2C
#define CONFIG_MISC_INIT_F
@@ -111,59 +125,40 @@
#endif
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#define CONFIG_ENV_OVERWRITE
+/* Compact Flash */
+#ifdef CONFIG_COMPACT_FLASH
-#define PCI_66M
-#ifdef PCI_66M
-#define CONFIG_83XX_CLKIN 66666666 /* in Hz */
-#else
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#endif
+#define CFG_IDE_MAXBUS 1
+#define CFG_IDE_MAXDEVICE 1
-#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef PCI_66M
-#define CONFIG_SYS_CLK_FREQ 66666666
-#else
-#define CONFIG_SYS_CLK_FREQ 33333333
-#endif
-#endif
+#define CFG_ATA_IDE0_OFFSET 0x0000
+#define CFG_ATA_BASE_ADDR CFG_CF_BASE
+#define CFG_ATA_DATA_OFFSET 0x0000
+#define CFG_ATA_REG_OFFSET 0
+#define CFG_ATA_ALT_OFFSET 0x0200
+#define CFG_ATA_STRIDE 2
-#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */
+#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */
-#undef CFG_DRAM_TEST /* memory test, takes time */
-#define CFG_MEMTEST_START 0x00003000 /* memtest region */
-#define CFG_MEMTEST_END 0x07100000 /* only has 128M */
+#define CONFIG_DOS_PARTITION
-/*
- * DDR Setup
- */
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
-#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
+#endif
/*
- * 32-bit data path mode.
- *
- * Please note that using this mode for devices with the real density of 64-bit
- * effectively reduces the amount of available memory due to the effect of
- * wrapping around while translating address to row/columns, for example in the
- * 256MB module the upper 128MB get aliased with contents of the lower
- * 128MB); normally this define should be used for devices with real 32-bit
- * data path.
+ * DDR Setup
*/
-#undef CONFIG_DDR_32BIT
-
-#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
-#define CFG_SDRAM_BASE CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
-#undef CONFIG_DDR_2T_TIMING
+#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
#define CFG_83XX_DDR_USES_CS0
+#define CFG_MEMTEST_START 0x1000 /* memtest region */
+#define CFG_MEMTEST_END 0x2000
-#ifndef CONFIG_SPD_EEPROM
-/*
- * Manually set up DDR parameters
- */
+#ifdef CONFIG_HARD_I2C
+#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
+#endif
+
+#ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */
#define CFG_DDR_SIZE 256 /* Mb */
#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
@@ -171,46 +166,65 @@
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
#endif
-/* FLASH on the Local Bus */
+/*
+ *Flash on the Local Bus
+ */
+
#define CFG_FLASH_CFI /* use the Common Flash Interface */
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
-#define CFG_FLASH_SIZE 16 /* FLASH size in MB */
#define CFG_FLASH_EMPTY_INFO
+#define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+
+/* The ITX has two flash chips, but the ITX-GP has only one. To support both
+boards, we say we have two, but don't display a message if we find only one. */
+#define CFG_FLASH_QUIET_TEST
+#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000}
+#define CFG_FLASH_SIZE 16 /* FLASH size in MB */
+#define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */
+
+/*
+ * BRx, ORx, LBLAWBARx, and LBLAWARx
+ */
+
+/* Flash */
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V)
#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
-#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
-#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16Mb window bytes */
+#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE
+#define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT))
-/* VSC7385 on the Local Bus */
-#define CFG_VSC7385_BASE 0xF8000000 /* start of VSC7385 */
+/* Vitesse 7385 */
-#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V)
-#define CFG_OR1_PRELIM (0xFFFE0000 /* 128KB */ | \
- OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
- OR_GPCM_SETA | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
+#ifdef CONFIG_VSC7385
-#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE /* Access window base at VSC7385 base */
-#define CFG_LBLAWAR1_PRELIM 0x80000010 /* Access window size 128K */
+#define CFG_VSC7385_BASE 0xF8000000
-#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
-#define CFG_MAX_FLASH_SECT 135 /* sectors per device */
+#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V)
+#define CFG_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+ OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
+ OR_GPCM_EHTR | OR_GPCM_EAD)
-#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000}
+#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE
+#define CFG_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
-#undef CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+#endif
-#define CFG_LED_BASE 0xF9000000 /* start of LED and Board ID */
+/* LED */
+
+#define CFG_LED_BASE 0xF9000000
#define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V)
-#define CFG_OR2_PRELIM (0xFFE00000 /* 2MB */ | \
- OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | \
- OR_GPCM_SCY_9 | \
- OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
+#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
+ OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \
+ OR_GPCM_EHTR | OR_GPCM_EAD)
+
+/* Compact Flash */
#ifdef CONFIG_COMPACT_FLASH
@@ -219,32 +233,16 @@
#define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V)
#define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
-#define CFG_LBLAWBAR2_PRELIM CFG_CF_BASE /* Window base at flash base + LED & Board ID */
-#define CFG_LBLAWAR2_PRELIM 0x8000000F /* 64K bytes */
-
-#undef CONFIG_IDE_RESET
-#undef CONFIG_IDE_PREINIT
-
-#define CFG_IDE_MAXBUS 1
-#define CFG_IDE_MAXDEVICE 1
-
-#define CFG_ATA_IDE0_OFFSET 0x0000
-#define CFG_ATA_BASE_ADDR CFG_CF_BASE
-#define CFG_ATA_DATA_OFFSET 0x0000
-#define CFG_ATA_REG_OFFSET 0
-#define CFG_ATA_ALT_OFFSET 0x0200
-#define CFG_ATA_STRIDE 2
-
-#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */
+#define CFG_LBLAWBAR3_PRELIM CFG_CF_BASE
+#define CFG_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
#endif
-#define CONFIG_DOS_PARTITION
-
-#define CFG_MID_FLASH_JUMP 0x7F000000
+/*
+ * U-Boot memory configuration
+ */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
@@ -253,10 +251,10 @@
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK
-#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
-#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -272,98 +270,10 @@
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
#define CFG_LBC_LBCR 0x00000000
-#undef CFG_LB_SDRAM /* if board has SRDAM on local bus */
-
-#ifdef CFG_LB_SDRAM
-/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- * port-size = 32-bits = BR2[19:20] = 11
- * no parity checking = BR2[21:22] = 00
- * SDRAM for MSEL = BR2[24:26] = 011
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
- */
-
-#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
-#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-#define CFG_LBLAWBAR2_PRELIM 0xF0000000
-#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */
-
-#define CFG_BR2_PRELIM (CFG_LBC_SDRAM_BASE | BR_PS_32 | BR_MS_SDRAM | BR_V)
-#define CFG_OR2_PRELIM (0xFC000000 /* 64 MB */ | \
- OR_SDRAM_XAM | \
- ((9 - 7) << OR_SDRAM_COLS_SHIFT) | \
- ((13 - 9) << OR_SDRAM_ROWS_SHIFT) | \
- OR_SDRAM_EAD)
-
#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/
/*
- * LSDMR masks
- */
-#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
-#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
-#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
-#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
-#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16))
-#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
-#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
-#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19))
-#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
-#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
-#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
-#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
-#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27))
-#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
-#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
-#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
-
-#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
-
-#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \
- | CFG_LBC_LSDMR_BSMA1516 \
- | CFG_LBC_LSDMR_RFCR8 \
- | CFG_LBC_LSDMR_PRETOACT6 \
- | CFG_LBC_LSDMR_ACTTORW3 \
- | CFG_LBC_LSDMR_BL8 \
- | CFG_LBC_LSDMR_WRC3 \
- | CFG_LBC_LSDMR_CL3 \
- )
-
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
- | CFG_LBC_LSDMR_OP_PCHALL)
-#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
- | CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
- | CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
- | CFG_LBC_LSDMR_OP_MRW)
-#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
- | CFG_LBC_LSDMR_OP_NORMAL)
-#endif
-
-/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
@@ -374,20 +284,16 @@
#define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_BAUDRATE 115200
#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500)
#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600)
-/* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
-#endif
-
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
-#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_FLAT_TREE
+#define CONFIG_OF_BOARD_SETUP
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
@@ -397,6 +303,9 @@
#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500"
+/*
+ * PCI
+ */
#ifdef CONFIG_PCI
#define CONFIG_MPC83XX_PCI2
@@ -447,14 +356,18 @@
#endif
+#define PCI_66M
+#ifdef PCI_66M
+#define CONFIG_83XX_CLKIN 66666666 /* in Hz */
+#else
+#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
+#endif
+
/* TSEC */
#ifdef CONFIG_TSEC_ENET
-#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI
-#endif
-
#define CONFIG_MII
#define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */
@@ -468,6 +381,7 @@
#endif
#ifdef CONFIG_MPC83XX_TSEC2
+#define CONFIG_HAS_ETH1
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
#define CFG_TSEC2_OFFSET 0x25000
#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */
@@ -479,14 +393,15 @@
#endif
-
/*
* Environment
*/
+#define CONFIG_ENV_OVERWRITE
+
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH
- #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
- #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+ #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE))
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH /* Flash is not usable now */
@@ -533,16 +448,23 @@
/* Watchdog */
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#ifdef CONFIG_WATCHDOG
-#define CFG_WATCHDOG_VALUE 0xFFFFFFC3
-#endif
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CFG_HUSH_PARSER /* Use the HUSH parser */
+#define CFG_PROMPT_HUSH_PS2 "> "
+
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
-#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */
+#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
+
+#ifdef CONFIG_MPC8349ITX
+#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */
+#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
@@ -562,15 +484,15 @@
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/* Cache Configuration */
+/*
+ * Cache Configuration
+ */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */
#endif
-#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-
#define CFG_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_1X1 |\
@@ -578,12 +500,12 @@
HRCWL_VCO_1X2 |\
HRCWL_CORE_TO_CSB_2X1)
-#ifdef PCI_64BIT
+#ifdef CFG_LOWBOOT
#define CFG_HRCW_HIGH (\
HRCWH_PCI_HOST |\
- HRCWH_64_BIT_PCI |\
+ HRCWH_32_BIT_PCI |\
HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_DISABLE |\
+ HRCWH_PCI2_ARBITER_ENABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
@@ -596,7 +518,7 @@
HRCWH_PCI_HOST |\
HRCWH_32_BIT_PCI |\
HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_DISABLE |\
+ HRCWH_PCI2_ARBITER_ENABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0XFFF00100 |\
HRCWH_BOOTSEQ_DISABLE |\
@@ -606,30 +528,32 @@
HRCWH_TSEC2M_IN_GMII )
#endif
-/* System performance */
+/*
+ * System performance
+ */
#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
#define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
#define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
#define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
-#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count */
-/* System IO Config */
+/*
+ * System IO Config
+ */
#define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */
#define CFG_SICRL (SICRL_LDP_A | SICRL_USB1)
-#define CFG_HID0_INIT 0x000000000
-
-#define CFG_HID0_FINAL CFG_HID0_INIT
+#define CFG_HID0_INIT 0x000000000
+#define CFG_HID0_FINAL CFG_HID0_INIT
#define CFG_HID2 HID2_HBE
-/* DDR @ 0x00000000 */
+/* DDR */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-/* PCI @ 0x80000000 */
+/* PCI */
#ifdef CONFIG_PCI
#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
@@ -706,97 +630,72 @@
#endif
#ifdef CONFIG_MPC83XX_TSEC2
-#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02
#endif
-#if 1
-#define CONFIG_IPADDR 10.82.19.159
-#define CONFIG_SERVERIP 10.82.48.106
-#define CONFIG_GATEWAYIP 10.82.19.254
-#define CONFIG_NETMASK 255.255.252.0
-#define CONFIG_NETDEV eth0
-
-#define CONFIG_HOSTNAME mpc8349emitx
-#define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs
-#define CONFIG_BOOTFILE timur/uImage
-
-#define CONFIG_UBOOTPATH timur/u-boot.bin
-#else
#define CONFIG_IPADDR 192.168.1.253
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.252.0
#define CONFIG_NETDEV eth0
+#ifdef CONFIG_MPC8349ITX
#define CONFIG_HOSTNAME mpc8349emitx
-#define CONFIG_ROOTPATH /nfsroot/rootfs
-#define CONFIG_BOOTFILE uImage
-
-#define CONFIG_UBOOTPATH u-boot.bin
+#else
+#define CONFIG_HOSTNAME mpc8349emitxgp
#endif
-#define CONFIG_UBOOTSTART fe700000
-#define CONFIG_UBOOTEND fe77ffff
-
-#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
-
-#define CONFIG_BAUDRATE 115200
+/* Default path and filenames */
+#define CONFIG_ROOTPATH /nfsroot/rootfs
+#define CONFIG_BOOTFILE uImage
+#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-#undef CONFIG_BOOTCOMMAND
-#ifdef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTDELAY 6
+#ifdef CONFIG_MPC8349ITX
+#define CONFIG_FDTFILE mpc8349emitx.dtb
#else
-#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
+#define CONFIG_FDTFILE mpc8349emitxgp.dtb
#endif
+#define CONFIG_BOOTDELAY 0
+
#define XMK_STR(x) #x
#define MK_STR(x) XMK_STR(x)
#define CONFIG_BOOTARGS \
"root=/dev/nfs rw" \
" nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \
- " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \
+ " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \
MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \
" console=ttyS0," MK_STR(CONFIG_BAUDRATE)
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
- "tftpflash=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \
- "erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \
- "cp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize\0" \
- "tftpupdate=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \
- "protect off FEF00000 FEF7FFFF; " \
- "erase FEF00000 FEF7FFFF; " \
- "cp.b $loadaddr FEF00000 $filesize; " \
- "protect on FEF00000 FEF7FFFF; " \
- "cmp.b $loadaddr FEF00000 $filesize\0" \
- "tftplinux=tftpboot $loadaddr $bootfile; bootm\0" \
- "copyuboot=erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \
- "cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0" \
+ "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
"fdtaddr=400000\0" \
- "fdtfile=mpc8349emitx.dtb\0" \
- ""
+ "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"
#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
+ "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
+ " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ " console=$console,$baudrate $othbootargs; " \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
+ "setenv bootargs root=/dev/ram rw" \
+ " console=$console,$baudrate $othbootargs; " \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
#undef MK_STR
#undef XMK_STR
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 8ad6551..d2af0e1 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -100,12 +100,19 @@
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_BASE
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CFG_83XX_DDR_USES_CS0
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_DDR_ECC /* support DDR ECC function */
#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
+/*
+ * DDRCDR - DDR Control Driver Register
+ */
+#define CFG_DDRCDR_VALUE 0x80080001
+
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#if defined(CONFIG_SPD_EEPROM)
/*
@@ -117,6 +124,21 @@
* Manually set up DDR parameters
*/
#define CFG_DDR_SIZE 256 /* MB */
+#if defined(CONFIG_DDR_II)
+#define CFG_DDRCDR 0x80080001
+#define CFG_DDR_CS0_BNDS 0x0000000f
+#define CFG_DDR_CS0_CONFIG 0x80330102
+#define CFG_DDR_TIMING_0 0x00220802
+#define CFG_DDR_TIMING_1 0x38357322
+#define CFG_DDR_TIMING_2 0x2f9048c8
+#define CFG_DDR_TIMING_3 0x00000000
+#define CFG_DDR_CLK_CNTL 0x02000000
+#define CFG_DDR_MODE 0x47d00432
+#define CFG_DDR_MODE2 0x8000c000
+#define CFG_DDR_INTERVAL 0x03cf0080
+#define CFG_DDR_SDRAM_CFG 0x43000000
+#define CFG_DDR_SDRAM_CFG2 0x00401000
+#else
#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
#define CFG_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
#define CFG_DDR_TIMING_2 0x00000800 /* may need tuning */
@@ -124,6 +146,7 @@
#define CFG_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
#define CFG_DDR_INTERVAL 0x045b0100 /* page mode */
#endif
+#endif
/*
* Memory test
@@ -168,7 +191,7 @@
#define CFG_FLASH_CFI /* use the Common Flash Interface */
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
+#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
@@ -176,10 +199,12 @@
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
BR_V) /* valid */
-#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
+#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
+ OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
+ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
-#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
+#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
#undef CFG_FLASH_CHECKSUM
@@ -188,7 +213,7 @@
*/
#define CFG_BCSR 0xF8000000
#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
-#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
+#define CFG_LBLAWAR1_PRELIM 0x8000000F /* Access window size 64K */
#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
@@ -278,8 +303,8 @@
/*
* Windows to access PIB via local bus
*/
-#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
-#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
+#define CFG_LBLAWBAR3_PRELIM 0xf8010000 /* windows base 0xf8010000 */
+#define CFG_LBLAWAR3_PRELIM 0x8000000e /* windows size 32KB */
/*
* CS4 on Local Bus, to PIB
@@ -309,6 +334,7 @@
#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
@@ -324,6 +350,7 @@
#define OF_CPU "PowerPC,8360@0"
#define OF_SOC "soc8360@e0000000"
+#define OF_QE "qe@e0100000"
#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH "/soc8360@e0000000/serial@4500"
@@ -609,7 +636,7 @@
"ramdiskaddr=1000000\0" \
"ramdiskfile=ramfs.83xx\0" \
"fdtaddr=400000\0" \
- "fdtfile=mpc8349emds.dtb\0" \
+ "fdtfile=mpc8360emds.dtb\0" \
""
#define CONFIG_NFSBOOTCOMMAND \
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 728083b..ed03577 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -57,17 +57,6 @@
*/
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
-#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK))
-#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */
-#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */
-#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */
-#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */
-#define CFG_SCCR_VAL ( CFG_SCCR_INIT \
- | CFG_SCCR_TSEC1CM \
- | CFG_SCCR_TSEC2CM \
- | CFG_SCCR_ENCCM \
- | CFG_SCCR_USBCM )
-
/* board pre init: do not call, nothing to do */
#undef CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
new file mode 100644
index 0000000..65aac5c
--- /dev/null
+++ b/include/configs/sbc8349.h
@@ -0,0 +1,734 @@
+/*
+ * WindRiver SBC8349 U-Boot configuration file.
+ * Copyright (c) 2006, 2007 Wind River Systems, Inc.
+ *
+ * Paul Gortmaker <paul.gortmaker@windriver.com>
+ * Based on the MPC8349EMDS config.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * sbc8349 board configuration file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 Family */
+#define CONFIG_MPC83XX 1 /* MPC83XX family */
+#define CONFIG_MPC834X 1 /* MPC834X family */
+#define CONFIG_MPC8349 1 /* MPC8349 specific */
+#define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */
+
+#undef CONFIG_PCI
+/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
+#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
+
+#define PCI_66M
+#ifdef PCI_66M
+#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
+#else
+#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#ifdef PCI_66M
+#define CONFIG_SYS_CLK_FREQ 66000000
+#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
+#else
+#define CONFIG_SYS_CLK_FREQ 33000000
+#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
+#endif
+#endif
+
+#undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+
+#define CFG_IMMR 0xE0000000
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00000000 /* memtest region */
+#define CFG_MEMTEST_END 0x00100000
+
+/*
+ * DDR Setup
+ */
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
+#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
+#define CFG_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
+#define CONFIG_DDR_2T_TIMING
+
+#if defined(CONFIG_SPD_EEPROM)
+/*
+ * Determine DDR configuration from I2C interface.
+ */
+#define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */
+
+#else
+/*
+ * Manually set up DDR parameters
+ * NB: manual DDR setup untested on sbc834x
+ */
+#define CFG_DDR_SIZE 256 /* MB */
+#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+#define CFG_DDR_TIMING_1 0x36332321
+#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
+#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
+#define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
+
+#if defined(CONFIG_DDR_32BIT)
+/* set burst length to 8 for 32-bit data path */
+#define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */
+#else
+/* the default burst length is 4 - for 64-bit data path */
+#define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */
+#endif
+#endif
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE 0x10000000 /* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI /* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CFG_FLASH_BASE 0xFF800000 /* start of FLASH */
+#define CFG_FLASH_SIZE 8 /* flash size in MB */
+/* #define CFG_FLASH_USE_BUFFER_WRITE */
+
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \
+ (2 << BR_PS_SHIFT) | /* 32 bit port size */ \
+ BR_V) /* valid */
+
+#define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */
+#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */
+#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
+
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CFG_MID_FLASH_JUMP 0x7F000000
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ * LCRR: DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
+#define CFG_LBC_LBCR 0x00000000
+
+#undef CFG_LB_SDRAM /* if board has SDRAM on local bus */
+
+#ifdef CFG_LB_SDRAM
+/* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ * port-size = 32-bits = BR2[19:20] = 11
+ * no parity checking = BR2[21:22] = 00
+ * SDRAM for MSEL = BR2[24:26] = 011
+ * Valid = BR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
+ *
+ * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
+#define CFG_LBLAWBAR2_PRELIM 0xF0000000
+#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ * 64MB mask for AM, OR2[0:7] = 1111 1100
+ * XAM, OR2[17:18] = 11
+ * 9 columns OR2[19-21] = 010
+ * 13 rows OR2[23-25] = 100
+ * EAD set for extra time OR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
+ */
+
+#define CFG_OR2_PRELIM 0xFC006901
+
+#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
+#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
+#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
+#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
+#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
+
+#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \
+ | CFG_LBC_LSDMR_BSMA1516 \
+ | CFG_LBC_LSDMR_RFCR8 \
+ | CFG_LBC_LSDMR_PRETOACT6 \
+ | CFG_LBC_LSDMR_ACTTORW3 \
+ | CFG_LBC_LSDMR_BL8 \
+ | CFG_LBC_LSDMR_WRC3 \
+ | CFG_LBC_LSDMR_CL3 \
+ )
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_PCHALL)
+#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_MRW)
+#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
+ | CFG_LBC_LSDMR_OP_NORMAL)
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,8349@0"
+#define OF_SOC "soc8349@e0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500"
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_CMD_TREE
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
+#define CFG_I2C1_OFFSET 0x3000
+#define CFG_I2C2_OFFSET 0x3100
+#define CFG_I2C_OFFSET CFG_I2C2_OFFSET
+/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */
+
+/* TSEC */
+#define CFG_TSEC1_OFFSET 0x24000
+#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET 0x25000
+#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_MMIO_BASE 0x90000000
+#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
+#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xE2000000
+#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
+
+#define CFG_PCI2_MEM_BASE 0xA0000000
+#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI2_MMIO_BASE 0xB0000000
+#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE
+#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */
+#define CFG_PCI2_IO_BASE 0x00000000
+#define CFG_PCI2_IO_PHYS 0xE2100000
+#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
+
+#if defined(CONFIG_PCI)
+
+#define PCI_64BIT
+#define PCI_ONE_PCI1
+#if defined(PCI_64BIT)
+#undef PCI_ALL_PCI1
+#undef PCI_TWO_PCI1
+#undef PCI_ONE_PCI1
+#endif
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xFIXME
+ #define PCI_ENET0_MEMADDR 0xFIXME
+ #define PCI_IDSEL_NUMBER 0xFIXME
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+#endif /* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+#define CONFIG_TSEC_ENET /* TSEC ethernet support */
+
+#if defined(CONFIG_TSEC_ENET)
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+#define CONFIG_MPC83XX_TSEC1 1
+#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
+#define CONFIG_MPC83XX_TSEC2 1
+#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
+#define CONFIG_PHY_BCM5421S 1
+#define TSEC1_PHY_ADDR 0x19
+#define TSEC2_PHY_ADDR 0x1a
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC0"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+ #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+ #define CFG_ENV_SIZE 0x2000
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+#else
+ #define CFG_NO_FLASH 1 /* Flash is not usable now */
+ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+ #define CFG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_PCI)
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_PCI \
+ | CFG_CMD_I2C) \
+ & \
+ ~(CFG_CMD_ENV \
+ | CFG_CMD_LOADS))
+#else
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C) \
+ & \
+ ~(CFG_CMD_ENV \
+ | CFG_CMD_LOADS))
+#endif
+#else
+#if defined(CONFIG_PCI)
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_PCI \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C \
+ )
+#else
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C \
+ | CFG_CMD_MII \
+ )
+#endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */
+
+#if 1 /*528/264*/
+#define CFG_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_1X1 |\
+ HRCWL_CSB_TO_CLKIN |\
+ HRCWL_VCO_1X2 |\
+ HRCWL_CORE_TO_CSB_2X1)
+#elif 0 /*396/132*/
+#define CFG_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_1X1 |\
+ HRCWL_CSB_TO_CLKIN |\
+ HRCWL_VCO_1X4 |\
+ HRCWL_CORE_TO_CSB_3X1)
+#elif 0 /*264/132*/
+#define CFG_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_1X1 |\
+ HRCWL_CSB_TO_CLKIN |\
+ HRCWL_VCO_1X4 |\
+ HRCWL_CORE_TO_CSB_2X1)
+#elif 0 /*132/132*/
+#define CFG_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_1X1 |\
+ HRCWL_CSB_TO_CLKIN |\
+ HRCWL_VCO_1X4 |\
+ HRCWL_CORE_TO_CSB_1X1)
+#elif 0 /*264/264 */
+#define CFG_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_1X1 |\
+ HRCWL_CSB_TO_CLKIN |\
+ HRCWL_VCO_1X4 |\
+ HRCWL_CORE_TO_CSB_1X1)
+#endif
+
+#if defined(PCI_64BIT)
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_64_BIT_PCI |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_PCI2_ARBITER_DISABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_TSEC1M_IN_GMII |\
+ HRCWH_TSEC2M_IN_GMII )
+#else
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_32_BIT_PCI |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_PCI2_ARBITER_ENABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_TSEC1M_IN_GMII |\
+ HRCWH_TSEC2M_IN_GMII )
+#endif
+
+/* System IO Config */
+#define CFG_SICRH SICRH_TSOBI1
+#define CFG_SICRL SICRL_LDP_A
+
+#define CFG_HID0_INIT 0x000000000
+#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+
+/* #define CFG_HID0_FINAL (\
+ HID0_ENABLE_INSTRUCTION_CACHE |\
+ HID0_ENABLE_M_BIT |\
+ HID0_ENABLE_ADDRESS_BROADCAST ) */
+
+
+#define CFG_HID2 HID2_HBE
+
+/* DDR @ 0x00000000 */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI @ 0x80000000 */
+#ifdef CONFIG_PCI
+#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT1L (0)
+#define CFG_IBAT1U (0)
+#define CFG_IBAT2L (0)
+#define CFG_IBAT2U (0)
+#endif
+
+#ifdef CONFIG_MPC83XX_PCI2
+#define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT3L (0)
+#define CFG_IBAT3U (0)
+#define CFG_IBAT4L (0)
+#define CFG_IBAT4U (0)
+#endif
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
+#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT7L (0)
+#define CFG_IBAT7U (0)
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+#define CFG_DBAT4L CFG_IBAT4L
+#define CFG_DBAT4U CFG_IBAT4U
+#define CFG_DBAT5L CFG_IBAT5L
+#define CFG_DBAT5U CFG_IBAT5U
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+#define CFG_DBAT7L CFG_IBAT7L
+#define CFG_DBAT7U CFG_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR 00:a0:1e:a0:13:8d
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e
+#endif
+
+#define CONFIG_IPADDR 192.168.1.234
+
+#define CONFIG_HOSTNAME SBC8349
+#define CONFIG_ROOTPATH /tftpboot/rootfs
+#define CONFIG_BOOTFILE uImage
+
+#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK 255.255.255.0
+
+#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=sbc8349\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
+ "update=protect off fff00000 fff3ffff; " \
+ "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
+ "upd=run load;run update\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=sbc8349.dtb\0" \
+ ""
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#endif /* __CONFIG_H */
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 03dd0ca..c2a4ff5 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -10,12 +10,6 @@
* the License, or (at your option) any later version.
*/
-/*
- * mpc83xx.h
- *
- * MPC83xx specific definitions
- */
-
#ifndef __MPC83XX_H__
#define __MPC83XX_H__
@@ -24,406 +18,1005 @@
#include <asm/e300.h>
#endif
-/*
- * MPC83xx cpu provide RCR register to do reset thing specially. easier
- * to implement
+/* MPC83xx cpu provide RCR register to do reset thing specially
*/
-
#define MPC83xx_RESET
-/*
- * System reset offset (PowerPC standard)
+/* System reset offset (PowerPC standard)
*/
-#define EXC_OFF_SYS_RESET 0x0100
+#define EXC_OFF_SYS_RESET 0x0100
-/*
- * Default Internal Memory Register Space (Freescale recomandation)
+/* IMMRBAR - Internal Memory Register Base Address
*/
-#define CONFIG_DEFAULT_IMMR 0xFF400000
+#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */
+#define IMMRBAR 0x0000 /* Register offset to immr */
+#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */
+#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
-/*
- * Watchdog
+/* LAWBAR - Local Access Window Base Address Register
*/
-#define SWCRR 0x0204
-#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
-#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
-#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */
-#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
-#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
+#define LBLAWBAR0 0x0020 /* Register offset to immr */
+#define LBLAWAR0 0x0024
+#define LBLAWBAR1 0x0028
+#define LBLAWAR1 0x002C
+#define LBLAWBAR2 0x0030
+#define LBLAWAR2 0x0034
+#define LBLAWBAR3 0x0038
+#define LBLAWAR3 0x003C
+#define LAWBAR_BAR 0xFFFFF000 /* Base address mask */
+
+/* SPRIDR - System Part and Revision ID Register
+ */
+#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */
+#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */
+
+#define SPR_8349E_REV10 0x80300100
+#define SPR_8349_REV10 0x80310100
+#define SPR_8347E_REV10_TBGA 0x80320100
+#define SPR_8347_REV10_TBGA 0x80330100
+#define SPR_8347E_REV10_PBGA 0x80340100
+#define SPR_8347_REV10_PBGA 0x80350100
+#define SPR_8343E_REV10 0x80360100
+#define SPR_8343_REV10 0x80370100
+
+#define SPR_8349E_REV11 0x80300101
+#define SPR_8349_REV11 0x80310101
+#define SPR_8347E_REV11_TBGA 0x80320101
+#define SPR_8347_REV11_TBGA 0x80330101
+#define SPR_8347E_REV11_PBGA 0x80340101
+#define SPR_8347_REV11_PBGA 0x80350101
+#define SPR_8343E_REV11 0x80360101
+#define SPR_8343_REV11 0x80370101
+
+#define SPR_8349E_REV31 0x80300300
+#define SPR_8349_REV31 0x80310300
+#define SPR_8347E_REV31_TBGA 0x80320300
+#define SPR_8347_REV31_TBGA 0x80330300
+#define SPR_8347E_REV31_PBGA 0x80340300
+#define SPR_8347_REV31_PBGA 0x80350300
+#define SPR_8343E_REV31 0x80360300
+#define SPR_8343_REV31 0x80370300
+
+#define SPR_8360E_REV10 0x80480010
+#define SPR_8360_REV10 0x80490010
+#define SPR_8360E_REV11 0x80480011
+#define SPR_8360_REV11 0x80490011
+#define SPR_8360E_REV12 0x80480012
+#define SPR_8360_REV12 0x80490012
+#define SPR_8360E_REV20 0x80480020
+#define SPR_8360_REV20 0x80490020
+
+#define SPR_8323E_REV10 0x80620010
+#define SPR_8323_REV10 0x80630010
+#define SPR_8321E_REV10 0x80660010
+#define SPR_8321_REV10 0x80670010
+#define SPR_8323E_REV11 0x80620011
+#define SPR_8323_REV11 0x80630011
+#define SPR_8321E_REV11 0x80660011
+#define SPR_8321_REV11 0x80670011
+
+/* SPCR - System Priority Configuration Register
+ */
+#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */
+#define SPCR_PCIHPE_SHIFT (31-3)
+#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */
+#define SPCR_PCIPR_SHIFT (31-7)
+#define SPCR_OPT 0x00800000 /* Optimize */
+#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */
+#define SPCR_TBEN_SHIFT (31-9)
+#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */
+#define SPCR_COREPR_SHIFT (31-11)
+
+#if defined(CONFIG_MPC834X)
+/* SPCR bits - MPC8349 specific */
+#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */
+#define SPCR_TSEC1DP_SHIFT (31-19)
+#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */
+#define SPCR_TSEC1BDP_SHIFT (31-21)
+#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */
+#define SPCR_TSEC1EP_SHIFT (31-23)
+#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */
+#define SPCR_TSEC2DP_SHIFT (31-27)
+#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */
+#define SPCR_TSEC2BDP_SHIFT (31-29)
+#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */
+#define SPCR_TSEC2EP_SHIFT (31-31)
+#endif
-#define SWCNR 0x0208
-#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
-#define SWCNR_RES ~(SWCNR_SWCN)
+/* SICRL/H - System I/O Configuration Register Low/High
+ */
+#if defined(CONFIG_MPC834X)
+/* SICRL bits - MPC8349 specific */
+#define SICRL_LDP_A 0x80000000
+#define SICRL_USB1 0x40000000
+#define SICRL_USB0 0x20000000
+#define SICRL_UART 0x0C000000
+#define SICRL_GPIO1_A 0x02000000
+#define SICRL_GPIO1_B 0x01000000
+#define SICRL_GPIO1_C 0x00800000
+#define SICRL_GPIO1_D 0x00400000
+#define SICRL_GPIO1_E 0x00200000
+#define SICRL_GPIO1_F 0x00180000
+#define SICRL_GPIO1_G 0x00040000
+#define SICRL_GPIO1_H 0x00020000
+#define SICRL_GPIO1_I 0x00010000
+#define SICRL_GPIO1_J 0x00008000
+#define SICRL_GPIO1_K 0x00004000
+#define SICRL_GPIO1_L 0x00003000
+
+/* SICRH bits - MPC8349 specific */
+#define SICRH_DDR 0x80000000
+#define SICRH_TSEC1_A 0x10000000
+#define SICRH_TSEC1_B 0x08000000
+#define SICRH_TSEC1_C 0x04000000
+#define SICRH_TSEC1_D 0x02000000
+#define SICRH_TSEC1_E 0x01000000
+#define SICRH_TSEC1_F 0x00800000
+#define SICRH_TSEC2_A 0x00400000
+#define SICRH_TSEC2_B 0x00200000
+#define SICRH_TSEC2_C 0x00100000
+#define SICRH_TSEC2_D 0x00080000
+#define SICRH_TSEC2_E 0x00040000
+#define SICRH_TSEC2_F 0x00020000
+#define SICRH_TSEC2_G 0x00010000
+#define SICRH_TSEC2_H 0x00008000
+#define SICRH_GPIO2_A 0x00004000
+#define SICRH_GPIO2_B 0x00002000
+#define SICRH_GPIO2_C 0x00001000
+#define SICRH_GPIO2_D 0x00000800
+#define SICRH_GPIO2_E 0x00000400
+#define SICRH_GPIO2_F 0x00000200
+#define SICRH_GPIO2_G 0x00000180
+#define SICRH_GPIO2_H 0x00000060
+#define SICRH_TSOBI1 0x00000002
+#define SICRH_TSOBI2 0x00000001
+
+#elif defined(CONFIG_MPC8360)
+/* SICRL bits - MPC8360 specific */
+#define SICRL_LDP_A 0xC0000000
+#define SICRL_LCLK_1 0x10000000
+#define SICRL_LCLK_2 0x08000000
+#define SICRL_SRCID_A 0x03000000
+#define SICRL_IRQ_CKSTP_A 0x00C00000
+
+/* SICRH bits - MPC8360 specific */
+#define SICRH_DDR 0x80000000
+#define SICRH_SECONDARY_DDR 0x40000000
+#define SICRH_SDDROE 0x20000000
+#define SICRH_IRQ3 0x10000000
+#define SICRH_UC1EOBI 0x00000004
+#define SICRH_UC2E1OBI 0x00000002
+#define SICRH_UC2E2OBI 0x00000001
+
+#elif defined(CONFIG_MPC832X)
+/* SICRL bits - MPC832X specific */
+#define SICRL_LDP_LCS_A 0x80000000
+#define SICRL_IRQ_CKS 0x20000000
+#define SICRL_PCI_MSRC 0x10000000
+#define SICRL_URT_CTPR 0x06000000
+#define SICRL_IRQ_CTPR 0x00C00000
+#endif
-#define SWSRR 0x020E
+/* SWCRR - System Watchdog Control Register
+ */
+#define SWCRR 0x0204 /* Register offset to immr */
+#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */
+#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */
+#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */
+#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */
+#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
+
+/* SWCNR - System Watchdog Counter Register
+ */
+#define SWCNR 0x0208 /* Register offset to immr */
+#define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */
+#define SWCNR_RES ~(SWCNR_SWCN)
-/*
- * Default Internal Memory Register Space (Freescale recomandation)
+/* SWSRR - System Watchdog Service Register
*/
-#define IMMRBAR 0x0000
-#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Identifies the 12 most-significant address bits of the base of the 1 MByte internal memory window. */
-#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
+#define SWSRR 0x020E /* Register offset to immr */
-/*
- * Default Internal Memory Register Space (Freescale recomandation)
+/* ACR - Arbiter Configuration Register
*/
-#define LBLAWBAR0 0x0020
-#define LBLAWAR0 0x0024
-#define LBLAWBAR1 0x0028
-#define LBLAWAR1 0x002C
-#define LBLAWBAR2 0x0030
-#define LBLAWAR2 0x0034
-#define LBLAWBAR3 0x0038
-#define LBLAWAR3 0x003C
+#define ACR_COREDIS 0x10000000 /* Core disable */
+#define ACR_COREDIS_SHIFT (31-7)
+#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */
+#define ACR_PIPE_DEP_SHIFT (31-15)
+#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */
+#define ACR_PCI_RPTCNT_SHIFT (31-19)
+#define ACR_RPTCNT 0x00000700 /* Repeat count */
+#define ACR_RPTCNT_SHIFT (31-23)
+#define ACR_APARK 0x00000030 /* Address parking */
+#define ACR_APARK_SHIFT (31-27)
+#define ACR_PARKM 0x0000000F /* Parking master */
+#define ACR_PARKM_SHIFT (31-31)
+
+/* ATR - Arbiter Timers Register
+ */
+#define ATR_DTO 0x00FF0000 /* Data time out */
+#define ATR_ATO 0x000000FF /* Address time out */
-/*
- * The device ID and revision numbers
- */
-#define SPR_8349E_REV10 0x80300100
-#define SPR_8349_REV10 0x80310100
-#define SPR_8347E_REV10_TBGA 0x80320100
-#define SPR_8347_REV10_TBGA 0x80330100
-#define SPR_8347E_REV10_PBGA 0x80340100
-#define SPR_8347_REV10_PBGA 0x80350100
-#define SPR_8343E_REV10 0x80360100
-#define SPR_8343_REV10 0x80370100
-
-#define SPR_8349E_REV11 0x80300101
-#define SPR_8349_REV11 0x80310101
-#define SPR_8347E_REV11_TBGA 0x80320101
-#define SPR_8347_REV11_TBGA 0x80330101
-#define SPR_8347E_REV11_PBGA 0x80340101
-#define SPR_8347_REV11_PBGA 0x80350101
-#define SPR_8343E_REV11 0x80360101
-#define SPR_8343_REV11 0x80370101
-
-#define SPR_8360E_REV10 0x80480010
-#define SPR_8360_REV10 0x80490010
-#define SPR_8360E_REV11 0x80480011
-#define SPR_8360_REV11 0x80490011
-#define SPR_8360E_REV12 0x80480012
-#define SPR_8360_REV12 0x80490012
+/* AER - Arbiter Event Register
+ */
+#define AER_ETEA 0x00000020 /* Transfer error */
+#define AER_RES 0x00000010 /* Reserved transfer type */
+#define AER_ECW 0x00000008 /* External control word transfer type */
+#define AER_AO 0x00000004 /* Address Only transfer type */
+#define AER_DTO 0x00000002 /* Data time out */
+#define AER_ATO 0x00000001 /* Address time out */
+
+/* AEATR - Arbiter Event Address Register
+ */
+#define AEATR_EVENT 0x07000000 /* Event type */
+#define AEATR_MSTR_ID 0x001F0000 /* Master Id */
+#define AEATR_TBST 0x00000800 /* Transfer burst */
+#define AEATR_TSIZE 0x00000700 /* Transfer Size */
+#define AEATR_TTYPE 0x0000001F /* Transfer Type */
-/*
- * Base Registers & Option Registers
- */
-#define BR0 0x5000
-#define BR1 0x5008
-#define BR2 0x5010
-#define BR3 0x5018
-#define BR4 0x5020
-#define BR5 0x5028
-#define BR6 0x5030
-#define BR7 0x5038
-
-#define BR_BA 0xFFFF8000
-#define BR_BA_SHIFT 15
-#define BR_PS 0x00001800
-#define BR_PS_SHIFT 11
-#define BR_PS_8 0x00000800 /* Port Size 8 bit */
-#define BR_PS_16 0x00001000 /* Port Size 16 bit */
-#define BR_PS_32 0x00001800 /* Port Size 32 bit */
-#define BR_DECC 0x00000600
-#define BR_DECC_SHIFT 9
-#define BR_WP 0x00000100
-#define BR_WP_SHIFT 8
-#define BR_MSEL 0x000000E0
-#define BR_MSEL_SHIFT 5
-#define BR_MS_GPCM 0x00000000 /* GPCM */
-#define BR_MS_SDRAM 0x00000060 /* SDRAM */
-#define BR_MS_UPMA 0x00000080 /* UPMA */
-#define BR_MS_UPMB 0x000000A0 /* UPMB */
-#define BR_MS_UPMC 0x000000C0 /* UPMC */
-#if defined (CONFIG_MPC8360)
-#define BR_ATOM 0x0000000C
-#define BR_ATOM_SHIFT 2
+/* HRCWL - Hard Reset Configuration Word Low
+ */
+#define HRCWL_LBIUCM 0x80000000
+#define HRCWL_LBIUCM_SHIFT 31
+#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
+#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
+
+#define HRCWL_DDRCM 0x40000000
+#define HRCWL_DDRCM_SHIFT 30
+#define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000
+#define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000
+
+#define HRCWL_SPMF 0x0f000000
+#define HRCWL_SPMF_SHIFT 24
+#define HRCWL_CSB_TO_CLKIN_16X1 0x00000000
+#define HRCWL_CSB_TO_CLKIN_1X1 0x01000000
+#define HRCWL_CSB_TO_CLKIN_2X1 0x02000000
+#define HRCWL_CSB_TO_CLKIN_3X1 0x03000000
+#define HRCWL_CSB_TO_CLKIN_4X1 0x04000000
+#define HRCWL_CSB_TO_CLKIN_5X1 0x05000000
+#define HRCWL_CSB_TO_CLKIN_6X1 0x06000000
+#define HRCWL_CSB_TO_CLKIN_7X1 0x07000000
+#define HRCWL_CSB_TO_CLKIN_8X1 0x08000000
+#define HRCWL_CSB_TO_CLKIN_9X1 0x09000000
+#define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000
+#define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000
+#define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000
+#define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000
+#define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000
+#define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000
+
+#define HRCWL_VCO_BYPASS 0x00000000
+#define HRCWL_VCO_1X2 0x00000000
+#define HRCWL_VCO_1X4 0x00200000
+#define HRCWL_VCO_1X8 0x00400000
+
+#define HRCWL_COREPLL 0x007F0000
+#define HRCWL_COREPLL_SHIFT 16
+#define HRCWL_CORE_TO_CSB_BYPASS 0x00000000
+#define HRCWL_CORE_TO_CSB_1X1 0x00020000
+#define HRCWL_CORE_TO_CSB_1_5X1 0x00030000
+#define HRCWL_CORE_TO_CSB_2X1 0x00040000
+#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
+#define HRCWL_CORE_TO_CSB_3X1 0x00060000
+
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+#define HRCWL_CEVCOD 0x000000C0
+#define HRCWL_CEVCOD_SHIFT 6
+#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
+#define HRCWL_CE_PLL_VCO_DIV_8 0x00000040
+#define HRCWL_CE_PLL_VCO_DIV_2 0x00000080
+
+#define HRCWL_CEPDF 0x00000020
+#define HRCWL_CEPDF_SHIFT 5
+#define HRCWL_CE_PLL_DIV_1X1 0x00000000
+#define HRCWL_CE_PLL_DIV_2X1 0x00000020
+
+#define HRCWL_CEPMF 0x0000001F
+#define HRCWL_CEPMF_SHIFT 0
+#define HRCWL_CE_TO_PLL_1X16_ 0x00000000
+#define HRCWL_CE_TO_PLL_1X2 0x00000002
+#define HRCWL_CE_TO_PLL_1X3 0x00000003
+#define HRCWL_CE_TO_PLL_1X4 0x00000004
+#define HRCWL_CE_TO_PLL_1X5 0x00000005
+#define HRCWL_CE_TO_PLL_1X6 0x00000006
+#define HRCWL_CE_TO_PLL_1X7 0x00000007
+#define HRCWL_CE_TO_PLL_1X8 0x00000008
+#define HRCWL_CE_TO_PLL_1X9 0x00000009
+#define HRCWL_CE_TO_PLL_1X10 0x0000000A
+#define HRCWL_CE_TO_PLL_1X11 0x0000000B
+#define HRCWL_CE_TO_PLL_1X12 0x0000000C
+#define HRCWL_CE_TO_PLL_1X13 0x0000000D
+#define HRCWL_CE_TO_PLL_1X14 0x0000000E
+#define HRCWL_CE_TO_PLL_1X15 0x0000000F
+#define HRCWL_CE_TO_PLL_1X16 0x00000010
+#define HRCWL_CE_TO_PLL_1X17 0x00000011
+#define HRCWL_CE_TO_PLL_1X18 0x00000012
+#define HRCWL_CE_TO_PLL_1X19 0x00000013
+#define HRCWL_CE_TO_PLL_1X20 0x00000014
+#define HRCWL_CE_TO_PLL_1X21 0x00000015
+#define HRCWL_CE_TO_PLL_1X22 0x00000016
+#define HRCWL_CE_TO_PLL_1X23 0x00000017
+#define HRCWL_CE_TO_PLL_1X24 0x00000018
+#define HRCWL_CE_TO_PLL_1X25 0x00000019
+#define HRCWL_CE_TO_PLL_1X26 0x0000001A
+#define HRCWL_CE_TO_PLL_1X27 0x0000001B
+#define HRCWL_CE_TO_PLL_1X28 0x0000001C
+#define HRCWL_CE_TO_PLL_1X29 0x0000001D
+#define HRCWL_CE_TO_PLL_1X30 0x0000001E
+#define HRCWL_CE_TO_PLL_1X31 0x0000001F
#endif
-#define BR_V 0x00000001
-#define BR_V_SHIFT 0
-#if defined (CONFIG_MPC8349)
-#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
-#elif defined (CONFIG_MPC8360)
-#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_ATOM|BR_V)
+
+/* HRCWH - Hardware Reset Configuration Word High
+ */
+#define HRCWH_PCI_HOST 0x80000000
+#define HRCWH_PCI_HOST_SHIFT 31
+#define HRCWH_PCI_AGENT 0x00000000
+
+#if defined(CONFIG_MPC834X)
+#define HRCWH_32_BIT_PCI 0x00000000
+#define HRCWH_64_BIT_PCI 0x40000000
#endif
-#define OR0 0x5004
-#define OR1 0x500C
-#define OR2 0x5014
-#define OR3 0x501C
-#define OR4 0x5024
-#define OR5 0x502C
-#define OR6 0x5034
-#define OR7 0x503C
+#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000
+#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000
-#define OR_GPCM_AM 0xFFFF8000
-#define OR_GPCM_AM_SHIFT 15
-#define OR_GPCM_BCTLD 0x00001000
-#define OR_GPCM_BCTLD_SHIFT 12
-#define OR_GPCM_CSNT 0x00000800
-#define OR_GPCM_CSNT_SHIFT 11
-#define OR_GPCM_ACS 0x00000600
-#define OR_GPCM_ACS_SHIFT 9
-#define OR_GPCM_ACS_0b10 0x00000400
-#define OR_GPCM_ACS_0b11 0x00000600
-#define OR_GPCM_XACS 0x00000100
-#define OR_GPCM_XACS_SHIFT 8
-#define OR_GPCM_SCY 0x000000F0
-#define OR_GPCM_SCY_SHIFT 4
-#define OR_GPCM_SCY_1 0x00000010
-#define OR_GPCM_SCY_2 0x00000020
-#define OR_GPCM_SCY_3 0x00000030
-#define OR_GPCM_SCY_4 0x00000040
-#define OR_GPCM_SCY_5 0x00000050
-#define OR_GPCM_SCY_6 0x00000060
-#define OR_GPCM_SCY_7 0x00000070
-#define OR_GPCM_SCY_8 0x00000080
-#define OR_GPCM_SCY_9 0x00000090
-#define OR_GPCM_SCY_10 0x000000a0
-#define OR_GPCM_SCY_11 0x000000b0
-#define OR_GPCM_SCY_12 0x000000c0
-#define OR_GPCM_SCY_13 0x000000d0
-#define OR_GPCM_SCY_14 0x000000e0
-#define OR_GPCM_SCY_15 0x000000f0
-#define OR_GPCM_SETA 0x00000008
-#define OR_GPCM_SETA_SHIFT 3
-#define OR_GPCM_TRLX 0x00000004
-#define OR_GPCM_TRLX_SHIFT 2
-#define OR_GPCM_EHTR 0x00000002
-#define OR_GPCM_EHTR_SHIFT 1
-#define OR_GPCM_EAD 0x00000001
-#define OR_GPCM_EAD_SHIFT 0
-
-#define OR_UPM_AM 0xFFFF8000
-#define OR_UPM_AM_SHIFT 15
-#define OR_UPM_XAM 0x00006000
-#define OR_UPM_XAM_SHIFT 13
-#define OR_UPM_BCTLD 0x00001000
-#define OR_UPM_BCTLD_SHIFT 12
-#define OR_UPM_BI 0x00000100
-#define OR_UPM_BI_SHIFT 8
-#define OR_UPM_TRLX 0x00000004
-#define OR_UPM_TRLX_SHIFT 2
-#define OR_UPM_EHTR 0x00000002
-#define OR_UPM_EHTR_SHIFT 1
-#define OR_UPM_EAD 0x00000001
-#define OR_UPM_EAD_SHIFT 0
-
-#define OR_SDRAM_AM 0xFFFF8000
-#define OR_SDRAM_AM_SHIFT 15
-#define OR_SDRAM_XAM 0x00006000
-#define OR_SDRAM_XAM_SHIFT 13
-#define OR_SDRAM_COLS 0x00001C00
-#define OR_SDRAM_COLS_SHIFT 10
-#define OR_SDRAM_ROWS 0x000001C0
-#define OR_SDRAM_ROWS_SHIFT 6
-#define OR_SDRAM_PMSEL 0x00000020
-#define OR_SDRAM_PMSEL_SHIFT 5
-#define OR_SDRAM_EAD 0x00000001
-#define OR_SDRAM_EAD_SHIFT 0
+#define HRCWH_PCI_ARBITER_DISABLE 0x00000000
+#define HRCWH_PCI_ARBITER_ENABLE 0x20000000
-/*
- * Hard Reset Configration Word - High
- */
-#define HRCWH_PCI_AGENT 0x00000000
-#define HRCWH_PCI_HOST 0x80000000
+#if defined(CONFIG_MPC834X)
+#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
+#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
-#if defined (CONFIG_MPC8349)
-#define HRCWH_32_BIT_PCI 0x00000000
-#define HRCWH_64_BIT_PCI 0x40000000
+#elif defined(CONFIG_MPC8360)
+#define HRCWH_PCICKDRV_DISABLE 0x00000000
+#define HRCWH_PCICKDRV_ENABLE 0x10000000
#endif
-#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000
-#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000
+#define HRCWH_CORE_DISABLE 0x08000000
+#define HRCWH_CORE_ENABLE 0x00000000
+
+#define HRCWH_FROM_0X00000100 0x00000000
+#define HRCWH_FROM_0XFFF00100 0x04000000
+
+#define HRCWH_BOOTSEQ_DISABLE 0x00000000
+#define HRCWH_BOOTSEQ_NORMAL 0x01000000
+#define HRCWH_BOOTSEQ_EXTENDED 0x02000000
+
+#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000
+#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000
-#if defined (CONFIG_MPC8349)
-#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
-#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
-#elif defined (CONFIG_MPC8360)
-#define HRCWH_PCICKDRV_DISABLE 0x00000000
-#define HRCWH_PCICKDRV_ENABLE 0x10000000
+#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
+#define HRCWH_ROM_LOC_PCI1 0x00100000
+#if defined(CONFIG_MPC834X)
+#define HRCWH_ROM_LOC_PCI2 0x00200000
+#endif
+#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
+#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
+#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
+
+#if defined(CONFIG_MPC834X)
+#define HRCWH_TSEC1M_IN_RGMII 0x00000000
+#define HRCWH_TSEC1M_IN_RTBI 0x00004000
+#define HRCWH_TSEC1M_IN_GMII 0x00008000
+#define HRCWH_TSEC1M_IN_TBI 0x0000C000
+#define HRCWH_TSEC2M_IN_RGMII 0x00000000
+#define HRCWH_TSEC2M_IN_RTBI 0x00001000
+#define HRCWH_TSEC2M_IN_GMII 0x00002000
+#define HRCWH_TSEC2M_IN_TBI 0x00003000
+#endif
+
+#if defined(CONFIG_MPC8360)
+#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000
+#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010
#endif
-#define HRCWH_CORE_DISABLE 0x08000000
-#define HRCWH_CORE_ENABLE 0x00000000
+#define HRCWH_BIG_ENDIAN 0x00000000
+#define HRCWH_LITTLE_ENDIAN 0x00000008
-#define HRCWH_FROM_0X00000100 0x00000000
-#define HRCWH_FROM_0XFFF00100 0x04000000
+#define HRCWH_LALE_NORMAL 0x00000000
+#define HRCWH_LALE_EARLY 0x00000004
-#define HRCWH_BOOTSEQ_DISABLE 0x00000000
-#define HRCWH_BOOTSEQ_NORMAL 0x01000000
-#define HRCWH_BOOTSEQ_EXTENDED 0x02000000
+#define HRCWH_LDP_SET 0x00000000
+#define HRCWH_LDP_CLEAR 0x00000002
-#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000
-#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000
+/* RSR - Reset Status Register
+ */
+#define RSR_RSTSRC 0xE0000000 /* Reset source */
+#define RSR_RSTSRC_SHIFT 29
+#define RSR_BSF 0x00010000 /* Boot seq. fail */
+#define RSR_BSF_SHIFT 16
+#define RSR_SWSR 0x00002000 /* software soft reset */
+#define RSR_SWSR_SHIFT 13
+#define RSR_SWHR 0x00001000 /* software hard reset */
+#define RSR_SWHR_SHIFT 12
+#define RSR_JHRS 0x00000200 /* jtag hreset */
+#define RSR_JHRS_SHIFT 9
+#define RSR_JSRS 0x00000100 /* jtag sreset status */
+#define RSR_JSRS_SHIFT 8
+#define RSR_CSHR 0x00000010 /* checkstop reset status */
+#define RSR_CSHR_SHIFT 4
+#define RSR_SWRS 0x00000008 /* software watchdog reset status */
+#define RSR_SWRS_SHIFT 3
+#define RSR_BMRS 0x00000004 /* bus monitop reset status */
+#define RSR_BMRS_SHIFT 2
+#define RSR_SRS 0x00000002 /* soft reset status */
+#define RSR_SRS_SHIFT 1
+#define RSR_HRS 0x00000001 /* hard reset status */
+#define RSR_HRS_SHIFT 0
+#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\
+ RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
+ RSR_BMRS | RSR_SRS | RSR_HRS)
+/* RMR - Reset Mode Register
+ */
+#define RMR_CSRE 0x00000001 /* checkstop reset enable */
+#define RMR_CSRE_SHIFT 0
+#define RMR_RES ~(RMR_CSRE)
-#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
-#define HRCWH_ROM_LOC_PCI1 0x00100000
-#if defined (CONFIG_MPC8349)
-#define HRCWH_ROM_LOC_PCI2 0x00200000
+/* RCR - Reset Control Register
+ */
+#define RCR_SWHR 0x00000002 /* software hard reset */
+#define RCR_SWSR 0x00000001 /* software soft reset */
+#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
+
+/* RCER - Reset Control Enable Register
+ */
+#define RCER_CRE 0x00000001 /* software hard reset */
+#define RCER_RES ~(RCER_CRE)
+
+/* SPMR - System PLL Mode Register
+ */
+#define SPMR_LBIUCM 0x80000000
+#define SPMR_DDRCM 0x40000000
+#define SPMR_SPMF 0x0F000000
+#define SPMR_CKID 0x00800000
+#define SPMR_CKID_SHIFT 23
+#define SPMR_COREPLL 0x007F0000
+#define SPMR_CEVCOD 0x000000C0
+#define SPMR_CEPDF 0x00000020
+#define SPMR_CEPMF 0x0000001F
+
+/* OCCR - Output Clock Control Register
+ */
+#define OCCR_PCICOE0 0x80000000
+#define OCCR_PCICOE1 0x40000000
+#define OCCR_PCICOE2 0x20000000
+#define OCCR_PCICOE3 0x10000000
+#define OCCR_PCICOE4 0x08000000
+#define OCCR_PCICOE5 0x04000000
+#define OCCR_PCICOE6 0x02000000
+#define OCCR_PCICOE7 0x01000000
+#define OCCR_PCICD0 0x00800000
+#define OCCR_PCICD1 0x00400000
+#define OCCR_PCICD2 0x00200000
+#define OCCR_PCICD3 0x00100000
+#define OCCR_PCICD4 0x00080000
+#define OCCR_PCICD5 0x00040000
+#define OCCR_PCICD6 0x00020000
+#define OCCR_PCICD7 0x00010000
+#define OCCR_PCI1CR 0x00000002
+#define OCCR_PCI2CR 0x00000001
+#define OCCR_PCICR OCCR_PCI1CR
+
+/* SCCR - System Clock Control Register
+ */
+#define SCCR_ENCCM 0x03000000
+#define SCCR_ENCCM_SHIFT 24
+#define SCCR_ENCCM_0 0x00000000
+#define SCCR_ENCCM_1 0x01000000
+#define SCCR_ENCCM_2 0x02000000
+#define SCCR_ENCCM_3 0x03000000
+
+#define SCCR_PCICM 0x00010000
+#define SCCR_PCICM_SHIFT 16
+
+/* SCCR bits - MPC8349 specific */
+#ifdef CONFIG_MPC834X
+#define SCCR_TSEC1CM 0xc0000000
+#define SCCR_TSEC1CM_SHIFT 30
+#define SCCR_TSEC1CM_0 0x00000000
+#define SCCR_TSEC1CM_1 0x40000000
+#define SCCR_TSEC1CM_2 0x80000000
+#define SCCR_TSEC1CM_3 0xC0000000
+
+#define SCCR_TSEC2CM 0x30000000
+#define SCCR_TSEC2CM_SHIFT 28
+#define SCCR_TSEC2CM_0 0x00000000
+#define SCCR_TSEC2CM_1 0x10000000
+#define SCCR_TSEC2CM_2 0x20000000
+#define SCCR_TSEC2CM_3 0x30000000
#endif
-#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
-#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
-#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
-
-#if defined (CONFIG_MPC8349)
-#define HRCWH_TSEC1M_IN_RGMII 0x00000000
-#define HRCWH_TSEC1M_IN_RTBI 0x00004000
-#define HRCWH_TSEC1M_IN_GMII 0x00008000
-#define HRCWH_TSEC1M_IN_TBI 0x0000C000
-
-#define HRCWH_TSEC2M_IN_RGMII 0x00000000
-#define HRCWH_TSEC2M_IN_RTBI 0x00001000
-#define HRCWH_TSEC2M_IN_GMII 0x00002000
-#define HRCWH_TSEC2M_IN_TBI 0x00003000
+
+#define SCCR_USBMPHCM 0x00c00000
+#define SCCR_USBMPHCM_SHIFT 22
+#define SCCR_USBDRCM 0x00300000
+#define SCCR_USBDRCM_SHIFT 20
+
+#define SCCR_USBCM_0 0x00000000
+#define SCCR_USBCM_1 0x00500000
+#define SCCR_USBCM_2 0x00A00000
+#define SCCR_USBCM_3 0x00F00000
+
+/* CSn_BDNS - Chip Select memory Bounds Register
+ */
+#define CSBNDS_SA 0x00FF0000
+#define CSBNDS_SA_SHIFT 8
+#define CSBNDS_EA 0x000000FF
+#define CSBNDS_EA_SHIFT 24
+
+/* CSn_CONFIG - Chip Select Configuration Register
+ */
+#define CSCONFIG_EN 0x80000000
+#define CSCONFIG_AP 0x00800000
+#define CSCONFIG_ROW_BIT 0x00000700
+#define CSCONFIG_ROW_BIT_12 0x00000000
+#define CSCONFIG_ROW_BIT_13 0x00000100
+#define CSCONFIG_ROW_BIT_14 0x00000200
+#define CSCONFIG_COL_BIT 0x00000007
+#define CSCONFIG_COL_BIT_8 0x00000000
+#define CSCONFIG_COL_BIT_9 0x00000001
+#define CSCONFIG_COL_BIT_10 0x00000002
+#define CSCONFIG_COL_BIT_11 0x00000003
+
+/* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
+ */
+#define TIMING_CFG1_PRETOACT 0x70000000
+#define TIMING_CFG1_PRETOACT_SHIFT 28
+#define TIMING_CFG1_ACTTOPRE 0x0F000000
+#define TIMING_CFG1_ACTTOPRE_SHIFT 24
+#define TIMING_CFG1_ACTTORW 0x00700000
+#define TIMING_CFG1_ACTTORW_SHIFT 20
+#define TIMING_CFG1_CASLAT 0x00070000
+#define TIMING_CFG1_CASLAT_SHIFT 16
+#define TIMING_CFG1_REFREC 0x0000F000
+#define TIMING_CFG1_REFREC_SHIFT 12
+#define TIMING_CFG1_WRREC 0x00000700
+#define TIMING_CFG1_WRREC_SHIFT 8
+#define TIMING_CFG1_ACTTOACT 0x00000070
+#define TIMING_CFG1_ACTTOACT_SHIFT 4
+#define TIMING_CFG1_WRTORD 0x00000007
+#define TIMING_CFG1_WRTORD_SHIFT 0
+#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
+#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
+
+/* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
+ */
+#define TIMING_CFG2_CPO 0x0F800000
+#define TIMING_CFG2_CPO_SHIFT 23
+#define TIMING_CFG2_ACSM 0x00080000
+#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
+#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
+#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */
+
+/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
+ */
+#define SDRAM_CFG_MEM_EN 0x80000000
+#define SDRAM_CFG_SREN 0x40000000
+#define SDRAM_CFG_ECC_EN 0x20000000
+#define SDRAM_CFG_RD_EN 0x10000000
+#define SDRAM_CFG_SDRAM_TYPE 0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
+#define SDRAM_CFG_DYN_PWR 0x00200000
+#define SDRAM_CFG_32_BE 0x00080000
+#define SDRAM_CFG_8_BE 0x00040000
+#define SDRAM_CFG_NCAP 0x00020000
+#define SDRAM_CFG_2T_EN 0x00008000
+#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
+
+/* DDR_SDRAM_MODE - DDR SDRAM Mode Register
+ */
+#define SDRAM_MODE_ESD 0xFFFF0000
+#define SDRAM_MODE_ESD_SHIFT 16
+#define SDRAM_MODE_SD 0x0000FFFF
+#define SDRAM_MODE_SD_SHIFT 0
+#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */
+#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */
+#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
+#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */
+#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */
+#define DDR_MODE_WEAK 0x0002 /* weak drivers */
+#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */
+#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */
+#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
+#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
+#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
+#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
+#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */
+#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */
+#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
+#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
+#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */
+#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */
+#define DDR_MODE_MODEREG 0x0000 /* select mode register */
+
+/* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
+ */
+#define SDRAM_INTERVAL_REFINT 0x3FFF0000
+#define SDRAM_INTERVAL_REFINT_SHIFT 16
+#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
+#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
+
+/* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
+ */
+#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000
+
+/* ECC_ERR_INJECT - Memory data path error injection mask ECC
+ */
+#define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */
+#define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */
+#define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */
+#define ECC_ERR_INJECT_EEIM_SHIFT 0
+
+/* CAPTURE_ECC - Memory data path read capture ECC
+ */
+#define CAPTURE_ECC_ECE (0xff000000>>24)
+#define CAPTURE_ECC_ECE_SHIFT 0
+
+/* ERR_DETECT - Memory error detect
+ */
+#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */
+#define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */
+#define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */
+#define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */
+
+/* ERR_DISABLE - Memory error disable
+ */
+#define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */
+#define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */
+#define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */
+#define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\
+ ECC_ERROR_DISABLE_MBED)
+/* ERR_INT_EN - Memory error interrupt enable
+ */
+#define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */
+#define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */
+#define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */
+#define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\
+ ECC_ERR_INT_EN_MSEE)
+/* CAPTURE_ATTRIBUTES - Memory error attributes capture
+ */
+#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */
+#define ECC_CAPT_ATTR_BNUM_SHIFT 28
+#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */
+#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0
+#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1
+#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2
+#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3
+#define ECC_CAPT_ATTR_TSIZ_SHIFT 24
+#define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */
+#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
+#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
+#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4
+#define ECC_CAPT_ATTR_TSRC_TSEC2 0x5
+#define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07)
+#define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8
+#define ECC_CAPT_ATTR_TSRC_I2C 0x9
+#define ECC_CAPT_ATTR_TSRC_JTAG 0xA
+#define ECC_CAPT_ATTR_TSRC_PCI1 0xD
+#define ECC_CAPT_ATTR_TSRC_PCI2 0xE
+#define ECC_CAPT_ATTR_TSRC_DMA 0xF
+#define ECC_CAPT_ATTR_TSRC_SHIFT 16
+#define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */
+#define ECC_CAPT_ATTR_TTYP_WRITE 0x1
+#define ECC_CAPT_ATTR_TTYP_READ 0x2
+#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3
+#define ECC_CAPT_ATTR_TTYP_SHIFT 12
+#define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */
+
+/* ERR_SBE - Single bit ECC memory error management
+ */
+#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */
+#define ECC_ERROR_MAN_SBET_SHIFT 16
+#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */
+#define ECC_ERROR_MAN_SBEC_SHIFT 0
+
+/* BR - Base Registers
+ */
+#define BR0 0x5000 /* Register offset to immr */
+#define BR1 0x5008
+#define BR2 0x5010
+#define BR3 0x5018
+#define BR4 0x5020
+#define BR5 0x5028
+#define BR6 0x5030
+#define BR7 0x5038
+
+#define BR_BA 0xFFFF8000
+#define BR_BA_SHIFT 15
+#define BR_PS 0x00001800
+#define BR_PS_SHIFT 11
+#define BR_PS_8 0x00000800 /* Port Size 8 bit */
+#define BR_PS_16 0x00001000 /* Port Size 16 bit */
+#define BR_PS_32 0x00001800 /* Port Size 32 bit */
+#define BR_DECC 0x00000600
+#define BR_DECC_SHIFT 9
+#define BR_WP 0x00000100
+#define BR_WP_SHIFT 8
+#define BR_MSEL 0x000000E0
+#define BR_MSEL_SHIFT 5
+#define BR_MS_GPCM 0x00000000 /* GPCM */
+#define BR_MS_SDRAM 0x00000060 /* SDRAM */
+#define BR_MS_UPMA 0x00000080 /* UPMA */
+#define BR_MS_UPMB 0x000000A0 /* UPMB */
+#define BR_MS_UPMC 0x000000C0 /* UPMC */
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+#define BR_ATOM 0x0000000C
+#define BR_ATOM_SHIFT 2
#endif
+#define BR_V 0x00000001
+#define BR_V_SHIFT 0
-#if defined (CONFIG_MPC8360)
-#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000
-#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010
+#if defined(CONFIG_MPC834X)
+#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
+#elif defined(CONFIG_MPC8360)
+#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
#endif
-#define HRCWH_BIG_ENDIAN 0x00000000
-#define HRCWH_LITTLE_ENDIAN 0x00000008
+/* OR - Option Registers
+ */
+#define OR0 0x5004 /* Register offset to immr */
+#define OR1 0x500C
+#define OR2 0x5014
+#define OR3 0x501C
+#define OR4 0x5024
+#define OR5 0x502C
+#define OR6 0x5034
+#define OR7 0x503C
+
+#define OR_GPCM_AM 0xFFFF8000
+#define OR_GPCM_AM_SHIFT 15
+#define OR_GPCM_BCTLD 0x00001000
+#define OR_GPCM_BCTLD_SHIFT 12
+#define OR_GPCM_CSNT 0x00000800
+#define OR_GPCM_CSNT_SHIFT 11
+#define OR_GPCM_ACS 0x00000600
+#define OR_GPCM_ACS_SHIFT 9
+#define OR_GPCM_ACS_0b10 0x00000400
+#define OR_GPCM_ACS_0b11 0x00000600
+#define OR_GPCM_XACS 0x00000100
+#define OR_GPCM_XACS_SHIFT 8
+#define OR_GPCM_SCY 0x000000F0
+#define OR_GPCM_SCY_SHIFT 4
+#define OR_GPCM_SCY_1 0x00000010
+#define OR_GPCM_SCY_2 0x00000020
+#define OR_GPCM_SCY_3 0x00000030
+#define OR_GPCM_SCY_4 0x00000040
+#define OR_GPCM_SCY_5 0x00000050
+#define OR_GPCM_SCY_6 0x00000060
+#define OR_GPCM_SCY_7 0x00000070
+#define OR_GPCM_SCY_8 0x00000080
+#define OR_GPCM_SCY_9 0x00000090
+#define OR_GPCM_SCY_10 0x000000a0
+#define OR_GPCM_SCY_11 0x000000b0
+#define OR_GPCM_SCY_12 0x000000c0
+#define OR_GPCM_SCY_13 0x000000d0
+#define OR_GPCM_SCY_14 0x000000e0
+#define OR_GPCM_SCY_15 0x000000f0
+#define OR_GPCM_SETA 0x00000008
+#define OR_GPCM_SETA_SHIFT 3
+#define OR_GPCM_TRLX 0x00000004
+#define OR_GPCM_TRLX_SHIFT 2
+#define OR_GPCM_EHTR 0x00000002
+#define OR_GPCM_EHTR_SHIFT 1
+#define OR_GPCM_EAD 0x00000001
+#define OR_GPCM_EAD_SHIFT 0
+
+#define OR_UPM_AM 0xFFFF8000
+#define OR_UPM_AM_SHIFT 15
+#define OR_UPM_XAM 0x00006000
+#define OR_UPM_XAM_SHIFT 13
+#define OR_UPM_BCTLD 0x00001000
+#define OR_UPM_BCTLD_SHIFT 12
+#define OR_UPM_BI 0x00000100
+#define OR_UPM_BI_SHIFT 8
+#define OR_UPM_TRLX 0x00000004
+#define OR_UPM_TRLX_SHIFT 2
+#define OR_UPM_EHTR 0x00000002
+#define OR_UPM_EHTR_SHIFT 1
+#define OR_UPM_EAD 0x00000001
+#define OR_UPM_EAD_SHIFT 0
+
+#define OR_SDRAM_AM 0xFFFF8000
+#define OR_SDRAM_AM_SHIFT 15
+#define OR_SDRAM_XAM 0x00006000
+#define OR_SDRAM_XAM_SHIFT 13
+#define OR_SDRAM_COLS 0x00001C00
+#define OR_SDRAM_COLS_SHIFT 10
+#define OR_SDRAM_ROWS 0x000001C0
+#define OR_SDRAM_ROWS_SHIFT 6
+#define OR_SDRAM_PMSEL 0x00000020
+#define OR_SDRAM_PMSEL_SHIFT 5
+#define OR_SDRAM_EAD 0x00000001
+#define OR_SDRAM_EAD_SHIFT 0
+
+#define OR_AM_32KB 0xFFFF8000
+#define OR_AM_64KB 0xFFFF0000
+#define OR_AM_128KB 0xFFFE0000
+#define OR_AM_256KB 0xFFFC0000
+#define OR_AM_512KB 0xFFF80000
+#define OR_AM_1MB 0xFFF00000
+#define OR_AM_2MB 0xFFE00000
+#define OR_AM_4MB 0xFFC00000
+#define OR_AM_8MB 0xFF800000
+#define OR_AM_16MB 0xFF000000
+#define OR_AM_32MB 0xFE000000
+#define OR_AM_64MB 0xFC000000
+#define OR_AM_128MB 0xF8000000
+#define OR_AM_256MB 0xF0000000
+#define OR_AM_512MB 0xE0000000
+#define OR_AM_1GB 0xC0000000
+#define OR_AM_2GB 0x80000000
+#define OR_AM_4GB 0x00000000
+
+#define LBLAWAR_EN 0x80000000
+#define LBLAWAR_4KB 0x0000000B
+#define LBLAWAR_8KB 0x0000000C
+#define LBLAWAR_16KB 0x0000000D
+#define LBLAWAR_32KB 0x0000000E
+#define LBLAWAR_64KB 0x0000000F
+#define LBLAWAR_128KB 0x00000010
+#define LBLAWAR_256KB 0x00000011
+#define LBLAWAR_512KB 0x00000012
+#define LBLAWAR_1MB 0x00000013
+#define LBLAWAR_2MB 0x00000014
+#define LBLAWAR_4MB 0x00000015
+#define LBLAWAR_8MB 0x00000016
+#define LBLAWAR_16MB 0x00000017
+#define LBLAWAR_32MB 0x00000018
+#define LBLAWAR_64MB 0x00000019
+#define LBLAWAR_128MB 0x0000001A
+#define LBLAWAR_256MB 0x0000001B
+#define LBLAWAR_512MB 0x0000001C
+#define LBLAWAR_1GB 0x0000001D
+#define LBLAWAR_2GB 0x0000001E
+
+/* LBCR - Local Bus Configuration Register
+ */
+#define LBCR_LDIS 0x80000000
+#define LBCR_LDIS_SHIFT 31
+#define LBCR_BCTLC 0x00C00000
+#define LBCR_BCTLC_SHIFT 22
+#define LBCR_LPBSE 0x00020000
+#define LBCR_LPBSE_SHIFT 17
+#define LBCR_EPAR 0x00010000
+#define LBCR_EPAR_SHIFT 16
+#define LBCR_BMT 0x0000FF00
+#define LBCR_BMT_SHIFT 8
+
+/* LCRR - Clock Ratio Register
+ */
+#define LCRR_DBYP 0x80000000
+#define LCRR_DBYP_SHIFT 31
+#define LCRR_BUFCMDC 0x30000000
+#define LCRR_BUFCMDC_SHIFT 28
+#define LCRR_BUFCMDC_1 0x10000000
+#define LCRR_BUFCMDC_2 0x20000000
+#define LCRR_BUFCMDC_3 0x30000000
+#define LCRR_BUFCMDC_4 0x00000000
+#define LCRR_ECL 0x03000000
+#define LCRR_ECL_SHIFT 24
+#define LCRR_ECL_4 0x00000000
+#define LCRR_ECL_5 0x01000000
+#define LCRR_ECL_6 0x02000000
+#define LCRR_ECL_7 0x03000000
+#define LCRR_EADC 0x00030000
+#define LCRR_EADC_SHIFT 16
+#define LCRR_EADC_1 0x00010000
+#define LCRR_EADC_2 0x00020000
+#define LCRR_EADC_3 0x00030000
+#define LCRR_EADC_4 0x00000000
+#define LCRR_CLKDIV 0x0000000F
+#define LCRR_CLKDIV_SHIFT 0
+#define LCRR_CLKDIV_2 0x00000002
+#define LCRR_CLKDIV_4 0x00000004
+#define LCRR_CLKDIV_8 0x00000008
+
+/* DMAMR - DMA Mode Register
+ */
+#define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */
+#define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */
+#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */
+#define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */
+
+/* DMASR - DMA Status Register
+ */
+#define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */
+#define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */
-#define HRCWH_LALE_NORMAL 0x00000000
-#define HRCWH_LALE_EARLY 0x00000004
+/* CONFIG_ADDRESS - PCI Config Address Register
+ */
+#define PCI_CONFIG_ADDRESS_EN 0x80000000
+#define PCI_CONFIG_ADDRESS_BN_SHIFT 16
+#define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000
+#define PCI_CONFIG_ADDRESS_DN_SHIFT 11
+#define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800
+#define PCI_CONFIG_ADDRESS_FN_SHIFT 8
+#define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700
+#define PCI_CONFIG_ADDRESS_RN_SHIFT 0
+#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc
+
+/* POTAR - PCI Outbound Translation Address Register
+ */
+#define POTAR_TA_MASK 0x000fffff
-#define HRCWH_LDP_SET 0x00000000
-#define HRCWH_LDP_CLEAR 0x00000002
+/* POBAR - PCI Outbound Base Address Register
+ */
+#define POBAR_BA_MASK 0x000fffff
-/*
- * Hard Reset Configration Word - Low
- */
-#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
-#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
-
-#define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000
-#define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000
-
-#define HRCWL_CSB_TO_CLKIN_16X1 0x00000000
-#define HRCWL_CSB_TO_CLKIN_1X1 0x01000000
-#define HRCWL_CSB_TO_CLKIN_2X1 0x02000000
-#define HRCWL_CSB_TO_CLKIN_3X1 0x03000000
-#define HRCWL_CSB_TO_CLKIN_4X1 0x04000000
-#define HRCWL_CSB_TO_CLKIN_5X1 0x05000000
-#define HRCWL_CSB_TO_CLKIN_6X1 0x06000000
-#define HRCWL_CSB_TO_CLKIN_7X1 0x07000000
-#define HRCWL_CSB_TO_CLKIN_8X1 0x08000000
-#define HRCWL_CSB_TO_CLKIN_9X1 0x09000000
-#define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000
-#define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000
-#define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000
-#define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000
-#define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000
-#define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000
-
-#define HRCWL_VCO_BYPASS 0x00000000
-#define HRCWL_VCO_1X2 0x00000000
-#define HRCWL_VCO_1X4 0x00200000
-#define HRCWL_VCO_1X8 0x00400000
-
-#define HRCWL_CORE_TO_CSB_BYPASS 0x00000000
-#define HRCWL_CORE_TO_CSB_1X1 0x00020000
-#define HRCWL_CORE_TO_CSB_1_5X1 0x00030000
-#define HRCWL_CORE_TO_CSB_2X1 0x00040000
-#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
-#define HRCWL_CORE_TO_CSB_3X1 0x00060000
-
-#if defined (CONFIG_MPC8360)
-#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
-#define HRCWL_CE_PLL_VCO_DIV_8 0x00000040
-#define HRCWL_CE_PLL_VCO_DIV_2 0x00000080
-
-#define HRCWL_CE_PLL_DIV_1X1 0x00000000
-#define HRCWL_CE_PLL_DIV_2X1 0x00000020
-
-#define HRCWL_CE_TO_PLL_1X16_ 0x00000000
-#define HRCWL_CE_TO_PLL_1X2 0x00000002
-#define HRCWL_CE_TO_PLL_1X3 0x00000003
-#define HRCWL_CE_TO_PLL_1X4 0x00000004
-#define HRCWL_CE_TO_PLL_1X5 0x00000005
-#define HRCWL_CE_TO_PLL_1X6 0x00000006
-#define HRCWL_CE_TO_PLL_1X7 0x00000007
-#define HRCWL_CE_TO_PLL_1X8 0x00000008
-#define HRCWL_CE_TO_PLL_1X9 0x00000009
-#define HRCWL_CE_TO_PLL_1X10 0x0000000A
-#define HRCWL_CE_TO_PLL_1X11 0x0000000B
-#define HRCWL_CE_TO_PLL_1X12 0x0000000C
-#define HRCWL_CE_TO_PLL_1X13 0x0000000D
-#define HRCWL_CE_TO_PLL_1X14 0x0000000E
-#define HRCWL_CE_TO_PLL_1X15 0x0000000F
-#define HRCWL_CE_TO_PLL_1X16 0x00000010
-#define HRCWL_CE_TO_PLL_1X17 0x00000011
-#define HRCWL_CE_TO_PLL_1X18 0x00000012
-#define HRCWL_CE_TO_PLL_1X19 0x00000013
-#define HRCWL_CE_TO_PLL_1X20 0x00000014
-#define HRCWL_CE_TO_PLL_1X21 0x00000015
-#define HRCWL_CE_TO_PLL_1X22 0x00000016
-#define HRCWL_CE_TO_PLL_1X23 0x00000017
-#define HRCWL_CE_TO_PLL_1X24 0x00000018
-#define HRCWL_CE_TO_PLL_1X25 0x00000019
-#define HRCWL_CE_TO_PLL_1X26 0x0000001A
-#define HRCWL_CE_TO_PLL_1X27 0x0000001B
-#define HRCWL_CE_TO_PLL_1X28 0x0000001C
-#define HRCWL_CE_TO_PLL_1X29 0x0000001D
-#define HRCWL_CE_TO_PLL_1X30 0x0000001E
-#define HRCWL_CE_TO_PLL_1X31 0x0000001F
-#endif
+/* POCMR - PCI Outbound Comparision Mask Register
+ */
+#define POCMR_EN 0x80000000
+#define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */
+#define POCMR_SE 0x20000000 /* streaming enable */
+#define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */
+#define POCMR_CM_MASK 0x000fffff
+#define POCMR_CM_4G 0x00000000
+#define POCMR_CM_2G 0x00080000
+#define POCMR_CM_1G 0x000C0000
+#define POCMR_CM_512M 0x000E0000
+#define POCMR_CM_256M 0x000F0000
+#define POCMR_CM_128M 0x000F8000
+#define POCMR_CM_64M 0x000FC000
+#define POCMR_CM_32M 0x000FE000
+#define POCMR_CM_16M 0x000FF000
+#define POCMR_CM_8M 0x000FF800
+#define POCMR_CM_4M 0x000FFC00
+#define POCMR_CM_2M 0x000FFE00
+#define POCMR_CM_1M 0x000FFF00
+#define POCMR_CM_512K 0x000FFF80
+#define POCMR_CM_256K 0x000FFFC0
+#define POCMR_CM_128K 0x000FFFE0
+#define POCMR_CM_64K 0x000FFFF0
+#define POCMR_CM_32K 0x000FFFF8
+#define POCMR_CM_16K 0x000FFFFC
+#define POCMR_CM_8K 0x000FFFFE
+#define POCMR_CM_4K 0x000FFFFF
+
+/* PITAR - PCI Inbound Translation Address Register
+ */
+#define PITAR_TA_MASK 0x000fffff
-/*
- * LCRR - Clock Ratio Register (10.3.1.16)
- */
-#define LCRR_DBYP 0x80000000
-#define LCRR_DBYP_SHIFT 31
-#define LCRR_BUFCMDC 0x30000000
-#define LCRR_BUFCMDC_1 0x10000000
-#define LCRR_BUFCMDC_2 0x20000000
-#define LCRR_BUFCMDC_3 0x30000000
-#define LCRR_BUFCMDC_4 0x00000000
-#define LCRR_BUFCMDC_SHIFT 28
-#define LCRR_ECL 0x03000000
-#define LCRR_ECL_4 0x00000000
-#define LCRR_ECL_5 0x01000000
-#define LCRR_ECL_6 0x02000000
-#define LCRR_ECL_7 0x03000000
-#define LCRR_ECL_SHIFT 24
-#define LCRR_EADC 0x00030000
-#define LCRR_EADC_1 0x00010000
-#define LCRR_EADC_2 0x00020000
-#define LCRR_EADC_3 0x00030000
-#define LCRR_EADC_4 0x00000000
-#define LCRR_EADC_SHIFT 16
-#define LCRR_CLKDIV 0x0000000F
-#define LCRR_CLKDIV_2 0x00000002
-#define LCRR_CLKDIV_4 0x00000004
-#define LCRR_CLKDIV_8 0x00000008
-#define LCRR_CLKDIV_SHIFT 0
+/* PIBAR - PCI Inbound Base/Extended Address Register
+ */
+#define PIBAR_MASK 0xffffffff
+#define PIEBAR_EBA_MASK 0x000fffff
-/*
- * SCCR-System Clock Control Register
- */
-#define SCCR_TSEC1CM_0 0x00000000
-#define SCCR_TSEC1CM_1 0x40000000
-#define SCCR_TSEC1CM_2 0x80000000
-#define SCCR_TSEC1CM_3 0xC0000000
-#define SCCR_TSEC2CM_0 0x00000000
-#define SCCR_TSEC2CM_1 0x10000000
-#define SCCR_TSEC2CM_2 0x20000000
-#define SCCR_TSEC2CM_3 0x30000000
-#define SCCR_ENCCM_0 0x00000000
-#define SCCR_ENCCM_1 0x01000000
-#define SCCR_ENCCM_2 0x02000000
-#define SCCR_ENCCM_3 0x03000000
-#define SCCR_USBCM_0 0x00000000
-#define SCCR_USBCM_1 0x00500000
-#define SCCR_USBCM_2 0x00A00000
-#define SCCR_USBCM_3 0x00F00000
-
-#define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \
- | SCCR_TSEC2CM_3 \
- | SCCR_ENCCM_3 \
- | SCCR_USBCM_3 )
-
-#define SCCR_DEFAULT 0xFFFFFFFF
+/* PIWAR - PCI Inbound Windows Attributes Register
+ */
+#define PIWAR_EN 0x80000000
+#define PIWAR_PF 0x20000000
+#define PIWAR_RTT_MASK 0x000f0000
+#define PIWAR_RTT_NO_SNOOP 0x00040000
+#define PIWAR_RTT_SNOOP 0x00050000
+#define PIWAR_WTT_MASK 0x0000f000
+#define PIWAR_WTT_NO_SNOOP 0x00004000
+#define PIWAR_WTT_SNOOP 0x00005000
+#define PIWAR_IWS_MASK 0x0000003F
+#define PIWAR_IWS_4K 0x0000000B
+#define PIWAR_IWS_8K 0x0000000C
+#define PIWAR_IWS_16K 0x0000000D
+#define PIWAR_IWS_32K 0x0000000E
+#define PIWAR_IWS_64K 0x0000000F
+#define PIWAR_IWS_128K 0x00000010
+#define PIWAR_IWS_256K 0x00000011
+#define PIWAR_IWS_512K 0x00000012
+#define PIWAR_IWS_1M 0x00000013
+#define PIWAR_IWS_2M 0x00000014
+#define PIWAR_IWS_4M 0x00000015
+#define PIWAR_IWS_8M 0x00000016
+#define PIWAR_IWS_16M 0x00000017
+#define PIWAR_IWS_32M 0x00000018
+#define PIWAR_IWS_64M 0x00000019
+#define PIWAR_IWS_128M 0x0000001A
+#define PIWAR_IWS_256M 0x0000001B
+#define PIWAR_IWS_512M 0x0000001C
+#define PIWAR_IWS_1G 0x0000001D
+#define PIWAR_IWS_2G 0x0000001E
#endif /* __MPC83XX_H__ */