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authorYork Sun <yorksun@freescale.com>2014-03-27 17:54:47 -0700
committerYork Sun <yorksun@freescale.com>2014-04-22 17:58:48 -0700
commit34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85 (patch)
treef155ebdbac95a5ef637e7796ad22935029a56ce6 /include
parent8d451a7129ee6820cc126c77f0f0a175a2cb2e8d (diff)
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driver/ddr/fsl: Add DDR4 support to Freescale DDR driver
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/common_timing_params.h23
-rw-r--r--include/ddr_spd.h226
-rw-r--r--include/fsl_ddr.h7
-rw-r--r--include/fsl_ddr_dimm_params.h77
-rw-r--r--include/fsl_ddr_sdram.h63
-rw-r--r--include/fsl_ddrc_version.h18
-rw-r--r--include/fsl_immap.h35
7 files changed, 402 insertions, 47 deletions
diff --git a/include/common_timing_params.h b/include/common_timing_params.h
index 76338d4..821de21 100644
--- a/include/common_timing_params.h
+++ b/include/common_timing_params.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -14,32 +14,45 @@ typedef struct {
unsigned int tckmin_x_ps;
unsigned int tckmax_ps;
- unsigned int tckmax_max_ps;
unsigned int trcd_ps;
unsigned int trp_ps;
unsigned int tras_ps;
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
+ unsigned int taamin_ps;
+#endif
- unsigned int twr_ps; /* maximum = 63750 ps */
+#ifdef CONFIG_SYS_FSL_DDR4
+ unsigned int trfc1_ps;
+ unsigned int trfc2_ps;
+ unsigned int trfc4_ps;
+ unsigned int trrds_ps;
+ unsigned int trrdl_ps;
+ unsigned int tccdl_ps;
+#else
unsigned int twtr_ps; /* maximum = 63750 ps */
unsigned int trfc_ps; /* maximum = 255 ns + 256 ns + .75 ns
= 511750 ps */
unsigned int trrd_ps; /* maximum = 63750 ps */
+ unsigned int trtp_ps; /* byte 38, spd->trtp */
+#endif
+ unsigned int twr_ps; /* maximum = 63750 ps */
unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
unsigned int refresh_rate_ps;
unsigned int extended_op_srt;
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
unsigned int tis_ps; /* byte 32, spd->ca_setup */
unsigned int tih_ps; /* byte 33, spd->ca_hold */
unsigned int tds_ps; /* byte 34, spd->data_setup */
unsigned int tdh_ps; /* byte 35, spd->data_hold */
- unsigned int trtp_ps; /* byte 38, spd->trtp */
unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */
unsigned int tqhs_ps; /* byte 45, spd->tqhs */
+#endif
unsigned int ndimms_present;
- unsigned int lowest_common_SPD_caslat;
+ unsigned int lowest_common_spd_caslat;
unsigned int highest_common_derated_caslat;
unsigned int additive_latency;
unsigned int all_dimms_burst_lengths_bitmask;
diff --git a/include/ddr_spd.h b/include/ddr_spd.h
index 15a3e8d..cf2aac6 100644
--- a/include/ddr_spd.h
+++ b/include/ddr_spd.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -290,11 +290,220 @@ typedef struct ddr3_spd_eeprom_s {
} ddr3_spd_eeprom_t;
+/* From JEEC Standard No. 21-C release 23A */
+struct ddr4_spd_eeprom_s {
+ /* General Section: Bytes 0-127 */
+ uint8_t info_size_crc; /* 0 # bytes */
+ uint8_t spd_rev; /* 1 Total # bytes of SPD */
+ uint8_t mem_type; /* 2 Key Byte / mem type */
+ uint8_t module_type; /* 3 Key Byte / Module Type */
+ uint8_t density_banks; /* 4 Density and Banks */
+ uint8_t addressing; /* 5 Addressing */
+ uint8_t package_type; /* 6 Package type */
+ uint8_t opt_feature; /* 7 Optional features */
+ uint8_t thermal_ref; /* 8 Thermal and refresh */
+ uint8_t oth_opt_features; /* 9 Other optional features */
+ uint8_t res_10; /* 10 Reserved */
+ uint8_t module_vdd; /* 11 Module nominal voltage */
+ uint8_t organization; /* 12 Module Organization */
+ uint8_t bus_width; /* 13 Module Memory Bus Width */
+ uint8_t therm_sensor; /* 14 Module Thermal Sensor */
+ uint8_t ext_type; /* 15 Extended module type */
+ uint8_t res_16;
+ uint8_t timebases; /* 17 MTb and FTB */
+ uint8_t tck_min; /* 18 tCKAVGmin */
+ uint8_t tck_max; /* 19 TCKAVGmax */
+ uint8_t caslat_b1; /* 20 CAS latencies, 1st byte */
+ uint8_t caslat_b2; /* 21 CAS latencies, 2nd byte */
+ uint8_t caslat_b3; /* 22 CAS latencies, 3rd byte */
+ uint8_t caslat_b4; /* 23 CAS latencies, 4th byte */
+ uint8_t taa_min; /* 24 Min CAS Latency Time */
+ uint8_t trcd_min; /* 25 Min RAS# to CAS# Delay Time */
+ uint8_t trp_min; /* 26 Min Row Precharge Delay Time */
+ uint8_t tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */
+ uint8_t tras_min_lsb; /* 28 tRASmin, lsb */
+ uint8_t trc_min_lsb; /* 29 tRCmin, lsb */
+ uint8_t trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */
+ uint8_t trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */
+ uint8_t trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */
+ uint8_t trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */
+ uint8_t trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */
+ uint8_t trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */
+ uint8_t tfaw_msb; /* 36 Upper Nibble for tFAW */
+ uint8_t tfaw_min; /* 37 tFAW, lsb */
+ uint8_t trrds_min; /* 38 tRRD_Smin, MTB */
+ uint8_t trrdl_min; /* 39 tRRD_Lmin, MTB */
+ uint8_t tccdl_min; /* 40 tCCS_Lmin, MTB */
+ uint8_t res_41[60-41]; /* 41 Rserved */
+ uint8_t mapping[78-60]; /* 60~77 Connector to SDRAM bit map */
+ uint8_t res_78[117-78]; /* 78~116, Reserved */
+ int8_t fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */
+ int8_t fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */
+ int8_t fine_trrds_min; /* 119 Fine offset for tRRD_Smin */
+ int8_t fine_trc_min; /* 120 Fine offset for tRCmin */
+ int8_t fine_trp_min; /* 121 Fine offset for tRPmin */
+ int8_t fine_trcd_min; /* 122 Fine offset for tRCDmin */
+ int8_t fine_taa_min; /* 123 Fine offset for tAAmin */
+ int8_t fine_tck_max; /* 124 Fine offset for tCKAVGmax */
+ int8_t fine_tck_min; /* 125 Fine offset for tCKAVGmin */
+ /* CRC: Bytes 126-127 */
+ uint8_t crc[2]; /* 126-127 SPD CRC */
+
+ /* Module-Specific Section: Bytes 128-255 */
+ union {
+ struct {
+ /* 128 (Unbuffered) Module Nominal Height */
+ uint8_t mod_height;
+ /* 129 (Unbuffered) Module Maximum Thickness */
+ uint8_t mod_thickness;
+ /* 130 (Unbuffered) Reference Raw Card Used */
+ uint8_t ref_raw_card;
+ /* 131 (Unbuffered) Address Mapping from
+ Edge Connector to DRAM */
+ uint8_t addr_mapping;
+ /* 132~253 (Unbuffered) Reserved */
+ uint8_t res_132[254-132];
+ /* 254~255 CRC */
+ uint8_t crc[2];
+ } unbuffered;
+ struct {
+ /* 128 (Registered) Module Nominal Height */
+ uint8_t mod_height;
+ /* 129 (Registered) Module Maximum Thickness */
+ uint8_t mod_thickness;
+ /* 130 (Registered) Reference Raw Card Used */
+ uint8_t ref_raw_card;
+ /* 131 DIMM Module Attributes */
+ uint8_t modu_attr;
+ /* 132 RDIMM Thermal Heat Spreader Solution */
+ uint8_t thermal;
+ /* 133 Register Manufacturer ID Code, LSB */
+ uint8_t reg_id_lo;
+ /* 134 Register Manufacturer ID Code, MSB */
+ uint8_t reg_id_hi;
+ /* 135 Register Revision Number */
+ uint8_t reg_rev;
+ /* 136 Address mapping from register to DRAM */
+ uint8_t reg_map;
+ /* 137~253 Reserved */
+ uint8_t res_137[254-137];
+ /* 254~255 CRC */
+ uint8_t crc[2];
+ } registered;
+ struct {
+ /* 128 (Loadreduced) Module Nominal Height */
+ uint8_t mod_height;
+ /* 129 (Loadreduced) Module Maximum Thickness */
+ uint8_t mod_thickness;
+ /* 130 (Loadreduced) Reference Raw Card Used */
+ uint8_t ref_raw_card;
+ /* 131 DIMM Module Attributes */
+ uint8_t modu_attr;
+ /* 132 RDIMM Thermal Heat Spreader Solution */
+ uint8_t thermal;
+ /* 133 Register Manufacturer ID Code, LSB */
+ uint8_t reg_id_lo;
+ /* 134 Register Manufacturer ID Code, MSB */
+ uint8_t reg_id_hi;
+ /* 135 Register Revision Number */
+ uint8_t reg_rev;
+ /* 136 Address mapping from register to DRAM */
+ uint8_t reg_map;
+ /* 137 Register Output Drive Strength for CMD/Add*/
+ uint8_t reg_drv;
+ /* 138 Register Output Drive Strength for CK */
+ uint8_t reg_drv_ck;
+ /* 139 Data Buffer Revision Number */
+ uint8_t data_buf_rev;
+ /* 140 DRAM VrefDQ for Package Rank 0 */
+ uint8_t vrefqe_r0;
+ /* 141 DRAM VrefDQ for Package Rank 1 */
+ uint8_t vrefqe_r1;
+ /* 142 DRAM VrefDQ for Package Rank 2 */
+ uint8_t vrefqe_r2;
+ /* 143 DRAM VrefDQ for Package Rank 3 */
+ uint8_t vrefqe_r3;
+ /* 144 Data Buffer VrefDQ for DRAM Interface */
+ uint8_t data_intf;
+ /*
+ * 145 Data Buffer MDQ Drive Strength and RTT
+ * for data rate <= 1866
+ */
+ uint8_t data_drv_1866;
+ /*
+ * 146 Data Buffer MDQ Drive Strength and RTT
+ * for 1866 < data rate <= 2400
+ */
+ uint8_t data_drv_2400;
+ /*
+ * 147 Data Buffer MDQ Drive Strength and RTT
+ * for 2400 < data rate <= 3200
+ */
+ uint8_t data_drv_3200;
+ /* 148 DRAM Drive Strength */
+ uint8_t dram_drv;
+ /*
+ * 149 DRAM ODT (RTT_WR, RTT_NOM)
+ * for data rate <= 1866
+ */
+ uint8_t dram_odt_1866;
+ /*
+ * 150 DRAM ODT (RTT_WR, RTT_NOM)
+ * for 1866 < data rate <= 2400
+ */
+ uint8_t dram_odt_2400;
+ /*
+ * 151 DRAM ODT (RTT_WR, RTT_NOM)
+ * for 2400 < data rate <= 3200
+ */
+ uint8_t dram_odt_3200;
+ /*
+ * 152 DRAM ODT (RTT_PARK)
+ * for data rate <= 1866
+ */
+ uint8_t dram_odt_park_1866;
+ /*
+ * 153 DRAM ODT (RTT_PARK)
+ * for 1866 < data rate <= 2400
+ */
+ uint8_t dram_odt_park_2400;
+ /*
+ * 154 DRAM ODT (RTT_PARK)
+ * for 2400 < data rate <= 3200
+ */
+ uint8_t dram_odt_park_3200;
+ uint8_t res_155[254-155]; /* Reserved */
+ /* 254~255 CRC */
+ uint8_t crc[2];
+ } loadreduced;
+ uint8_t uc[128]; /* 128-255 Module-Specific Section */
+ } mod_section;
+
+ uint8_t res_256[320-256]; /* 256~319 Reserved */
+
+ /* Module supplier's data: Byte 320~383 */
+ uint8_t mmid_lsb; /* 320 Module MfgID Code LSB */
+ uint8_t mmid_msb; /* 321 Module MfgID Code MSB */
+ uint8_t mloc; /* 322 Mfg Location */
+ uint8_t mdate[2]; /* 323~324 Mfg Date */
+ uint8_t sernum[4]; /* 325~328 Module Serial Number */
+ uint8_t mpart[20]; /* 329~348 Mfg's Module Part Number */
+ uint8_t mrev; /* 349 Module Revision Code */
+ uint8_t dmid_lsb; /* 350 DRAM MfgID Code LSB */
+ uint8_t dmid_msb; /* 351 DRAM MfgID Code MSB */
+ uint8_t stepping; /* 352 DRAM stepping */
+ uint8_t msd[29]; /* 353~381 Mfg's Specific Data */
+ uint8_t res_382[2]; /* 382~383 Reserved */
+
+ uint8_t user[512-384]; /* 384~511 End User Programmable */
+};
+
extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd);
extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd);
extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd);
extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd);
extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd);
+unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd);
/*
* Byte 2 Fundamental Memory Types.
@@ -310,6 +519,7 @@ extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd);
#define SPD_MEMTYPE_DDR2_FBDIMM (0x09)
#define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A)
#define SPD_MEMTYPE_DDR3 (0x0B)
+#define SPD_MEMTYPE_DDR4 (0x0C)
/* DIMM Type for DDR2 SPD (according to v1.3) */
#define DDR2_SPD_DIMMTYPE_UNDEFINED (0x00)
@@ -338,4 +548,18 @@ extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd);
#define DDR3_SPD_MODULETYPE_16B_SO_DIMM (0x0C)
#define DDR3_SPD_MODULETYPE_32B_SO_DIMM (0x0D)
+/* DIMM Type for DDR4 SPD */
+#define DDR4_SPD_MODULETYPE_MASK (0x0f)
+#define DDR4_SPD_MODULETYPE_EXT (0x00)
+#define DDR4_SPD_MODULETYPE_RDIMM (0x01)
+#define DDR4_SPD_MODULETYPE_UDIMM (0x02)
+#define DDR4_SPD_MODULETYPE_SO_DIMM (0x03)
+#define DDR4_SPD_MODULETYPE_LRDIMM (0x04)
+#define DDR4_SPD_MODULETYPE_MINI_RDIMM (0x05)
+#define DDR4_SPD_MODULETYPE_MINI_UDIMM (0x06)
+#define DDR4_SPD_MODULETYPE_72B_SO_UDIMM (0x08)
+#define DDR4_SPD_MODULETYPE_72B_SO_RDIMM (0x09)
+#define DDR4_SPD_MODULETYPE_16B_SO_DIMM (0x0C)
+#define DDR4_SPD_MODULETYPE_32B_SO_DIMM (0x0D)
+
#endif /* _DDR_SPD_H_ */
diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h
index 72c0b2e..5c49b22 100644
--- a/include/fsl_ddr.h
+++ b/include/fsl_ddr.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -9,6 +9,7 @@
#ifndef FSL_DDR_MAIN_H
#define FSL_DDR_MAIN_H
+#include <fsl_ddrc_version.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
@@ -22,6 +23,10 @@
#define ddr_out32(a, v) out_be32(a, v)
#endif
+#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
+
+u32 fsl_ddr_get_version(void);
+
#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
/*
* Bind the main DDR setup driver's generic names
diff --git a/include/fsl_ddr_dimm_params.h b/include/fsl_ddr_dimm_params.h
index 99a72bc..09a67a6 100644
--- a/include/fsl_ddr_dimm_params.h
+++ b/include/fsl_ddr_dimm_params.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -13,7 +13,7 @@
#define EDC_ECC 2
#define EDC_AC_PARITY 4
-/* Parameters for a DDR2 dimm computed from the SPD */
+/* Parameters for a DDR dimm computed from the SPD */
typedef struct dimm_params_s {
/* DIMM organization parameters */
@@ -32,7 +32,12 @@ typedef struct dimm_params_s {
unsigned int n_row_addr;
unsigned int n_col_addr;
unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
+#ifdef CONFIG_SYS_FSL_DDR4
+ unsigned int bank_addr_bits;
+ unsigned int bank_group_bits;
+#else
unsigned int n_banks_per_sdram_device;
+#endif
unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
unsigned int row_density;
@@ -43,19 +48,19 @@ typedef struct dimm_params_s {
/* DIMM timing parameters */
- unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */
- unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */
- unsigned int taa_ps; /* minimum CAS latency time, only for ddr3 */
- unsigned int tfaw_ps; /* four active window delay, only for ddr3 */
+ int mtb_ps; /* medium timebase ps */
+ int ftb_10th_ps; /* fine timebase, in 1/10 ps */
+ int taa_ps; /* minimum CAS latency time */
+ int tfaw_ps; /* four active window delay */
/*
* SDRAM clock periods
* The range for these are 1000-10000 so a short should be sufficient
*/
- unsigned int tckmin_x_ps;
- unsigned int tckmin_x_minus_1_ps;
- unsigned int tckmin_x_minus_2_ps;
- unsigned int tckmax_ps;
+ int tckmin_x_ps;
+ int tckmin_x_minus_1_ps;
+ int tckmin_x_minus_2_ps;
+ int tckmax_ps;
/* SPD-defined CAS latencies */
unsigned int caslat_x;
@@ -65,32 +70,46 @@ typedef struct dimm_params_s {
unsigned int caslat_lowest_derated; /* Derated CAS latency */
/* basic timing parameters */
- unsigned int trcd_ps;
- unsigned int trp_ps;
- unsigned int tras_ps;
-
- unsigned int twr_ps; /* maximum = 63750 ps */
- unsigned int twtr_ps; /* maximum = 63750 ps */
- unsigned int trfc_ps; /* max = 255 ns + 256 ns + .75 ns
+ int trcd_ps;
+ int trp_ps;
+ int tras_ps;
+
+#ifdef CONFIG_SYS_FSL_DDR4
+ int trfc1_ps;
+ int trfc2_ps;
+ int trfc4_ps;
+ int trrds_ps;
+ int trrdl_ps;
+ int tccdl_ps;
+#else
+ int twr_ps; /* maximum = 63750 ps */
+ int trfc_ps; /* max = 255 ns + 256 ns + .75 ns
= 511750 ps */
+ int trrd_ps; /* maximum = 63750 ps */
+ int twtr_ps; /* maximum = 63750 ps */
+ int trtp_ps; /* byte 38, spd->trtp */
+#endif
- unsigned int trrd_ps; /* maximum = 63750 ps */
- unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
+ int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
- unsigned int refresh_rate_ps;
- unsigned int extended_op_srt;
+ int refresh_rate_ps;
+ int extended_op_srt;
- /* DDR3 doesn't need these as below */
- unsigned int tis_ps; /* byte 32, spd->ca_setup */
- unsigned int tih_ps; /* byte 33, spd->ca_hold */
- unsigned int tds_ps; /* byte 34, spd->data_setup */
- unsigned int tdh_ps; /* byte 35, spd->data_hold */
- unsigned int trtp_ps; /* byte 38, spd->trtp */
- unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */
- unsigned int tqhs_ps; /* byte 45, spd->tqhs */
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
+ int tis_ps; /* byte 32, spd->ca_setup */
+ int tih_ps; /* byte 33, spd->ca_hold */
+ int tds_ps; /* byte 34, spd->data_setup */
+ int tdh_ps; /* byte 35, spd->data_hold */
+ int tdqsq_max_ps; /* byte 44, spd->tdqsq */
+ int tqhs_ps; /* byte 45, spd->tqhs */
+#endif
/* DDR3 RDIMM */
unsigned char rcw[16]; /* Register Control Word 0-15 */
+#ifdef CONFIG_SYS_FSL_DDR4
+ unsigned int dq_mapping[18];
+ unsigned int dq_mapping_ors;
+#endif
} dimm_params_t;
extern unsigned int ddr_compute_dimm_parameters(
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index 2a36431..e39b716 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -13,11 +13,13 @@
* Pick a basic DDR Technology.
*/
#include <ddr_spd.h>
+#include <fsl_ddrc_version.h>
-#define SDRAM_TYPE_DDR1 2
-#define SDRAM_TYPE_DDR2 3
-#define SDRAM_TYPE_LPDDR1 6
-#define SDRAM_TYPE_DDR3 7
+#define SDRAM_TYPE_DDR1 2
+#define SDRAM_TYPE_DDR2 3
+#define SDRAM_TYPE_LPDDR1 6
+#define SDRAM_TYPE_DDR3 7
+#define SDRAM_TYPE_DDR4 5
#define DDR_BL4 4 /* burst length 4 */
#define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */
@@ -54,6 +56,12 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
#endif
+#elif defined(CONFIG_SYS_FSL_DDR4)
+#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
+typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
+#ifndef CONFIG_FSL_SDRAM_TYPE
+#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4
+#endif
#endif /* #if defined(CONFIG_SYS_FSL_DDR1) */
#define FSL_DDR_ODT_NEVER 0x0
@@ -116,7 +124,8 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#define TIMING_CFG_2_CPO_MASK 0x0F800000
-#if defined(CONFIG_P4080)
+#if defined(CONFIG_SYS_FSL_DDR_VER) && \
+ (CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4)
#define RD_TO_PRE_MASK 0xf
#define RD_TO_PRE_SHIFT 13
#define WR_DATA_DELAY_MASK 0xf
@@ -154,9 +163,27 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#define DDR_CDR2_ODT_MASK 0x1
#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
+#define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8))
#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
+#ifdef CONFIG_SYS_FSL_DDR3L
+#define DDR_CDR_ODT_OFF 0x0
+#define DDR_CDR_ODT_120ohm 0x1
+#define DDR_CDR_ODT_200ohm 0x2
+#define DDR_CDR_ODT_75ohm 0x3
+#define DDR_CDR_ODT_60ohm 0x5
+#define DDR_CDR_ODT_46ohm 0x7
+#elif defined(CONFIG_SYS_FSL_DDR4)
+#define DDR_CDR_ODT_OFF 0x0
+#define DDR_CDR_ODT_100ohm 0x1
+#define DDR_CDR_ODT_120OHM 0x2
+#define DDR_CDR_ODT_80ohm 0x3
+#define DDR_CDR_ODT_60ohm 0x4
+#define DDR_CDR_ODT_40ohm 0x5
+#define DDR_CDR_ODT_50ohm 0x6
+#define DDR_CDR_ODT_30ohm 0x7
+#else
#define DDR_CDR_ODT_OFF 0x0
#define DDR_CDR_ODT_120ohm 0x1
#define DDR_CDR_ODT_180ohm 0x2
@@ -165,6 +192,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#define DDR_CDR_ODT_60hm 0x5
#define DDR_CDR_ODT_70ohm 0x6
#define DDR_CDR_ODT_47ohm 0x7
+#endif /* DDR3L */
#else
#define DDR_CDR_ODT_75ohm 0x0
#define DDR_CDR_ODT_55ohm 0x1
@@ -188,6 +216,7 @@ typedef struct fsl_ddr_cfg_regs_s {
unsigned int timing_cfg_2;
unsigned int ddr_sdram_cfg;
unsigned int ddr_sdram_cfg_2;
+ unsigned int ddr_sdram_cfg_3;
unsigned int ddr_sdram_mode;
unsigned int ddr_sdram_mode_2;
unsigned int ddr_sdram_mode_3;
@@ -196,6 +225,14 @@ typedef struct fsl_ddr_cfg_regs_s {
unsigned int ddr_sdram_mode_6;
unsigned int ddr_sdram_mode_7;
unsigned int ddr_sdram_mode_8;
+ unsigned int ddr_sdram_mode_9;
+ unsigned int ddr_sdram_mode_10;
+ unsigned int ddr_sdram_mode_11;
+ unsigned int ddr_sdram_mode_12;
+ unsigned int ddr_sdram_mode_13;
+ unsigned int ddr_sdram_mode_14;
+ unsigned int ddr_sdram_mode_15;
+ unsigned int ddr_sdram_mode_16;
unsigned int ddr_sdram_md_cntl;
unsigned int ddr_sdram_interval;
unsigned int ddr_data_init;
@@ -204,6 +241,10 @@ typedef struct fsl_ddr_cfg_regs_s {
unsigned int ddr_init_ext_addr;
unsigned int timing_cfg_4;
unsigned int timing_cfg_5;
+ unsigned int timing_cfg_6;
+ unsigned int timing_cfg_7;
+ unsigned int timing_cfg_8;
+ unsigned int timing_cfg_9;
unsigned int ddr_zq_cntl;
unsigned int ddr_wrlvl_cntl;
unsigned int ddr_wrlvl_cntl_2;
@@ -211,6 +252,14 @@ typedef struct fsl_ddr_cfg_regs_s {
unsigned int ddr_sr_cntr;
unsigned int ddr_sdram_rcw_1;
unsigned int ddr_sdram_rcw_2;
+ unsigned int ddr_sdram_rcw_3;
+ unsigned int ddr_sdram_rcw_4;
+ unsigned int ddr_sdram_rcw_5;
+ unsigned int ddr_sdram_rcw_6;
+ unsigned int dq_map_0;
+ unsigned int dq_map_1;
+ unsigned int dq_map_2;
+ unsigned int dq_map_3;
unsigned int ddr_eor;
unsigned int ddr_cdr1;
unsigned int ddr_cdr2;
@@ -225,7 +274,7 @@ typedef struct memctl_options_partial_s {
unsigned int all_dimms_burst_lengths_bitmask;
unsigned int all_dimms_registered;
unsigned int all_dimms_unbuffered;
- /* unsigned int lowest_common_SPD_caslat; */
+ /* unsigned int lowest_common_spd_caslat; */
unsigned int all_dimms_minimum_trcd_ps;
} memctl_options_partial_t;
diff --git a/include/fsl_ddrc_version.h b/include/fsl_ddrc_version.h
new file mode 100644
index 0000000..60ba98b
--- /dev/null
+++ b/include/fsl_ddrc_version.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_DDRC_VER_H
+#define __FSL_DDRC_VER_H
+
+/*
+ * Only the versions with distinct features or registers are listed here.
+ */
+#define FSL_DDR_VER_4_4 44
+#define FSL_DDR_VER_4_6 46
+#define FSL_DDR_VER_4_7 47
+#define FSL_DDR_VER_5_0 50
+
+#endif /* __FSL_DDRC_VER_H */
diff --git a/include/fsl_immap.h b/include/fsl_immap.h
index 00902ca..d63cc19 100644
--- a/include/fsl_immap.h
+++ b/include/fsl_immap.h
@@ -1,7 +1,7 @@
/*
* Common internal memory map for some Freescale SoCs
*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -50,7 +50,8 @@ struct ccsr_ddr {
u8 res_150[16];
u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
- u8 reg_168[8];
+ u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */
+ u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */
u32 ddr_zq_cntl; /* ZQ calibration control*/
u32 ddr_wrlvl_cntl; /* write leveling control*/
u8 reg_178[4];
@@ -60,14 +61,40 @@ struct ccsr_ddr {
u8 reg_188[8];
u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
- u8 res_198[104];
+ u8 res_198[0x1a0-0x198];
+ u32 ddr_sdram_rcw_3;
+ u32 ddr_sdram_rcw_4;
+ u32 ddr_sdram_rcw_5;
+ u32 ddr_sdram_rcw_6;
+ u8 res_1b0[0x200-0x1b0];
u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
- u8 res_218[0x908];
+ u8 res_218[0x220-0x218];
+ u32 sdram_mode_9; /* SDRAM Mode Configuration 9 */
+ u32 sdram_mode_10; /* SDRAM Mode Configuration 10 */
+ u32 sdram_mode_11; /* SDRAM Mode Configuration 11 */
+ u32 sdram_mode_12; /* SDRAM Mode Configuration 12 */
+ u32 sdram_mode_13; /* SDRAM Mode Configuration 13 */
+ u32 sdram_mode_14; /* SDRAM Mode Configuration 14 */
+ u32 sdram_mode_15; /* SDRAM Mode Configuration 15 */
+ u32 sdram_mode_16; /* SDRAM Mode Configuration 16 */
+ u8 res_240[0x250-0x240];
+ u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */
+ u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */
+ u8 res_258[0x260-0x258];
+ u32 sdram_cfg_3;
+ u8 res_264[0x2a0-0x264];
+ u32 deskew_cntl;
+ u8 res_2a4[0x400-0x2a4];
+ u32 dq_map_0;
+ u32 dq_map_1;
+ u32 dq_map_2;
+ u32 dq_map_3;
+ u8 res_410[0xb20-0x410];
u32 ddr_dsr1; /* Debug Status 1 */
u32 ddr_dsr2; /* Debug Status 2 */
u32 ddr_cdr1; /* Control Driver 1 */