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authorAneesh Bansal <aneesh.bansal@freescale.com>2014-05-14 11:45:15 +0530
committerYork Sun <yorksun@freescale.com>2014-05-16 16:24:27 -0500
commit3051f3f999cc1bae465126f5766329058e12acfa (patch)
tree3991d52f252da31cd263e5cc41a1023491810c50 /include
parent80ba6a6f2ae347b84a607ec085c6f0acd1584aaa (diff)
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powerpc/mpc85xx: SECURE BOOT- corrected CSPR settings for BSC9132QDS NAND
In case of secure boot from NAND, CSPR and FTIM settings are same as non-secure NAND boot. CSPR0 is configured as NAND and CSPR1 is configured as NOR. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/BSC9132QDS.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index e76a04b..7bb5d33 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -360,7 +360,7 @@ combinations. this should be removed later
#endif
/* Set up IFC registers for boot location NOR/NAND */
-#if defined(CONFIG_NAND)
+#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR