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authorYork Sun <yorksun@freescale.com>2012-02-29 12:36:51 +0000
committerAndy Fleming <afleming@freescale.com>2012-04-24 23:58:30 -0500
commit1ba62f10172ead798a8176435cfffff2f79f21c5 (patch)
tree5e9b575825060fae4ebefa3193ad5f1124c0fefd /include
parent119a55f9cff4884a0ad3353d8752ee8787e232da (diff)
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powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
P1010RDB and p1_pc_rdb_pc has incorrect configuration for CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING. Incorrect setting causes DDR failure in case of SPD absent. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/P1010RDB.h2
-rw-r--r--include/configs/p1_p2_rdb_pc.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index f2d3366..08fc4e8 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -181,7 +181,7 @@
/* DDR Setup */
#define CONFIG_FSL_DDR3
-#define CONFIG_DDR_RAW_TIMING
+#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS 0x52
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 3098c5a..a8db06f 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -227,7 +227,7 @@
/* DDR Setup */
#define CONFIG_FSL_DDR3
-#define CONFIG_DDR_RAW_TIMING
+#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS 0x52