summaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorTom Rini <trini@ti.com>2014-08-31 07:45:55 -0400
committerTom Rini <trini@ti.com>2014-08-31 07:45:55 -0400
commit0a64bc20f7f160904d3795536ec70446ad743826 (patch)
treeb8187d17273524de0d6d9b8f3ae7958aab2b2ae1 /include
parent16e16fdde21c9255e338d2eaea339c3ca905da22 (diff)
parent857b9cb69ffc2b5a607e55a09325290274c7272e (diff)
downloadu-boot-imx-0a64bc20f7f160904d3795536ec70446ad743826.zip
u-boot-imx-0a64bc20f7f160904d3795536ec70446ad743826.tar.gz
u-boot-imx-0a64bc20f7f160904d3795536ec70446ad743826.tar.bz2
Merge branch 'master' of git://git.denx.de/u-boot-nios
Diffstat (limited to 'include')
-rw-r--r--include/configs/nios2-generic.h11
-rw-r--r--include/nios2-io.h153
-rw-r--r--include/nios2-yanu.h99
-rw-r--r--include/nios2.h40
4 files changed, 9 insertions, 294 deletions
diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h
index 51b1d00..6247bf1 100644
--- a/include/configs/nios2-generic.h
+++ b/include/configs/nios2-generic.h
@@ -22,7 +22,7 @@
/*
* SERIAL
*/
-#define CONFIG_ALTERA_UART
+#define CONFIG_ALTERA_JTAG_UART
#if defined(CONFIG_ALTERA_JTAG_UART)
# define CONFIG_SYS_NIOS_CONSOLE CONFIG_SYS_JTAG_UART_BASE
#else
@@ -56,6 +56,9 @@
#define CONFIG_BOARD_SPECIFIC_LED
#define CONFIG_GPIO_LED /* Enable GPIO LED driver */
#define CONFIG_GPIO /* Enable GPIO driver */
+#define LED_PIO_BASE USER_LED_PIO_8OUT_BASE
+#define LED_PIO_WIDTH 8
+#define LED_PIO_RSTVAL 0xff
#define STATUS_LED_BIT 0 /* Bit-0 on GPIO */
#define STATUS_LED_STATE 1 /* Blinking */
@@ -86,6 +89,10 @@
# define CONFIG_CMD_PING
#endif
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_LMB
+
/*
* ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
* CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
@@ -95,7 +102,7 @@
*/
#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */
+#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */
#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
#define CONFIG_ENV_ADDR ((CONFIG_SYS_RESET_ADDR + \
CONFIG_SYS_MONITOR_LEN) | \
diff --git a/include/nios2-io.h b/include/nios2-io.h
deleted file mode 100644
index 6f1ae50..0000000
--- a/include/nios2-io.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*************************************************************************
- * Altera Nios2 Standard Peripherals
- ************************************************************************/
-
-#ifndef __NIOS2IO_H__
-#define __NIOS2IO_H__
-
-/*------------------------------------------------------------------------
- * UART (http://www.altera.com/literature/ds/ds_nios_uart.pdf)
- *----------------------------------------------------------------------*/
-typedef volatile struct nios_uart_t {
- unsigned rxdata; /* Rx data reg */
- unsigned txdata; /* Tx data reg */
- unsigned status; /* Status reg */
- unsigned control; /* Control reg */
- unsigned divisor; /* Baud rate divisor reg */
- unsigned endofpacket; /* End-of-packet reg */
-}nios_uart_t;
-
-/* status register */
-#define NIOS_UART_PE (1 << 0) /* parity error */
-#define NIOS_UART_FE (1 << 1) /* frame error */
-#define NIOS_UART_BRK (1 << 2) /* break detect */
-#define NIOS_UART_ROE (1 << 3) /* rx overrun */
-#define NIOS_UART_TOE (1 << 4) /* tx overrun */
-#define NIOS_UART_TMT (1 << 5) /* tx empty */
-#define NIOS_UART_TRDY (1 << 6) /* tx ready */
-#define NIOS_UART_RRDY (1 << 7) /* rx ready */
-#define NIOS_UART_E (1 << 8) /* exception */
-#define NIOS_UART_DCTS (1 << 10) /* cts change */
-#define NIOS_UART_CTS (1 << 11) /* cts */
-#define NIOS_UART_EOP (1 << 12) /* eop detected */
-
-/* control register */
-#define NIOS_UART_IPE (1 << 0) /* parity error int ena*/
-#define NIOS_UART_IFE (1 << 1) /* frame error int ena */
-#define NIOS_UART_IBRK (1 << 2) /* break detect int ena */
-#define NIOS_UART_IROE (1 << 3) /* rx overrun int ena */
-#define NIOS_UART_ITOE (1 << 4) /* tx overrun int ena */
-#define NIOS_UART_ITMT (1 << 5) /* tx empty int ena */
-#define NIOS_UART_ITRDY (1 << 6) /* tx ready int ena */
-#define NIOS_UART_IRRDY (1 << 7) /* rx ready int ena */
-#define NIOS_UART_IE (1 << 8) /* exception int ena */
-#define NIOS_UART_TBRK (1 << 9) /* transmit break */
-#define NIOS_UART_IDCTS (1 << 10) /* cts change int ena */
-#define NIOS_UART_RTS (1 << 11) /* rts */
-#define NIOS_UART_IEOP (1 << 12) /* eop detected int ena */
-
-
-/*------------------------------------------------------------------------
- * TIMER (http://www.altera.com/literature/ds/ds_nios_timer.pdf)
- *----------------------------------------------------------------------*/
-typedef volatile struct nios_timer_t {
- unsigned status; /* Timer status reg */
- unsigned control; /* Timer control reg */
- unsigned periodl; /* Timeout period low */
- unsigned periodh; /* Timeout period high */
- unsigned snapl; /* Snapshot low */
- unsigned snaph; /* Snapshot high */
-}nios_timer_t;
-
-/* status register */
-#define NIOS_TIMER_TO (1 << 0) /* Timeout */
-#define NIOS_TIMER_RUN (1 << 1) /* Timer running */
-
-/* control register */
-#define NIOS_TIMER_ITO (1 << 0) /* Timeout int ena */
-#define NIOS_TIMER_CONT (1 << 1) /* Continuous mode */
-#define NIOS_TIMER_START (1 << 2) /* Start timer */
-#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */
-
-
-/*------------------------------------------------------------------------
- * PIO (http://www.altera.com/literature/ds/ds_nios_pio.pdf)
- *----------------------------------------------------------------------*/
-typedef volatile struct nios_pio_t {
- unsigned int data; /* Data value at each PIO in/out */
- unsigned int direction; /* Data direct. for each PIO bit */
- unsigned int interruptmask; /* Per-bit IRQ enable/disable */
- unsigned int edgecapture; /* Per-bit sync. edge detect & hold */
-}nios_pio_t;
-
-/* direction register */
-#define NIOS_PIO_OUT (1) /* PIO bit is output */
-#define NIOS_PIO_IN (0) /* PIO bit is input */
-
-
-/*------------------------------------------------------------------------
- * SPI (http://www.altera.com/literature/ds/ds_nios_spi.pdf)
- *----------------------------------------------------------------------*/
-typedef volatile struct nios_spi_t {
- unsigned rxdata; /* Rx data reg */
- unsigned txdata; /* Tx data reg */
- unsigned status; /* Status reg */
- unsigned control; /* Control reg */
- unsigned reserved; /* (master only) */
- unsigned slaveselect; /* SPI slave select mask (master only) */
-}nios_spi_t;
-
-/* status register */
-#define NIOS_SPI_ROE (1 << 3) /* rx overrun */
-#define NIOS_SPI_TOE (1 << 4) /* tx overrun */
-#define NIOS_SPI_TMT (1 << 5) /* tx empty */
-#define NIOS_SPI_TRDY (1 << 6) /* tx ready */
-#define NIOS_SPI_RRDY (1 << 7) /* rx ready */
-#define NIOS_SPI_E (1 << 8) /* exception */
-
-/* control register */
-#define NIOS_SPI_IROE (1 << 3) /* rx overrun int ena */
-#define NIOS_SPI_ITOE (1 << 4) /* tx overrun int ena */
-#define NIOS_SPI_ITRDY (1 << 6) /* tx ready int ena */
-#define NIOS_SPI_IRRDY (1 << 7) /* rx ready int ena */
-#define NIOS_SPI_IE (1 << 8) /* exception int ena */
-#define NIOS_SPI_SSO (1 << 10) /* override SS_n output */
-
-/*------------------------------------------------------------------------
- * JTAG UART
- *----------------------------------------------------------------------*/
-typedef volatile struct nios_jtag_t {
- unsigned data; /* Data register */
- unsigned control; /* Control register */
-}nios_jtag_t;
-
-/* data register */
-#define NIOS_JTAG_RVALID (1<<15) /* Read valid */
-#define NIOS_JTAG_DATA(d) ((d)&0x0ff) /* Read data */
-#define NIOS_JTAG_RAVAIL(d) ((d)>>16) /* Read space avail */
-
-/* control register */
-#define NIOS_JTAG_RE (1 << 0) /* read intr enable */
-#define NIOS_JTAG_WE (1 << 1) /* write intr enable */
-#define NIOS_JTAG_RI (1 << 8) /* read intr pending */
-#define NIOS_JTAG_WI (1 << 9) /* write intr pending*/
-#define NIOS_JTAG_AC (1 << 10) /* activity indicator */
-#define NIOS_JTAG_RRDY (1 << 12) /* read available */
-#define NIOS_JTAG_WSPACE(d) ((d)>>16) /* Write space avail */
-
-/*------------------------------------------------------------------------
- * SYSTEM ID
- *----------------------------------------------------------------------*/
-typedef volatile struct nios_sysid_t {
- unsigned id; /* The system build id*/
- unsigned timestamp; /* Timestamp */
-}nios_sysid_t;
-
-#endif /* __NIOS2IO_H__ */
diff --git a/include/nios2-yanu.h b/include/nios2-yanu.h
deleted file mode 100644
index 6c16f5b..0000000
--- a/include/nios2-yanu.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2006, Imagos S.a.s <www.imagos.it>
- * Renato Andreola <renato.andreola@imagos.it>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*************************************************************************
- * Altera NiosII YANU serial interface by Imagos
- * please see http://www.opencores.org/project,yanu for
- * information/downloads
- ************************************************************************/
-
-#ifndef __NIOS2_YANU_H__
-#define __NIOS2_YANU_H__
-
-#define YANU_MAX_PRESCALER_N ((1 << 4) - 1) /* 15 */
-#define YANU_MAX_PRESCALER_M ((1 << 11) -1) /* 2047 */
-#define YANU_FIFO_SIZE (16)
-#define YANU_RXFIFO_SIZE (YANU_FIFO_SIZE)
-#define YANU_TXFIFO_SIZE (YANU_FIFO_SIZE)
-
-#define YANU_RXFIFO_DLY (10*11)
-#define YANU_TXFIFO_THR (10)
-#define YANU_DATA_CHAR_MASK (0xFF)
-
-/* data register */
-#define YANU_DATA_OFFSET (0) /* data register offset */
-
-#define YANU_CONTROL_OFFSET (4) /* control register offset */
-/* interrupt enable */
-#define YANU_CONTROL_IE_RRDY (1<<0) /* ie on received character ready */
-#define YANU_CONTROL_IE_OE (1<<1) /* ie on rx overrun */
-#define YANU_CONTROL_IE_BRK (1<<2) /* ie on break detect */
-#define YANU_CONTROL_IE_FE (1<<3) /* ie on framing error */
-#define YANU_CONTROL_IE_PE (1<<4) /* ie on parity error */
-#define YANU_CONTROL_IE_TRDY (1<<5) /* ie interrupt on tranmitter ready */
-/* control bits */
-#define YANU_CONTROL_BITS_POS (6) /* bits number pos */
-#define YANU_CONTROL_BITS (1<<YANU_CONTROL_BITS_POS) /* number of rx/tx bits per word. 3 bit unsigned integer */
-#define YANU_CONTROL_BITS_N (3) /* ... its bit filed length */
-#define YANU_CONTROL_PARENA (1<<9) /* enable parity bit transmission/reception */
-#define YANU_CONTROL_PAREVEN (1<<10) /* parity even */
-#define YANU_CONTROL_STOPS (1<<11) /* number of stop bits */
-#define YANU_CONTROL_HHENA (1<<12) /* Harware Handshake enable... */
-#define YANU_CONTROL_FORCEBRK (1<<13) /* if set than txd = active (0) */
-/* tuning part */
-#define YANU_CONTROL_RDYDLY (1<<14) /* delay from "first" before setting rrdy (in bit) */
-#define YANU_CONTROL_RDYDLY_N (8) /* ... its bit filed length */
-#define YANU_CONTROL_TXTHR (1<<22) /* tx interrupt threshold: the trdy set if txfifo_chars<= txthr (chars) */
-#define YANU_CONTROL_TXTHR_N (4) /* ... its bit field length */
-
-#define YANU_BAUD_OFFSET (8) /* baud register offset */
-#define YANU_BAUDM (1<<0) /* baud mantissa lsb */
-#define YANU_BAUDM_N (12) /* ...its bit filed length */
-#define YANU_BAUDE (1<<12) /* baud exponent lsb */
-#define YANU_BAUDE_N (4) /* ...its bit field length */
-
-#define YANU_ACTION_OFFSET (12) /* action register... write only */
-#define YANU_ACTION_RRRDY (1<<0) /* reset rrdy */
-#define YANU_ACTION_ROE (1<<1) /* reset oe */
-#define YANU_ACTION_RBRK (1<<2) /* reset brk */
-#define YANU_ACTION_RFE (1<<3) /* reset fe */
-#define YANU_ACTION_RPE (1<<4) /* reset pe */
-#define YANU_ACTION_SRRDY (1<<5) /* set rrdy */
-#define YANU_ACTION_SOE (1<<6) /* set oe */
-#define YANU_ACTION_SBRK (1<<7) /* set brk */
-#define YANU_ACTION_SFE (1<<8) /* set fe */
-#define YANU_ACTION_SPE (1<<9) /* set pe */
-#define YANU_ACTION_RFIFO_PULL (1<<10) /* pull a char from rx fifo we MUST do it before taking a char */
-#define YANU_ACTION_RFIFO_CLEAR (1<<11) /* clear rx fifo */
-#define YANU_ACTION_TFIFO_CLEAR (1<<12) /* clear tx fifo */
-#define YANU_ACTION_RTRDY (1<<13) /* clear trdy */
-#define YANU_ACTION_STRDY (1<<14) /* set trdy */
-
-#define YANU_STATUS_OFFSET (16)
-#define YANU_STATUS_RRDY (1<<0) /* rxrdy flag */
-#define YANU_STATUS_TRDY (1<<1) /* txrdy flag */
-#define YANU_STATUS_OE (1<<2) /* rx overrun error */
-#define YANU_STATUS_BRK (1<<3) /* rx break detect flag */
-#define YANU_STATUS_FE (1<<4) /* rx framing error flag */
-#define YANU_STATUS_PE (1<<5) /* rx parity erro flag */
-#define YANU_RFIFO_CHARS_POS (6)
-#define YANU_RFIFO_CHARS (1<<RFIFO_CHAR_POS) /* number of chars into rx fifo */
-#define YANU_RFIFO_CHARS_N (5) /* ...its bit field length: 32 chars */
-#define YANU_TFIFO_CHARS_POS (11)
-#define YANU_TFIFO_CHARS (1<<TFIFO_CHAR_POS) /* number of chars into tx fifo */
-#define YANU_TFIFO_CHARS_N (5) /* ...its bit field length: 32 chars */
-
-typedef volatile struct yanu_uart_t {
- volatile unsigned data;
- volatile unsigned control; /* control register (RW) 32-bit */
- volatile unsigned baud; /* baud/prescaler register (RW) 32-bit */
- volatile unsigned action; /* action register (W) 32-bit */
- volatile unsigned status; /* status register (R) 32-bit */
- volatile unsigned magic; /* magic register (R) 32-bit */
-} yanu_uart_t;
-
-#endif
diff --git a/include/nios2.h b/include/nios2.h
deleted file mode 100644
index 0539ec3..0000000
--- a/include/nios2.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __NIOS2_H__
-#define __NIOS2_H__
-
-/*------------------------------------------------------------------------
- * Control registers -- use with wrctl() & rdctl()
- *----------------------------------------------------------------------*/
-#define CTL_STATUS 0 /* Processor status reg */
-#define CTL_ESTATUS 1 /* Exception status reg */
-#define CTL_BSTATUS 2 /* Break status reg */
-#define CTL_IENABLE 3 /* Interrut enable reg */
-#define CTL_IPENDING 4 /* Interrut pending reg */
-
-/*------------------------------------------------------------------------
- * Access to control regs
- *----------------------------------------------------------------------*/
-
-#define rdctl(reg) __builtin_rdctl(reg)
-#define wrctl(reg, val) __builtin_wrctl(reg, val)
-
-/*------------------------------------------------------------------------
- * Control reg bit masks
- *----------------------------------------------------------------------*/
-#define STATUS_IE (1<<0) /* Interrupt enable */
-#define STATUS_U (1<<1) /* User-mode */
-
-/*------------------------------------------------------------------------
- * Bit-31 Cache bypass -- only valid for data access. When data cache
- * is not implemented, bit 31 is ignored for compatibility.
- *----------------------------------------------------------------------*/
-#define CACHE_BYPASS(a) ((a) | 0x80000000)
-#define CACHE_NO_BYPASS(a) ((a) & ~0x80000000)
-
-#endif /* __NIOS2_H__ */